WO2025152140A1

WO2025152140A1 - Array substrate and display apparatus

Info

Publication number: WO2025152140A1
Application number: PCT/CN2024/073206
Authority: WO
Inventors: Changchang Liu; Zhu WANG; Ling Shi
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2024-01-19
Filing date: 2024-01-19
Publication date: 2025-07-24
Anticipated expiration: 2026-07-19
Also published as: CN120677867A

Abstract

An array substrate is provided. The array substrate includes a first reset signal network (LP1). The first reset signal network includes a plurality of first reset signal lines (VINT1) and a plurality of first loops (LP1) interconnected together. A respective first loop (LP1) of the plurality of first loops (LP1) is connected to two adjacent first reset signal lines (VINT1) of the plurality of first reset signal lines (VINT1), respectively. A respective first reset signal line (VINT1) of the plurality of first reset signal lines (VINT1) is connected to two first loops (LP1), respectively. The two first loops (LP1) are in two adjacent rows of subpixels, respectively.

Description

ARRAY SUBSTRATE AND DISPLAY APPARATUS

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to an array substrate and a display apparatus.

BACKGROUND

Organic Light Emitting Diode (OLED) display is one of the hotspots in the field of flat panel display research today. Unlike Thin Film Transistor-Liquid Crystal Display (TFT-LCD) , which uses a stable voltage to control brightness, OLED is driven by a driving current required to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units configured with pixel-driving circuits arranged in multiple rows and columns. Each pixel-driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the row in which the pixel unit is gated is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to an OLED device. The OLED device is driven to emit light of a corresponding brightness.

SUMMARY

In one aspect, the present disclosure provides an array substrate, comprising a first reset signal network; wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of first loops interconnected together; a respective first loop of the plurality of first loops is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively; a respective first reset signal line of the plurality of first reset signal lines is connected to two first loops, respectively; the two first loops are in two adjacent rows of subpixels, respectively.

Optionally, the respective first reset signal line comprises a first main body and a plurality of first branches connected to the first main body; the first main body extends along a first direction; a respective first branch of the plurality of first branches extends along a second direction; the first direction and the second direction are different from each other; and the respective first branch is connected to two first loops, respectively.

Optionally, the plurality of first loops are in a layer different from the plurality of first reset signal lines; and the respective first reset signal line is connected to the respective first loop through a via extending through at least one layer comprising an insulating material.

Optionally, the plurality of first loops are in a third gate metal layer; the plurality of first reset signal lines are in a first signal line layer; and the respective first reset signal line is connected to the respective first loop through a via extending through a passivation layer.

Optionally, the array substrate comprises a plurality of pixel driving circuits; wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a first reset transistor; first electrodes of two first reset transistors in two adjacent pixel driving circuits in a same row are parts of a unitary structure; and the respective first reset signal line is connected to the unitary structure comprising the first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row through a first single via.

Optionally, the unitary structure further comprises active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row; and an orthographic projection of the respective first reset signal line on a base substrate at least partially overlaps with an orthographic projection of the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.

Optionally, the array substrate comprises a plurality of pixel driving circuits; wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a data write transistor, a compensating transistor, a first light emitting control transistor, and a driving transistor; an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent unitary structures from two adjacent pixel driving circuits on the base substrate; and a respective unitary structure of the two adjacent unitary structures comprises at least portions of a second electrode of the data write transistor, a second electrode of the first light emitting control transistor, and a first electrode of the driving transistor.

Optionally, the array substrate comprises a plurality of pixel driving circuits; wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a compensating transistor, a driving transistor, a third reset transistor, and a third node connecting line; the third node connecting line is connected to a first electrode of the compensating transistor through a first via, is connected to a second electrode of the third reset transistor through a second via, and is connected to a second electrode of the driving transistor through a third via.

Optionally, an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent third node connecting lines from two adjacent pixel driving circuits on the base substrate.

Optionally, the array substrate further comprises a plurality of first gate lines; wherein an orthographic projection of the third node connecting line on a base substrate partially overlaps with an orthographic projection of the respective first gate line on the base substrate.

Optionally, the array substrate further comprises a plurality of second gate lines; wherein the orthographic projection of the third node connecting line on the base substrate partially overlaps with an orthographic projection of the respective second gate line on the base substrate.

Optionally, the array substrate further comprises a plurality of data lines; wherein an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent data lines of the plurality of data lines on the base substrate.

Optionally, the array substrate further comprises a second reset signal network; wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of second loops interconnected together; a respective second loop of the plurality of second loops is connected to two adjacent second reset signal lines of the plurality of second reset signal lines, respectively; a respective second reset signal line of the plurality of second reset signal lines is connected to two second loops, respectively; and the two second loops are in two adjacent rows of subpixels, respectively.

Optionally, the respective second reset signal line comprises a second main body and a plurality of second branches connected to the second main body; the second main body extends along a first direction; a respective second branch of the plurality of second branches extends along a second direction; the first direction and the second direction are different from each other; and the respective second branch is connected to two second loops, respectively.

Optionally, the plurality of second loops are in a layer different from the plurality of second reset signal lines; and the respective second reset signal line is connected to the respective second loop through a via extending through at least one layer comprising an insulating material.

Optionally, the plurality of second loops are in a third gate metal layer; the plurality of second reset signal lines are in a first signal line layer; and the respective second reset signal line is connected to the respective second loop through a via extending through a passivation layer.

Optionally, the array substrate comprises a plurality of pixel driving circuits; wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a second reset transistor; first electrodes of two second reset transistors in two adjacent pixel driving circuits in a same row are parts of a unitary structure; and the respective second reset signal line is connected to the unitary structure comprising the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row through a second single via.

Optionally, the unitary structure further comprises active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row; and an orthographic projection of the respective second reset signal line on a base substrate at least partially overlaps with an orthographic projection of the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.

Optionally, the respective first loop surrounds a window region in the array substrate, wherein an accessory is installed in the window region.

In another aspect, the present disclosure provides an array substrate, comprising a second reset signal network; wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of second loops interconnected together; a respective second loop of the plurality of second loops is connected to two adjacent second reset signal lines of the plurality of second reset signal lines, respectively; a respective second reset signal line of the plurality of second reset signal lines is connected to two second loops, respectively; and the two second loops are in two adjacent rows of subpixels, respectively.

In another aspect, the present disclosure provides a display apparatus, comprising the array substrate described herein, and one or more integrated circuits connected to the array substrate.

BRIEF DESCRIPTION OF THE FIGURES

The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present invention.

FIG. 1 is a plan view of an array substrate in some embodiments according to the present disclosure.

FIG. 2A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure.

FIG. 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

FIG. 3A is a diagram illustrating the structure of pixel driving circuits in an array substrate in some embodiments according to the present disclosure.

FIG. 3B is a schematic diagram illustrating an arrangement of pixel driving circuits in the array substrate depicted in FIG. 3A.

FIG. 3C is a diagram illustrating the structure of a first semiconductor material layer in the array substrate depicted in FIG. 3A.

FIG. 3D is a diagram illustrating the structure of a first gate metal layer in the array substrate depicted in FIG. 3A.

FIG. 3E is a diagram illustrating the structure of a second gate metal layer in the array substrate depicted in FIG. 3A.

FIG. 3F is a diagram illustrating vias extending through a first inter-layer dielectric layer in the array substrate depicted in FIG. 3A.

FIG. 3G is a diagram illustrating the structure of a second semiconductor material layer in the array substrate depicted in FIG. 3A.

FIG. 3H is a diagram illustrating vias extending through a second inter-layer dielectric layer in the array substrate depicted in FIG. 3A.

FIG. 3I is a diagram illustrating the structure of a third gate metal layer in the array substrate depicted in FIG. 3A.

FIG. 3J is a diagram illustrating vias extending through a passivation layer in the array substrate depicted in FIG. 3A.

FIG. 3K is a diagram illustrating the structure of a first signal line layer in the array substrate depicted in FIG. 3A.

FIG. 3L is a diagram illustrating vias extending through a first planarization layer in the array substrate depicted in FIG. 3A.

FIG. 3M is a diagram illustrating the structure of a second signal line layer in the array substrate depicted in FIG. 3A.

FIG. 3N is a diagram illustrating vias extending through a second planarization layer in the array substrate depicted in FIG. 3A.

FIG. 3O is a diagram illustrating the structure of an anode layer in the array substrate depicted in FIG. 3A.

FIG. 3P is a diagram illustrating a superimposed structure of FIG. 3C to FIG. 3M.

FIG. 3Q is a diagram illustrating a superimposed structure of FIG. 3C to FIG. 3K.

FIG. 4 is a cross-sectional view along an A-A’ line in FIG. 3A.

FIG. 5 is a diagram illustrating a first reset signal network in an array substrate in some embodiments according to the present disclosure.

FIG. 6 is a diagram illustrating a second reset signal network in an array substrate in some embodiments according to the present disclosure.

FIG. 7 is a diagram illustrating a plurality of first reset signal lines and a plurality of data lines in an array substrate in some embodiments according to the present disclosure.

FIG. 8A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure.

FIG. 8B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

DETAILED DESCRIPTION

The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of some embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

The present disclosure provides, inter alia, an array substrate and a display apparatus that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a first reset signal network. Optionally, the first reset signal network comprises a plurality of first reset signal lines and a plurality of first loops interconnected together. Optionally, a respective first loop of the plurality of first loops is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively. Optionally, a respective first reset signal line of the plurality of first reset signal lines is connected to two first loops, respectively. Optionally, the two first loops are in two adjacent rows of subpixels, respectively.

Various appropriate pixel driving circuits may be used in the present array substrate. Examples of appropriate driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, the respective one of the plurality of pixel driving circuits is an 8T1C driving circuit. Various appropriate light emitting elements may be used in the present array substrate. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.

FIG. 1 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 1, the array substrate includes an array of subpixels Sp. Each subpixel includes an electronic component, e.g., a light emitting element. In one example, the light emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of voltage supply line Vdd, and a respective second voltage supply line (e.g., a low voltage supply line Vss) . Light emission in a respective subpixel Sp is driven by a respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input, through the respective high voltage supply line of the plurality of voltage supply line Vdd, to the respective pixel driving circuit PDC connected to an anode of the light emitting element; a low voltage signal (e.g., a VSS signal) is input, through a low voltage supply line, to a cathode of the light emitting element. A voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV that drives light emission in the light emitting element.

FIG. 2A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 2A, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate electrode connected to a respective second reset control signal line rst2 of a plurality of second reset control signal lines, a first electrode connected to a respective second reset signal line Vint2 of a plurality of second reset signal lines, and a second electrode connected to a first electrode of a third reset transistor Tr3; the third reset transistor Tr3 having a gate electrode connected to a respective second gate line of a plurality of second gate lines GL2, a first electrode connected to the second electrode of the second reset transistor Tr2, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate electrode connected to a respective first gate line GL1 of a plurality of first gate lines, a first electrode connected to a respective data line DL of a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a second transistor T2 having a gate electrode connected to the respective second gate line GL2 of the plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate electrode of the driving transistor Td; a third transistor T3 having a gate electrode connected to a respective light emitting control signal line em of a plurality of light emitting control signal lines, a first electrode connected to a respective voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate electrode connected to the respective second reset control signal line rst2 of the plurality of second reset control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to an anode of a light emitting element LE; and a first reset transistor Tr1 having a gate electrode connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the respective voltage supply line and the first electrode of the third transistor T3.

As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. A direction of a current flowing through the transistor may be configured to be from a first electrode to a second electrode, or from a second electrode to a first electrode. Accordingly, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

The pixel driving circuit further include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the third reset transistor Tr3. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.

The array substrate in some embodiments includes a plurality of subpixels. In some embodiments, the plurality of subpixels includes a respective first subpixel, a respective second subpixel, a respective third subpixel, and a respective fourth subpixel. Optionally, a respective pixel of the array substrate includes the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel. The plurality of subpixels in the array substrate are arranged in an array. In one example, the array of the plurality of subpixels includes a S1-S2-S3-S4 format repeating array, in which S1 stands for the respective first subpixel, S2 stands for the respective second subpixel, S3 stands for the respective third subpixel, and S4 stands for the respective fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C4 stands for the respective fourth subpixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2’ format, in which C1 stands for the respective first subpixel of a first color, C2 stands for the respective second subpixel of a second color, C3 stands for the respective third subpixel of a third color, and C2’ stands for the respective fourth subpixel of the second color. In another example, the C1-C2- C3-C2’ format is an R-G-B-G format, in which the respective first subpixel is a red subpixel, the respective second subpixel is a green subpixel, the respective third subpixel is a blue subpixel, and the respective fourth subpixel is a green subpixel.

In some embodiments, a minimum repeating unit of the plurality of subpixels of the array substrate includes the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel. Optionally, each of the respective first subpixel, the respective second subpixel, the respective third subpixel, and the respective fourth subpixel, includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td.

The present disclosure may be implemented in pixel driving circuit having transistors of various types, including a pixel driving circuit having p-type transistors, a pixel driving circuit having n-type transistors, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to FIG. 2A, the second transistor T2 and the fourth transistor T4 are n-type transistors such as metal oxide transistors, and other transistors are p-type transistors such as polysilicon transistors. For a p-type transistor, an effective control signal (e.g., a turn-on control signal) is a low voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, an effective control signal (e.g., a turn-on control signal) is a high voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a low voltage signal.

In some embodiments, the pixel driving circuit includes a driving transistor Td, a data write transistor (e.g., the first transistor T1) , a compensating transistor (e.g., the second transistor T2) , two light emitting control transistors (e.g., the third transistor T3 and the fourth transistor T4) , and three reset transistors (e.g., the first reset transistor Tr1, the second reset transistor Tr2, and the third reset transistor Tr3) .

FIG. 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 2A and FIG. 2B, during one frame of image, the operation of the pixel driving circuit includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4, a fifth sub-phase, a sixth sub-phase t6, and a seventh sub-phase t7.

In the first sub-phase t1, a turning-on reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn on the first reset transistor Tr1; allowing an initialization voltage signal from the respective first reset signal line Vint1 to pass from a first electrode of the first reset transistor Tr1 to a second electrode of the first reset transistor Tr1; and in turn to the fourth node N4. The anode of the light emitting element LE is initialized. A turning-on reset control signal is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the second reset transistor Tr2 to turn on the second reset transistor Tr2; a turning-on control signal, with respect to the third reset transistor Tr3, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the third reset transistor Tr3 to turn on the third reset transistor Tr3; allowing an initialization voltage signal from the respective second reset signal line Vint2 of the plurality of second reset signal lines to pass through the second reset transistor Tr2 and the third reset transistor Tr3; and in turn to the third node N3. The second electrode of the driving transistor Td is initialized. In the first sub-phase t1, a turning-off control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2. In the first sub-phase t1, a turning-off reset control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn off the fourth transistor T4.

In the second sub-phase t2, a turning-on reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn on the first reset transistor Tr1; a turning-on reset control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn on the fourth transistor T4; a turning-on control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn on the second transistor T2; allowing an initialization voltage signal from the respective first reset signal line Vint1 to pass through the first reset transistor Tr1, the fourth transistor T4, and the second transistor T2; and in turn to the first capacitor electrode Ce1 and the gate electrode of the driving transistor Td. The gate electrode of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the respective voltage supply line Vdd. The first capacitor electrode Ce1 is charged in the second sub-phase t2 due to an increasing voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. In the second sub-phase t2, the respective first gate line GL1 of the plurality of first gate lines is provided with a turning-off signal, thus the first transistor T1 is turned off. The respective light emitting control signal line em of the plurality of light emitting control signal lines is provided with a high voltage signal to turn off the third transistor T3.

In the third sub-phase t3, a turning-off control signal is provided through the respective first gate line GL1 of the plurality of first gate lines to the gate electrode of the first transistor T1 to turn off the first transistor T1; a turning-off control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2; a turning-off reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn off the first reset transistor Tr1; and a turning-off reset control signal, with respect to the second reset transistor Tr2, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2.

In the fourth sub-phase t4, a turning-on control signal is provided through the respective first gate line GL1 of the plurality of first gate lines to the gate electrode of the first transistor T1 to turn on the first transistor T1; a turning-on control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn on the second transistor T2; a turning-off control signal, with respect to the third reset transistor Tr3, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the third reset transistor Tr3 to turn off the third reset transistor Tr3. A second electrode of the driving transistor Td is connected with the first electrode of the second transistor T2. A gate electrode of the driving transistor Td is electrically connected with the second electrode of the second transistor T2. Because the second transistor T2 is turned on in the fourth sub-phase t4, the gate electrode and the second electrode of the driving transistor Td are connected and short circuited, and only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, thus rendering the driving transistor Td in a diode connecting mode. The first transistor T1 is turned on in the fourth sub-phase t4. The data voltage signal transmitted through the respective data line DL is received by a first electrode of the first transistor T1, and in turn transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. A second node N2 connecting to the first electrode of the driving transistor Td has a voltage level of the data voltage signal. Because only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, the voltage level at the first node N1 in the fourth sub-phase t4 increase gradually to (Vdata + Vth) , wherein the Vdata is the voltage level of the data voltage signal, and the Vth is the voltage level of the threshold voltage Th of the PN junction. The storage capacitor Cst is discharged because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value. In the fourth sub-phase t4, the respective light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3. In the fourth sub-phase t4, a turning-off reset control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn off the fourth transistor T4.

In the fifth sub-phase t5, a turning-off control signal is provided through the respective first gate line GL1 of the plurality of first gate lines to the gate electrode of the first transistor T1 to turn off the first transistor T1.

The sixth sub-phase t6 is an on-bias sub-phase serving as a stabilization period where no significant signal changes occur, ensuring that the circuit maintains its state before the light emission. In the sixth sub-phase t6, a turning-off control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2.

In the seventh sub-phase t7, the turning-off reset control signal is again provided through the respective second reset control signal line rst2 to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2. The respective first gate line GL1 is provided with a turning-off signal, the first transistor T1 is turned off. In the seventh sub-phase t7, a turning-off control signal, with respect to the second transistor T2, is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2. The respective light emitting control signal line em of the plurality of light emitting control signal line is provided with a low voltage signal to turn on the third transistor T3. A turning-on control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn on the fourth transistor T4. The voltage level at the first node N1 in the seventh sub-phase t7 is maintained at (Vdata + Vth) , the driving transistor Td is turned on by the voltage level, and working in the saturation area. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. A voltage level at a third node N3 connected to the second electrode of the driving transistor Td equals to a light emitting voltage of the light emitting element LE.

FIG. 3A is a diagram illustrating the structure of pixel driving circuits in an array substrate in some embodiments according to the present disclosure. FIG. 3B is a schematic diagram illustrating an arrangement of pixel driving circuits in the array substrate depicted in FIG. 3A. FIG. 3C is a diagram illustrating the structure of a first semiconductor material layer in the array substrate depicted in FIG. 3A. FIG. 3D is a diagram illustrating the structure of a first gate metal layer in the array substrate depicted in FIG. 3A. FIG. 3E is a diagram illustrating the structure of a second gate metal layer in the array substrate depicted in FIG. 3A. FIG. 3F is a diagram illustrating vias extending through a first inter-layer dielectric layer in the array substrate depicted in FIG. 3A. FIG. 3G is a diagram illustrating the structure of a second semiconductor material layer in the array substrate depicted in FIG. 3A. FIG. 3H is a diagram illustrating vias extending through a second inter-layer dielectric layer in the array substrate depicted in FIG. 3A. FIG. 3I is a diagram illustrating the structure of a third gate metal layer in the array substrate depicted in FIG. 3A. FIG. 3J is a diagram illustrating vias extending through a passivation layer in the array substrate depicted in FIG. 3A. FIG. 3K is a diagram illustrating the structure of a first signal line layer in the array substrate depicted in FIG. 3A. FIG. 3L is a diagram illustrating vias extending through a first planarization layer in the array substrate depicted in FIG. 3A. FIG. 3M is a diagram illustrating the structure of a second signal line layer in the array substrate depicted in FIG. 3A. FIG. 3N is a diagram illustrating vias extending through a second planarization layer in the array substrate depicted in FIG. 3A. FIG. 3O is a diagram illustrating the structure of an anode layer in the array substrate depicted in FIG. 3A. FIG. 3P is a diagram illustrating a superimposed structure of FIG. 3C to FIG. 3M. FIG. 3Q is a diagram illustrating a superimposed structure of FIG. 3C to FIG. 3K. FIG. 4 is a cross-sectional view along an A-A’ line in FIG. 3A. FIG. 3A to FIG. 3Q depicts a portion of the array substrate having four pixel driving circuits, including PDC1, PDC2, PDC3, and PDC4.

Referring to FIG. 3A to FIG. 3Q, and FIG. 4, the array substrate in some embodiments includes a base substrate BS, a buffer layer BUF on the base substrate BS, a first semiconductor material layer SML1 on a side of the buffer layer BUF away from the base substrate BS, a gate insulating layer GI on a side of the first semiconductor material layer SML1 away from the base substrate BS, a first gate metal layer Gate1 on a side of the gate insulating layer GI away from the first semiconductor material layer SML1, an insulating layer IN on a side of the first gate metal layer Gate1 away from the gate insulating layer GI, a second gate metal layer Gate2 on a side of the insulating layer IN away from the first gate metal layer Gate1, a first inter-layer dielectric layer ILD1 on a side of the second gate metal layer Gate2 away from the insulating layer IN, a second semiconductor material layer SML2 on a side of the first inter-layer dielectric layer ILD1 away from the second gate metal layer Gate2, a second inter-layer dielectric layer ILD2 on a side of the second semiconductor material layer SML2 away from the first inter-layer dielectric layer ILD1, a third gate metal layer Gate3 on a side of the second inter-layer dielectric layer ILD2 away from the second semiconductor material layer SML2, a passivation layer PVX on a side of the third gate metal layer Gate3 away from the second inter-layer dielectric layer ILD2, a first signal line layer SD1 on a side of the passivation layer PVX away from the third gate metal layer Gate3, a first planarization layer PLN1 on a side of the first signal line layer SD1 away from the passivation layer PVX, a second signal line layer SD2 on a side of the first planarization layer PLN1 away from the first signal line layer SD1, a second planarization layer PLN2 on a side of the second signal line layer SD2 away from the first planarization layer PLN1, and an anode layer ADL on a side of the second planarization layer PLN2 away from the second signal line layer SD2.

Referring to FIG. 2A, FIG. 3A, FIG. 3C, and FIG. 4, the first semiconductor material layer SML1 in some embodiments includes at least active layers of multiple transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least respective portions of first electrodes of multiple transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least respective portions of second electrodes of multiple transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 includes active layers, first electrodes, and second electrodes of multiple transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the first reset transistor Tr1, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Various appropriate semiconductor materials may be used for making the first semiconductor material layer SML1. Examples of the semiconductor materials for making the first semiconductor material layer SML1 include silicon-based semiconductor materials such as polycrystalline silicon, single-crystal silicon, and amorphous silicon.

In FIG. 3C, a pixel driving circuit corresponding to PDC2 in FIG. 3B is annotated with labels indicating components of each of multiple transistors (T1, T3, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

Optionally, the active layers (ACT1, ACT3, ACTr1, ACTr2, ACTr3, and ACTd) , the first electrodes (S1, S3, Sr1, Sr2, Sr3, and Sd) , and the second electrodes (D1, D3, Dr1, Dr2, Dr3, and Dd) of the respective transistors (T1, T3, Tr1, Tr2, Tr3, and Td) are in a same layer.

Referring to FIG. 2A, FIG. 3A, FIG. 3D, and FIG. 4, the first gate metal layer Gate1 in some embodiments includes a plurality of first gate lines (e.g., a respective first gate line GL1) , a plurality of light emitting control signal lines (e.g., a respective light emitting control signal line em) , at least portions of a plurality of second gate lines (e.g., a respective second gate line first branch GL2-1) , a plurality of first reset control signal lines (e.g., a respective first reset control signal line rst1) , at least portions of a plurality of second reset control signal lines (e.g., a respective second reset control signal line first branch rst2-1) , and a first capacitor electrode Ce1 of the storage capacitor Cst. Various appropriate electrode materials and various appropriate fabricating methods may be used to make the first gate metal layer Gate1. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of first gate lines, the plurality of light emitting control signal lines, at least portions of the plurality of second gate lines, the plurality of first reset control signal lines, at least portions of the plurality of second reset control signal lines, and the first capacitor electrode Ce1 are in a same layer.

As used herein, the term “same layer” refers to the relationship between the layers simultaneously formed in the same step. In one example, the plurality of first gate lines and the first capacitor electrode Ce1 are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a same layer of material. In another example, the plurality of first gate lines and the first capacitor electrode Ce1 can be formed in a same layer by simultaneously performing the step of forming the plurality of first gate lines, and the step of forming the first capacitor electrode Ce1. The term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

Referring to FIG. 2A, FIG. 3A, FIG. 3E, and FIG. 4, the second gate metal layer Gate2 in some embodiments includes at least portions of a plurality of second gate lines (e.g., a respective second gate line second branch GL2-2) , at least portions of a plurality of second reset control signal lines (e.g., a respective second reset control signal line second branch rst2-2) , and a second capacitor electrode Ce2 of the storage capacitor Cst. Various appropriate electrode materials and various appropriate fabricating methods may be used to make the second gate metal layer Gate2. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the respective second gate line second branch GL2-2, the respective second reset control signal line second branch rst2-2, and the second capacitor electrode are in a same layer.

In some embodiments, in a hole region H, a portion of the second capacitor electrode Ce2 is absent. Optionally, an orthographic projection of the second capacitor electrode Ce2 on a base substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers, with a margin, an orthographic projection of the first capacitor electrode Ce1 on the base substrate BS except for the hole region H in which a portion of the second capacitor electrode Ce2 is absent. Optionally, the first via v1 extends through the passivation layer PVX, the second inter-layer dielectric layer ILD2, the first inter-layer dielectric layer ILD1, the hole region H, and the insulating layer IN.

Vias extending through the first inter-layer dielectric layer ILD1 are depicted in FIG. 3F.

Referring to FIG. 2A, FIG. 3A, FIG. 3G, and FIG. 4, the second semiconductor material layer SML2 in some embodiments includes at least an active layer of the second transistor T2 and at least an active layer of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a first electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a second electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a first electrode of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a second electrode of the fourth transistor T4. Optionally, the second semiconductor material layer SML2 includes the active layer, the first electrode, and the second electrode of the second transistor T2. Optionally, the second semiconductor material layer SML2 includes the active layer, the first electrode, and the second electrode of the fourth transistor T4. In the present array substrate, at least the active layers of the second transistor T2 and the fourth transistor T4 are in a layer different from at least the active layers of other transistors of the pixel driving circuit. Various appropriate semiconductor materials may be used for making the second semiconductor material layer SML2. Examples of the semiconductor materials for making the second semiconductor material layer SML2 include metal oxide-based semiconductor material such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.

In FIG. 3G, a pixel driving circuit corresponding to PDC2 in FIG. 3B is annotated with labels indicating components of the second transistor T2 and the fourth transistor T4 in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2; and the fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are in a same layer. Optionally, the active layer ACT4, the first electrode S4, and the second electrode D4 of the fourth transistor T4 are in a same layer.

Vias extending through the second inter-layer dielectric layer ILD2 are depicted in FIG. 3H.

Referring to FIG. 2A, FIG. 3A, FIG. 3I, and FIG. 4, the third gate metal layer Gate3 in some embodiments includes at least portions of a plurality of second gate lines (e.g., a respective second gate line third branch GL2-3) , at least portions of a plurality of second reset control signal lines (e.g., a respective second reset control signal line third branch rst2-3) , a plurality of first loops (e.g., a respective first loop LP1) , and a plurality of second loops (e.g., a respective second loop LP2) . Various appropriate electrode materials and various appropriate fabricating methods may be used to make the third gate metal layer Gate3. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like.

Vias extending through the passivation layer PVX are depicted in FIG. 3J.

Referring to FIG. 2A, FIG. 3A, FIG. 3K, and FIG. 4, the first signal line layer SD1 in some embodiments includes a plurality of first reset signal lines (e.g., a respective first reset signal line Vint1) , a plurality of second reset signal lines (e.g., a respective second reset signal line Vint2) , a first node connecting line Cln1, a third node connecting line Cln3, a fourth node connecting line Cln4, a voltage connecting pad VCP, and a data connecting pad DCP. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the first signal line layer SD1. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of first reset signal lines, the plurality of second reset signal lines, the first node connecting line Cln1, the third node connecting line Cln3, the fourth node connecting line Cln4, the voltage connecting pad VCP, and the data connecting pad DCP are in a same layer.

In some embodiments, the respective first reset signal line includes a plurality of first branches (e.g., a respective first branch BR1) . In some embodiments, the respective second reset signal line includes a plurality of second branches (e.g., a respective second branch BR2) .

In some embodiments, the first node connecting line Cln1 is connected to the first capacitor electrode Ce1, and is connected to the second electrode D2 of the second transistor T2.

In some embodiments, the third node connecting line Cln3 is connected to the first electrode S2 of the second transistor T2 through a first via v1, is connected to the second electrode Dr3 of the third reset transistor Tr3 through a second via v2, and is connected to the second electrode Dd of the driving transistor Td through a third via v3. Optionally, the first via v1 extends through the passivation layer PVX and the second inter-layer dielectric layer ILD2. Optionally, the second via v2 extends through the passivation layer PVX, the second inter-layer dielectric layer ILD2, the first inter-layer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. Optionally, the third via v3 extends through the passivation layer PVX, the second inter-layer dielectric layer ILD2, the first inter-layer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

In some embodiments, the third node connecting line Cln3 crosses over the respective first gate line GL1 and the respective second gate line. In some embodiments, the third node connecting line Cln3 crosses over the respective first gate line GL1, the respective second gate line first branch GL2-1, the respective second gate line second branch GL2-2, and the respective second gate line third branch GL2-3. In some embodiments, an orthographic projection of the third node connecting line Cln3 on a base substrate BS partially overlaps with an orthographic projection of the respective first gate line GL1 on the base substrate BS, partially overlaps with an orthographic projection of the respective second gate line first branch GL2-1 on the base substrate BS, partially overlaps with an orthographic projection of the respective second gate line second branch GL2-2 on the base substrate BS, and partially overlaps with an orthographic projection of the respective second gate line third branch GL2-3 on the base substrate BS.

In some embodiments, the fourth node connecting line Cln4 is connected to the second electrode Dr1 of the first reset transistor Tr1, and is connected to the second electrode D4 of the fourth transistor T4.

Vias extending through the first planarization layer PLN1 are depicted in FIG. 3L.

Referring to FIG. 2A, FIG. 3A, FIG. 3M, and FIG. 4, the second signal line layer SD2 in some embodiments includes a plurality of voltage supply lines (e.g., the respective voltage supply line Vdd) and a plurality of data lines (e.g., the respective data line DL) , and an anode contact pad ACP. Various appropriate conductive materials and various appropriate fabricating methods may be used to make the second signal line layer SD2. For example, a conductive material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate conductive materials for making the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, and the like. Optionally, the plurality of voltage supply lines (e.g., the respective voltage supply line Vdd) , the plurality of data lines (e.g., the respective data line DL) , and the anode contact pad ACP are in a same layer.

In some embodiments, the respective second gate line GL2 includes multiple branches in different layers, respectively. In some embodiments, the respective second gate line GL2 includes the respective second gate line first branch GL2-1, the respective second gate line second branch GL2-2, and the respective second gate line third branch GL2-3 in three different layers. Optionally, the respective second gate line first branch GL2-1 is in the first gate metal layer Gate1, the respective second gate line second branch GL2-2 is in the second gate metal layer Gate2, and the respective second gate line third branch GL2-3 is in the third gate metal layer Gate3. In some embodiments, an orthographic projection of the respective second gate line first branch GL2-1 on a base substrate BS at least partially overlaps with an orthographic projection of the respective second gate line second branch GL2-2 on the base substrate BS, and at least partially overlaps with an orthographic projection of the respective second gate line third branch GL2-3 on the base substrate BS. Optionally, the respective second gate line first branch GL2-1, the respective second gate line second branch GL2-2, and the respective second gate line third branch GL2-3 are configured to be provided with a same gate scanning signal.

In some embodiments, the respective second reset control signal line rst2 includes multiple branches in different layers, respectively. In some embodiments, the respective second reset control signal line rst2 includes the respective second reset control signal line first branch rst2-1, the respective second reset control signal line second branch rst2-2, and the respective second reset control signal line third branch rst2-3. Optionally, the respective second reset control signal line first branch rst2-1 is in the first gate metal layer Gate1, the respective second reset control signal line second branch rst2-2 is in the second gate metal layer Gate2, and the respective second reset control signal line third branch rst2-3 is in the third gate metal layer Gate3. In some embodiments, an orthographic projection of the respective second reset control signal line first branch rst2-1 on a base substrate BS at least partially overlaps with an orthographic projection of the respective second reset control signal line second branch rst2-2 on the base substrate BS, and at least partially overlaps with an orthographic projection of the respective second reset control signal line third branch rst2-3 on the base substrate BS. Optionally, the respective second reset control signal line first branch rst2-1, the respective second reset control signal line second branch rst2-2, and the respective second reset control signal line third branch rst2-3 are configured to be provided with a same reset control signal.

FIG. 5 is a diagram illustrating a first reset signal network in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 3A to FIG. 3Q, FIG. 4, and FIG. 5, the array substrate in some embodiments includes a first reset signal network. In some embodiments, the first reset signal network includes a plurality of first reset signal lines and a plurality of first loops interconnected together. In some embodiments, a respective first loop LP1 of the plurality of first loops is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively. In some embodiments, a respective first reset signal line Vint1 of the plurality of first reset signal lines is connected to two first loops, respectively, wherein the two first loops are in two adjacent rows of subpixels, respectively.

In some embodiments, the respective first reset signal line Vint1 includes a first main body MB1 and a plurality of first branches connected to the first main body MB1. In some embodiments, the first main body MB1 extends along a first direction DR1, a respective first branch BR1 of the plurality of first branches extends along a second direction DR2, the first direction DR1 and the second direction DR2 are different from each other. In one particular example, the first direction DR1 is perpendicular to the second direction DR2. In some embodiments, the respective first branch BR1 is connected to two first loops, respectively, wherein the two first loops are in two adjacent rows of subpixels, respectively.

In some embodiments, the respective first loop LP1 surrounds a window region in the array substrate, wherein an accessory is installed in the window region. Examples of accessories include a photosensor, a fingerprint sensor, and a camera.

In some embodiments, the plurality of first loops are in the third gate metal layer Gate3, and the plurality of first reset signal lines are in the first signal line layer SL1. In some embodiments, the respective first reset signal line Vint1 is connected to the respective first loop LP1 through a via extending through the passivation layer PVX.

In some embodiments, first electrodes of two first reset transistors in two adjacent pixel driving circuits in a same row (e.g., PDC1 and PDC2 in FIG. 3B, or PDC3 and PDC4 in FIG. 3B) are parts of a unitary structure. In some embodiments, the respective first reset signal line Vint1 is connected to the unitary structure comprising the first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row through a first single via sv1. Optionally, the first single via sv1 extends through the passivation layer PVX, the second inter-layer dielectric layer IL2, the first inter-layer dielectric layer IL1, the insulating layer IN, and the gate insulating layer GI.

In some embodiments, the unitary structure further includes active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row. In some embodiments, the unitary structure further includes second electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row.

In some embodiments, an orthographic projection of the respective first reset signal line Vint1 on a base substrate BS at least partially overlaps with an orthographic projection of the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate BS.

The inventors of the present disclosure discover that the structure of the first reset signal network can achieve a symmetric layout, a more uniform electrical environment, and a more planarized anode layer.

In some embodiments, an orthographic projection of the respective first branch BR1 on a base substrate BS spaces apart orthographic projections of two adjacent unitary structures from two adjacent pixel driving circuits on the base substrate BS, wherein a respective unitary structure of the two adjacent unitary structures includes at least portions of the second electrode D1 of the first transistor T1, the second electrode D3 of the third transistor T3, and the first electrode Sd of the driving transistor Td. The inventors of the present disclosure discover that the structure of the first reset signal network can effectively prevent interference between the two adjacent unitary structures from the two adjacent pixel driving circuits. In some embodiments, the respective unitary structure of the two adjacent unitary structures corresponds to the second node N2.

FIG. 6 is a diagram illustrating a second reset signal network in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 3A to FIG. 3Q, FIG. 4, and FIG. 6, the array substrate in some embodiments includes a second reset signal network. In some embodiments, the second reset signal network includes a plurality of second reset signal lines and a plurality of second loops interconnected together. In some embodiments, a respective second loop LP2 of the plurality of second loops is connected to two adjacent second reset signal lines of the plurality of second reset signal lines, respectively. In some embodiments, a respective second reset signal line Vint2 of the plurality of second reset signal lines is connected to two second loops, respectively, wherein the two second loops are in two adjacent rows of subpixels, respectively.

In some embodiments, the respective second reset signal line Vint2 includes a second main body MB2 and a plurality of second branches connected to the second main body MB2. In some embodiments, the second main body MB2 extends along a first direction DR1, a respective second branch BR2 of the plurality of second branches extends along a second direction DR2, the first direction DR1 and the second direction DR2 are different from each other. In one particular example, the first direction DR1 is perpendicular to the second direction DR2. In some embodiments, the respective second branch BR2 is connected to two second loops, respectively, wherein the two second loops are in two adjacent rows of subpixels, respectively.

In some embodiments, the plurality of second loops are in the third gate metal layer Gate3, and the plurality of second reset signal lines are in the first signal line layer SL1. In some embodiments, the respective second reset signal line Vint2 is connected to the respective second loop LP2 through a via extending through the passivation layer PVX.

In some embodiments, first electrodes of two second reset transistors in two adjacent pixel driving circuits in a same row (e.g., PDC1 and PDC2 in FIG. 3B, or PDC3 and PDC4 in FIG. 3B) are parts of a unitary structure. In some embodiments, the respective second reset signal line Vint2 is connected to the unitary structure comprising the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row through a second single via sv2. Optionally, the second single via sv2 extends through the passivation layer PVX, the second inter-layer dielectric layer IL2, the first inter-layer dielectric layer IL1, the insulating layer IN, and the gate insulating layer GI.

In some embodiments, the unitary structure further includes active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row. In some embodiments, the unitary structure further includes second electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row.

In some embodiments, an orthographic projection of the respective second reset signal line Vint2 on a base substrate BS at least partially overlaps with an orthographic projection of the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate BS.

The inventors of the present disclosure discover that the structure of the second reset signal network can achieve a symmetric layout, a more uniform electrical environment, and a more planarized anode layer.

In some embodiments, an orthographic projection of the respective second branch BR2 on a base substrate BS spaces apart orthographic projections of two adjacent third node connecting lines (e.g., Cln3) from two adjacent pixel driving circuits on the base substrate BS. The inventors of the present disclosure discover that the structure of the second reset signal network can effectively prevent interference between the two adjacent third node connecting lines from the two adjacent pixel driving circuits. In some embodiments, the respective third node connecting line of the two adjacent third node connecting lines corresponds to the third node N3.

FIG. 7 is a diagram illustrating a plurality of first reset signal lines and a plurality of data lines in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 7, in some embodiments, an orthographic projection of the respective first branch BR1 on a base substrate BS spaces apart orthographic projections of two adjacent data lines of the plurality of data lines on the base substrate BS. The inventors of the present disclosure discover that the layout can effectively prevent interference between the two adjacent data lines.

Referring to FIG. 3Q, FIG. 3K, and FIG. 3C, second electrodes of the third reset transistor Tr3 and the driving transistor Td are in the semiconductor material layer SML, and the second electrodes of the third reset transistor Tr3 and the driving transistor Td are spaced apart from each other in the semiconductor material layer SML. In some embodiments, the array substrate further includes a third node connecting line Cln3 in a layer different from the second electrodes of the third reset transistor Tr3 and the driving transistor Td. In some embodiments, the third node connecting line Cln3 is connected to the second electrode Dr3 of the third reset transistor Tr3, and is connected to the second electrode Dd of the driving transistor Td, thereby electrically connecting the second electrodes of the third reset transistor Tr3 and the driving transistor Td. In one example, the third node connecting line Cln3 is in the first signal line layer.

In some embodiments, the third node connecting line Cln3 crosses over the respective first gate line GL1 of the plurality of first gate lines. In some embodiments, an orthographic projection of the third node connecting line Cln3 on a base substrate partially overlaps with an orthographic projection of the respective first gate line GL1 on the base substrate.

In some embodiments, the third node connecting line Cln3 further crosses over the respective second gate line. In some embodiments, the third node connecting line Cln3 further crosses over the respective second gate line first branch GL2-1, the respective second gate line second branch GL2-2, and the respective second gate line third branch GL2-3. In some embodiments, an orthographic projection of the third node connecting line Cln3 on a base substrate partially overlaps with an orthographic projection of the respective second gate line on the base substrate. In some embodiments, an orthographic projection of the third node connecting line Cln3 on a base substrate partially overlaps with an orthographic projection of the respective second gate line first branch GL2-1 on the base substrate, partially overlaps with an orthographic projection of the respective second gate line second branch GL2-2 on the base substrate, and partially overlaps with an orthographic projection of the respective second gate line third branch GL2-3 on the base substrate.

Various alternative implementations may be practiced in the present disclosure. FIG. 8A is a circuit diagram illustrating the structure of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 8A, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate electrode connected to a respective second reset control signal line rst2 of a plurality of second reset control signal lines, a first electrode connected to a respective second reset signal line Vint2 of a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate electrode connected to a respective first gate line GL1 of a plurality of first gate lines, a first electrode connected to a respective data line DL of a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a second transistor T2 having a gate electrode connected to a respective second gate line GL2 of a plurality of second gate lines, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate electrode of the driving transistor Td; a third transistor T3 having a gate electrode connected to a respective light emitting control signal line em of a plurality of light emitting control signal lines, a first electrode connected to a respective voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate electrode connected to the second reset control signal line rst2 of the plurality of second reset control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to an anode of a light emitting element LE; a first reset transistor Tr1 having a gate electrode connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE; and a third reset transistor Tr3 having a gate electrode connected to a respective third reset control signal line rst3 of a plurality of third reset control signal lines, a first electrode connected to a respective third reset signal line of a plurality of third reset signal lines, and a second electrode connected to the first electrode of the second transistor T2, the second electrode of the driving transistor Td, and the second electrode of the second reset transistor Tr2, and the first electrode of the fourth transistor T4. The second capacitor electrode Ce2 is connected to the respective voltage supply line and the first electrode of the third transistor T3.

The pixel driving circuit further include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the third reset transistor Tr3, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.

The present disclosure may be implemented in pixel driving circuit having transistors of various types, including a pixel driving circuit having p-type transistors, a pixel driving circuit having n-type transistors, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to FIG. 8A, the second transistor T2 and the fourth transistor T4 are n-type transistors such as metal oxide transistors, and other transistors are p-type transistors such as polysilicon transistors. For a p-type transistor, an effective control signal (e.g., a turn-on control signal) is a low voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, an effective control signal (e.g., a turn-on control signal) is a high voltage signal, and an ineffective control signal (e.g., a turn-off control signal) is a low voltage signal.

FIG. 8B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 8A and FIG. 8B, during one frame of image, the operation of the pixel driving circuit includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4, a fifth sub-phase, a sixth sub-phase t6, and a seventh sub-phase t7.

In the first sub-phase t1, a turning-on reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn on the first reset transistor Tr1; allowing an initialization voltage signal from the respective first reset signal line Vint1 to pass from a first electrode of the first reset transistor Tr1to a second electrode of the first reset transistor Tr1; and in turn to the fourth node N4. The anode of the light emitting element LE is initialized. A turning-on reset control signal is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the second reset transistor Tr2 to turn on the second reset transistor Tr2; allowing an initialization voltage signal from the respective second reset signal line Vint2 of the plurality of second reset signal lines to pass through the second reset transistor Tr2; and in turn to the second node N2. The second electrode of the driving transistor Td is initialized. In the first sub-phase t1, a turning-off control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2. In the first sub-phase t1, a turning-off reset control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn off the fourth transistor T4. In the first sub-phase t1, a turning-off control signal is provided through the respective third reset control signal line of the plurality of third reset control signal lines to the gate electrode of the third reset transistor Tr3 to turn off the third reset transistor Tr3.

In the second sub-phase t2, a turning-on reset control signal is provided through the respective third reset control signal line rst3 of the plurality of third reset control signal lines to the gate electrode of the third reset transistor Tr3 to turn on the third reset transistor Tr3; allowing an initialization voltage signal from the respective third reset signal line Vint3 to pass through the third reset transistor Tr3; and in turn to the third node N3. The second electrode of the driving transistor Td is initialized. In the second sub-phase t2, a turning-on control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn on the second transistor T2, allowing an initialization voltage signal from the respective third reset signal line Vint3 to pass through the third reset transistor Tr3 and the second transistor T2; and in turn to the first capacitor electrode Ce1 and the gate electrode of the driving transistor Td. The gate electrode of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the respective voltage supply line Vdd. The first capacitor electrode Ce1 is charged in the second sub-phase t2 due to an increasing voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. In the second sub-phase t2, the respective first gate line GL1 of the plurality of first gate lines is provided with a turning-off signal, thus the first transistor T1 is turned off. The respective light emitting control signal line em of the plurality of light emitting control signal lines is provided with a high voltage signal to turn off the third transistor T3. In the second sub-phase t2, a turning-off reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn off the first reset transistor Tr1; a turning-on reset control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn on the fourth transistor T4.

In the third sub-phase t3, a turning-off control signal is provided through the respective first gate line GL1 of the plurality of first gate lines to the gate electrode of the first transistor T1 to turn off the first transistor T1; a turning-off control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2; a turning-off reset control signal is provided through the respective first reset control signal line rst1 of the plurality of first reset control signal lines to the gate electrode of the first reset transistor Tr1 to turn off the first reset transistor Tr1; a turning-off reset control signal is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2; and a turning-off control signal is provided through the respective third reset control signal line of the plurality of third reset control signal lines to the gate electrode of the third reset transistor Tr3 to turn off the third reset transistor Tr3.

In the fourth sub-phase t4, a turning-on control signal is provided through the respective first gate line GL1 of the plurality of first gate lines to the gate electrode of the first transistor T1 to turn on the first transistor T1; a turning-on control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn on the second transistor T2; a turning-off control signal is provided through the respective third reset control signal line of the plurality of third reset control signal lines to the gate electrode of the third reset transistor Tr3 to turn off the third reset transistor Tr3. A second electrode of the driving transistor Td is connected with the first electrode of the second transistor T2. A gate electrode of the driving transistor Td is electrically connected with the second electrode of the second transistor T2. Because the second transistor T2 is turned on in the fourth sub-phase t4, the gate electrode and the second electrode of the driving transistor Td are connected and short circuited, and only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, thus rendering the driving transistor Td in a diode connecting mode. The first transistor T1 is turned on in the fourth sub-phase t4. The data voltage signal transmitted through the respective data line DL is received by a first electrode of the first transistor T1, and in turn transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. A second node N2 connecting to the first electrode of the driving transistor Td has a voltage level of the data voltage signal. Because only the PN junction between the gate electrode and a first electrode of the driving transistor Td is effective, the voltage level at the first node N1 in the fourth sub-phase t4 increase gradually to (Vdata + Vth) , wherein the Vdata is the voltage level of the data voltage signal, and the Vth is the voltage level of the threshold voltage Th of the PN junction. The storage capacitor Cst is discharged because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value. In the fourth sub-phase t4, the respective light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3. In the fourth sub-phase t4, a turning-off reset control signal, with respect to the second reset transistor Tr2, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2.

The sixth sub-phase t6 is an on-bias sub-phase serving as a stabilization period where no significant signal changes occur, ensuring that the circuit maintains its state before the light emission. In the sixth sub-phase t6, a turning-off control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2.

In the seventh sub-phase t7, the turning-off reset control signal is again provided through the respective second reset control signal line rst2 to the gate electrode of the second reset transistor Tr2 to turn off the second reset transistor Tr2. The respective first gate line GL1 is provided with a turning-off signal, the first transistor T1 is turned off. In the seventh sub-phase t7, a turning-off control signal is provided through the respective second gate line GL2 of the plurality of second gate lines to the gate electrode of the second transistor T2 to turn off the second transistor T2. The respective light emitting control signal line em of the plurality of light emitting control signal line is provided with a low voltage signal to turn on the third transistor T3. A turning-on control signal, with respect to the fourth transistor T4, is provided through the respective second reset control signal line rst2 of the plurality of second reset control signal lines to the gate electrode of the fourth transistor T4 to turn on the fourth transistor T4. The voltage level at the first node N1 in the seventh sub-phase t7 is maintained at (Vdata + Vth) , the driving transistor Td is turned on by the voltage level, and working in the saturation area. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. A voltage level at a third node N3 connected to the second electrode of the driving transistor Td equals to a light emitting voltage of the light emitting element LE.

Referring to FIG. 3A to FIG. 3Q, in some embodiments, corresponding layers of a first pixel driving circuit and corresponding layers of a second pixel driving circuit directly adjacent to each other and in the present stage (e.g., in a same row) have a substantially mirror symmetry with respect to each other, e.g., about a plane perpendicular to a main surface of the array substrate and substantially parallel to the data lines in FIG. 3A. As used herein, the term “corresponding layers of a first pixel driving circuit and corresponding layers of a second pixel driving circuit” is not intended to include layers that are not parts of the pixel driving circuits. For example, the term “corresponding layers of a first pixel driving circuit and corresponding layers of a second pixel driving circuit” do not include an anode layer or a pixel definition layer. In one example, the term “corresponding layers of a first pixel driving circuit and corresponding layers of a second pixel driving circuit” refers to conductive layers of the first pixel driving circuit and conductive layers of a second pixel driving circuit. In one specific example, “corresponding layers” include at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, “corresponding layers” further includes at least one of a gate insulating layer, an insulating layer, a first inter-layer dielectric layer, a second inter-layer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer.

In another aspect, the present invention provides a display apparatus, including the array substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the array substrate.

Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the display apparatus is an organic light emitting diode display apparatus. Optionally, the display apparatus is a liquid crystal display apparatus.

In another aspect, the present invention provides a method of fabricating an array substrate. In some embodiments, the method includes forming a first reset signal network. In some embodiments, forming the first reset signal network includes forming a plurality of first reset signal lines and a plurality of first loops interconnected together. A respective first loop of the plurality of first loops is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively. A respective first reset signal line of the plurality of first reset signal lines is connected to two first loops, respectively. The two first loops are in two adjacent rows of subpixels, respectively.

The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention” , “the present invention” or the like does not necessarily limit the claim scope to a specific embodiment, and the reference to exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Moreover, these claims may refer to use “first” , “second” , etc. following with noun or element. Such terms should be understood as a nomenclature and should not be construed as giving the limitation on the number of the elements modified by such nomenclature unless specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.

Claims

An array substrate, comprising a first reset signal network;

wherein the first reset signal network comprises a plurality of first reset signal lines and a plurality of first loops interconnected together;

a respective first loop of the plurality of first loops is connected to two adjacent first reset signal lines of the plurality of first reset signal lines, respectively;

a respective first reset signal line of the plurality of first reset signal lines is connected to two first loops, respectively;

the two first loops are in two adjacent rows of subpixels, respectively.
The array substrate of claim 1, wherein the respective first reset signal line comprises a first main body and a plurality of first branches connected to the first main body;

the first main body extends along a first direction;

a respective first branch of the plurality of first branches extends along a second direction;

the first direction and the second direction are different from each other; and

the respective first branch is connected to two first loops, respectively.
The array substrate of claim 1, wherein the plurality of first loops are in a layer different from the plurality of first reset signal lines; and

the respective first reset signal line is connected to the respective first loop through a via extending through at least one layer comprising an insulating material.
The array substrate of claim 1, wherein the plurality of first loops are in a third gate metal layer;

the plurality of first reset signal lines are in a first signal line layer; and

the respective first reset signal line is connected to the respective first loop through a via extending through a passivation layer.
The array substrate of any one of claims 1 to 4, comprising a plurality of pixel driving circuits;

wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a first reset transistor;

first electrodes of two first reset transistors in two adjacent pixel driving circuits in a same row are parts of a unitary structure; and

the respective first reset signal line is connected to the unitary structure comprising the first electrodes of the two first reset transistors in the two adjacent pixel driving circuits in the same row through a first single via.
The array substrate of claim 5, wherein the unitary structure further comprises active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row; and

an orthographic projection of the respective first reset signal line on a base substrate at least partially overlaps with an orthographic projection of the active layers of the two first reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.
The array substrate of claim 2, comprising a plurality of pixel driving circuits;

wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a data write transistor, a compensating transistor, a first light emitting control transistor, and a driving transistor;

an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent unitary structures from two adjacent pixel driving circuits on the base substrate; and

a respective unitary structure of the two adjacent unitary structures comprises at least portions of a second electrode of the data write transistor, a second electrode of the first light emitting control transistor, and a first electrode of the driving transistor.
The array substrate of claim 2, comprising a plurality of pixel driving circuits;

wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a compensating transistor, a driving transistor, a third reset transistor, and a third node connecting line;

the third node connecting line is connected to a first electrode of the compensating transistor through a first via, is connected to a second electrode of the third reset transistor through a second via, and is connected to a second electrode of the driving transistor through a third via.
The array substrate of claim 8, wherein an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent third node connecting lines from two adjacent pixel driving circuits on the base substrate.
The array substrate of claim 8, further comprising a plurality of first gate lines;

wherein an orthographic projection of the third node connecting line on a base substrate partially overlaps with an orthographic projection of the respective first gate line on the base substrate.
The array substrate of claim 10, further comprising a plurality of second gate lines;

wherein the orthographic projection of the third node connecting line on the base substrate partially overlaps with an orthographic projection of the respective second gate line on the base substrate.
The array substrate of claim 2, further comprising a plurality of data lines;

wherein an orthographic projection of the respective first branch on a base substrate spaces apart orthographic projections of two adjacent data lines of the plurality of data lines on the base substrate.
The array substrate of any one of claims 1 to 12, further comprising a second reset signal network;

wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of second loops interconnected together;

a respective second loop of the plurality of second loops is connected to two adjacent second reset signal lines of the plurality of second reset signal lines, respectively;

a respective second reset signal line of the plurality of second reset signal lines is connected to two second loops, respectively; and

the two second loops are in two adjacent rows of subpixels, respectively.
The array substrate of claim 13, wherein the respective second reset signal line comprises a second main body and a plurality of second branches connected to the second main body;

the second main body extends along a first direction;

a respective second branch of the plurality of second branches extends along a second direction;

the first direction and the second direction are different from each other; and

the respective second branch is connected to two second loops, respectively.
The array substrate of claim 13, wherein the plurality of second loops are in a layer different from the plurality of second reset signal lines; and

the respective second reset signal line is connected to the respective second loop through a via extending through at least one layer comprising an insulating material.
The array substrate of claim 13, wherein the plurality of second loops are in a third gate metal layer;

the plurality of second reset signal lines are in a first signal line layer; and

the respective second reset signal line is connected to the respective second loop through a via extending through a passivation layer.
The array substrate of any one of claims 13 to 16, comprising a plurality of pixel driving circuits;

wherein a respective pixel driving circuit of the plurality of pixel driving circuit comprises a second reset transistor;

first electrodes of two second reset transistors in two adjacent pixel driving circuits in a same row are parts of a unitary structure; and

the respective second reset signal line is connected to the unitary structure comprising the first electrodes of the two second reset transistors in the two adjacent pixel driving circuits in the same row through a second single via.
The array substrate of claim 17, wherein the unitary structure further comprises active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row; and

an orthographic projection of the respective second reset signal line on a base substrate at least partially overlaps with an orthographic projection of the active layers of the two second reset transistors in the two adjacent pixel driving circuits in the same row on the base substrate.
The array substrate of any one of claims 1 to 17, wherein the respective first loop surrounds a window region in the array substrate, wherein an accessory is installed in the window region.
An array substrate, comprising a second reset signal network;

wherein the second reset signal network comprises a plurality of second reset signal lines and a plurality of second loops interconnected together;

a respective second loop of the plurality of second loops is connected to two adjacent second reset signal lines of the plurality of second reset signal lines, respectively;

a respective second reset signal line of the plurality of second reset signal lines is connected to two second loops, respectively; and

the two second loops are in two adjacent rows of subpixels, respectively.
A display apparatus, comprising the array substrate of any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.