WO2025067366A1 - 用于管理加速器的方法、装置、设备和存储介质 - Google Patents

用于管理加速器的方法、装置、设备和存储介质 Download PDF

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Publication number
WO2025067366A1
WO2025067366A1 PCT/CN2024/121559 CN2024121559W WO2025067366A1 WO 2025067366 A1 WO2025067366 A1 WO 2025067366A1 CN 2024121559 W CN2024121559 W CN 2024121559W WO 2025067366 A1 WO2025067366 A1 WO 2025067366A1
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Prior art keywords
accelerators
accelerator
computing device
interface information
group
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English (en)
French (fr)
Inventor
张精义
陈响亮
谢钱军
鞠文龙
葛士建
张永肃
彭亮
张宇
王剑
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Beijing Zitiao Network Technology Co Ltd
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Beijing Zitiao Network Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • Example embodiments of the present disclosure generally relate to the field of computers, and more particularly to methods, devices, apparatuses, and computer-readable storage media for managing accelerators.
  • processors need to be extremely efficient when handling complex data analysis, machine learning, and deep learning tasks, so it is expected that processors can be configured in a more efficient way.
  • a method for managing an accelerator comprises: obtaining interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; using a driver of the computing device to initialize the group of accelerators according to the interface information; and using at least a portion of the initialized group of accelerators to perform a task.
  • a device for managing accelerators includes: an interface information acquisition module configured to acquire interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of a group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; an accelerator initialization module configured to use a driver of the computing device to initialize the group of accelerators according to the interface information; and a task execution module configured to use at least a portion of the initialized group of accelerators to execute a task.
  • an electronic device in a third aspect of the present disclosure, includes at least one processing unit; and at least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When the instructions are executed by the at least one processing unit, the device executes the method of the first aspect.
  • a computer-readable storage medium is provided.
  • a computer program is stored thereon, and the computer program can be executed by a processor to implement the method of the first aspect.
  • FIG1 is a schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented.
  • FIG2 shows a schematic diagram of an example architecture of a processing unit including an accelerator according to some embodiments of the present disclosure
  • FIG3 is a schematic diagram showing an example mapping relationship between an accelerator and other hardware resources according to some embodiments of the present disclosure
  • FIG4 is a schematic diagram showing an example of interface information according to some embodiments of the present disclosure.
  • FIG5 shows a schematic diagram of an example for managing an accelerator according to some embodiments of the present disclosure
  • FIG6 shows a flowchart of a method for managing an accelerator according to some embodiments of the present disclosure
  • FIG. 7 shows a block diagram of an apparatus for managing an accelerator according to some embodiments of the present disclosure.
  • FIG8 shows a block diagram of a device capable of implementing various embodiments of the present disclosure.
  • a prompt message is sent to the user to clearly prompt the user that the operation requested to be performed will require obtaining and using the user's personal information.
  • the user can autonomously choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.
  • the prompt information in response to receiving an active request from the user, may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form.
  • the pop-up window may also carry a selection control for the user to select "agree” or “disagree” to provide personal information to the electronic device.
  • the term "in response to” as used herein refers to a state in which a corresponding event occurs or a condition is satisfied. It will be understood that the timing of executing a subsequent action executed in response to the event or condition is not necessarily strongly related to the time when the event occurs or the condition is satisfied. For example, in some cases, the subsequent action may be executed immediately when the event occurs or the condition is satisfied; while in other cases, the subsequent action may be executed some time after the event occurs or the condition is satisfied.
  • a graphics processing unit can work more efficiently than a central processing unit (CPU) in graphics rendering.
  • a tensor processing unit (TPU) designed for deep learning tasks can significantly increase the speed of machine learning model training and reasoning.
  • accelerators supported by application platforms usually have programmable features, allowing developers to customize and optimize them as needed. Therefore, accelerators become an important solution to meet application needs.
  • interface information associated with a group of accelerators in a computing device is obtained.
  • the interface information at least indicates the corresponding identification information and corresponding mapping information of these accelerators.
  • the mapping information of each accelerator indicates the hardware resources used for the accelerator in the computing device, such as an address translation unit, an interrupt service unit, etc.
  • the driver of the computing device then initializes the group of accelerators according to the interface information, for example, enumerates these accelerators. Furthermore, in subsequent business processing, at least a part of this group of initialized accelerators is used to perform tasks according to actual needs.
  • the accelerator is used as a platform device, and PCIe enumeration is not required, but the enumeration of the accelerator is completed by the driver. In this way, the configuration flexibility and utilization rate of the accelerator can be improved.
  • a computing device 110 includes hardware for performing computing-related tasks.
  • a computing device 110 is, for example, a personal computer, a server, a mobile device, and the like.
  • the computing device 110 includes one or more accelerators 130, such as accelerator 130-1, accelerator 130-2, ... accelerator 130-N, etc. These accelerators may be individually or collectively referred to as accelerators 130. Such accelerators 130 may be utilized to increase the execution speed of a particular type of task (such as graphics processing, machine learning, etc.) or a particular type of data.
  • accelerators 130 such as accelerator 130-1, accelerator 130-2, ... accelerator 130-N, etc.
  • These accelerators may be individually or collectively referred to as accelerators 130.
  • Such accelerators 130 may be utilized to increase the execution speed of a particular type of task (such as graphics processing, machine learning, etc.) or a particular type of data.
  • the operating system 120 may be software running on the computing device 110 for allocating resources to applications running on the computing device 110. Furthermore, the operating system 120 may utilize the computing device 110 to perform tasks, and may also utilize the accelerator 130 to accelerate specific types of tasks or specific types of data.
  • the architecture 200 may include multiple processing units, such as processing unit 210-1, processing unit 210-2, ... processing unit 210-X, etc. These processing units may be referred to as processing units 210 individually or collectively.
  • Each processing unit 210 may include multiple processing cores, such as processing core 220-1, processing core 220-2, ... processing core 220-Y, etc. These processing cores may be individually or collectively referred to as processing cores 220. As a basic component of processing unit 210, processing core 220 may execute various instructions and coordinate system resources in a coordinated or independent manner. Processing core 220 may run multiple threads or processes simultaneously and share certain resources such as cache, registers, etc.
  • Each processing unit 210 may also include a system memory management unit (SMMU) 230.
  • the SMMU 230 may be used for address translation between the interface device and the bus, memory attribute translation, permission checking, etc.
  • Each processing unit 210 may further include an accelerator 130.
  • the accelerator 130 may include multiple acceleration units, such as an acceleration unit 250-1, an acceleration unit 250-2, ..., an acceleration unit 250-Z, etc. These acceleration units may be individually or collectively referred to as acceleration units 250.
  • An accelerator 130 including multiple acceleration units 250 is also referred to as a first accelerator.
  • an accelerator 130 can be regarded as an independent platform device, as a parent device of multiple acceleration units 250 attached to it. Therefore, unified acceleration unit resource management, device overall error handling and recovery and other operational support can be provided for the accelerator.
  • one acceleration unit 250 can be regarded as an independent platform device, or a combination of multiple acceleration units 250 can be regarded as a platform device.
  • one or more acceleration units 250 can be used as a sub-device attached to an accelerator 130.
  • each processing unit 210 is shown as including the same number of processing cores and acceleration units, these processing units 210 may respectively include any appropriate number of processing cores and acceleration units, or may only include an appropriate number of processing cores and one accelerator, and the present disclosure is not limited to this.
  • mapping relationship 300 shows a schematic diagram of an example mapping relationship 300 between an accelerator and other hardware resources according to some embodiments of the present disclosure.
  • the mapping relationship 300 generally involves the accelerator 130, the SMMU 230, and the interrupt controller 320.
  • the accelerator 130, the SMMU 230 and the interrupt controller 320 can be regarded as hardware resources available to the accelerator 130 in the computing device 110.
  • the accelerator 130 is mounted to the bus 310 through the SMMU 230.
  • the SMMU 310 is used to achieve security isolation between the accelerators 130 or between the multiple acceleration units 250 contained in each accelerator 130.
  • the SMMU 310 can assign a stream ID (Stream ID, SID) to each attached or mounted accelerator 130.
  • the SID can be used to identify different accelerators 130, thereby achieving security isolation between accelerators.
  • the SMMU 310 can also assign a substream ID (SubStream ID, SSID) to each attached or mounted acceleration unit 250.
  • the SSID can be used to identify different acceleration units 250, thereby achieving isolation of process address space.
  • the SMMU 230 may convert the stream identifier into a device identifier (device ID) recognizable by the interrupt controller 320, and communicate with the interrupt controller 320 through the bus 310.
  • the interrupt controller 320 is used to manage and distribute interrupt signals generated by hardware devices. For example, the accelerator 130 or the acceleration unit 250 triggers an interrupt signal, and such an interrupt signal is sent to the interrupt controller 320 via the SMMU 230.
  • the interrupt controller 320 provides an interrupt translation service (ITS) so that the operating system 120 can determine which accelerator 130 or which acceleration unit 250 the interrupt signal is triggered by, and then execute the corresponding interrupt handler.
  • ITS interrupt translation service
  • the above describes an example architecture for managing accelerators from a hardware level.
  • the example architecture 200 and the example mapping relationship 300 may be implemented in the environment 100.
  • the operating system 120 may obtain interface information associated with a set of accelerators 130 in the computing device 110.
  • Such interface information may include corresponding identification information of a set of accelerators 130, and may also include corresponding mapping information.
  • the mapping information of each accelerator 130 may indicate the hardware resources used for the accelerator in the computing device 110, such as indicating the SMMU and ITS used for the accelerator.
  • the interface information may be reported by the firmware to the operating system 120.
  • the firmware may report the interface information used by the accelerator 130 to the operating system 120.
  • the interface information may include a description table and a mapping table to help the operating system 120 identify the accelerator and determine the hardware resources for the accelerator.
  • Figure 4 shows a schematic diagram of an example 400 of interface information according to some embodiments of the present disclosure.
  • Example 400 may include at least one of a mapping table 410, a description table 420 (also referred to as a first description table), or a description table 430 (also referred to as a second description table).
  • the mapping table 410 indicates the hardware resources for each accelerator in the computing device 110, such as SMMU, interrupt translation services provided by the interrupt controller, etc.
  • the mapping table 410 includes an ITS node 412, an SMMU node 414, and a component node 416.
  • the component node 416 indicates the mapping relationship between the accelerator 130 (for example, accelerator 1, accelerator 2, accelerator 3, etc. shown in Figure 4) and the SMMU and ITS.
  • the SMMU node 414 indicates the SMMU hardware information in the computing device 110
  • the ITS node 416 indicates the ITS-related hardware information in the computing device 110.
  • the mapping table 410 can be, for example, an input-output remapping table (IORT).
  • the description table 420 includes a set of corresponding hardware identifiers (HIDs) and corresponding register addresses of the accelerator 130 to ensure that the operating system can normally access the registers of the accelerator 130.
  • a description table 420 may include, for example, a differentiated system description table (DSDT).
  • DSDT differentiated system description table
  • ACPI Advanced Configuration and Power Interface
  • the DSDT supports matching the defined and described hardware identifiers to the corresponding accelerators.
  • a hardware identifier is a unique identification symbol used to mark and distinguish a hardware device, also known as a hardware identifier, which usually includes a set of numbers and letters. Generally speaking, a hardware identifier is assigned to each device by a device manufacturer during the manufacturing process. However, the ACPI specification does not describe an accelerator 130 that is considered a platform device.
  • a set of hardware identifiers of accelerators can be customized to ensure that the operating system 120 can identify and run the accelerators.
  • the accelerator 130 includes three types of accelerators, such as CDA accelerators, DTE accelerators, and DLA accelerators.
  • CDA accelerators their hardware identifiers are, for example, BCDA0000, BCDA0001, BCDA0002, etc.
  • DTE accelerators their hardware identifiers are, for example, BDTE0000, BDTE0001, BDTE0002, etc.
  • DLA accelerators their hardware identifiers are, for example, DBLA0000, DBLA0001, DBLA002, etc. In this way, it is possible to use the accelerator as a platform device and assign a hardware identifier to it.
  • one or some of the accelerators 130 may include multiple acceleration units 250, or multiple acceleration units of the first accelerator may need to be exposed to the operating system as platform devices.
  • the description table 420 may include a hardware identifier of the first accelerator and a register address corresponding to the first accelerator, and may also include register addresses corresponding to each acceleration unit.
  • the acceleration unit it is possible to use the acceleration unit as a sub-device and assign a register address to it. In this way, flexible configuration of the acceleration unit can be achieved.
  • the description table 430 includes corresponding identifiers of hardware resources for a group of accelerators 130 in the computing device 110 to ensure that the group of accelerators 130 can normally access the interrupt controller.
  • a description table 420 includes, for example, an Advanced Programmable Interrupt Controller Description Table (MADT).
  • MADT includes The relevant information of the interrupt controller, such as the ITS index shown in Figure 4, ITS0, ITS1, ITS2, etc.
  • FIG5 shows a schematic diagram of an example 500 for managing accelerators according to some embodiments of the present disclosure.
  • the firmware side reports interface information associated with the accelerator, such as IORT, MADT, DSDT, etc. in ACPI shown in FIG4.
  • the driver side matches the accelerator according to the reported interface information and performs accelerator enumeration. That is, the driver side searches for all available accelerators in the computing device 110 and performs hardware enablement on the found accelerators.
  • the user side uses at least a portion of the enumerated accelerators to perform specific tasks, such as parallel computing tasks. Depending on the specific implementation, the user side may use one or more of the enumerated accelerators, or one or more acceleration units.
  • the accelerator or acceleration unit can be used as an independent device.
  • one or more acceleration units can be allocated to a virtual machine for use. Referring to FIG. 2 , for a processing unit 210, the operating system 120 can also allocate a first number of processing cores 220 and a second number of acceleration units 250 therein to a virtual machine, and perform tasks through the virtual machine. In this way, the flexibility of using the acceleration unit in different application scenarios can be achieved.
  • the operating system 120 can use the SMMU 230 to assign an SSID to each acceleration unit 250.
  • an appropriate number of processing cores 220 and an appropriate number of acceleration units 250 are bound for use, for example, four processing cores 220 and four acceleration units 250 are assigned to one virtual machine.
  • the operating system 120 can also dynamically configure the first number and the second number. Additionally or alternatively, the first number of processing cores 220 and the second number of acceleration units 250 can also be used as an independent device in non-virtualization deployment.
  • the computing device 110 is based on an advanced reduced instruction set architecture, and as shown in FIG2 , the computing device 110 may include multiple processing units 210, which may further include a group of accelerators 130. In this way, the requirements for the computing power, energy efficiency, and power consumption of the advanced reduced instruction set architecture, as well as the diversified application scenarios and the requirements for programmability can be met.
  • the present disclosure proposes to use the accelerator as a platform device and define its hardware identification. Furthermore, according to the interface information associated with the accelerator obtained, the driver can be used to complete the initialization of the accelerator and use the initialized accelerator to perform tasks.
  • the accelerator management solution for non-PCIe bus standards can be implemented without PCIe bus enumeration. In this way, the configuration flexibility and utilization rate of the accelerator can be improved.
  • FIG. 6 shows a flow chart of a method 600 for managing an accelerator according to some embodiments of the present disclosure.
  • the method 600 may be implemented at the operating system 120.
  • the method 600 is described below with reference to FIG. 1 .
  • the operating system 120 obtains interface information associated with a set of accelerators in the computing device.
  • the interface information indicates at least corresponding identification information and corresponding mapping information of a set of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device.
  • the operating system 120 utilizes a driver of the computing device to initialize a set of accelerators according to the interface information.
  • the operating system 120 utilizes at least a portion of the initialized set of accelerators to execute a task.
  • the interface information is reported by firmware to an operating system of the computing device.
  • the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.
  • At least a first accelerator in a group of accelerators includes multiple acceleration units
  • the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to multiple acceleration units respectively.
  • the at least one hardware resource includes at least one of: a system memory management unit, or an interrupt translation service.
  • initializing a group of accelerators includes: using a driver to set corresponding sharing modes of a plurality of acceleration units, wherein the sharing mode of an acceleration unit indicates whether the acceleration unit is shared by a plurality of processes.
  • the computing device is based on an advanced reduced instruction set architecture, and a set of accelerators is included in a processing unit of the computing device.
  • FIG. 7 shows a schematic structural block diagram of an apparatus 700 for managing an accelerator according to some embodiments of the present disclosure.
  • the apparatus 700 may be implemented as or included in the operating system 120.
  • Each module/component in the apparatus 700 may be implemented by hardware, software, firmware, or any combination thereof.
  • the apparatus 700 includes an interface information acquisition module 710, which is configured to acquire interface information associated with a group of accelerators in a computing device.
  • the interface information at least indicates corresponding identification information and corresponding mapping information of a group of accelerators, wherein the mapping information of one accelerator indicates the hardware resources used for the accelerator in the computing device.
  • the apparatus 700 also includes an accelerator initialization module 720, which is configured to use a driver of the computing device to initialize a group of accelerators according to the interface information.
  • the apparatus 700 also includes a task execution module 730, which is configured to use at least a part of the initialized group of accelerators to execute a task.
  • the interface information is reported by firmware to an operating system of the computing device.
  • the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.
  • At least a first accelerator in a group of accelerators includes multiple acceleration units
  • the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to multiple acceleration units respectively.
  • the computing device is based on an advanced reduced instruction set architecture, and a set of accelerators is included in a processing unit of the computing device.
  • the computing device includes multiple processing cores, a second accelerator in a group of accelerators includes multiple acceleration units, and the task execution module is also configured to assign a first number of processing cores in the multiple processing cores and a second number of acceleration units in the multiple acceleration units to the virtual machine; and execute the task through the virtual machine.
  • FIG8 shows a block diagram of an electronic device 800 in which one or more embodiments of the present disclosure may be implemented. It should be understood that the electronic device 800 shown in FIG8 is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein. The electronic device 800 shown in FIG8 may be used to implement the operating system 120 of FIG1 .
  • the electronic device 800 is in the form of a general electronic device.
  • the components of the electronic device 800 may include, but are not limited to, one or more processors or processing units 810, a memory 820, a storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860.
  • the processing unit 810 may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 820. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 800.
  • the electronic device 800 typically includes a plurality of computer storage media. Such media may be any accessible media that is accessible to the electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media.
  • the memory 820 may be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof.
  • the storage device 830 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and/or data (e.g., training data for training) and may be accessed within the electronic device 800.
  • a machine-readable medium such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and/or data (e.g., training data for training) and may be accessed within the electronic device 800.
  • the electronic device 800 may further include additional removable/non-removable, volatile/non-volatile storage media.
  • a disk drive for reading or writing from a removable, non-volatile disk e.g., a “floppy disk”
  • an optical drive for reading or writing from a removable, non-volatile optical disk may be provided.
  • each drive may be connected to a bus (not shown) by one or more data media interfaces.
  • the memory 820 may include a computer program product 825 having one or more program modules configured to perform various methods or actions of various embodiments of the present disclosure.
  • the communication unit 840 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 800 can be implemented with a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 800 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.
  • PC network personal computer
  • the input device 850 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc.
  • the output device 860 may be one or more output devices, such as a display, a speaker, a printer, etc.
  • the electronic device 800 may also communicate with one or more external devices (not shown) through the communication unit 840 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 800, or communicate with any device that allows the electronic device 800 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input/output (I/O) interface (not shown).
  • I/O input/output
  • a computer-readable storage medium on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above.
  • a computer program product is also provided, wherein the computer program product is tangibly The method is stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.
  • These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions/actions specified in one or more boxes in the flowchart and/or block diagram is generated.
  • These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and/or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions/actions specified in one or more boxes in the flowchart and/or block diagram.
  • Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions/actions specified in one or more boxes in the flowchart and/or block diagram.
  • each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification.
  • the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved.
  • each square box in the block diagram and/or flow chart, and the combination of the square boxes in the block diagram and/or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

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Abstract

根据本公开的实施例，提供了用于管理加速器的方法、装置、设备和存储介质。用于管理加速器的方法包括获取与计算设备中的一组加速器相关联的接口信息，接口信息至少指示一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示计算设备中用于该加速器的硬件资源；利用计算设备的驱动器，根据接口信息初始化一组加速器；以及利用经初始化的一组加速器的至少一部分来执行任务。以此方式，可以提高加速器的配置灵活性和使用率。

Description

用于管理加速器的方法、装置、设备和存储介质
本申请要求2023年09月27日递交的、申请号为202311270375.5、标题为“用于管理加速器的方法、装置、设备和存储介质”的中国发明专利申请的优先权，该中国专利申请的全部内容通过引用并入本申请中。
技术领域
本公开的示例实施例总体涉及计算机领域，特别地涉及用于管理加速器方法、装置、设备和计算机可读存储介质。
背景技术
随着大数据和人工智能应用的快速发展，对计算能力的需求也大幅增加。例如，处理器在处理复杂的数据分析、机器学习和深度学习等任务时需要具备极高的效率，因而期望可以以更为有效的方式配置处理器。
发明内容
在本公开的第一方面，提供了一种管理加速器的方法。该方法包括：获取与计算设备中的一组加速器相关联的接口信息，接口信息至少指示一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示计算设备中用于该加速器的硬件资源；利用计算设备的驱动器，根据接口信息初始化一组加速器；以及利用经初始化的一组加速器的至少一部分来执行任务。
在本公开的第二方面，提供了一种用于管理加速器的装置。该装置包括：接口信息获取模块，被配置为获取与计算设备中的一组加速器相关联的接口信息，接口信息至少指示一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示计算设备中用于该加速器的硬件资源；加速器初始化模块，被配置为利用计算设备的驱动器，根据接口信息初始化一组加速器；以及任务执行模块，被配置为利用经初始化的一组加速器的至少一部分来执行任务。
在本公开的第三方面，提供了一种电子设备。该设备包括至少一个处理单元；以及至少一个存储器，至少一个存储器被耦合到至少一个处理单元并且存储用于由至少一个处理单元执行的指令。指令在由至少一个处理单元执行时使设备执行第一方面的方法。
在本公开的第四方面，提供了一种计算机可读存储介质。该计算机可读存储介质 上存储有计算机程序，计算机程序可由处理器执行以实现第一方面的方法。
应当理解，本内容部分中所描述的内容并非旨在限定本公开的实施例的关键特征或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的描述而变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了本公开的实施例能够在其中实现的示例环境的示意图；
图2示出了根据本公开的一些实施例的包括加速器的处理单元的一个示例架构的示意图；
图3示出了根据本公开的一些实施例的加速器与其他硬件资源之间的示例映射关系的示意图；
图4示出了根据本公开的一些实施例的接口信息的一个示例的示意图；
图5示出了根据本公开的一些实施例的用于管理加速器的一个示例的示意图；
图6示出了根据本公开的一些实施例的管理加速器的方法的流程图；
图7示出了根据本公开的一些实施例的用于管理加速器的装置的框图；以及
图8示出了能够实施本公开的多个实施例的设备的框图。
具体实施方式
可以理解的是，在使用本公开各实施例公开的技术方案之前，均应当依据相关法律法规通过恰当的方式对本公开所涉及个人信息的类型、使用范围、使用场景等告知用户并获得用户的授权。
例如，在响应于接收到用户的主动请求时，向用户发送提示信息，以明确地提示用户，其请求执行的操作将需要获取和使用到用户的个人信息。从而，使得用户可以根据提示信息来自主地选择是否向执行本公开技术方案的操作的电子设备、应用程序、服务器或存储介质等软件或硬件提供个人信息。
作为一种可选的但非限定性的实现方式，响应于接收到用户的主动请求，向用户发送提示信息的方式例如可以是弹出窗口的方式，弹出窗口中可以以文字的方式呈现提示信息。此外，弹出窗口中还可以承载供用户选择“同意”或者“不同意”向电子设备提供个人信息的选择控件。
可以理解的是，上述通知和获取用户授权过程仅是示意性的，不对本公开的实现方式构成限定，其它满足相关法律法规的方式也可应用于本公开的实现方式中。
可以理解的是，本技术方案所涉及的数据(包括但不限于数据本身、数据的获取 或使用)应当遵循相应法律法规及相关规定的要求。
在此使用的术语“响应于”表示相应的事件发生或者条件得以满足的状态。将会理解，响应于该事件或者条件而被执行的后续动作的执行时机，与该事件发生或者条件成立的时间，二者之间未必是强关联的。例如，在某些情况下，后续动作可在事件发生或者条件成立时立即被执行；而在另一些情况下，后续动作可在事件发生或者条件成立后经过一段时间才被执行。
下面将参照附图更详细地描述本公开的实施例。虽然附图中示出了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反，提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
需要注意的是，本文中所提供的任何节/子节的标题并不是限制性的。本文通篇描述了各种实施例，并且任何类型的实施例都可以包括在任何节/子节下。此外，在任一节/子节中描述的实施例可以以任何方式与同一节/子节和/或不同节/子节中描述的任何其他实施例相结合。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“一些实施例”应当理解为“至少一些实施例”。下文还可能包括其他明确的和隐含的定义。术语“第一”、“第二”等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。
如前文所简要提及的，由于对计算能力的需求与日俱增，传统的通用处理器在处理复杂的数据分析、机器学习和深度学习等任务时可能效率不够高。考虑到通用处理器在处理特定任务时可能会消耗较多的能量，引入专门的加速器可以提供更高的能效和更低的功耗。这对于延长电池寿命、减少热量的产生以及提高设备性能等至关重要。例如，图形处理单元(GPU)可以在图形渲染方面比中央处理单元(CPU)更高效地工作。又例如，针对深度学习任务设计的张量处理单元(TPU)，可以大幅提升机器学习模型训练和推理时候的速度。
此外，一些应用平台支持的加速器通常具有可编程的特性，使得开发人员能够根据需要进行定制和优化。因此，加速器成为满足应用需求的重要的解决方案。
一些加速器设备，例如针对周边组件互连高速(PPCIe)总线标准的加速器设备，可以在X86应用平台上进行配置。然而，针对非PCIe总线标准的加速器设备，如何在一些应用平台例如基于高级精简指令集的平台上进行配置，尚没有通用的解决方案。
为了至少部分地解决上述问题，本公开的实施例提出了一种用于管理加速器的方案。根据本公开的各种实施例，获取与计算设备中的一组加速器相关联的接口信息。 接口信息至少指示这些加速器的相应标识信息和相应映射信息。每个加速器的映射信息指示计算设备中用于该加速器的硬件资源，例如地址转换单元、中断服务单元等。计算设备的驱动器进而根据接口信息初始化这组加速器，例如对这些加速器进行枚举。进一步地，在后续的业务处理中，根据实际需求利用这组经初始化的加速器的至少一部分来执行任务。根据本公开的实施例中，将加速器作为平台设备来使用，不需要PCIe枚举，而是由驱动来完成加速器的枚举。由此，可以提高加速器的配置灵活性和使用率。
下面参考附图来描述本公开的示例实施例。
图1示出了本公开的实施例能够在其中实现的示例环境100的示意图。在环境100中，计算设备110包括用于执行与计算相关的任务的硬件。这样的计算设备110例如为个人计算机、服务器、移动设备等等。
计算设备110包括一个或多个加速器130，例如加速器130-1、加速器130-2……加速器130-N等。这些加速器可以单独地或统称为加速器130。可以利用这样的加速器130来提高特定类型任务(诸如图形处理、机器学习等等)或特定类型数据的执行速度。
操作系统120可以是运行在计算设备110上的软件，用于向计算设备110上运行的应用分配资源。进一步地，操作系统120可以利用计算设备110来执行任务，还可以利用加速器130针对特定类型的任务或特定类型的数据进行加速。
应当理解，仅出于示例性的目的描述环境100的结构和功能，而不暗示对于本公开的范围的任何限制。以下将参考图2和图3从硬件层面来描述用于管理加速器的架构。
图2示出了根据本公开的一些实施例的包括加速器的处理单元的示例架构200的示意图。架构200可以包括多个处理单元，例如处理单元210-1、处理单元210-2……处理单元210-X等。这些处理单元可以单独地或统称为处理单元210。
每个处理单元210可以包括多个处理核，例如处理核220-1、处理核220-2……处理核220-Y等。这些处理核可以单独地或统称为处理核220。处理核220作为处理单元210的基本组成部分，可以协同地或独立地执行各种指令并协调系统资源。处理核220可以同时运行多个线程或进程，并共享某些资源例如缓存、寄存器等。
每个处理单元210还可以包括系统存储器管理单元(SMMU)230。SMMU 230可以用于接口设备与总线之间的地址转换、内存属性转换、权限检查等。
每个处理单元210还可以包括加速器130。在一些实施例中，诸如图2所示，加速器130可以包括多个加速单元，例如加速单元250-1、加速单元250-2……加速单元250-Z等。这些加速单元可以单独地或统称为加速单元250。包含多个加速单元250的加速器130也被称为第一加速器。
在一些实施例中，一个加速器130可以被视为一个独立的平台设备，作为附属于它的多个加速单元250的父设备。由此，针对该加速器可以提供统一的加速单元资源管理、设备整体错误处理和恢复等操作支持。
在一些实施例中，取决于基本输入/输出系统(BIOS)中的设备配置设置以及动态高级配置与电源接口(ACPI)的支持，一个加速单元250可以被视为一个独立的平台设备，或者将多个加速单元250的组合视为一个平台设备。由此，一个或多个加速单元250可以作为一个加速器130附属的子设备。
应当理解，尽管每个处理单元210被示出为包括相同数目的处理核和加速单元，但是这些处理单元210可以分别包括任意适当数目的处理核和加速单元，或者也可以仅包括适当数目的处理核和一个加速器，本公开对此不作限制。
图3示出了根据本公开的一些实施例的加速器与其他硬件资源之间的示例映射关系300的示意图。映射关系300总体上涉及加速器130、SMMU 230以及中断控制器320。针对加速器130而言，SMMU 230和中断控制器320可以视为计算设备110中可用于该加速器130的硬件资源。
加速器130通过SMMU 230挂载到总线310。加速器130之间或者每个加速器130所包含的多个加速单元250之间利用SMMU 310实现安全隔离。例如，SMMU 310可以为所附接或挂载的每个加速器130分配流标识(Stream ID，SID)。由此，可以使用SID识别不同的加速器130，从而实现加速器之间的安全隔离。又例如，SMMU 310还可以为附接或挂载的每个加速单元250分配子流标识(SubStream ID，SSID)。由此，可以使用SSID识别不同的加速单元250，从而实现进程地址空间的隔离。
SMMU 230可以将流标识转换为中断控制器320可识别的设备标识(device ID)，并且通过总线310与中断控制器320进行通信。中断控制器320用于管理和分发硬件设备产生的中断信号。例如，加速器130或加速单元250触发中断信号，这样的中断信号经由SMMU 230发送到中断控制器320。中断控制器320提供中断翻译服务(ITS)，以便于操作系统120确定该中断信号是由哪个加速器130或哪个加速单元250所触发，进而执行相应的中断处理程序。
以上从硬件层面对用于管理加速器的示例架构进行了介绍。示例架构200和示例映射关系300可以实现在环境100中。继续参考图1，操作系统120可以获取与计算设备110中的一组加速器130相关联的接口信息。这样的接口信息可以包括一组加速器130的相应的标识信息，还可以包括相应的映射信息。每个加速器130的映射信息可以指示计算设备110中用于该加速器的硬件资源，例如指示用于该加速器的SMMU和ITS。
在一些实施例中，接口信息可以由固件上报给操作系统120。例如，在加电自检(POST)阶段，固件可以向操作系统120上报加速器130使用的接口信息。
在一些实施例中，接口信息可以包括描述表和映射表，以帮助操作系统120识别加速器和确定用于该加速器的硬件资源。图4示出了根据本公开的一些实施例的接口信息的示例400的示意图。示例400可以包括映射表410、描述表420(也称为第一描述表)或描述表430(也称为第二描述表)中的至少一项。
在一些实施例中，映射表410指示计算设备110中用于每个加速器的硬件资源，例如SMMU、由中断控制器提供的中断翻译服务等。示例性地，映射表410包括ITS节点412、SMMU节点414、组件节点416。在映射表410中，组件节点416指示加速器130(例如，图4所示的加速器1、加速器2、加速器3等)与SMMU、ITS之间的映射关系。通过这样的映射表410，可以保证加速器130在操作系统120中可以正常发起中断，例如线中断和消息信号中断(MSI)。SMMU节点414指示计算设备110中的SMMU硬件信息，ITS节点416指示计算设备110中的ITS相关硬件信息。映射表410例如可以是输入输出重映射表(IORT)。
在一些实施例中，描述表420包括一组加速器130的相应硬件标识(HID)和相应寄存器地址，以保证操作系统可以正常访问的加速器130的寄存器。这样的描述表420例如可以包括区分系统描述表(DSDT)。在高级配置与电源接口(ACPI)规范中，DSDT支持将定义并描述的硬件标识匹配到相应的加速器。
硬件标识是用于标记和区分硬件设备的唯一识别符号，也称为硬件标识符，通常包含一组数字和字母。通常来说，硬件标识是由设备制造商在生产制造过程中分配给每个设备的。然而，ACPI规范中没有针对被视为平台设备的加速器130的描述。
在一些实施例中，可以通过自定义一组加速器的硬件标识来保证操作系统120可以识别、运行加速器。示例性地，加速器130包括三种类型的加速器，诸如CDA加速器、DTE加速器以及DLA加速器等。对于CDA加速器，其硬件标识例如为BCDA0000、BCDA0001、BCDA0002等。对于DTE加速器，其硬件标识例如为BDTE0000、BDTE0001、BDTE0002等。对于DLA加速器，其硬件标识例如为DBLA0000、DBLA0001、DBLA002等。由此，可以实现将加速器作为平台设备并为其分配硬件标识。
在一些实施例中，加速器130中的某个或某些加速器(也称为第一加速器)可以包括多个加速单元250，或者需要将第一加速器的多个加速单元作为平台设备暴露给操作系统。在这种实施例中，描述表420可以包括第一加速器的硬件标识和对应于第一加速器的寄存器地址，还可以包括分别对应于每个加速单元的寄存器地址。由此，可以实现将加速单元作为子设备并为其分配寄存器地址。以此方式，可以实现对加速单元的灵活配置。
在一些实施例中，描述表430包括计算设备110中用于一组加速器130的硬件资源的相应标识，以保证一组加速器130可以正常访问中断控制器。这样的描述表420例如包括高级可编程中断控制器描述表(MADT)。在ACPI规范中，MADT包含中 断控制器的相关信息，例如图4中所示的ITS索引，ITS 0、ITS1、ITS2等。
以上通过多个实施例描述了与一组加速器130相关联的接口信息。在获取到这样的接口信息后，操作系统120可以利用计算设备110的驱动器根据这样的接口信息来初始化一组加速器130。换言之，由驱动器对所上报的加速器及其加速单元(如果适用的话)进行枚举。示例性地，驱动器首先检测计算设备110中的加速器130，然后逐一列举并初始化可用的加速器130。进一步地，操作系统120可以利用经初始化的加速器130来执行任务。示例性地，在初始化加速器130后，操作系统120可以在经初始化的加速器130中选择具有合适的计算架构和编程接口的加速器来执行计算。以下参考图5描述一个具体地示例。
图5示出了根据本公开的一些实施例的用于管理加速器的示例500的示意图。具体地，在框510，固件侧上报与加速器相关联的接口信息，例如图4所示的ACPI中的IORT、MADT、DSDT等。在框520，驱动侧根据上报的接口信息匹配加速器，并进行加速器枚举。亦即，驱动侧在计算设备110中查找所有可用的加速器，并对查找到的加速器执行硬件使能。在框530，用户侧使用所枚举的加速器中的至少一部分执行具体地任务，例如并行计算的任务。取决于具体实现，用户侧可以使用所枚举的加速器中的一个或多个加速器，或者一个或多个加速单元。
在一些实施例中，操作系统120(例如，驱动器)还可以利用驱动器设置加速单元的共享模式。这样的共享模式指示该加速单元是否可以被多个进程共享。以此方式，可以解决加速单元数目限制的问题。
示例性地，操作系统120可以根据需求将一组加速器中的多个加速单元均设置为支持共享模式，使得这些加速单元只可以被多个进程共享使用。这样的多个加速单元可以是附属于一个加速器的加速单元，也可以是附属于不同加速器的加速单元，本公开对此不作限制。又如，固件侧可以在接口信息中上报哪个或哪些加速单元支持共享模式。进而，驱动侧可以根据固件侧的上报来设置共享模式。
在一些实施例中，加速器或加速单元可以作为独立设备来使用。在一些实施例中，某个或某些加速单元可以被分配给虚拟机来使用。参考图2，针对一个处理单元210，操作系统120还可以将其中的第一数目的处理核220和第二数目的加速单元250分配给虚拟机，并且通过该虚拟机来执行任务。以此方式，可以实现不同应用场景下使用加速单元的灵活性。
示例性地，操作系统120可以利用SMMU 230为每个加速单元250分配SSID。在进行虚拟化部署时，将适当数目的处理核220和适当数目的加速单元250绑定使用，例如将四个处理核220和四个加速单元250分配给一个虚拟机。针对不同的应用场景，操作系统120还可以动态配置第一数目和第二数目。附加地或备选地，第一数目的处理核220和第二数目的加速单元250也可以作为非虚拟化部署时的一个独立设备。
在一些实施例中，计算设备110是基于高级精简指令集架构的，并且如图2所示，计算设备110可以包括多个处理单元210，进而可以包含一组加速器130。以此方式，可以满足对高级精简指令集架构的计算能力、能效和功耗的需求，以及多样化的应用场景和对可编程性的要求。
综上所述，本公开提出将加速器作为平台设备使用并定义其硬件标识。进一步地，根据所获取的与加速器相关联的接口信息，可以利用驱动器来完成加速器的初始化并利用经初始化的加速器执行任务。由此，无需PCIe总线枚举即可实现针对非PCIe总线标准的加速器管理方案。以此方式，可以提高加速器的配置灵活性和使用率。
示例过程
图6示出了根据本公开的一些实施例的用于管理加速器的方法600的流程图。方法600可以被实现在操作系统120处。下面参考图1描述方法600。
在框610，操作系统120获取与计算设备中的一组加速器相关联的接口信息。接口信息至少指示一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示计算设备中用于该加速器的硬件资源。
在框620，操作系统120利用计算设备的驱动器，根据接口信息初始化一组加速器。
在框630，操作系统120利用经初始化的一组加速器的至少一部分来执行任务。
在一些实施例中，接口信息是由固件上报给计算设备的操作系统的。
在一些实施例中，接口信息包括以下至少一项：第一描述表，包括一组加速器的相应硬件标识和相应寄存器地址，映射表，针对一组加速器中的每个加速器，映射表指示计算设备中用于该加速器的至少一个硬件资源，或第二描述表，包括计算设备中用于一组加速器的硬件资源的相应标识。
在一些实施例中，一组加速器中的至少第一加速器包括多个加速单元，并且第一描述表包括以下至少任一项：第一加速器的硬件标识，对应于第一加速器的寄存器地址，或分别对应于多个加速单元的寄存器地址。
在一些实施例中，至少一个硬件资源包括以下至少一项：系统存储器管理单元，或中断翻译服务。
在一些实施例中，初始化一组加速器包括：利用驱动器设置多个加速单元的相应共享模式，其中一个加速单元的共享模式指示该加速单元是否被多个进程共享。
在一些实施例中，计算设备是基于高级精简指令集架构的，并且计算设备的处理单元中包括一组加速器。
在一些实施例中，计算设备包括多个处理核，一组加速器中的第二加速器包括多个加速单元，并且执行任务包括：将多个处理核中的第一数目的处理核和多个加速单 元中的第二数目的加速单元分配给虚拟机；以及通过虚拟机来执行任务。
示例装置和设备
图7示出了根据本公开的某些实施例的用于管理加速器的装置700的示意性结构框图。装置700可以被实现为或者被包括在操作系统120中。装置700中的各个模块/组件可以由硬件、软件、固件或者它们的任意组合来实现。
如图所示，装置700包括接口信息获取模块710，被配置为获取与计算设备中的一组加速器相关联的接口信息。接口信息至少指示一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示计算设备中用于该加速器的硬件资源。装置700还包括加速器初始化模块720，被配置为利用计算设备的驱动器，根据接口信息初始化一组加速器。装置700还包括任务执行模块730，被配置为利用经初始化的一组加速器的至少一部分来执行任务。
在一些实施例中，接口信息是由固件上报给计算设备的操作系统的。
在一些实施例中，接口信息包括以下至少一项：第一描述表，包括一组加速器的相应硬件标识和相应寄存器地址，映射表，针对一组加速器中的每个加速器，映射表指示计算设备中用于该加速器的至少一个硬件资源，或第二描述表，包括计算设备中用于一组加速器的硬件资源的相应标识。
在一些实施例中，一组加速器中的至少第一加速器包括多个加速单元，并且第一描述表包括以下至少任一项：第一加速器的硬件标识，对应于第一加速器的寄存器地址，或分别对应于多个加速单元的寄存器地址。
在一些实施例中，至少一个硬件资源包括以下至少一项：系统存储器管理单元，或中断翻译服务。
在一些实施例中，加速器初始化模块720还被配置为利用驱动器设置多个加速单元的相应共享模式，其中一个加速单元的共享模式指示该加速单元是否被多个进程共享。
在一些实施例中，计算设备是基于高级精简指令集架构的，并且计算设备的处理单元中包括一组加速器。
在一些实施例中，计算设备包括多个处理核，一组加速器中的第二加速器包括多个加速单元，并且任务执行模块还被配置为将多个处理核中的第一数目的处理核和多个加速单元中的第二数目的加速单元分配给虚拟机；以及通过虚拟机来执行任务。
图8示出了示出了其中可以实施本公开的一个或多个实施例的电子设备800的框图。应当理解，图8所示出的电子设备800仅仅是示例性的，而不应当构成对本文所描述的实施例的功能和范围的任何限制。图8所示出的电子设备800可以用于实现图1的操作系统120。
如图8所示，电子设备800是通用电子设备的形式。电子设备800的组件可以包括但不限于一个或多个处理器或处理单元810、存储器820、存储设备830、一个或多个通信单元840、一个或多个输入设备850以及一个或多个输出设备860。处理单元810可以是实际或虚拟处理器并且能够根据存储器820中存储的程序来执行各种处理。在多处理器系统中，多个处理单元并行执行计算机可执行指令，以提高电子设备800的并行处理能力。
电子设备800通常包括多个计算机存储介质。这样的介质可以是电子设备800可访问的任何可以获取的介质，包括但不限于易失性和非易失性介质、可拆卸和不可拆卸介质。存储器820可以是易失性存储器(例如寄存器、高速缓存、随机访问存储器(RAM))、非易失性存储器(例如，只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、闪存)或它们的某种组合。存储设备830可以是可拆卸或不可拆卸的介质，并且可以包括机器可读介质，诸如闪存驱动、磁盘或者任何其他介质，其可以能够用于存储信息和/或数据(例如用于训练的训练数据)并且可以在电子设备800内被访问。
电子设备800可以进一步包括另外的可拆卸/不可拆卸、易失性/非易失性存储介质。尽管未在图8中示出，可以提供用于从可拆卸、非易失性磁盘(例如“软盘”)进行读取或写入的磁盘驱动和用于从可拆卸、非易失性光盘进行读取或写入的光盘驱动。在这些情况中，每个驱动可以由一个或多个数据介质接口被连接至总线(未示出)。存储器820可以包括计算机程序产品825，其具有一个或多个程序模块，这些程序模块被配置为执行本公开的各种实施例的各种方法或动作。
通信单元840实现通过通信介质与其他电子设备进行通信。附加地，电子设备800的组件的功能可以以单个计算集群或多个计算机器来实现，这些计算机器能够通过通信连接进行通信。因此，电子设备800可以使用与一个或多个其他服务器、网络个人计算机(PC)或者另一个网络节点的逻辑连接来在联网环境中进行操作。
输入设备850可以是一个或多个输入设备，例如鼠标、键盘、追踪球等。输出设备860可以是一个或多个输出设备，例如显示器、扬声器、打印机等。电子设备800还可以根据需要通过通信单元840与一个或多个外部设备(未示出)进行通信，外部设备诸如存储设备、显示设备等，与一个或多个使得用户与电子设备800交互的设备进行通信，或者与使得电子设备800与一个或多个其他电子设备通信的任何设备(例如，网卡、调制解调器等)进行通信。这样的通信可以经由输入/输出(I/O)接口(未示出)来执行。
根据本公开的示例性实现方式，提供了一种计算机可读存储介质，其上存储有计算机可执行指令，其中计算机可执行指令被处理器执行以实现上文描述的方法。根据本公开的示例性实现方式，还提供了一种计算机程序产品，计算机程序产品被有形地 存储在非瞬态计算机可读介质上并且包括计算机可执行指令，而计算机可执行指令被处理器执行以实现上文描述的方法。
这里参照根据本公开实现的方法、装置、设备和计算机程序产品的流程图和/或框图描述了本公开的各个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机可读程序指令实现。
这些计算机可读程序指令可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理单元，从而生产出一种机器，使得这些指令在通过计算机或其他可编程数据处理装置的处理单元执行时，产生了实现流程图和/或框图中的一个或多个方框中规定的功能/动作的装置。也可以把这些计算机可读程序指令存储在计算机可读存储介质中，这些指令使得计算机、可编程数据处理装置和/或其他设备以特定方式工作，从而，存储有指令的计算机可读介质则包括一个制造品，其包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各个方面的指令。
可以把计算机可读程序指令加载到计算机、其他可编程数据处理装置、或其他设备上，使得在计算机、其他可编程数据处理装置或其他设备上执行一系列操作步骤，以产生计算机实现的过程，从而使得在计算机、其他可编程数据处理装置、或其他设备上执行的指令实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
附图中的流程图和框图显示了根据本公开的多个实现的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
以上已经描述了本公开的各实现，上述说明是示例性的，并非穷尽性的，并且也不限于所公开的各实现。在不偏离所说明的各实现的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实现的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其他普通技术人员能理解本文公开的各个实现方式。

Claims (11)

  1. 一种用于管理加速器的方法，包括：
    获取与计算设备中的一组加速器相关联的接口信息，所述接口信息至少指示所述一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示所述计算设备中用于该加速器的硬件资源；
    利用所述计算设备的驱动器，根据所述接口信息初始化所述一组加速器；以及
    利用经初始化的所述一组加速器的至少一部分来执行任务。
  2. 根据权利要求1所述的方法，其中所述接口信息是由固件上报给所述计算设备的操作系统的。
  3. 根据权利要求1所述的方法，其中所述接口信息包括以下至少一项：
    第一描述表，包括所述一组加速器的相应硬件标识和相应寄存器地址，
    映射表，针对所述一组加速器中的每个加速器，所述映射表指示所述计算设备中用于该加速器的至少一个硬件资源，或
    第二描述表，包括所述计算设备中用于所述一组加速器的硬件资源的相应标识。
  4. 根据权利要求3所述的方法，其中所述一组加速器中的至少第一加速器包括多个加速单元，并且所述第一描述表包括以下至少任一项：
    所述第一加速器的硬件标识，
    对应于所述第一加速器的寄存器地址，或
    分别对应于所述多个加速单元的寄存器地址。
  5. 根据权利要求3所述的方法，其中所述至少一个硬件资源包括以下至少一项：
    系统存储器管理单元，或
    中断翻译服务。
  6. 根据权利要求4所述的方法，其中初始化所述一组加速器包括：
    利用所述驱动器设置所述多个加速单元的相应共享模式，其中一个加速单元的共享模式指示该加速单元是否被多个进程共享。
  7. 根据权利要求1所述的方法，其中所述计算设备是基于高级精简指令集架构的，并且所述计算设备的处理单元中包括所述一组加速器。
  8. 根据权利要求1所述的方法，其中所述计算设备包括多个处理核，所述一组加速器中的第二加速器包括多个加速单元，并且执行所述任务包括：
    将所述多个处理核中的第一数目的处理核和所述多个加速单元中的第二数目的加速单元分配给虚拟机；以及
    通过所述虚拟机来执行所述任务。
  9. 一种用于管理加速器的装置，包括：
    接口信息获取模块，被配置为获取与计算设备中的一组加速器相关联的接口信息，所述接口信息至少指示所述一组加速器的相应标识信息和相应映射信息，其中一个加速器的映射信息指示所述计算设备中用于该加速器的硬件资源；
    加速器初始化模块，被配置为利用所述计算设备的驱动器，根据所述接口信息初始化所述一组加速器；以及
    任务执行模块，被配置为利用经初始化的所述一组加速器的至少一部分来执行任务。
  10. 一种电子设备，包括：
    至少一个处理单元；以及
    至少一个存储器，所述至少一个存储器被耦合到所述至少一个处理单元并且存储用于由所述至少一个处理单元执行的指令，所述指令在由所述至少一个处理单元执行时使所述电子设备执行根据权利要求1至8中任一项所述的方法。
  11. 一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序可由处理器执行以实现根据权利要求1至8中任一项所述的方法。
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