WO2024258445A1 - Electronic devices with substrates less than 50 micrometer thick and methods of manufacture - Google Patents

Electronic devices with substrates less than 50 micrometer thick and methods of manufacture Download PDF

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Publication number
WO2024258445A1
WO2024258445A1 PCT/US2023/083951 US2023083951W WO2024258445A1 WO 2024258445 A1 WO2024258445 A1 WO 2024258445A1 US 2023083951 W US2023083951 W US 2023083951W WO 2024258445 A1 WO2024258445 A1 WO 2024258445A1
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Prior art keywords
wafer
pad
silicon layer
layer
front side
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French (fr)
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ManKit LAM
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Microchip Technology Inc
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Microchip Technology Inc
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Priority claimed from US18/533,252 external-priority patent/US20240421230A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01904—Manufacture or treatment of bond pads using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01908—Manufacture or treatment of bond pads using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills

Definitions

  • the present disclosure relates to field effect transistors, in particular, field effect transistors with substrates less than 50 pm thick so they may have low RDS (on) values and methods to produce field effect transistors with substrates less than 50 pm thick.
  • RDS(on) stands for “drain-source on resistance,” or the total resistance between the drain and source in a metal oxide field effect transistor (MOSFET) when the MOSFET is fully “on.”
  • MOSFET metal oxide field effect transistor
  • the first method is problematic because the thicker periphery sections of the wafer must be cut away after building the vertical MOSFET(s) and the wafer may break into pieces while being cut. There is also a practical limit to how thin the wafer may be ground without breaking during the grinding process. The thicker periphery sections of the wafer are sacrificed, which is a waste of good silicon. Production costs are high because many steps are used to grind and cut the wafer.
  • the second method is problematic because the support material must be removed after building the vertical MOSFET(s) and the wafer may break into pieces while the support material is removed.
  • SUMMARY Aspects provide a process for production of vertical MOSFET devices to attain substrates less than 50 pm thick yielding low RDS(on) values that does not tend to break the wafer into pieces.
  • a method comprising: providing a wafer having a front side and a back side, a metal layer having a gate pad and a source pad at the front side, and a silicon layer at the back side wherein the silicon layer has a pre-process thickness; molding a structural support coating over the gate pad and source pad at the front side of the wafer; back-side processing the wafer to remove a portion of the silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad.
  • An aspect provides the method as in the previous paragraph, wherein the pre-process thickness of the silicon layer is greater than or equal to 700 pm.
  • An aspect provides the method as in any one of the prior two paragraphs, wherein the post-process thickness of the silicon layer is less than or equal to 50 pm.
  • An aspect provides the method as in any one of the prior three paragraphs, wherein the structural support coating comprises polymer.
  • An aspect provides the method as in any one of the prior four paragraphs, wherein the back-side processing comprises grinding and the removing of the structural support coating comprising grinding.
  • An aspect provides the method as in any one of the prior five paragraphs, comprising plating the front side of the wafer to build up the gate pad and source pad.
  • An aspect provides the method as in the prior paragraph, wherein the plating comprises plating with copper (Cu).
  • An aspect provides the method as in any one of the prior seven paragraphs, comprising adding a drain pad layer on the back side of the wafer.
  • An aspect provides the method as in any one of the prior eight paragraphs, comprising plating the front and back sides of the wafer with oxidizing inhibiting layers.
  • An aspect provides the method as in any one of the prior nine paragraphs, comprising singulating the wafer to form individual chips.
  • An aspect provides a field effect transistor comprising: a silicon layer less than 50 microns thick, a source pad on the silicon layer; a gate pad on the silicon layer; and a structural support coating on the silicon layer between the source pad and the gate pad.
  • an electronic device comprising: a silicon layer less than 50 pm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating on the front side between the source pad and the gate pad.
  • An aspect provides the electronic device as in the prior paragraph, wherein the structural support coating comprises polymer.
  • An aspect provides the electronic device as in any one of the prior two paragraphs, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
  • An aspect provides the electronic device as in any one of the prior three paragraphs, comprising a copper (Cu) layer on the gate pad and source pad on the front side of the wafer.
  • Cu copper
  • An aspect provides the electronic device as in any one of the prior four paragraphs, wherein the electronic device has an RDS(on) value less than 10 milliohms.
  • An aspect provides the electronic device as in any one of the prior five paragraphs, comprising a drain pad layer on the back side of the silicon layer.
  • An aspect provides the electronic device as in any one of the prior six paragraphs, comprising oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer.
  • oxidizing inhibiting layers comprise an electroless nickel immersion gold plating.
  • a field effect transistor comprising: a silicon layer less than 50 pm thick and defining a back side of the field effect transistor, a metal layer on the silicon layer, wherein the metal layer defines a front side of the field effect transistor, wherein the metal layer has a source pad and a gate pad; a polymer coating on the front side between the source pad and the gate pad; a copper layer on the source pad and the gate pad; a drain pad layer on the back side of the silicon layer; and oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer, wherein the field effect transistor has an RDS(on) value less than 10 milliohms.
  • An aspect provides the field effect transistor as in the prior paragraph, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
  • the figures illustrate examples of vertical MOSFET devices attaining substrates less than 50 pm thick yielding low RDS(on) values and methods for manufacturing vertical MOSFET devices attaining low RDS(on) values via ultra-thin substrates.
  • FIGURE 1 A shows a cross-sectional, side view of a field effect transistor (FET) wafer having a silicon layer and a metal layer on one side of the silicon layer and defines a front side.
  • FET field effect transistor
  • FIGURE IB shows a cross-sectional, side view of the FET wafer of FIGURE 1A, wherein a metal is plated on the wafer to build up gate pads and source pads on corresponding portions of the metal layer.
  • FIGURE 1C shows a cross-sectional, side view of the FET wafer of FIGURE IB, wherein the FET wafer is overmolded with a structural support coating.
  • FIGURE ID shows a cross-sectional, side view of the FET wafer of FIGURE 1C, wherein the silicon layer has been ground to a thickness less than 50 pm.
  • FIGURE IE shows a cross-sectional, side view of the FET wafer of FIGURE ID, wherein a drain pad layer is applied to the silicon layer.
  • FIGURE IF shows a cross-sectional, side view of the FET wafer of FIGURE IE, wherein the front side of the FET wafer has been ground to remove a portion of the structural support coating, whereby the gate pads and source pads are exposed or revealed.
  • FIGURE 1G shows a cross-sectional, side view of the FET wafer of FIGURE IF, wherein plating layers are added to the front and back sides of the FET wafer.
  • FIGURE 1H shows a cross-sectional, side view of the FET wafer of FIGURE 1G, wherein the FET wafer has been singulated or cut into individual chips.
  • FIGURE 2 shows a flowchart for manufacturing vertical MOSFET devices with substrates less than 50 pm thick yielding low RDS(on) values.
  • FIGURE 3 shows a cross-sectional side view of a microchip package comprising MOSFET devices substrates less than 50 pm thick yielding low RDS(on) values.
  • FIGURES 4A through 4F show a MOSFET device being produced from a wafer.
  • FIGURE 4A is a top view showing a source pad, a gate pad and a die top passivation layer.
  • FIGURE 4B is a cross-sectional, side view of the MOSFET device shown in FIGURE 4A showing the silicon layer is full thickness.
  • FIGURE 4C is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A and 4B showing a copper plating on the front side of the wafer forming a source contact on the source pad and a gate contact on the gate pad.
  • FIGURE 4D is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4C showing a structural support coating over the passivation layer, the source pad, the source contact, the gate pad, and the gate contact.
  • FIGURE 4E is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4D and shows the silicon layer has been ground to a very thin thickness to attain ultra low RDS(on) values.
  • FIGURE 4F is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4E and shows the structural support coating has been ground away until the portions of it over the source contact and the gate contact are removed.
  • MOSFET devices with substrates less than 50 pm thick may have RDS(on) values less than 10 milliohms.
  • the structural support coating provides mechanical support to allow the MOSFET wafer to be ground to an ultra-thin thickness.
  • the MOSFET wafer may be ground to less than 50 pm thickness, and even down to 1 pm thickness.
  • the ultra-thin MOSFET wafer may be plated with a Cu layer to enhance electrical and thermal conductivity.
  • the wafer thinning process may comprise several stages: course grinding, fine grinding, and stress relief by dry polishing or wet polishing.
  • FIGURE 1 A shows a cross-sectional, side view of a field effect transistor (FET) wafer.
  • the FET wafer 100 has a silicon layer 110 and a metal layer 112.
  • the metal layer 112 defines a front side.
  • the wafer 100 may be an 8-inch, full thickness wafer (thickness between 0.4 mm (400 microns) and 0.8 mm (800 microns)).
  • a metal layer 112 is on one side of the silicon layer 110, wherein the metal may be aluminum or any other metal.
  • the metal layer 112 may define gate pads 113 and source pads 115.
  • a full thickness FET wafer 100 including the silicon layer 110 and the metal layer 112 may be greater than or equal to about 725 microns thick.
  • FIGURE 1 A shows a raw die with which one may start the process.
  • a doped region of the silicon layer 110 i.e. the transistor source may be under the source pads 115.
  • An insulation layer may be under the gate pads 113 (there may be a layer of poly silicon below the gate pad and above the insulation layer). The gate pad 113 and insulation layer may act as the gate of the transistor.
  • FIGURE IB shows a cross-sectional, side view of the FET wafer 100 of FIGURE 1A.
  • a metal is plated on the wafer 110 to build up gate contacts 114 and source contacts 116 on corresponding gate pads 113 and source pads 115 of the metal layer 112.
  • the metal of the gate contacts 114 and source contacts 116 may be Cu or any other metal. The result may be copper on aluminum.
  • the gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE IB may be 850 microns.
  • FIGURE 1C shows a cross-sectional, side view of the FET wafer 100 of FIGURE IB.
  • the FET wafer 100 is overmolded with a structural support coating 118, wherein the structural support coating 118 may be a polymer.
  • the structural support coating 118 may be an epoxy mold compound (EMC) and may be applied using a compression molding process.
  • EMC epoxy mold compound
  • the structural support coating 118 may be about 75 microns, gate contacts 114 and source contacts 116 may be about 125 microns, and the silicon layer may be about 725 microns, so that the entire FET wafer 100 as shown in FIGURE 1C may be 925 microns.
  • FIGURE ID shows a cross-sectional, side view of the FET wafer of FIGURE 1C.
  • the silicon layer 110 may be ground to an ultra-thin thickness (i.e., less than 50 microns, in one example between 2 microns and 25 microns). Because the gate and source pads 114 and 116 and the structural support coating 118 provide structural rigidity and support, a significant portion of the silicon layer 110 may be ground away. In theory, from the perspective of structural rigidity and support provided by the structural support coating 118, the silicon layer 110 may be ground to 1 pm thick), but some silicon should remain to provide for a “drain.” Drains 111 may be in the remaining silicon layer 110.
  • the gate contacts 114 and source contacts 116 may be about 125 microns, and the structural support coating 118 is about 75 microns, then the entire FET wafer 100 as shown in FIGURE ID may be 250 microns.
  • FIGURE IE shows a cross-sectional, side view of the FET wafer 100 of FIGURE ID.
  • a drain pad layer 120 may be applied to the silicon layer 110.
  • the drain pad layer 120 may be Ti-Cu or other metal and may be applied by a sputter process to the backside of the FET wafer 100.
  • the silicon layer 110 is about 50 microns
  • the gate contacts 114 and source contacts 116 is about 125 microns
  • the structural support coating 118 is about 75 microns, that the entire FET wafer 100 as shown in FIGURE IE may be 252 microns.
  • FIGURE IF shows a cross-sectional, side view of the FET wafer 100 of FIGURE IE.
  • the front side of the FET wafer 100 has been ground to remove a portion of the structural support coating 118, whereby the gate contacts 114 and source contacts 116 may be exposed or revealed. This may allow other components to be soldered to the gate contacts 114 and source contacts 116.
  • the structural support coating 118 (see FIGURE IE) is removed from the front sides of the gate contacts 114 and source contacts 116, material of structural support coating 118 may remain between the gate contacts 114 and source contacts 116 and have the same thickness as the gate contacts 114 and source contacts 116.
  • a surface of the structural support coating 118, a surface of the source contact 116, and a surface of the gate contact 114 may be coplanar.
  • the drain pad layer 120 may be about 2 microns thick
  • the silicon layer 110 is about 50 microns
  • the gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE IF may be 177 microns in thickness.
  • FIGURE 1G shows a cross-sectional, side view of the FET wafer of FIGURE IF.
  • a plating layer 122 may be added to the front side of the FET wafer 100 and another plating layer 124 may be added to the back side of the FET wafer 100.
  • These plating layers may inhibit the Cu from oxidizing and may provide common PCB layers for solder and bonding.
  • the plating layers may be electroless nickel immersion gold (ENIG) plating or electroless nickel palladium gold (ENEPIG) plating.
  • ENIG electroless nickel immersion gold
  • ENEPIG electroless nickel palladium gold
  • the plating of the front and back sides of the wafer may be with oxidizing inhibiting layers.
  • the plating layers 122 and 124 may be about 2 microns each, the drain pad layer 120 may be about 2 microns thick, the silicon layer 110 may be about 50 microns, and the gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE 1G may be 181 microns.
  • FIGURE 1H shows a cross-sectional, side view of the FET wafer 100 of FIGURE 1G.
  • the FET wafer 100 may be singulated or cut into individual chips 126.
  • FIGURE 2 shows a flowchart for manufacturing vertical MOSFET devices with substrates less than 50 pm thick yielding low RDS(on) values.
  • a wafer is provided 202 having a front side and a back side, a metal layer having a gate pad and a source pad at the front side, and a silicon layer at the back side wherein the silicon layer has a pre-process thickness. See FIGURE 1 A.
  • a structural support coating is molded 204 over the gate pad and source pad at the front side of the wafer. See FIGURE 1C.
  • the wafer is back-side processed 206 to remove a portion of the silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness. See FIGURE ID.
  • the structural support coating is removed 208 at the front side of the wafer sufficiently to expose the gate pad and source pad. See FIGURE IF.
  • FIGURE 3 shows a cross-sectional side view of a microchip package 300 comprising two MOSFET devices 302 and 304.
  • the MOSFET devices 302 and 304 are mounted on a printed circuit board 306. Because the MOSFET devices 302 and 304 have substrates less than 50 pm thick, the overall thickness 308 of the microchip package 300 is small.
  • FIGURES 4A through 4F show a MOSFET device being produced from a wafer.
  • FIGURE 4A is a top view showing a source pad 115, a gate pad 113 and a die top passivation layer 119.
  • FIGURE 4B is a cross-sectional, side view of the MOSFET device shown in FIGURE 4A.
  • FIGURE 4B shows the silicon layer 110 is full thickness (about 723 pm), which is a typical fab-out thickness.
  • Top aluminum bond pads are at the front side of the silicon layer 110 forming a source pad 115 and a gate pad 113.
  • a drain 111 is in the silicon layer 110.
  • FIGURE 4C is a cross-sectional, side view of the MOSFET device shown in FIGURES 4 A and 4B.
  • FIGURE 4C shows a copper plating on the front side of the wafer forming a source contact 116 on the source pad 115 and a gate contact 114 on the gate pad 113.
  • FIGURE 4D is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4C.
  • FIGURE 4D shows a structural support coating 118 over the passivation layer 119, the source pad 115, the source contact 116, the gate pad 113, and the gate contact 114.
  • the silicon layer 110 is full thickness (about 723 pm).
  • FIGURE 4E is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4D.
  • FIGURE 4E shows a structural support coating 118 over the passivation layer 119, the source pad 115, the source contact 116, the gate pad 113, and the gate contact 114.
  • the silicon layer 110 has been ground to a very thin thickness (less than or equal to 50 pm and as thin as 1 pm) to attain ultra low RDS(on) values less than 10 milliohms.
  • the drain 111 is in the thin thickness silicon layer 110.
  • FIGURE 4F is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4E.
  • FIGURE 4F shows the structural support coating 118 has been ground away until the portions of it over the source contact 116 and the gate contact 114 are removed. However, the structural support coating 118 adjacent the source contact 116 and the gate contact 114 remains. In particular, the structural support coating 118 between the source contact 116 and the gate contact 114 remains.
  • the drain 111 is in the thin thickness silicon layer 110.

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Abstract

A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 µm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.

Description

ELECTRONIC DEVICES WITH SUBSTRATES LESS THAN 50 MICROMETER THICK AND METHODS OF MANUFACTURE
PRIORITY
This application claims priority to U.S. Provisional Patent Application No. 63/472,953, filed June 14, 2023, the contents of which are hereby incorporated in their entirety.
TECHNICAL FIELD
The present disclosure relates to field effect transistors, in particular, field effect transistors with substrates less than 50 pm thick so they may have low RDS (on) values and methods to produce field effect transistors with substrates less than 50 pm thick.
BACKGROUND
Relative to metal oxide field effect transistors, RDS(on) stands for “drain-source on resistance,” or the total resistance between the drain and source in a metal oxide field effect transistor (MOSFET) when the MOSFET is fully “on.” There are two prevailing methods for production of vertical MOSFET devices to attain ultra-thin substrates (> 50 pm), which have RDS(on) values (> 10 milliohms): (1) grinding a center section of a wafer to an ultra-thin thickness while leaving thicker periphery sections and building the vertical MOSFET on the ultra-thin center section; and (2) adhering a wafer to a support material such as glass, grinding the entire wafer to an ultra-thin thickness, and building the vertical MOSFET on the ultra-thin wafer.
The first method is problematic because the thicker periphery sections of the wafer must be cut away after building the vertical MOSFET(s) and the wafer may break into pieces while being cut. There is also a practical limit to how thin the wafer may be ground without breaking during the grinding process. The thicker periphery sections of the wafer are sacrificed, which is a waste of good silicon. Production costs are high because many steps are used to grind and cut the wafer.
The second method is problematic because the support material must be removed after building the vertical MOSFET(s) and the wafer may break into pieces while the support material is removed.
There is a need for a process for production of vertical MOSFET devices to attain substrates less than 50 pm thick yielding low RDS(on) values that does not tend to break the wafer into pieces.
SUMMARY Aspects provide a process for production of vertical MOSFET devices to attain substrates less than 50 pm thick yielding low RDS(on) values that does not tend to break the wafer into pieces.
According to an aspect, there is provided a method comprising: providing a wafer having a front side and a back side, a metal layer having a gate pad and a source pad at the front side, and a silicon layer at the back side wherein the silicon layer has a pre-process thickness; molding a structural support coating over the gate pad and source pad at the front side of the wafer; back-side processing the wafer to remove a portion of the silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad.
An aspect provides the method as in the previous paragraph, wherein the pre-process thickness of the silicon layer is greater than or equal to 700 pm.
An aspect provides the method as in any one of the prior two paragraphs, wherein the post-process thickness of the silicon layer is less than or equal to 50 pm.
An aspect provides the method as in any one of the prior three paragraphs, wherein the structural support coating comprises polymer.
An aspect provides the method as in any one of the prior four paragraphs, wherein the back-side processing comprises grinding and the removing of the structural support coating comprising grinding.
An aspect provides the method as in any one of the prior five paragraphs, comprising plating the front side of the wafer to build up the gate pad and source pad.
An aspect provides the method as in the prior paragraph, wherein the plating comprises plating with copper (Cu).
An aspect provides the method as in any one of the prior seven paragraphs, comprising adding a drain pad layer on the back side of the wafer.
An aspect provides the method as in any one of the prior eight paragraphs, comprising plating the front and back sides of the wafer with oxidizing inhibiting layers.
An aspect provides the method as in any one of the prior nine paragraphs, comprising singulating the wafer to form individual chips. An aspect provides a field effect transistor comprising: a silicon layer less than 50 microns thick, a source pad on the silicon layer; a gate pad on the silicon layer; and a structural support coating on the silicon layer between the source pad and the gate pad.
According to one aspect, there is provided an electronic device comprising: a silicon layer less than 50 pm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating on the front side between the source pad and the gate pad.
An aspect provides the electronic device as in the prior paragraph, wherein the structural support coating comprises polymer.
An aspect provides the electronic device as in any one of the prior two paragraphs, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
An aspect provides the electronic device as in any one of the prior three paragraphs, comprising a copper (Cu) layer on the gate pad and source pad on the front side of the wafer.
An aspect provides the electronic device as in any one of the prior four paragraphs, wherein the electronic device has an RDS(on) value less than 10 milliohms.
An aspect provides the electronic device as in any one of the prior five paragraphs, comprising a drain pad layer on the back side of the silicon layer.
An aspect provides the electronic device as in any one of the prior six paragraphs, comprising oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer.
An aspect provides the electronic device as in the prior paragraph, wherein the oxidizing inhibiting layers comprise an electroless nickel immersion gold plating.
According to an aspect, there is provided a field effect transistor comprising: a silicon layer less than 50 pm thick and defining a back side of the field effect transistor, a metal layer on the silicon layer, wherein the metal layer defines a front side of the field effect transistor, wherein the metal layer has a source pad and a gate pad; a polymer coating on the front side between the source pad and the gate pad; a copper layer on the source pad and the gate pad; a drain pad layer on the back side of the silicon layer; and oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer, wherein the field effect transistor has an RDS(on) value less than 10 milliohms. An aspect provides the field effect transistor as in the prior paragraph, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
BRIEF DESCRIPTION OF THE DRAWINGS
The figures illustrate examples of vertical MOSFET devices attaining substrates less than 50 pm thick yielding low RDS(on) values and methods for manufacturing vertical MOSFET devices attaining low RDS(on) values via ultra-thin substrates.
FIGURE 1 A shows a cross-sectional, side view of a field effect transistor (FET) wafer having a silicon layer and a metal layer on one side of the silicon layer and defines a front side.
FIGURE IB shows a cross-sectional, side view of the FET wafer of FIGURE 1A, wherein a metal is plated on the wafer to build up gate pads and source pads on corresponding portions of the metal layer.
FIGURE 1C shows a cross-sectional, side view of the FET wafer of FIGURE IB, wherein the FET wafer is overmolded with a structural support coating.
FIGURE ID shows a cross-sectional, side view of the FET wafer of FIGURE 1C, wherein the silicon layer has been ground to a thickness less than 50 pm.
FIGURE IE shows a cross-sectional, side view of the FET wafer of FIGURE ID, wherein a drain pad layer is applied to the silicon layer.
FIGURE IF shows a cross-sectional, side view of the FET wafer of FIGURE IE, wherein the front side of the FET wafer has been ground to remove a portion of the structural support coating, whereby the gate pads and source pads are exposed or revealed.
FIGURE 1G shows a cross-sectional, side view of the FET wafer of FIGURE IF, wherein plating layers are added to the front and back sides of the FET wafer.
FIGURE 1H shows a cross-sectional, side view of the FET wafer of FIGURE 1G, wherein the FET wafer has been singulated or cut into individual chips.
FIGURE 2 shows a flowchart for manufacturing vertical MOSFET devices with substrates less than 50 pm thick yielding low RDS(on) values.
FIGURE 3 shows a cross-sectional side view of a microchip package comprising MOSFET devices substrates less than 50 pm thick yielding low RDS(on) values.
FIGURES 4A through 4F show a MOSFET device being produced from a wafer. FIGURE 4A is a top view showing a source pad, a gate pad and a die top passivation layer. FIGURE 4B is a cross-sectional, side view of the MOSFET device shown in FIGURE 4A showing the silicon layer is full thickness.
FIGURE 4C is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A and 4B showing a copper plating on the front side of the wafer forming a source contact on the source pad and a gate contact on the gate pad.
FIGURE 4D is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4C showing a structural support coating over the passivation layer, the source pad, the source contact, the gate pad, and the gate contact.
FIGURE 4E is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4D and shows the silicon layer has been ground to a very thin thickness to attain ultra low RDS(on) values.
FIGURE 4F is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4E and shows the structural support coating has been ground away until the portions of it over the source contact and the gate contact are removed.
The reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown.
DESCRIPTION
According to an aspect, there is provided a process for production of vertical MOSFET devices to attain substrates less than 50 pm thick yielding low RDS(on) values that does not tend to break the wafer into pieces. MOSFET devices with substrates less than 50 pm thick may have RDS(on) values less than 10 milliohms.
By over-molding the MOSFET wafer with a structural support coating prior to a grinding process, the structural support coating provides mechanical support to allow the MOSFET wafer to be ground to an ultra-thin thickness. In some aspects, the MOSFET wafer may be ground to less than 50 pm thickness, and even down to 1 pm thickness. The ultra-thin MOSFET wafer may be plated with a Cu layer to enhance electrical and thermal conductivity.
The wafer thinning process (grinding) may comprise several stages: course grinding, fine grinding, and stress relief by dry polishing or wet polishing.
FIGURE 1 A shows a cross-sectional, side view of a field effect transistor (FET) wafer. The FET wafer 100 has a silicon layer 110 and a metal layer 112. The metal layer 112 defines a front side. The wafer 100 may be an 8-inch, full thickness wafer (thickness between 0.4 mm (400 microns) and 0.8 mm (800 microns)). A metal layer 112 is on one side of the silicon layer 110, wherein the metal may be aluminum or any other metal. The metal layer 112 may define gate pads 113 and source pads 115. A full thickness FET wafer 100 including the silicon layer 110 and the metal layer 112 may be greater than or equal to about 725 microns thick. FIGURE 1 A shows a raw die with which one may start the process. A doped region of the silicon layer 110, i.e. the transistor source may be under the source pads 115. An insulation layer may be under the gate pads 113 (there may be a layer of poly silicon below the gate pad and above the insulation layer). The gate pad 113 and insulation layer may act as the gate of the transistor.
FIGURE IB shows a cross-sectional, side view of the FET wafer 100 of FIGURE 1A. A metal is plated on the wafer 110 to build up gate contacts 114 and source contacts 116 on corresponding gate pads 113 and source pads 115 of the metal layer 112. The metal of the gate contacts 114 and source contacts 116 may be Cu or any other metal. The result may be copper on aluminum. The gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE IB may be 850 microns.
FIGURE 1C shows a cross-sectional, side view of the FET wafer 100 of FIGURE IB. The FET wafer 100 is overmolded with a structural support coating 118, wherein the structural support coating 118 may be a polymer. The structural support coating 118 may be an epoxy mold compound (EMC) and may be applied using a compression molding process. The structural support coating 118 may be about 75 microns, gate contacts 114 and source contacts 116 may be about 125 microns, and the silicon layer may be about 725 microns, so that the entire FET wafer 100 as shown in FIGURE 1C may be 925 microns.
FIGURE ID shows a cross-sectional, side view of the FET wafer of FIGURE 1C. The silicon layer 110 may be ground to an ultra-thin thickness (i.e., less than 50 microns, in one example between 2 microns and 25 microns). Because the gate and source pads 114 and 116 and the structural support coating 118 provide structural rigidity and support, a significant portion of the silicon layer 110 may be ground away. In theory, from the perspective of structural rigidity and support provided by the structural support coating 118, the silicon layer 110 may be ground to 1 pm thick), but some silicon should remain to provide for a “drain.” Drains 111 may be in the remaining silicon layer 110. In an example where the silicon layer 110 is ground to a thickness of less than 50 microns, the gate contacts 114 and source contacts 116 may be about 125 microns, and the structural support coating 118 is about 75 microns, then the entire FET wafer 100 as shown in FIGURE ID may be 250 microns.
FIGURE IE shows a cross-sectional, side view of the FET wafer 100 of FIGURE ID. Depending on the thickness of the silicon layer 110 after grinding, a drain pad layer 120 may be applied to the silicon layer 110. The drain pad layer 120 may be Ti-Cu or other metal and may be applied by a sputter process to the backside of the FET wafer 100. In an example where the drain pad layer 120 is about 2 microns thick, the silicon layer 110 is about 50 microns, the gate contacts 114 and source contacts 116 is about 125 microns, and the structural support coating 118 is about 75 microns, that the entire FET wafer 100 as shown in FIGURE IE may be 252 microns.
FIGURE IF shows a cross-sectional, side view of the FET wafer 100 of FIGURE IE. The front side of the FET wafer 100 has been ground to remove a portion of the structural support coating 118, whereby the gate contacts 114 and source contacts 116 may be exposed or revealed. This may allow other components to be soldered to the gate contacts 114 and source contacts 116. While the structural support coating 118 (see FIGURE IE) is removed from the front sides of the gate contacts 114 and source contacts 116, material of structural support coating 118 may remain between the gate contacts 114 and source contacts 116 and have the same thickness as the gate contacts 114 and source contacts 116. After grinding, a surface of the structural support coating 118, a surface of the source contact 116, and a surface of the gate contact 114 may be coplanar. In an example, the drain pad layer 120 may be about 2 microns thick, the silicon layer 110 is about 50 microns, and the gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE IF may be 177 microns in thickness.
FIGURE 1G shows a cross-sectional, side view of the FET wafer of FIGURE IF. A plating layer 122 may be added to the front side of the FET wafer 100 and another plating layer 124 may be added to the back side of the FET wafer 100. These plating layers may inhibit the Cu from oxidizing and may provide common PCB layers for solder and bonding. The plating layers may be electroless nickel immersion gold (ENIG) plating or electroless nickel palladium gold (ENEPIG) plating. The plating of the front and back sides of the wafer may be with oxidizing inhibiting layers. In an example, the plating layers 122 and 124 may be about 2 microns each, the drain pad layer 120 may be about 2 microns thick, the silicon layer 110 may be about 50 microns, and the gate contacts 114 and source contacts 116 may be about 125 microns, so that the entire FET wafer 100 as shown in FIGURE 1G may be 181 microns.
FIGURE 1H shows a cross-sectional, side view of the FET wafer 100 of FIGURE 1G. The FET wafer 100 may be singulated or cut into individual chips 126.
FIGURE 2 shows a flowchart for manufacturing vertical MOSFET devices with substrates less than 50 pm thick yielding low RDS(on) values. A wafer is provided 202 having a front side and a back side, a metal layer having a gate pad and a source pad at the front side, and a silicon layer at the back side wherein the silicon layer has a pre-process thickness. See FIGURE 1 A. A structural support coating is molded 204 over the gate pad and source pad at the front side of the wafer. See FIGURE 1C. The wafer is back-side processed 206 to remove a portion of the silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness. See FIGURE ID. The structural support coating is removed 208 at the front side of the wafer sufficiently to expose the gate pad and source pad. See FIGURE IF.
FIGURE 3 shows a cross-sectional side view of a microchip package 300 comprising two MOSFET devices 302 and 304. The MOSFET devices 302 and 304 are mounted on a printed circuit board 306. Because the MOSFET devices 302 and 304 have substrates less than 50 pm thick, the overall thickness 308 of the microchip package 300 is small.
FIGURES 4A through 4F show a MOSFET device being produced from a wafer. FIGURE 4A is a top view showing a source pad 115, a gate pad 113 and a die top passivation layer 119.
FIGURE 4B is a cross-sectional, side view of the MOSFET device shown in FIGURE 4A. FIGURE 4B shows the silicon layer 110 is full thickness (about 723 pm), which is a typical fab-out thickness. Top aluminum bond pads are at the front side of the silicon layer 110 forming a source pad 115 and a gate pad 113. A drain 111 is in the silicon layer 110.
FIGURE 4C is a cross-sectional, side view of the MOSFET device shown in FIGURES 4 A and 4B. FIGURE 4C shows a copper plating on the front side of the wafer forming a source contact 116 on the source pad 115 and a gate contact 114 on the gate pad 113.
FIGURE 4D is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4C. FIGURE 4D shows a structural support coating 118 over the passivation layer 119, the source pad 115, the source contact 116, the gate pad 113, and the gate contact 114. The silicon layer 110 is full thickness (about 723 pm). FIGURE 4E is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4D. FIGURE 4E shows a structural support coating 118 over the passivation layer 119, the source pad 115, the source contact 116, the gate pad 113, and the gate contact 114. The silicon layer 110 has been ground to a very thin thickness (less than or equal to 50 pm and as thin as 1 pm) to attain ultra low RDS(on) values less than 10 milliohms. The drain 111 is in the thin thickness silicon layer 110.
FIGURE 4F is a cross-sectional, side view of the MOSFET device shown in FIGURES 4A through 4E. FIGURE 4F shows the structural support coating 118 has been ground away until the portions of it over the source contact 116 and the gate contact 114 are removed. However, the structural support coating 118 adjacent the source contact 116 and the gate contact 114 remains. In particular, the structural support coating 118 between the source contact 116 and the gate contact 114 remains. The drain 111 is in the thin thickness silicon layer 110.
Although examples have been described above, other variations and examples may be made from this disclosure without departing from the spirit and scope of these disclosed examples.

Claims

1. A method comprising: providing a wafer having a front side and a back side, a metal layer having a gate pad and a source pad at the front side, and a silicon layer at the back side wherein the silicon layer has a pre-process thickness; molding a structural support coating over the gate pad and source pad at the front side of the wafer; back-side processing the wafer to remove a portion of the silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad.
2. The method as in claim 1, wherein the pre-process thickness of the silicon layer is greater than or equal to 700 pm.
3. The method as in any one of claims 1 to 2, wherein the post-process thickness of the silicon layer is less than or equal to 50 pm.
4. The method as in any one of claims 1 to 3, wherein the structural support coating comprises polymer.
5. The method as in any one of claims 1 to 4, wherein the back-side processing comprises grinding and the removing of the structural support coating comprising grinding.
6. The method as in any one of claims 1 to 5, comprising plating the front side of the wafer to build up the gate pad and source pad.
7. The method as in claim 6, wherein the plating comprises plating with copper (Cu).
8. The method as in any one of claims 1 to 7, comprising adding a drain pad layer on the back side of the wafer.
9. The method as in any one of claims 1 to 8, comprising plating the front and back sides of the wafer with oxidizing inhibiting layers.
10. The method as in any one of claims 1 to 9, comprising singulating the wafer to form individual chips.
11. An electronic device comprising: a silicon layer less than 50 pm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating on the front side between the source pad and the gate pad.
12. The electronic device as in claim 11, wherein the structural support coating comprises polymer.
13. The electronic device as in any one of claims 11 to 12, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
14. The electronic device as in any one of claims 11 to 13, comprising a copper (Cu) layer on the gate pad and source pad on the front side of the wafer.
15. The electronic device as in any one of claims 11 to 14, wherein the electronic device has an RDS(on) value less than 10 milliohms.
16. The electronic device as in any one of claims 11 to 15, comprising a drain pad layer on the back side of the silicon layer.
17. The electronic device as in any one of claims 11 to 16, comprising oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer.
18. The electronic device as in claim 17, wherein the oxidizing inhibiting layers comprise an electroless nickel immersion gold plating.
19. A field effect transistor comprising: a silicon layer less than 50 pm thick and defining a back side of the field effect transistor, a metal layer on the silicon layer, wherein the metal layer defines a front side of the field effect transistor, wherein the metal layer has a source pad and a gate pad; a polymer coating on the front side between the source pad and the gate pad; a copper layer on the source pad and the gate pad; a drain pad layer on the back side of the silicon layer; and oxidizing inhibiting layers on the front side of the metal layer and the back side of the silicon layer, wherein the field effect transistor has an RDS(on) value less than 10 milliohms.
20. The field effect transistor as in claim 19, wherein a surface of the structural support coating, a surface of the source pad, and a surface of the gate pad are coplanar.
PCT/US2023/083951 2023-06-14 2023-12-14 Electronic devices with substrates less than 50 micrometer thick and methods of manufacture Ceased WO2024258445A1 (en)

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Citations (2)

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WO2021225119A1 (en) * 2020-05-08 2021-11-11 ローム株式会社 Semiconductor device
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Publication number Priority date Publication date Assignee Title
WO2021225119A1 (en) * 2020-05-08 2021-11-11 ローム株式会社 Semiconductor device
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