WO2024251279A1

WO2024251279A1 - Ldpc encoding enhancement for next-generation wlan systems

Info

Publication number: WO2024251279A1
Application number: PCT/CN2024/098239
Authority: WO
Inventors: Shengquan Hu; Jianhan Liu; Thomas Edward Pare Jr.
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2023-06-09
Filing date: 2024-06-07
Publication date: 2024-12-12
Anticipated expiration: 2025-12-09
Also published as: WO2024251279A9; EP4725144A1; CN121713417A

Abstract

Techniques pertaining to low-density parity-check (LDPC) encoding enhancement for next-generation wireless local area network (WLAN) systems in wireless communications are described. An apparatus (e.g., a station (STA) ) encodes a plurality of bits with an enlarged codeword length. The apparatus then communicates with the encoded plurality of bits in a wireless communication system.

Description

LDPC ENCODING ENHANCEMENT FOR NEXT-GENERATION WLAN SYSTEMS

CROSS REFERENCE TO RELATED PATENT APPLICATION

The present disclosure is part of a non-provisional patent application claiming the priority benefit of U.S. Provisional Patent Application No. 63/507,124, filed 09 June 2023, the content of which herein being incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure is generally related to wireless communications and, more particularly, to low-density parity-check (LDPC) encoding enhancement for next-generation wireless local area network (WLAN) systems in wireless communications.

BACKGROUND

Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted as prior art by inclusion in this section.

In wireless communications, LDPC encoding has been used in both cellular communications (e.g., 5^th Generation (5G) /New Radio (NR) ) in accordance with the 3^rd Generation Partnership Project (3GPP) standards as well as Wi-Fi (or WiFi) and WLAN systems in accordance with the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standards. In IEEE 802.11n/ac/ax/be, the highest coding rate is 5/6 and the codeword length is up to 1944 bits. However, to enhance system performance and coverage range, higher LDPC coding rates and increased codeword lengths may be necessary but have yet to be defined. Therefore, there is a need for a solution of LDPC encoding enhancement for next-generation WLAN systems.

SUMMARY

The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce concepts, highlights, benefits and advantages of the novel and non-obvious techniques described herein. Select implementations are further described below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

An objective of the present disclosure is to provide schemes, concepts, designs, techniques, methods and apparatuses pertaining to LDPC encoding enhancement for next-generation WLAN systems in wireless communications. It is believed that implementations of various schemes proposed herein may extend the LDPC coding rate up to 7/8 and 11/12 and increase the codeword length by two times to 2592 bits (=2*1296) or 3888 bits (= 2*1944) , or by three times to 3888 bits (= 3*1296) or 5832 bits (= 3*1944) , or by four times to 5184 bits (= 4*1296) or 7776 bits (= 4*1944) .

In one aspect, a method may involve encoding a plurality of bits with an enlarged codeword length. The method may also involve communicating with the encoded plurality of bits in a wireless communication system.

In another aspect, an apparatus may include a transceiver configured to communicate wirelessly and a processor coupled to the transceiver. The processor may encode a plurality of bits with an enlarged codeword length. The processor may also communicate with the encoded plurality of bits in a wireless communication system.

It is noteworthy that, although description provided herein may be in the context of certain radio access technologies, networks and network topologies such as, Wi-Fi, the proposed concepts, schemes and any variation (s) /derivative (s) thereof may be implemented in, for and by other types of radio access technologies, networks and network topologies such as, for example and without limitation, Bluetooth, ZigBee, 5^th Generation (5G) /New Radio (NR) , Long-Term Evolution (LTE) , LTE-Advanced, LTE-Advanced Pro, Internet-of-Things (IoT) , Industrial IoT (IIoT) and narrowband IoT (NB-IoT) . Thus, the scope of the present disclosure is not limited to the examples described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It is appreciable that the drawings are not necessarily in scale as some components may be shown to be out of proportion than the size in actual implementation to clearly illustrate the concept of the present disclosure.

FIG. 1 is a diagram of an example network environment in which various solutions and schemes in accordance with the present disclosure may be implemented.

FIG. 2 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 3 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 4 is a diagram of an example scenario under a proposed scheme in accordance with the present disclosure.

FIG. 5 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 6 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 7 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 8 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 9 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 10 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 11 is a diagram of an example design under a proposed scheme in accordance with the present disclosure.

FIG. 12 is a block diagram of an example communication system in accordance with an implementation of the present disclosure.

FIG. 13 is a flowchart of an example process in accordance with an implementation of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Detailed embodiments and implementations of the claimed subject matters are disclosed herein. However, it shall be understood that the disclosed embodiments and implementations are merely illustrative of the claimed subject matters which may be embodied in various forms. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that description of the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. In the description below, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

Overview

Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and/or solutions pertaining to LDPC encoding enhancement for next-generation WLAN systems in wireless communications. According to the present disclosure, a number of possible solutions may be implemented separately or jointly. That is, although these possible solutions may be described below separately, two or more of these possible solutions may be implemented in one combination or another.

FIG. 1 illustrates an example network environment 100 in which various solutions and schemes in accordance with the present disclosure may be implemented. FIG. 2 ～ FIG. 13 illustrate examples of implementation of various proposed schemes in network environment 100 in accordance with the present disclosure. The following description of various proposed schemes is provided with reference to FIG. 1 ～ FIG. 13.

Referring to part (A) of FIG. 1, network environment 100 may involve at least a station (STA) 110 communicating wirelessly with a STA 120. Either of STA 110 and STA 120 may be an access point (AP) STA or, alternatively, either of STA 110 and STA 120 may function as a non-AP STA. In some cases, STA 110 and STA 120 may be associated with a basic service set (BSS) in accordance with one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future-developed standards) . Each of STA 110 and STA 120 may be configured to communicate with each other by utilizing the LDPC encoding enhancement for next-generation WLAN systems in wireless communications in accordance with various proposed schemes described below. It is noteworthy that, while the various proposed schemes may be individually or separately described below, in actual implementations some or all of the proposed schemes may be utilized or otherwise implemented jointly. Of course, each of the proposed schemes may be utilized or otherwise implemented individually or separately.

Under current IEEE 802.11 specifications such as IEEE 802.11n/ac/ax/be, the LDPC coding rate (R) may be 1/2, 2/3, 3/4 or 5/6. As for the codeword (K = L *R) , L may be 648, 1296 or 1944. Correspondingly, the parity matrix (Z) may be 27, 54 or 81. Referring to part (B) of FIG. 1, with a coding rate = k /n, the number of rows may be n –k, the number of columns of information bits may be k and the number of columns of parity bits may be n –k, corresponding to the following parameters: a codeword length = n, information part = k, and parity part = n –k. For instance, with R = 3/4 and Z = 81, the codeword length = n = 24 *Z, the number of columns of information part = k = 18 *Z, and the number of columns of parity part =n –k = 6 *Z.

FIG. 2 illustrates an example design 200 under a proposed scheme in accordance with the present disclosure. Design 200 may pertain to a parity check matrix for an LDPC coding rate of R = 7/8. Under the proposed scheme, the coding rate R = 7/8 parity check matrix may be generated using a coding rate of R = 3/4 LDPC parity check matrix by performing a modulo-2 addition between rows 1 and 4, between rows 2 and 5, and between rows 3 and 6.

FIG. 3 illustrates an example design 300 under a proposed scheme in accordance with the present disclosure. Design 300 may pertain to a parity check matrix for an LDPC coding rate of R = 11/12. Under the proposed scheme, the coding rate R = 11/12 parity check matrix may be generated using a coding rate of R = 5/6 LDPC parity check matrix by performing a modulo-2 addition between rows 1 and 3, and between rows 2 and 4.

FIG. 4 illustrates an example scenario 400 under a proposed scheme in accordance with the present disclosure. Scenario 400 may pertain to enlargement of LDPC codeword length by using a lifting matrix. As defined in IEEE 802.11ad, the coding rate may be 1/2, 5/8, 3/4 or 13/16, and, for the parity matrix, Z = 42 and H = 336 *672, 252 *672, 168 *672 or 126 *672, respectively. As defined in IEEE 802.11ay, the coding rate may be 1/2, 5/8, 3/4, 13/16, 7/8, 2/3 or 5/6, and for the parity matrix, Z = 42 for a code length =672 and H = 336 *672, 252 *672, 168 *672, 126 *672, 2Z *2Z with a lifting matrix, respectively, with the code length = 2 *672 = 1344. Under the proposed scheme, a lifting matrix similar to that defined in IEEE 802.11ay may be utilized to increase the LDPC codeword length.

Referring to part (A) of FIG. 4, with an original code rate R = 3/4 LDPC parity check matrix, Z = 42 with 168 rows x 672 columns. Part (B) of FIG. 4 shows a lifting matrix for code rate of 3/4. Part (C) of FIG. 4 shows an LDPC code matrix for code rate of 3/4 resulting from applying the lifting matrix of part (B) of FIG. 4 to the original LDPC parity check matrix of part (A) of FIG. 4. The resultant matrix may have 2 *168 rows x 2 *672 column = 336 rows x 1344 columns.

In legacy Wi-Fi systems in accordance with IEEE 802.11n/ac/ax/be, there are three types of codeword length, namely: n = 648, 1296 or 1944. Submatrix size Z = 27 is used for n = 648, Z = 54 for n = 1296, and Z = 81 for n = 1944. Under the various proposed schemes in accordance with the present disclosure, LDPC codeword length may be increased (e.g., for IEEE 802.11bn and/or Ultra-High Reliability (UHR) communications) may be achieved by a one-step lifting. Under the proposed schemes, the codeword length n = 1296 and 1944 may be increased or otherwise enlarged to n = 2 *1296 = 2592, n = 2 *1944 = 3888, n = 3 *1296, n = 3 *1944, n = 4 *1296, and n = 4 *1944. To increase or enlarge the codeword length two times (2x) by applying a lifting matrix, each element in the lifting matrix acting on a Z x Z submatrix may create a submatrix of size 2Z x 2Z (e.g., 2Z x 2Z = 2 *54 x 2 *54 for codeword length n = 2 *1296, and 2Z x 2Z = 2 *81 x 2 *81 for codeword length n = 2 *1944) . To increase or enlarge the codeword length three times (3x) by applying a lifting matrix, each element in the lifting matrix acting on a Z x Z submatrix may create a submatrix of size 3Z x 3Z (e.g., 3Z x 3Z = 3 *54 x 3 *54 for codeword length n = 3 *1296, and 3Z x 3Z = 3 *81 x 3 *81 for codeword length n = 3 *1944) . To increase or enlarge the codeword length four times (4x) by applying a lifting matrix, each element in the lifting matrix acting on a Z x Z submatrix may create a submatrix of size 4Z x 4Z (e.g., 4Z x 4Z = 4 *54 x 4 *54 for codeword length n = 4 *1296, and 4Z x 4Z = 4 *81 x 4 *81 for codeword length n = 4 *1944) .

FIG. 5 illustrates an example design 500 under a proposed scheme in accordance with the present disclosure. Design 500 may pertain to increasing LDPC codeword length by one-step lifting (e.g., for IEEE 802.11bn/UHR) . Under the proposed scheme, a non-blank ( “0” ) element in a lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in enlargement. Referring to part (A) of FIG. 5, a non-blank “0” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 2Z x 2Z submatrix for two times (2x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-left corner to a lower-right corner of the 2Z x 2Z submatrix. Referring to part (B) of FIG. 5, a non-blank “0” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 3Z x 3Z submatrix for three times (3x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-left corner to a lower-right corner of the 3Z x 3Z submatrix. Referring to part (C) of FIG. 5, a non-blank “0” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 4Z x 4Z submatrix for four times (4x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-left corner to a lower-right corner of the 4Z x 4Z submatrix.

FIG. 6 illustrates an example design 600 under a proposed scheme in accordance with the present disclosure. Design 600 may pertain to increasing LDPC codeword length by one-step lifting (e.g., for IEEE 802.11bn/UHR) . Under the proposed scheme, a non-blank ( “1” ) element in a lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in enlargement. Referring to part (A) of FIG. 6, a non-blank “1” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 2Z x 2Z submatrix for two times (2x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-right corner to a lower-left corner of the 2Z x 2Z submatrix. Referring to part (B) of FIG. 6, a non-blank “1” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 3Z x 3Z submatrix for three times (3x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-right corner to a lower-left corner of the 3Z x 3Z submatrix. Referring to part (C) of FIG. 6, a non-blank “1” element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 4Z x 4Z submatrix for four times (4x) enlargement of the codeword length, with “i” denoting the value of an original element of the Z x Z cyclic permutation matrix Pi which is duplicated and disposed along a diagonal line from an upper-right corner to a lower-left corner of the 4Z x 4Z submatrix.

FIG. 7 illustrates an example design 700 under a proposed scheme in accordance with the present disclosure. Design 700 may pertain to increasing LDPC codeword length by one-step lifting (e.g., for IEEE 802.11bn/UHR) . Under the proposed scheme, a blank ( “” ) element in a lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in enlargement. Referring to part (A) of FIG. 7, a blank element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 2Z x 2Z zero-matrix for two times (2x) enlargement of the codeword length. Referring to part (B) of FIG. 7, a blank element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 3Z x 3Z zero-matrix for three times (3x) enlargement of the codeword length. Referring to part (C) of FIG. 7, a blank element in the lifting matrix may act on a Z x Z cyclic permutation matrix Pi in the LDPC parity check matrix to cause or result in a 4Z x 4Z zero-matrix for four times (4x) enlargement of the codeword length.

Under the various proposed schemes in accordance with the present disclosure, LDPC codeword length may be increased (e.g., for IEEE 802.11bn and/or UHR communications) may be achieved by a two-step lifting. Under the proposed schemes, for codeword length n = 4 *1296 and 4 *1944, a one-step lifting matrix or a two-step lifting matrix may be applied to increase or otherwise enlarge the codeword length. For the two-step lifting matrix, a first-step lifting matrix and a second-step lifting matrix may be applied, and the first-step lifting matrix and the second-step lifting matrix may be the same or different. For instance, for n =4 *1944, in a first step each element in the first-step lifting matrix (M1) acting on a Z x Z submatrix may create a submatrix of size Z1 x Z1 = 2 *Z x 2 *Z = 2 *81 x 2 *81, and the first-step lifting matrix M1 may be applied on an LDPC parity check matrix H1. Then, in a second step a second-step lifting matrix (M2) may be applied on H1, and each element in the second-step matrix M1 acting on the Z1 x Z1 submatrix may create a submatrix of size Z2 x Z2 = 2 *Z1 x 2 *Z1 = 2 *2 *81 x 2 *2 *81 = 4 *81 x 4 *81, and the final LDPC parity check matrix H2 may result by applying the second-step lifting matrix M2 on top of H1. Here, M1 = M2 or M1 ! = M2.

FIG. 8 illustrates an example design 800 under a proposed scheme in accordance with the present disclosure. Design 800 may pertain to an example of a lifting matrix design for Z = 54, R = 1/2. Part (A) of FIG. 8 shows an original parity check matrix for Z = 54 may have a code rate R = 1/2. Part (B) of FIG. 8 shows an example lifting matrix under the proposed scheme for Z = 54 and R = 1/2.

FIG. 9 illustrates an example design 900 under a proposed scheme in accordance with the present disclosure. Design 900 may pertain to an example of a lifting matrix design for Z = 81, R = 1/2. Part (A) of FIG. 9 shows an original parity check matrix for Z = 81 may have a code rate R = 1/2. Part (B) of FIG. 9 shows an example lifting matrix under the proposed scheme for Z = 81 and R = 1/2.

FIG. 10 illustrates an example design 1000 under a proposed scheme in accordance with the present disclosure. Design 1000 may pertain to an example of a lifting matrix design for Z = 54, R = 3/4. Part (A) of FIG. 10 shows an original parity check matrix for Z = 54 may have a code rate R = 3/4. Part (B) of FIG. 10 shows an example lifting matrix under the proposed scheme for Z = 54 and R = 3/4.

FIG. 11 illustrates an example design 1100 under a proposed scheme in accordance with the present disclosure. Design 1100 may pertain to an example of a lifting matrix design for Z = 81, R = 3/4. Part (A) of FIG. 11 shows an original parity check matrix for Z = 81 may have a code rate R = 3/4. Part (B) of FIG. 11 shows an example lifting matrix under the proposed scheme for Z = 81 and R = 3/4.

Illustrative Implementations

FIG. 12 illustrates an example system 1200 having at least an example apparatus 1210 and an example apparatus 1220 in accordance with an implementation of the present disclosure. Each of apparatus 1210 and apparatus 1220 may perform various functions to implement schemes, techniques, processes and methods described herein pertaining to LDPC encoding enhancement for next-generation WLAN systems in wireless communications including the various schemes described above with respect to various proposed designs, concepts, schemes, systems and methods described above as well as processes described below. For instance, apparatus 1210 may be implemented in STA 110 and apparatus 1220 may be implemented in STA 120, or vice versa.

Each of apparatus 1210 and apparatus 1220 may be a part of an electronic apparatus, which may be a non-AP STA or an AP STA, such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus. When implemented in a STA, each of apparatus 1210 and apparatus 1220 may be implemented in a smartphone, a smart watch, a personal digital assistant, a digital camera, or a computing equipment such as a tablet computer, a laptop computer or a notebook computer. Each of apparatus 1210 and apparatus 1220 may also be a part of a machine type apparatus, which may be an IoT apparatus such as an immobile or a stationary apparatus, a home apparatus, a wire communication apparatus or a computing apparatus. For instance, each of apparatus 1210 and apparatus 1220 may be implemented in a smart thermostat, a smart fridge, a smart door lock, a wireless speaker or a home control center. When implemented in or as a network apparatus, apparatus 1210 and/or apparatus 1220 may be implemented in a network node, such as an AP in a WLAN.

In some implementations, each of apparatus 1210 and apparatus 1220 may be implemented in the form of one or more integrated-circuit (IC) chips such as, for example and without limitation, one or more single-core processors, one or more multi-core processors, one or more reduced-instruction set computing (RISC) processors, or one or more complex-instruction-set-computing (CISC) processors. In the various schemes described above, each of apparatus 1210 and apparatus 1220 may be implemented in or as a STA or an AP. Each of apparatus 1210 and apparatus 1220 may include at least some of those components shown in FIG. 12 such as a processor 1212 and a processor 1222, respectively, for example. Each of apparatus 1210 and apparatus 1220 may further include one or more other components not pertinent to the proposed scheme of the present disclosure (e.g., internal power supply, display device and/or user interface device) , and, thus, such component (s) of apparatus 1210 and apparatus 1220 are neither shown in FIG. 12 nor described below in the interest of simplicity and brevity.

In one aspect, each of processor 1212 and processor 1222 may be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors or one or more CISC processors. That is, even though a singular term “aprocessor” is used herein to refer to processor 1212 and processor 1222, each of processor 1212 and processor 1222 may include multiple processors in some implementations and a single processor in other implementations in accordance with the present disclosure. In another aspect, each of processor 1212 and processor 1222 may be implemented in the form of hardware (and, optionally, firmware) with electronic components including, for example and without limitation, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and/or one or more varactors that are configured and arranged to achieve specific purposes in accordance with the present disclosure. In other words, in at least some implementations, each of processor 1212 and processor 1222 is a special-purpose machine specifically designed, arranged and configured to perform specific tasks including those pertaining to LDPC encoding enhancement for next-generation WLAN systems in wireless communications in accordance with various implementations of the present disclosure.

In some implementations, apparatus 1210 may also include a transceiver 1216 coupled to processor 1212. Transceiver 1216 may include a transmitter capable of wirelessly transmitting and a receiver capable of wirelessly receiving data. In some implementations, apparatus 1220 may also include a transceiver 1226 coupled to processor 1222. Transceiver 1226 may include a transmitter capable of wirelessly transmitting and a receiver capable of wirelessly receiving data. It is noteworthy that, although transceiver 1216 and transceiver 1226 are illustrated as being external to and separate from processor 1212 and processor 1222, respectively, in some implementations, transceiver 1216 may be an integral part of processor 1212 as a system on chip (SoC) , and transceiver 1226 may be an integral part of processor 1222 as a SoC.

In some implementations, apparatus 1210 may further include a memory 1214 coupled to processor 1212 and capable of being accessed by processor 1212 and storing data therein. In some implementations, apparatus 1220 may further include a memory 1224 coupled to processor 1222 and capable of being accessed by processor 1222 and storing data therein. Each of memory 1214 and memory 1224 may include a type of random-access memory (RAM) such as dynamic RAM (DRAM) , static RAM (SRAM) , thyristor RAM (T-RAM) and/or zero-capacitor RAM (Z-RAM) . Alternatively, or additionally, each of memory 1214 and memory 1224 may include a type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM) , erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM) . Alternatively, or additionally, each of memory 1214 and memory 1224 may include a type of non-volatile random-access memory (NVRAM) such as flash memory, solid-state memory, ferroelectric RAM (FeRAM) , magnetoresistive RAM (MRAM) and/or phase-change memory.

Each of apparatus 1210 and apparatus 1220 may be a communication entity capable of communicating with each other using various proposed schemes in accordance with the present disclosure. For illustrative purposes and without limitation, a description of capabilities of apparatus 1210, as STA 110, and apparatus 1220, as STA 120, is provided below in the context of example process 1300. It is noteworthy that, although a detailed description of capabilities, functionalities and/or technical features of apparatus 1220 is provided below, the same may be applied to apparatus 1210 although a detailed description thereof is not provided solely in the interest of brevity. It is also noteworthy that, although the example implementations described below are provided in the context of WLAN, the same may be implemented in other types of networks.

Illustrative Processes

FIG. 13 illustrates an example process 1300 in accordance with an implementation of the present disclosure. Process 1300 may represent an aspect of implementing various proposed designs, concepts, schemes, systems and methods described above. More specifically, process 1300 may represent an aspect of the proposed concepts and schemes pertaining to LDPC encoding enhancement for next-generation WLAN systems in wireless communications in accordance with the present disclosure. Process 1300 may include one or more operations, actions, or functions as illustrated by one or more of blocks 1310 and 1320. Although illustrated as discrete blocks, various blocks of process 1300 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Moreover, the blocks/sub-blocks of process 1300 may be executed in the order shown in FIG. 13 or, alternatively, in a different order. Furthermore, one or more of the blocks/sub-blocks of process 1300 may be executed repeatedly or iteratively. Process 1300 may be implemented by or in apparatus 1210 and apparatus 1220 as well as any variations thereof. Solely for illustrative purposes and without limiting the scope, process 1300 is described below in the context of apparatus 1210 implemented in or as STA 110 functioning as a non-AP STA or an AP STA and apparatus 1220 implemented in or as STA 120 functioning as an AP STA or a non-AP STA of a wireless network such as a WLAN in network environment 100 in accordance with one or more of IEEE 802.11 standards. Process 1300 may begin at block 1310.

At 1310, process 1300 may involve processor 1212 of apparatus 1210 encoding a plurality of bits with an enlarged codeword length. Process 1300 may proceed from 1310 to 1320.

At 1320, process 1300 may involve processor 1212 communicating, via transceiver 1216, with the encoded plurality of bits in a wireless communication system (e.g., by transmitting the encoded bits to apparatus 1220) .

In some implementations, in encoding, process 1300 may involve processor 1212 increasing a codeword length n by two times (2x) such that: (a) for n = 1296, the enlarged codeword length = 2 *1296 = 2595, and (b) for n = 1944, the enlarged codeword length = 2 *1944 = 3888. In some implementations, in encoding, process 1300 may further involve processor 1212 applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in an LDPC parity check matrix creates a submatrix of size 2Z x 2Z such that: (1) for n = 1296, 2Z x 2Z = 2 *54 x 2 *54, and (2) for n = 1944, 2Z x 2Z = 2 *81 x 2 *81. In some implementations, in applying the lifting matrix, process 1300 may involve processor 1212 applying the lifting matrix in a one-step lifting such that: (i) a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 2Z x 2Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 2Z x 2Z submatrix, (ii) a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 2Z x 2Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 2Z x 2Z submatrix, and (iii) a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 2Z x 2Z zero-matrix.

In some implementations, in encoding, process 1300 may involve processor 1212 increasing a codeword length n by three times (3x) such that: (a) for n = 1296, the enlarged codeword length = 3 *1296 = 3888, and (b) for n = 1944, the enlarged codeword length = 3 *1944 = 5832. In some implementations, in encoding, process 1300 may further involve processor 1212 applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in an LDPC parity check matrix creates a submatrix of size 3Z x 3Z such that: (1) for n = 1296, 3Z x 3Z = 3 *54 x 3 *54, and (2) for n = 1944, 3Z x 3Z = 3 *81 x 3 *81. In some implementations, in applying the lifting matrix, process 1300 may involve processor 1212 applying the lifting matrix in a one-step lifting such that: (i) a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 3Z x 3Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 3Z x 3Z submatrix, (ii) a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 3Z x 3Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 3Z x 3Z submatrix, and (iii) a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 3Z x 3Z zero-matrix.

In some implementations, in encoding, process 1300 may involve processor 1212 increasing a codeword length n by four times (4x) such that: (a) for n = 1296, the enlarged codeword length = 4 *1296 = 5184, and (b) for n = 1944, the enlarged codeword length = 4 *1944 = 7776. In some implementations, in encoding, process 1300 may further involve processor 1212 applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in an LDPC parity check matrix creates a submatrix of size 4Z x 4Z such that: (1) for n = 1296, 4Z x 4Z = 4 *54 x 4 *54, and (2) for n = 1944, 4Z x 4Z = 4 *81 x 4 *81. In some implementations, in applying the lifting matrix, process 1300 may involve processor 1212 applying the lifting matrix in a one-step lifting such that: (i) a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 4Z x 4Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 4Z x 4Z submatrix, (ii) a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 4Z x 4Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 4Z x 4Z submatrix, and (iii) a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 4Z x 4Z zero-matrix.

In some implementations, in encoding, process 1300 may involve processor 1212 increasing a codeword length by four times (4x) with a first-step lifting or a two-step lifting. In some implementations, in increasing the codeword length, process 1300 may involve processor 1212 increasing the codeword length with the two-step lifting by first applying a first-step lifting matrix (M1) and then applying a second-step lifting matrix (M2) . In some implementations, the first-step lifting matrix and the second-step lifting matrix may be same. Alternatively, the first-step lifting matrix and the second-step lifting matrix may be different.

Additional Notes

The herein-described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely examples, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected" , or "operably coupled" , to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable" , to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

Further, with respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

Moreover, it will be understood by those skilled in the art that, in general, terms used herein, and especially in the appended claims, e.g., bodies of the appended claims, are generally intended as “open” terms, e.g., the term “including” should be interpreted as “including but not limited to, ” the term “having” should be interpreted as “having at least, ” the term “includes” should be interpreted as “includes but is not limited to, ” etc. It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an, " e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more; ” the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number, e.g., the bare recitation of "two recitations, " without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc. ” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. In those instances where a convention analogous to “at least one of A, B, or C, etc. ” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention, e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc. It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B. ”

From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

A method, comprising:

encoding, by a processor of an apparatus, a plurality of bits with an enlarged codeword length; and

communicating, by the processor, with the encoded plurality of bits in a wireless communication system.
The method of Claim 1, wherein the encoding comprises increasing a codeword length n by two times (2x) such that:

for n = 1296, the enlarged codeword length = 2 *1296 = 2595, and

for n = 1944, the enlarged codeword length = 2 *1944 = 3888.
The method of Claim 2, wherein the encoding further comprises applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in a low-density parity-check (LDPC) parity check matrix creates a submatrix of size 2Z x 2Z such that:

for n = 1296, 2Z x 2Z = 2 *54 x 2 *54, and

for n = 1944, 2Z x 2Z = 2 *81 x 2 *81.
The method of Claim 3, wherein the applying of the lifting matrix comprises applying the lifting matrix in a one-step lifting such that:

a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 2Z x 2Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 2Z x 2Z submatrix,

a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 2Z x 2Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 2Z x 2Z submatrix, and

a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 2Z x 2Z zero-matrix.
The method of Claim 1, wherein the encoding comprises increasing a codeword length n by three times (3x) such that:

for n = 1296, the enlarged codeword length = 3 *1296 = 3888, and

for n = 1944, the enlarged codeword length = 3 *1944 = 5832.
The method of Claim 5, wherein the encoding further comprises applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in a low-density parity-check (LDPC) parity check matrix creates a submatrix of size 3Z x 3Z such that:

for n = 1296, 3Z x 3Z = 3 *54 x 3 *54, and

for n = 1944, 3Z x 3Z = 3 *81 x 3 *81.
The method of Claim 6, wherein the applying of the lifting matrix comprises applying the lifting matrix in a one-step lifting such that:

a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 3Z x 3Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 3Z x 3Z submatrix,

a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 3Z x 3Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 3Z x 3Z submatrix, and

a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 3Z x 3Z zero-matrix.
The method of Claim 1, wherein the encoding comprises increasing a codeword length n by four times (4x) such that:

for n = 1296, the enlarged codeword length = 4 *1296 = 5184, and

for n = 1944, the enlarged codeword length = 4 *1944 = 7776.
The method of Claim 8, wherein the encoding further comprises applying a lifting matrix such that each element in the lifting matrix acting on a Z x Z cyclic permutation matrix in a low-density parity-check (LDPC) parity check matrix creates a submatrix of size 4Z x 4Z such that:

for n = 1296, 4Z x 4Z = 4 *54 x 4 *54, and

for n = 1944, 4Z x 4Z = 4 *81 x 4 *81.
The method of Claim 9, wherein the applying of the lifting matrix comprises applying the lifting matrix in a one-step lifting such that:

a non-blank element “0” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 4Z x 4Z submatrix with a value of an original element of the Z x Z cyclic permutation matrix disposed along a diagonal line from an upper-left corner to a lower-right corner of the 4Z x 4Z submatrix,

a non-blank element “1” in the lifting matrix acting on the Z x Z cyclic permutation matrix creates the 4Z x 4Z submatrix with the value of the original element of the Z x Z cyclic permutation matrix disposed along another diagonal line from an upper-right corner to a lower-left corner of the 4Z x 4Z submatrix, and

a blank element in the lifting matrix acting on the Z x Z cyclic permutation matrix creates a 4Z x 4Z zero-matrix.
The method of Claim 1, the encoding comprises increasing a codeword length by four times (4x) with a first-step lifting or a two-step lifting.
The method of Claim 11, the increasing of the codeword length comprises increasing the codeword length with the two-step lifting by first applying a first-step lifting matrix (M1) and then applying a second-step lifting matrix (M2) .
The method of Claim 12, the first-step lifting matrix and the second-step lifting matrix are same.
The method of Claim 12, the first-step lifting matrix and the second-step lifting matrix are different.
An apparatus, comprising:

a transceiver configured to communicate wirelessly; and

a processor coupled to the transceiver and configured to perform operations comprising:

encoding a plurality of bits with an enlarged codeword length; and

communicating, via the transceiver, with the encoded plurality of bits in a wireless communication system.
The apparatus of Claim 15, wherein the encoding comprises increasing a codeword length n by two times (2x) such that:

for n = 1296, the enlarged codeword length = 2 *1296 = 2595, and

for n = 1944, the enlarged codeword length = 2 *1944 = 3888.
The apparatus of Claim 15, wherein the encoding comprises increasing a codeword length n by three times (3x) such that:

for n = 1296, the enlarged codeword length = 3 *1296 = 3888, and

for n = 1944, the enlarged codeword length = 3 *1944 = 5832.
The apparatus of Claim 15, wherein the encoding comprises increasing a codeword length n by four times (4x) such that:

for n = 1296, the enlarged codeword length = 4 *1296 = 5184, and

for n = 1944, the enlarged codeword length = 4 *1944 = 7776.
The apparatus of Claim 15, the encoding comprises increasing a codeword length with a first-step lifting.
The apparatus of Claim 15, the encoding comprises increasing a codeword length with a two-step lifting by first applying a first-step lifting matrix (M1) and then applying a second-step lifting matrix (M2) .