WO2024247875A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024247875A1
WO2024247875A1 PCT/JP2024/018981 JP2024018981W WO2024247875A1 WO 2024247875 A1 WO2024247875 A1 WO 2024247875A1 JP 2024018981 W JP2024018981 W JP 2024018981W WO 2024247875 A1 WO2024247875 A1 WO 2024247875A1
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Prior art keywords
layer
buffer
expansion coefficient
alloy layer
linear expansion
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French (fr)
Japanese (ja)
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聡 田中
次郎 新開
弘 佐藤
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • This disclosure relates to a semiconductor device.
  • a semiconductor device suitable for a power module As an example of a semiconductor device suitable for a power module, a semiconductor device has been proposed in which a buffer plate is bonded to the main electrode of a semiconductor chip, and bonding wires are bonded to the buffer plate.
  • the semiconductor device disclosed herein comprises a semiconductor chip including a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer plate being a laminate material or an alloy material having a Curie point of 300°C or higher, the laminate material having a first copper layer in contact with the buffer bonding material, an alloy layer having a Curie point of 300°C or higher provided on the first copper layer, and a second copper layer provided on the alloy layer.
  • FIG. 1 is a top view showing a semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a top view showing the semiconductor device according to the second embodiment.
  • FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment.
  • FIG. 5 is a diagram showing an example of the results of a power cycle test.
  • the purpose of this disclosure is to provide a semiconductor device that has a good lifespan even at high operating temperatures.
  • a semiconductor device includes a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer plate being a laminate material or an alloy material having a Curie point of 300°C or higher, the laminate material having a first copper layer in contact with the buffer bonding material, an alloy layer having a Curie point of 300°C or higher provided on the first copper layer, and a second copper layer provided on the alloy layer.
  • the buffer plate is an alloy material with a Curie point of 300°C or higher, or a laminated material with an alloy layer with a Curie point of 300°C or higher, the thermal expansion of the buffer plate is small at temperatures below 300°C. This also suppresses thermal deformation of the main electrode joined to the buffer plate by the buffer joining material. Therefore, even when used at high temperatures, internal destruction of the main electrode is suppressed, resulting in a good lifespan.
  • Internal destruction of the main electrode occurs when grain boundary sliding and cracks occurring at the grain boundaries of the crystals that make up the main electrode accumulate due to repeated thermal deformation. Internal destruction of the main electrode can be confirmed, for example, as a decrease in the density of the main electrode or an increase in the thickness of the main electrode. Furthermore, when internal destruction occurs in the main electrode, the effective bonding area between the main electrode and the components sandwiching it decreases. For this reason, internal destruction can also be confirmed as an increase in electrical or thermal series resistance.
  • Internal destruction of the main electrode can also occur in power cycle tests. That is, in power cycle tests, the temperature repeatedly rises and falls, which can cause grain boundary sliding and cracks to occur in succession, resulting in internal destruction. For example, in the later stages of a power cycle test, internal destruction of the main electrode can be confirmed as breakage or peeling of the main electrode, as a sudden increase in electrical resistance or a break in the electrical resistance, or as a sudden increase in thermal resistance or the occurrence of thermal runaway. These phenomena become particularly noticeable just before the end of the life.
  • the buffer bonding material may have a sintered body with a porosity of 5% or more and 40% or less.
  • the thermal stress acting on the buffer bonding material is reduced, and thermal deformation of the main electrode is suppressed. Therefore, it is easier to obtain a good lifespan.
  • the alloy material and the alloy layer may contain iron and nickel, and the proportion of nickel in the alloy material and the alloy layer may be 40 mass% or more. In this case, it is easy to obtain a Curie point of 300°C or more in the alloy material and the alloy layer.
  • the alloy material and the alloy layer may contain iron, nickel and cobalt, and the total proportion of nickel and cobalt in the alloy material and the alloy layer may be 40 mass% or more. In this case, it is easy to obtain a Curie point of 300°C or more in the alloy material and the alloy layer.
  • a semiconductor device includes a semiconductor chip having a semiconductor substrate and a main electrode provided on the semiconductor substrate, a buffer plate, and a buffer bonding material provided between the main electrode and the buffer plate, the buffer bonding material having a sintered body with a porosity of 5% or more and 40% or less.
  • the buffer bonding material be a sintered body with a porosity of 5% to 40%, the thermal stress acting on the buffer bonding material is reduced, and thermal deformation of the main electrode is suppressed. Therefore, even when used at high temperatures, internal destruction of the main electrode is suppressed, and a good lifespan is achieved.
  • the main electrode may include an aluminum layer or an aluminum alloy layer. In this case, it is easy to obtain good electrical conductivity in the main electrode.
  • the first linear expansion coefficient of the semiconductor substrate and the second linear expansion coefficient of the buffer plate may be smaller than the third linear expansion coefficient of the main electrode, and the second linear expansion coefficient may be smaller than the first linear expansion coefficient.
  • the third linear expansion coefficient is larger than the first linear expansion coefficient
  • the main electrode tends to thermally deform to a greater extent than the semiconductor substrate.
  • the second linear expansion coefficient is smaller than the first linear expansion coefficient, the thermal deformation of the main electrode can be effectively suppressed by the buffer bonding material. Therefore, it is possible to suppress the thermal stress generated in the main electrode due to thermal deformation, and to suppress internal destruction of the aluminum layer or aluminum alloy layer contained in the main electrode.
  • the grain size of the crystals that make up the aluminum layer or aluminum alloy layer is small, at only a few micrometers. For this reason, crystal grain boundaries exist at high density in the aluminum layer or aluminum alloy layer, and when thermal distortion occurs between the layers sandwiching the main electrode due to temperature rise and fall cycles during power cycle testing, grain boundary sliding is likely to overlap.
  • the thermal deformation of the main electrode can be effectively suppressed by the buffer bonding material, and internal destruction of the aluminum layer or aluminum alloy layer contained in the main electrode can be suppressed.
  • the plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane
  • the plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane
  • the plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane.
  • the Z1 direction is defined as the upward direction
  • the Z2 direction is defined as the downward direction.
  • planar view refers to viewing an object from the Z1 side.
  • the first embodiment relates to a semiconductor device.
  • Fig. 1 is a top view showing the semiconductor device according to the first embodiment.
  • Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 1.
  • the semiconductor device 1 mainly includes a heat sink 120, a substrate 110, a terminal 102, a terminal 103, a case 190, a diode 300, and a buffer plate 500.
  • the heat sink 120 is, for example, a rectangular plate of uniform thickness in a plan view.
  • the material of the heat sink 120 is a metal with high thermal conductivity, such as copper (Cu), copper alloy, aluminum (Al), aluminum-silicon-carbon alloy (Al-Si-C alloy), etc.
  • the heat sink 120 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.
  • Case 190 is formed, for example, in a frame shape when viewed from above, and the outer shape of case 190 is the same as the outer shape of heat sink 120.
  • Case 190 is made of an insulating material such as resin.
  • Case 190 has a pair of side walls 191 and 192 facing each other, and a pair of end walls 193 and 194 connecting both ends of side walls 191 and 192.
  • Side walls 191 and 192 are arranged parallel to the ZX plane, and end walls 193 and 194 are arranged parallel to the YZ plane.
  • Side wall 191 is arranged on the Y1 side of side wall 192, and end wall 193 is arranged on the X2 side of end wall 194.
  • Terminal 102 is disposed on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is disposed on the upper surface (surface on the Z1 side) of end wall portion 194.
  • Terminal 102 and terminal 103 are each made of a metal plate.
  • the substrate 110 is disposed inside the case 190 on the Z1 side of the heat sink 120.
  • the substrate 110 has an insulating substrate 119, a second conductive pattern 112, a third conductive pattern 113, and a conductive layer 115.
  • the first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.
  • the second conductive pattern 112 and the third conductive pattern 113 are provided on the Z1 side surface of the insulating substrate 119.
  • the conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119.
  • the conductive layer 115 is bonded to the heat sink 120 by a bonding material 131.
  • the bonding material 131 may be a solder material or a sintered bonding material. When the bonding material 131 is a sintered bonding material, operation at a temperature close to or higher than the melting point of the solder becomes possible.
  • the diode 300 mainly has a silicon carbide substrate 310, an anode electrode 332, and a cathode electrode 333.
  • the silicon carbide substrate 310 has a principal surface 310A and a principal surface 310B opposite to the principal surface 310A.
  • the principal surface 310A is on the Z1 side of the principal surface 310B.
  • the shape of the silicon carbide substrate 310 is, for example, a rectangular parallelepiped.
  • the principal surfaces 310A and 310B are parallel to the XY plane.
  • the anode electrode 332 is provided on the principal surface 310A, and the cathode electrode 333 is provided on the principal surface 310B.
  • the diode 300 is provided on the third conductive pattern 113.
  • the anode electrode 332 includes, for example, an aluminum layer.
  • the anode electrode 332 may include an aluminum alloy layer such as an aluminum-silicon alloy (Al-Si alloy) or an Al-Si-Cu alloy instead of the aluminum layer.
  • the cathode electrode 333 has an ohmic layer and a junction layer provided on the ohmic layer.
  • the ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide.
  • the bonding layer includes a nickel layer.
  • the bonding layer may further include a gold layer or a silver layer provided on the nickel layer.
  • the cathode electrode 333 has a bonding layer, so that good bonding is obtained between the cathode electrode 333 and the third conductive pattern 113.
  • the cathode electrode 333 is bonded to the third conductive pattern 113 using a bonding material 133 such as a silver sintered body or a copper sintered body.
  • the diode 300 is an example of a semiconductor chip.
  • the silicon carbide substrate 310 is an example of a semiconductor substrate.
  • the anode electrode 332 is an example of a main electrode.
  • the buffer plate 500 is, for example, a laminated material having a first copper layer 510, an alloy layer 520, and a second copper layer 530.
  • the alloy layer 520 is provided on the Z1 side of the first copper layer 510, and the second copper layer 530 is provided on the Z1 side of the alloy layer 520. That is, the alloy layer 520 is provided on the first copper layer 510, and the second copper layer 530 is provided on the alloy layer 520.
  • the alloy layer 520 is an alloy material having a Curie point of 300°C or higher.
  • the alloy layer 520 includes, for example, iron (Fe) and nickel (Ni), and the proportion of Ni in the alloy layer 520 is 40% by mass or more.
  • the alloy layer 520 includes, for example, Fe, Ni, and cobalt (Co), and the total proportion of Ni and Co in the alloy layer 520 may be 40% by mass or more.
  • the alloy layer 520 may include 29% by mass of Ni and 17% by mass of Co. In either case, the alloy layer 520 may contain Fe at a ratio of 45% by mass or more, or may contain Fe at a ratio of 48% by mass or more.
  • the alloy layer 520 may contain manganese at about 0.7% by mass.
  • the material of the alloy layer 520 may be Kovar (registered trademark).
  • the thickness T2 of the buffer plate 500 is, for example, 0.05 mm or more and 0.5 mm or less. The thickness T2 of the buffer plate 500 may be 0.05 mm or more and 0.25 mm or less.
  • the thickness T2 of the buffer plate 500 is smaller than the thickness T1 of the diode 300.
  • the buffer plate 500 is provided on the anode electrode 332.
  • the first copper layer 510 is bonded to the anode electrode 332 using a buffer bonding material 135 such as a silver sintered body or a copper sintered body.
  • the buffer bonding material 135 has a sintered body with a porosity of 5% to 40%.
  • the silicon carbide substrate 310 has a first linear expansion coefficient ⁇ 1, the buffer plate 500 has a second linear expansion coefficient ⁇ 2, and the anode electrode 332 has a third linear expansion coefficient ⁇ 3.
  • the linear expansion coefficient in the present disclosure is the linear expansion coefficient in a direction parallel to the main surface 310A at 25° C., unless otherwise specified.
  • the linear expansion coefficient in the present disclosure is the linear expansion coefficient when the silicon carbide substrate 310, the buffer plate 500, and the anode electrode 332 are separated from each other and are taken as a single body, unless otherwise specified.
  • the first linear expansion coefficient ⁇ 1 and the second linear expansion coefficient ⁇ 2 are smaller than the third linear expansion coefficient ⁇ 3.
  • the second linear expansion coefficient ⁇ 2 may be larger or smaller than the first linear expansion coefficient ⁇ 1, but when the difference between the first linear expansion coefficient ⁇ 1 and the second linear expansion coefficient ⁇ 2 is small, the thermal stress applied to the anode electrode 332 is easily suppressed.
  • the second linear expansion coefficient ⁇ 2 is smaller than the first linear expansion coefficient ⁇ 1, the life is more likely to be extended than when the second linear expansion coefficient ⁇ 2 is larger than the first linear expansion coefficient ⁇ 1.
  • the first linear expansion coefficient ⁇ 1 is 4.0 ⁇ 10 ⁇ 6 /°C
  • the second linear expansion coefficient ⁇ 2 is 1.2 ⁇ 10 ⁇ 6 /°C or more and 3.9 ⁇ 10 ⁇ 6 /°C or less.
  • the value of “ ⁇ 2 ⁇ 1” is ⁇ 2.8 ⁇ 10 ⁇ 6 /°C or more and ⁇ 0.1 ⁇ 10 ⁇ 6 /°C or less, and it is easier to obtain a longer life than when the value of “ ⁇ 2 ⁇ 1” is positive.
  • the linear expansion coefficient of an iron-nickel alloy is about 1.2 ⁇ 10 ⁇ 6 /°C
  • the linear expansion coefficient of copper is about 16.5 ⁇ 10 ⁇ 6 /°C
  • the linear expansion coefficient of aluminum is about 23.1 ⁇ 10 ⁇ 6 /°C.
  • the third linear expansion coefficient ⁇ 3 is about 23.1 ⁇ 10 ⁇ 6 /° C.
  • the semiconductor device 1 further includes wires 162, 165, and 166.
  • the number of each of the wires 162, 165, and 166 is not limited, and may be one or two or more.
  • Wire 162 connects the second copper layer 530 of the buffer plate 500 to the second conductive pattern 112.
  • Wire 165 connects the second conductive pattern 112 to the terminal 102.
  • Wire 166 connects the third conductive pattern 113 to the terminal 103.
  • Wires 162, 165 and 166 are, for example, copper wires.
  • Each of wires 162, 165 and 166 has a diameter of, for example, 100 ⁇ m or more and 400 ⁇ m or less.
  • Wires 162, 165 and 166 are joined by, for example, ultrasonic joining.
  • the lifespan of semiconductor devices used in power modules at their operating temperatures is evaluated by a power cycle test.
  • a semiconductor device sample is repeatedly energized and cut off.
  • the maximum junction temperature (Tjmax) is set as the operating temperature for which the lifespan is to be evaluated.
  • ⁇ T the difference between the maximum junction temperature (Tjmax) and the minimum junction temperature (Tjmin)
  • the difference ( ⁇ T) is 185°C, so it is determined that the sample has reached its life when the bonding temperature (Tj) reaches 287°C. Also, if the maximum bonding temperature (Tjmax) is 250°C and the minimum bonding temperature (Tjmin) is 25°C, the difference ( ⁇ T) is 225°C, so it is determined that the sample has reached its life when the bonding temperature (Tj) reaches 295°C.
  • the alloy layer 520 is an alloy material with a Curie point of 300°C or higher. In other words, at temperatures below 300°C, the thermal expansion of the alloy layer 520 is small. Therefore, in this embodiment, thermal deformation of the alloy layer 520 and the buffer plate 500 is suppressed in a power cycle test with a maximum junction temperature (Tjmax) of 250°C.
  • Tjmax maximum junction temperature
  • Thermal deformation of the buffer plate 500 is suppressed, so that thermal deformation of the anode electrode 332 joined to the buffer plate 400 by the buffer bonding material 135 is also suppressed. Therefore, according to this embodiment, even when used at high temperatures, it is possible to suppress the thermal stress that occurs in the anode electrode 332 due to thermal deformation, and to suppress internal destruction of the anode electrode 332.
  • the buffer bonding material 135 has a sintered body with a porosity of 5% or more and 40% or less.
  • the higher the porosity the lower the thermal stress acting on the buffer bonding material 135 when heated, and as a result, the thermal stress generated in the anode electrode 332 can be suppressed.
  • the thermal stress generated in the anode electrode 332 is 54 MPa when the porosity is 0%, 36 MPa when the porosity is 5%, and 10 MPa when the porosity is 30%.
  • the thermal stress when the porosity is 5%, the thermal stress is 34% lower than when the porosity is 0%, and when the porosity is 30%, the thermal stress is 72% lower than when the porosity is 5%.
  • stress analysis using the finite element method has confirmed that even when the temperature of the buffer bonding material 135 made of sintered copper is 250°C, the thermal stress generated in the anode electrode 332 is reduced when the porosity is 5% or more and 40% or less.
  • the effect of reducing thermal stress due to an increase in the porosity of the sintered body becomes more pronounced when the sintered body is used at high temperatures. This is because in the case of bulk Cu, the Young's modulus obtained from the stress-strain curve does not usually have temperature dependence. On the other hand, the stress-strain curve of a Cu sintered body does have temperature dependence, and the Young's modulus from the stress-strain curve becomes smaller at higher temperatures. It has also been confirmed by the stress analysis using the above-mentioned finite element method that this phenomenon acts in a favorable direction to suppress thermal deformation of the anode electrode 332. Furthermore, a similar temperature dependence has been confirmed not only for Cu sintered bodies but also for Ag sintered bodies.
  • the porosity of the sintered body contained in the buffer bonding material 135 may be 5% or more and 30% or less, or may be 5% or more and 20% or less.
  • the thermal stress acting on the buffer bonding material 135 is reduced, and thermal deformation of the anode electrode 332 is suppressed. Therefore, according to this embodiment, even when used at high temperatures, the thermal stress generated in the anode electrode 332 due to thermal deformation can be suppressed, and internal destruction of the anode electrode 332 can be suppressed.
  • the effect of the alloy layer 520 being an alloy material with a Curie point of 300°C or higher and the effect of the buffer bonding material 135 being a sintered body with a porosity of 5% to 40% are obtained, but the effect of combining these can also be obtained as described below.
  • Thermal stress occurring in the anode electrode 332 can be mainly caused by two factors.
  • the first factor is thermal distortion due to the difference between the second linear expansion coefficient ⁇ 2 of the buffer plate 500 and the first linear expansion coefficient ⁇ 1 of the silicon carbide substrate 310
  • the second factor is the temperature dependency of the Young's modulus of the buffer bonding material 135.
  • the first factor by reducing the difference between the second linear expansion coefficient ⁇ 2 and the first linear expansion coefficient ⁇ 1, thermal distortion can be suppressed in a wide temperature range from the minimum bonding temperature, which is the operating temperature, to the maximum bonding temperature.
  • the Young's modulus of the buffer bonding material 135 decreases with increasing temperature, so the effect of suppressing thermal distortion can be maintained in a wide temperature range.
  • a bonding material made of bulk copper material is used instead of the buffer bonding material 135, the effect of suppressing thermal distortion may be reduced because the copper bulk material does not have the temperature dependency of the Young's modulus.
  • the anode electrode 332 includes an aluminum layer or an aluminum alloy layer, it is easy to obtain good electrical conductivity in the anode electrode 332.
  • the first linear expansion coefficient ⁇ 1 of the silicon carbide substrate 310 and the second linear expansion coefficient ⁇ 2 of the buffer plate 500 are smaller than the third linear expansion coefficient ⁇ 3 of the anode electrode 332, and the second linear expansion coefficient ⁇ 2 is smaller than the first linear expansion coefficient ⁇ 1.
  • the anode electrode 332 tends to thermally deform more than the silicon carbide substrate 310.
  • the second linear expansion coefficient ⁇ 2 is smaller than the first linear expansion coefficient ⁇ 1, the thermal deformation of the anode electrode 332 can be effectively suppressed by the buffer bonding material 135. Therefore, the thermal stress generated in the anode electrode 332 due to thermal deformation can be suppressed, and internal destruction of the anode electrode 332 can be suppressed.
  • the wire 162 by joining the wire 162 to the buffer plate 500, the wire 162 can be electrically connected to the anode electrode 332 via the buffer plate 500. Therefore, even if ultrasonic joining is used to join the wire 162, damage to the diode 300 can be suppressed. If the wire 162 is a copper wire, it is easy to join the wire 162 to the second copper layer 530 of the buffer plate 500, and it is also easy to obtain low electrical resistance for the wire 162.
  • the buffer plate 500 does not have to include the first copper layer 510 and the second copper layer 530.
  • the buffer plate 500 may be composed of an alloy layer 520 such as Kovar, whose Curie point is 300° C. or higher.
  • the alloy layer 520 contains Fe and Ni, and the proportion of Ni in the alloy layer 520 is 40 mass% or more, the alloy layer 520 is likely to have a Curie point of 300°C or higher.
  • the alloy layer 520 contains Fe, Ni, and Co, and the total proportion of Ni and Co in the alloy layer 520 is 40 mass% or more, the alloy layer 520 is also likely to have a Curie point of 300°C or higher.
  • the porosity of the sintered body contained in the buffer bonding material 135 does not have to be 5% or higher and 40% or lower. Also, if the porosity of the sintered body contained in the buffer bonding material 135 is 5% or higher and 40% or lower, the Curie point of the alloy layer 520 does not have to be 300°C or higher.
  • multiple diodes 300 may be provided on the third conductive pattern 113. In this case, the multiple diodes 300 are electrically connected in parallel to each other.
  • Fig. 3 is a top view showing the semiconductor device according to the second embodiment.
  • Fig. 4 is a cross-sectional view showing the semiconductor device according to the second embodiment. Fig. 4 corresponds to a cross-sectional view taken along line IV-IV in Fig. 3.
  • the semiconductor device 2 mainly includes a heat sink 120, a substrate 110, a terminal 101, a terminal 102, a terminal 103, a case 190, a transistor 200, a diode 300, a buffer plate 400, and a buffer plate 500.
  • Terminals 101 and 102 are arranged on the upper surface (surface on the Z1 side) of end wall portion 193, and terminal 103 is arranged on the upper surface (surface on the Z1 side) of end wall portion 194.
  • terminal 102 is arranged on the Y2 side of terminal 101.
  • Terminals 101, 102, and 103 are each made of a metal plate.
  • the substrate 110 has an insulating substrate 119, a first conductive pattern 111, a second conductive pattern 112, a third conductive pattern 113, a fourth conductive pattern 114, and a conductive layer 115.
  • the first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113, the fourth conductive pattern 114, and the conductive layer 115 are made of Cu.
  • the first conductive pattern 111, the second conductive pattern 112, the third conductive pattern 113 and the fourth conductive pattern 114 are provided on the Z1 side surface of the insulating substrate 119.
  • the conductive layer 115 is provided on the Z2 side surface of the insulating substrate 119.
  • the transistor 200 mainly has a silicon carbide substrate 210, a gate electrode 231, a source electrode 232, and a drain electrode 233.
  • the silicon carbide substrate 210 has a principal surface 210A and a principal surface 210B opposite to the principal surface 210A.
  • the principal surface 210A is on the Z1 side of the principal surface 210B.
  • the shape of the silicon carbide substrate 210 is, for example, a rectangular parallelepiped.
  • the principal surfaces 210A and 210B are parallel to the XY plane.
  • the gate electrode 231 and the source electrode 232 are provided on the principal surface 210A, and the drain electrode 233 is provided on the principal surface 210B.
  • the transistor 200 is provided on the fourth conductive pattern 114.
  • the gate electrode 231 and the source electrode 232 include, for example, an aluminum layer.
  • the gate electrode 231 and the source electrode 232 may include an aluminum alloy layer such as an Al-Si alloy or an Al-Si-Cu alloy instead of the aluminum layer.
  • the drain electrode 233 has an ohmic layer and a junction layer provided on the ohmic layer.
  • the ohmic layer includes, for example, nickel or a nickel alloy. Nickel or a nickel alloy has good contact resistance with silicon carbide.
  • the bonding layer includes a nickel layer.
  • the bonding layer may further include a gold layer or a silver layer provided on the nickel layer.
  • the drain electrode 233 includes a bonding layer, so that good bonding is obtained between the drain electrode 233 and the fourth conductive pattern 114.
  • the drain electrode 233 is bonded to the fourth conductive pattern 114 using a bonding material 132 such as a silver sintered body or a copper sintered body.
  • the transistor 200 is an example of a semiconductor chip.
  • the silicon carbide substrate 210 is an example of a semiconductor substrate.
  • the source electrode 232 is an example of a main electrode.
  • the buffer plate 400 is, for example, a laminated material having a first copper layer 410, an alloy layer 420, and a second copper layer 430.
  • the alloy layer 420 is provided on the Z1 side of the first copper layer 410, and the second copper layer 430 is provided on the Z1 side of the alloy layer 420. That is, the alloy layer 420 is provided on the first copper layer 410, and the second copper layer 430 is provided on the alloy layer 420.
  • the alloy layer 420 is an alloy material having a Curie point of 300°C or higher.
  • the alloy layer 420 includes, for example, Fe and Ni, and the proportion of Ni in the alloy layer 420 is 40% by mass or more.
  • the alloy layer 420 includes, for example, Fe, Ni, and Co, and the total proportion of Ni and Co in the alloy layer 420 may be 40% by mass or more.
  • the alloy layer 420 may include 29% by mass of Ni and 17% by mass of Co. In either case, the alloy layer 420 may contain Fe at a ratio of 45% by mass or more, or may contain Fe at a ratio of 48% by mass or more.
  • the alloy layer 420 may contain manganese at about 0.7% by mass.
  • the material of the alloy layer 420 may be Kovar.
  • the thickness T4 of the buffer plate 400 is, for example, 0.05 mm or more and 0.5 mm or less.
  • the thickness T4 of the buffer plate 400 may be 0.05 mm or more and 0.25 mm or less.
  • the thickness T4 of the buffer plate 400 is smaller than the thickness T3 of the transistor 200.
  • the buffer plate 400 is provided on the source electrode 232.
  • the first copper layer 410 is bonded to the source electrode 232 using a buffer bonding material 134 such as a silver sintered body or a copper sintered body.
  • the buffer bonding material 134 has a sintered body with a porosity of 5% to 40%.
  • the silicon carbide substrate 210 has a first linear expansion coefficient ⁇ 1'
  • the buffer plate 400 has a second linear expansion coefficient ⁇ 2'
  • the source electrode 232 has a third linear expansion coefficient ⁇ 3'.
  • the linear expansion coefficient in this disclosure is the linear expansion coefficient in a direction parallel to the main surface 210A at 25°C.
  • the linear expansion coefficient in this disclosure is the linear expansion coefficient when the silicon carbide substrate 210, the buffer plate 400, and the source electrode 232 are released from the bonded state and are taken as a single body.
  • the first linear expansion coefficient ⁇ 1' and the second linear expansion coefficient ⁇ 2' are smaller than the third linear expansion coefficient ⁇ 3', and the second linear expansion coefficient ⁇ 2' is smaller than the first linear expansion coefficient ⁇ 1'.
  • the first linear expansion coefficient ⁇ 1' is 4.0 ⁇ 10 -6 /° C.
  • the second linear expansion coefficient ⁇ 2' is not less than 1.2 ⁇ 10 -6 /° C. and not more than 3.9 ⁇ 10 -6 /° C.
  • the value of " ⁇ 2'- ⁇ 1'" is not less than -2.8 ⁇ 10 -6 /° C. and not more than -0.1 ⁇ 10 -6 /° C.
  • the third linear expansion coefficient ⁇ 3' is about 23.1 ⁇ 10 -6 /° C.
  • the semiconductor device 2 further includes wires 161, 162, 163, 164, 165, and 166.
  • the number of each of the wires 161, 162, 163, 164, 165, and 166 is not limited, and may be one or two or more.
  • Wire 161 connects gate electrode 231 of transistor 200 to first conductive pattern 111.
  • Wire 162 connects second copper layer 430 of buffer plate 400 to second conductive pattern 112.
  • Wire 163 connects third conductive pattern 113 to fourth conductive pattern 114.
  • Wire 164 connects first conductive pattern 111 to terminal 101.
  • Wire 165 connects second conductive pattern 112 to terminal 102.
  • Wire 166 connects anode electrode 332 of diode 300 to terminal 103.
  • Wires 161, 162, 163, 164, 165 and 166 are, for example, copper wires.
  • Each of wires 161, 162, 163, 164, 165 and 166 has a diameter of, for example, 100 ⁇ m or more and 400 ⁇ m or less.
  • Wires 161, 162, 163, 164, 165 and 166 are joined, for example, by ultrasonic joining.
  • the alloy layer 420 is an alloy material with a Curie point of 300°C or higher. In other words, at temperatures below 300°C, the thermal expansion of the alloy layer 420 is small. Therefore, in this embodiment, in a power cycle test with a maximum bonding temperature (Tjmax) of 250°C, thermal deformation of the alloy layer 420 and the buffer plate 400 is suppressed.
  • Tjmax maximum bonding temperature
  • Thermal deformation of the buffer plate 400 is suppressed, so that thermal deformation of the source electrode 232 joined to the buffer plate 400 by the buffer bonding material 134 is also suppressed. Therefore, according to this embodiment, even when used at high temperatures, it is possible to suppress thermal stress that occurs in the source electrode 232 due to thermal deformation, and to suppress internal destruction of the source electrode 232.
  • the buffer bonding material 134 has a sintered body with a porosity of 5% or more and 40% or less. Therefore, as with the diode 300, the thermal stress acting on the buffer bonding material 134 is reduced, and thermal deformation of the source electrode 232 is suppressed. Therefore, according to this embodiment, even when used at high temperatures, the thermal stress generated in the source electrode 232 due to thermal deformation can be suppressed, and internal destruction of the source electrode 232 can be suppressed.
  • the porosity of the sintered body contained in the buffer bonding material 134 may be 5% or more and 30% or less, or 5% or more and 20% or less.
  • the source electrode 232 includes an aluminum layer or an aluminum alloy layer, it is easy to obtain good electrical conductivity in the source electrode 232.
  • the first linear expansion coefficient ⁇ 1' of the silicon carbide substrate 210 and the second linear expansion coefficient ⁇ 2' of the buffer plate 400 are smaller than the third linear expansion coefficient ⁇ 3' of the source electrode 232, and the second linear expansion coefficient ⁇ 2' is smaller than the first linear expansion coefficient ⁇ 1'.
  • the source electrode 232 tends to thermally deform more than the silicon carbide substrate 210.
  • the second linear expansion coefficient ⁇ 2' is smaller than the first linear expansion coefficient ⁇ 1', the thermal deformation of the source electrode 232 can be effectively suppressed by the buffer bonding material 134. Therefore, the thermal stress generated in the source electrode 232 due to thermal deformation can be suppressed, and internal destruction of the source electrode 232 can be suppressed.
  • the wire 162 by joining the wire 162 to the buffer plate 400, the wire 162 can be electrically connected to the source electrode 232 via the buffer plate 400. Therefore, even if ultrasonic joining is used to join the wire 162, damage to the transistor 200 can be suppressed. If the wire 162 is a copper wire, it is easy to join the wire 162 to the second copper layer 430 of the buffer plate 400, and it is also easy to obtain low electrical resistance for the wire 162.
  • the buffer plate 400 does not have to include the first copper layer 410 and the second copper layer 430.
  • the buffer plate 400 may be composed of an alloy layer 420 such as Kovar, whose Curie point is 300° C. or higher.
  • the alloy layer 420 contains Fe and Ni, and the proportion of Ni in the alloy layer 420 is 40 mass% or more, it is easy to obtain a Curie point of 300°C or higher in the alloy layer 420.
  • the alloy layer 420 contains Fe, Ni, and Co, and the total proportion of Ni and Co in the alloy layer 420 is 40 mass% or more, it is also easy to obtain a Curie point of 300°C or higher in the alloy layer 420.
  • the porosity of the buffer bonding material 134 does not have to be 5% or higher and 40% or lower. Also, if the porosity of the buffer bonding material 134 is 5% or higher and 40% or lower, the Curie point of the alloy layer 420 does not have to be 300°C or higher.
  • multiple transistors 200 may be provided on the fourth conductive pattern 114. In this case, the multiple transistors 200 are electrically connected in parallel to each other.
  • the temperature of the sample was raised from room temperature (25°C) to 65°C, and then a current of 125A was repeatedly passed and cut off. The current was passed for 1 second, and the cut-off time was 13 seconds.
  • the maximum junction temperature (Tjmax) which is the maximum value of the junction temperature (Tj) in each cycle, was 250°C, and the difference ( ⁇ T) between the maximum junction temperature and the minimum junction temperature (65°C) in each cycle was 185°C.
  • the voltage at which current begins to flow when a low current of about 100 mA is passed through the sample corresponds to the junction temperature (Tj) of the sample. Therefore, if a low current of 100 mA, which is sufficiently smaller than the current passed immediately after current is passed through the sample for each cycle of current and cutoff, is passed through the sample and the voltage at which current begins to flow at this time is measured, the temperature at which current begins to flow in each cycle can be converted into the maximum junction temperature (Tjmax). As the power cycle test progresses, the sample gradually deteriorates and the maximum junction temperature (Tjmax) gradually increases, so the lifespan in this test is defined as the state where the difference ( ⁇ T) has increased by 20% from the start of current flow.
  • the minimum junction temperature is 65°C and the maximum junction temperature is 250°C
  • the difference ( ⁇ T) is 185°C
  • the lifespan is defined as the state where the maximum junction temperature (Tjmax) has reached 287°C.
  • Figure 5 shows an example of the results of a power cycle test.
  • Figure 5 shows the results of a power cycle test for a total of four types of samples (samples No. 1, No. 2, No. 3, and No. 4). In this power cycle test, diodes were used as samples.
  • the horizontal axis of Figure 5 shows the number of times that current was turned on and off, and the vertical axis shows the maximum junction temperature (Tjmax).
  • Tjmax maximum junction temperature
  • Table 1 shows an overview of the buffer plate and buffer bonding material of the four types of samples. Table 1 also shows the proportions of Ni and Co that make up the alloy layer. In addition, Table 1 also shows the number of cycles at which the difference ( ⁇ T) increased by 20% (life).
  • the material of the alloy layer was Invar, the Curie point was 280°C, and the porosity of the sintered body contained in the buffer bonding material was 3%.
  • the life was 19,700 cycles.
  • sample No. 2 the material of the alloy layer was Kovar, the Curie point was 435°C, and the porosity of the sintered body contained in the buffer bonding material was 3%.
  • the lifespan was 45,400 cycles.
  • the lifespan of sample No. 2 was 2.3 times that of sample No. 1.
  • sample No. 3 the material of the alloy layer was Invar, the Curie point was 280°C, and the porosity of the sintered body contained in the buffer bonding material was 30%.
  • the lifespan was 49,900 cycles.
  • the lifespan of sample No. 3 was 2.5 times that of sample No. 1.
  • sample No. 4 the material of the alloy layer was Kovar, the Curie point was 435°C, and the porosity of the sintered body contained in the buffer bonding material was 30%. The lifespan was 135,100 cycles. The lifespan of sample No. 4 was 6.8 times that of sample No. 1.
  • samples No. 2, No. 3, and No. 4 which satisfy at least one of the following conditions: the Curie point of the alloy layer is 300°C or higher, or the sintered body contained in the buffer bonding material is 5% to 40%, showed excellent lifespans even under conditions where the operating temperature was as high as 250°C.
  • the Curie point of the alloy layer or alloy material may be 350°C or higher, or 400°C or higher.
  • the porosity of a sintered body is defined as the ratio of the total area of pores to the area of the cross section of the buffer plate observed under an electron microscope.
  • the cross section of the sample is usually mechanically polished, with great care taken not to block the pores. It is easier to determine the porosity more accurately by removing surface damage using a sputtering method after mechanical polishing, or by increasing the accelerating voltage of the electron beam when observing under an electron microscope to eliminate the effects of the surface layer.
  • the porosity of the sintered body can be adjusted according to the applied pressure during heat treatment in hydrogen gas to form the buffer bonding material. For example, if the applied pressure is 20 MPa, the porosity will be about 3%, and if the applied pressure is 3 MPa, the porosity will be about 30%.
  • an aluminum alloy layer may be used in place of the aluminum layer in the main electrode.
  • the material used for the buffer bonding material is not limited.
  • the buffer bonding material may be made of a sintered body of an intermetallic compound containing copper, silver, nickel, or copper and tin.
  • the sintered body of an intermetallic compound containing copper and tin can be obtained, for example, by a transient liquid phase sintering method.
  • the semiconductor chip may be a silicon carbide chip.
  • Silicon carbide chips have excellent high-temperature resistance and are less likely to break down even when used at high temperatures. Silicon carbide chips also have high mechanical properties. Furthermore, internal destruction of the main electrode is suppressed, making it easier for the semiconductor device as a whole to have a long life even at high temperatures.
  • Reference Signs List 1 2 Semiconductor device 101, 102, 103 Terminal 110 Substrate 111 First conductive pattern 112 Second conductive pattern 113 Third conductive pattern 114 Fourth conductive pattern 115 Conductive layer 119 Insulating substrate 120 Heat sink 131, 132, 133 Bonding material 134, 135 Buffer bonding material 161, 162, 163, 164, 165, 166: Wire 190 Case 191, 192 Side wall portion 193, 194 End wall portion 200 Transistor (semiconductor chip) 210 Silicon carbide substrate (semiconductor substrate) 210A, 210B Main surface 231 Gate electrode 232 Source electrode (main electrode) 233 Drain electrode 300 Diode (semiconductor chip) 310 Silicon carbide substrate (semiconductor substrate) 310A, 310B Main surface 332 Anode electrode (main electrode) 333 cathode electrode 400, 500 buffer plate 410, 510 first copper layer 420, 520 alloy layer 430, 530 second copper layer

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013098266A (ja) * 2011-10-31 2013-05-20 Hitachi Ltd 半導体装置及びその製造方法
WO2020054688A1 (ja) * 2018-09-12 2020-03-19 ローム株式会社 半導体装置
WO2020105476A1 (ja) * 2018-11-22 2020-05-28 ローム株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013098266A (ja) * 2011-10-31 2013-05-20 Hitachi Ltd 半導体装置及びその製造方法
WO2020054688A1 (ja) * 2018-09-12 2020-03-19 ローム株式会社 半導体装置
WO2020105476A1 (ja) * 2018-11-22 2020-05-28 ローム株式会社 半導体装置

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