WO2024201263A1 - 半導体装置、及び半導体装置の作製方法 - Google Patents

半導体装置、及び半導体装置の作製方法 Download PDF

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Publication number
WO2024201263A1
WO2024201263A1 PCT/IB2024/052819 IB2024052819W WO2024201263A1 WO 2024201263 A1 WO2024201263 A1 WO 2024201263A1 IB 2024052819 W IB2024052819 W IB 2024052819W WO 2024201263 A1 WO2024201263 A1 WO 2024201263A1
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Prior art keywords
conductive layer
layer
insulating layer
opening
transistor
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English (en)
French (fr)
Japanese (ja)
Inventor
井口貴弘
神長正美
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257032287A priority Critical patent/KR20250169542A/ko
Priority to JP2025509042A priority patent/JPWO2024201263A1/ja
Priority to CN202480018439.9A priority patent/CN120898538A/zh
Publication of WO2024201263A1 publication Critical patent/WO2024201263A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device having a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • Semiconductor devices having transistors are widely used in electronic devices. For example, in display devices, by reducing the area occupied by transistors, the pixel size can be reduced and higher definition can be achieved. For this reason, there is a demand for miniaturization of transistors.
  • Devices requiring high-definition display devices such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • display devices for example, light-emitting devices having organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs: Light Emitting Diodes) have been developed.
  • organic EL Electro Luminescence
  • LEDs Light Emitting Diodes
  • Patent document 1 discloses a high-definition display device that uses organic EL elements.
  • the saturation of the transistor decreases.
  • a driving transistor that controls a current flowing through a light-emitting element (also called a light-emitting device) of a pixel of a display device is miniaturized, the channel length of the driving transistor becomes shorter. If this reduces the saturation of the driving transistor, the current flowing through the light-emitting element becomes unstable, and the light emission luminance of the light-emitting element may become unstable.
  • the current flowing through the light-emitting element may vary over time, and even when a still image is being displayed, the light emission luminance of the light-emitting element may vary over time.
  • high saturation means that the change in current in the saturation region in the Id-Vd characteristics of the transistor is small (the slope is small).
  • low saturation means that the change in current in the saturation region in the Id-Vd characteristics of the transistor is large (the slope is large).
  • One of the objectives of one embodiment of the present invention is to provide a transistor with high saturation. Another objective is to provide a transistor with a fine size. Another objective is to provide a transistor with good electrical characteristics. Another objective is to provide a semiconductor device including such a transistor. Another objective is to provide a highly reliable semiconductor device. Another objective is to provide a display device that can display high-quality images.
  • one of the objectives is to provide a small semiconductor device. Or, one of the objectives is to provide a semiconductor device with low wiring resistance. Or, one of the objectives is to provide a semiconductor device that operates at high speed. Or, one of the objectives is to provide a low-cost semiconductor device. Or, one of the objectives is to provide a semiconductor device with low power consumption. Or, one of the objectives is to provide a high-definition display device. Or, one of the objectives is to provide a method for manufacturing a semiconductor device with high productivity. Or, one of the objectives is to provide a method for manufacturing a semiconductor device with low manufacturing cost. Or, one of the objectives is to provide a new transistor, semiconductor device, display device, or a manufacturing method thereof.
  • One aspect of the present invention includes a transistor and a first insulating layer, the transistor having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a second insulating layer, and a third insulating layer, the first insulating layer being provided on the first conductive layer and having a first opening reaching the first conductive layer, the second conductive layer being provided on the first insulating layer and having a second opening having a region overlapping with the first opening, the third conductive layer having a region in contact with a side of the first insulating layer located within the first opening, the third conductive layer having a region in contact with the first conductive layer, and the top of the third conductive layer being in contact with the first insulating layer.
  • the second insulating layer may have a region located on the first insulating layer, and the second conductive layer may be provided on the second insulating layer.
  • the semiconductor layer may contain a metal oxide.
  • the metal oxide has two or three elements selected from In, element M, and Zn, and element M may be one or more elements selected from Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.
  • one aspect of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, processing the second conductive layer to form a first opening having an area overlapping with the first conductive layer, processing the first insulating layer to form a second opening that reaches the first conductive layer so as to have an area overlapping with the first opening, forming a conductive film to cover the first opening and the second opening, and performing anisotropic etching on the conductive film to form a second conductive layer having an area in contact with the first conductive layer and having a lower surface end on the first opening side of the second conductive layer.
  • a method for manufacturing a semiconductor device includes forming a third conductive layer so as to be located below the opening, forming an insulating film so as to cover the second conductive layer and the third conductive layer, forming a second insulating layer covering the third conductive layer by performing anisotropic etching on the insulating film until at least a part of the upper surface of the second conductive layer is exposed, forming a semiconductor layer so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer, forming a third insulating layer so as to have a region located inside the second opening, and forming a fourth conductive layer on the third insulating layer so as to have a region located inside the second opening.
  • one aspect of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, processing the first insulating layer to form a first opening that reaches the first conductive layer, forming a conductive film to cover the first opening, and performing anisotropic etching on the conductive film to form a second conductive layer having an area in contact with the first conductive layer and whose uppermost portion is located below the top surface end of the first insulating layer on the first opening side, and forming a second insulating layer to cover the first conductive layer, the second conductive layer, and the first insulating layer.
  • a method for manufacturing a semiconductor device includes forming a third conductive layer on the second insulating layer, the third conductive layer having a second opening having a region overlapping with the first opening, forming a third opening in the second insulating layer that reaches the first conductive layer inside the first opening, forming a semiconductor layer so as to have a region in contact with the first conductive layer and a region in contact with the third conductive layer, forming a third insulating layer so as to have a region located inside the first opening, and forming a fourth conductive layer on the third insulating layer so as to have a region located inside the first opening.
  • the semiconductor layer may be formed by forming a semiconductor film using the ALD method and then processing the semiconductor film.
  • One embodiment of the present invention can provide a transistor with high saturation. Or a transistor with a fine size can be provided. Or a transistor with good electrical characteristics can be provided. Or a semiconductor device including such a transistor can be provided. Or a highly reliable semiconductor device can be provided. Or a display device capable of displaying high-quality images can be provided.
  • a small-sized semiconductor device can be provided.
  • a semiconductor device with low wiring resistance can be provided.
  • a semiconductor device that operates at high speed can be provided.
  • a low-cost semiconductor device can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a high-definition display device can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a method for manufacturing a semiconductor device with low manufacturing cost can be provided.
  • a new transistor, semiconductor device, display device, or a method for manufacturing these can be provided.
  • Fig. 1A is a plan view showing a configuration example of a semiconductor device
  • Fig. 1B and Fig. 1C are cross-sectional views showing the configuration example of the semiconductor device.
  • 2A to 2C are plan views showing configuration examples of a semiconductor device.
  • 3A is a plan view showing a configuration example of a semiconductor device
  • FIG. 3B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 4A and 4B are cross-sectional views showing a configuration example of a semiconductor device.
  • FIG. 5 is a cross-sectional view showing an example of the configuration of a semiconductor device.
  • 6A and 6B are plan and cross-sectional views illustrating a configuration example of a semiconductor device.
  • FIG. 7A, 7B1, and 7B2 are cross-sectional views showing configuration examples of a semiconductor device.
  • FIG. 8 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device.
  • 10A is a plan view showing a configuration example of a semiconductor device
  • FIG. 10B is a cross-sectional view showing the configuration example of a semiconductor device.
  • Fig. 11A is a plan view showing a configuration example of a semiconductor device
  • Fig. 11B and Fig. 11C are cross-sectional views showing the configuration example of a semiconductor device.
  • 12A to 12D are plan views showing examples of the shapes of the openings.
  • FIG. 13A is a block diagram showing a configuration example of a display device
  • Fig. 13B is a plan view showing a configuration example of a pixel
  • Fig. 13C and Fig. 13D are circuit diagrams showing a configuration example of a pixel
  • 14A to 14D are circuit diagrams showing examples of pixel configurations.
  • 15A is a plan view showing an example of the configuration of a pixel
  • FIG 15B is a cross-sectional view showing an example of the configuration of a pixel.
  • 16A to 16I are circuit diagrams showing configuration examples of a semiconductor device.
  • 17A and 17B are plan and cross-sectional views illustrating a configuration example of a semiconductor device.
  • 18A and 18B are cross-sectional views showing a configuration example of a semiconductor device.
  • 19A and 19B are cross-sectional views showing a configuration example of a semiconductor device.
  • 20A is a plan view showing a configuration example of a semiconductor device
  • FIG 20B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 21A and 21B are cross-sectional views showing a configuration example of a semiconductor device.
  • 22A is a plan view showing a configuration example of a semiconductor device
  • FIG 22B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 23A is a plan view showing a configuration example of a semiconductor device
  • FIG 23B is a cross-sectional view showing the configuration example of a semiconductor device.
  • FIG 24A is a plan view showing a configuration example of a semiconductor device
  • FIG 24B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 25A to 25C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 26A to 26C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 27A to 27C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 28A and 28B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 29A and 29B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 30A to 30C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 31A to 31C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 32A to 32C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 33A and 33B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 34A to 34G are plan views showing examples of pixel configurations.
  • 35A to 35K are plan views showing examples of pixel configurations.
  • FIG. 36 is a perspective view showing a configuration example of a display device.
  • 37A and 37B are cross-sectional views showing a configuration example of a display device.
  • FIG. 38 is a cross-sectional view showing a configuration example of a display device.
  • 39A to 39C are cross-sectional views showing configuration examples of a display device.
  • FIG. 40A and 40B are cross-sectional views showing a configuration example of a display device.
  • FIG. 41 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 42 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 43 is a cross-sectional view showing a configuration example of a display device.
  • 44A and 44B are cross-sectional views showing a configuration example of a display device.
  • 45A to 45D are diagrams showing an example of an electronic device.
  • 46A to 46F are diagrams showing an example of an electronic device.
  • 47A to 47G are diagrams showing an example of an electronic device.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances or situation.
  • conductive layer can be changed to the term “conductive film.”
  • insulating layer can be changed to the term “insulating film.”
  • semiconductor layer can be changed to the term “semiconductor film.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • electrically connected includes a connection via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • planar shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it may also be said that the planar shapes roughly match. Furthermore, when the planar shapes match or roughly match, it can also be said that the ends are aligned or roughly aligned.
  • planar shape of a certain component refers to the contour shape of the component when viewed in a plane.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a fine curvature, or approximately planar with fine irregularities.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • an oxide film includes a film having an oxynitride, and a nitride film includes a film having a nitride oxide.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom to select materials and configurations and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • the layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be called a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a vertical transistor, a vertical channel transistor, or a vertical channel transistor, etc.
  • an insulating layer that functions as a spacer is provided between a lower electrode, which is one of the source electrode or drain electrode of a transistor, and an upper electrode, which is the other.
  • the insulating layer that functions as a spacer may be simply referred to as a spacer, but the spacer may also be interpreted as an insulating layer.
  • the spacer is provided with a first opening that reaches the lower electrode, and the upper electrode is provided with a second opening that has an area that overlaps with the first opening.
  • the semiconductor layer in which the channel is formed is provided so as to have a region in contact with the lower electrode and a region in contact with the upper electrode, and also a region located inside the first opening and a region located inside the second opening.
  • a gate insulating layer and a gate electrode are provided overlapping the semiconductor layer. Since the source electrode, semiconductor layer, and drain electrode can be provided overlapping, the occupied area can be significantly reduced compared to so-called planar type transistors in which the semiconductor layer is arranged on a flat surface.
  • the channel length direction of the transistor with the above configuration has a vertical component
  • the channel length can be set to a value smaller than the limit resolution of the exposure device. This makes it possible to provide, for example, a transistor with a large on-current.
  • the saturation of the transistor may decrease. Therefore, for example, when the above transistor is applied to a drive transistor of a light-emitting device, the current flowing through the light-emitting element may become unstable, and the light emission brightness of the light-emitting element may become unstable. For example, the current flowing through the light-emitting element may vary over time, and even when a still image is displayed, the light emission brightness of the light-emitting element may vary over time.
  • a driving transistor of a light-emitting device refers to a transistor that has a function of controlling a current flowing to a light-emitting element of a pixel of a display device.
  • one of the source or drain of the driving transistor can be electrically connected to one electrode of the light-emitting element.
  • one electrode of the capacitance can be electrically connected to one of the source or drain of the driving transistor and one electrode of the light-emitting element, and the other electrode of the capacitance can be electrically connected to the gate of the driving transistor.
  • a backgate electrode is provided in the transistor according to one embodiment of the present invention.
  • the backgate electrode is provided inside a first opening of the spacer.
  • the backgate electrode is provided so as to have a region in contact with a side surface located in the first opening of the spacer and a region in contact with an upper surface of the lower electrode.
  • the gate electrode may be called a front gate electrode.
  • the gate electrode may be called a first gate electrode
  • the backgate electrode may be called a second gate electrode.
  • the backgate electrode may be called a first gate electrode
  • the gate electrode may be called a second gate electrode.
  • the backgate electrode is electrically connected to the lower electrode, which is one of the source electrode and drain electrode of the transistor.
  • the lower electrode functions as the source electrode of the transistor
  • DIBL drain-induced barrier lowering
  • the saturation of the transistor can be increased.
  • the display device can display a high-quality image. Note that when the lower electrode functions as the drain electrode of the transistor, the transistor of one embodiment of the present invention can function as a diode.
  • a lower electrode, a spacer, and an upper electrode are formed in this order.
  • a second opening is formed in the upper electrode, and a first opening is formed in the spacer.
  • a conductive film is formed so as to cover the first opening.
  • the conductive film is formed so as to cover the side surface of the spacer located within the first opening, and the upper surface of the lower electrode exposed by the first opening.
  • the conductive film is formed so as to have a region in contact with the side surface located within the first opening of the spacer, and a region in contact with the lower electrode.
  • anisotropic etching is performed on the conductive film. This allows a backgate electrode to be formed inside the first opening so as to be electrically connected to the lower electrode.
  • the backgate electrode can be formed along the side surface located within the first opening of the spacer so as to have a region inside the first opening that contacts the lower electrode.
  • an insulating film is formed so as to cover the back gate electrode.
  • anisotropic etching is performed on the insulating film to form a back gate insulating layer so as to cover the back gate electrode.
  • the gate insulating layer may be called a front gate insulating layer.
  • the gate insulating layer may be called a first gate insulating layer
  • the back gate insulating layer may be called a second gate insulating layer.
  • the back gate insulating layer may be called a first gate insulating layer
  • the gate insulating layer may be called a second gate insulating layer.
  • a semiconductor layer, a gate insulating layer, and a gate electrode are formed.
  • a transistor according to one embodiment of the present invention can be formed.
  • the back gate electrode is formed by anisotropic etching, unlike when the back gate electrode is formed by, for example, photolithography, there is no need to use a mask. Therefore, by using anisotropic etching, the back gate electrode can be formed without considering, for example, the accuracy of mask alignment. As described above, even if the first opening in which the back gate electrode is formed is miniaturized, it is possible to prevent, for example, the back gate electrode from not being formed inside the first opening. Therefore, the transistor of one embodiment of the present invention can be a transistor of a fine size.
  • ⁇ Configuration Example 1 of Semiconductor Device> 1A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100. Some components are not illustrated in FIG. Some components are also not illustrated in the plan views illustrated later.
  • FIG. 1B is a cross-sectional view taken along dashed line A1-A2 in FIG. 1A
  • FIG. 1C is a cross-sectional view taken along dashed line B1-B2 in FIG. 1A.
  • FIGS. 2A, 2B, and 2C are plan views of FIG. 1A with some elements omitted.
  • the insulating layer 110 has a laminated structure of an insulating layer 110a on the substrate 102 and on the conductive layer 112a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. That is, FIG. 1B and FIG. 1C show an example in which the insulating layer 110 has a three-layer laminated structure. Note that the insulating layer 110 does not have to have a three-layer laminated structure, and may have, for example, a single-layer structure.
  • the insulating layer 110a can have a region in contact with the upper surface of the conductive layer 112a and a region in contact with the side surface of the conductive layer 112a.
  • the insulating layer 110c can have a region in contact with the lower surface of the conductive layer 112b.
  • the conductive layer 112b can have a region in contact with the upper surface of the insulating layer 110c.
  • the top of the conductive layer 103 is preferably located below the end of the upper surface of the insulating layer 110 on the opening 141 side. In other words, the conductive layer 103 is preferably not provided inside the opening 143 of the conductive layer 112b. This prevents, for example, the conductive layer 103 and the conductive layer 112b from contacting each other and causing a short circuit. Note that, although FIG. 1B and FIG.
  • the conductive layer 103 may have an area in contact with the side surface of the insulating layer 110c located in the opening 141.
  • the conductive layer 103 can be formed by forming a conductive film so as to cover the openings 141 and 143, and then performing anisotropic etching on the conductive film. This allows the conductive layer 112a to be formed inside the opening 141 so as to be electrically connected to the conductive layer 112a.
  • the conductive layer 103 is formed by anisotropic etching, unlike when the conductive layer 103 is formed by, for example, photolithography, there is no need to use a mask. Therefore, by using anisotropic etching, the conductive layer 103 can be formed without considering, for example, the accuracy of mask alignment. As described above, even if the opening 141 in which the conductive layer 103 is formed is miniaturized, it is possible to prevent, for example, the conductive layer 103 from not being formed inside the opening 141. Therefore, the transistor 100 can be a transistor of a fine size.
  • the insulating layer 105 is provided so as to cover the conductive layer 103 inside the opening 141.
  • the insulating layer 105 has, for example, a region in contact with the conductive layer 103 inside the opening 141 and a region in contact with the conductive layer 112a.
  • the insulating layer 105 can be formed by forming an insulating film to cover the openings 141 and 143, and then performing anisotropic etching on the insulating film.
  • the top of the insulating layer 105 can be made to coincide or approximately coincide with the upper surface of the conductive layer 112b.
  • the insulating layer 105 can have a region that contacts the side of the conductive layer 112b located within the opening 143.
  • the insulating layer 105a may be provided so as to cover at least a portion of the side of the conductive layer 112b, specifically, the side opposite the opening 143.
  • the insulating layer 105a may have a region in contact with the side of the conductive layer 112b opposite the opening 143.
  • the insulating layer 105a may be formed due to the formation process of the insulating layer 105. For example, when the top of the insulating layer 105 is located above the upper surface of the insulating layer 110, for example, the upper surface end of the insulating layer 110 on the opening 141 side, the insulating layer 105a may be provided.
  • the insulating layer 105a when the insulating layer 105 has a region in contact with the side located within the opening 143 of the conductive layer 112b, the insulating layer 105a may be provided.
  • the insulating layer 105a is formed, for example, as a residue when the insulating layer 105 is formed. Note that the insulating layer 105a may not be provided in some cases. For example, if the top of the insulating layer 105 coincides with the top surface of the insulating layer 110, for example, the top surface edge of the insulating layer 110 on the opening 141 side, or is located below the top surface of the insulating layer 110, the insulating layer 105a may not be provided.
  • the insulating layer 105 By forming the insulating layer 105 so that the insulating layer 105a is provided, it is possible to prevent the conductive layer 103 from being exposed by the above-mentioned anisotropic etching. This makes it possible to prevent the conductive layer 103 and the semiconductor layer 108 from coming into contact with each other and causing a short circuit.
  • FIG. 2A is a diagram in which the conductive layer 104 and the semiconductor layer 108 are omitted from FIG. 1A.
  • the insulating layer 105 is provided inside the opening 141 and the opening 143 so as to follow the outer periphery of the opening 141 and the opening 143 in a plan view.
  • FIG. 2B is a diagram in which the insulating layer 105 is further omitted from FIG. 2A. As shown in FIGS. 1B, 1C, and 2B, the conductive layer 103 is provided inside the opening 141 so as to follow the outer periphery of the opening 141 in a plan view.
  • Figure 2C is a diagram in which the insulating layer 110 is further omitted from Figure 2B. As shown in Figure 2C, the opening 143 of the conductive layer 112b has an area that overlaps with the conductive layer 103.
  • the semiconductor layer 108 has a region located inside the opening 141 and a region located inside the opening 143.
  • the semiconductor layer 108 is provided so as to cover the insulating layer 105.
  • the semiconductor layer 108 has a region in contact with the conductive layer 112a, a region in contact with the insulating layer 105, and a region in contact with the conductive layer 112b.
  • the semiconductor layer 108 is provided so as to have a region facing the conductive layer 103 through the insulating layer 105 inside the opening 141. In other words, the semiconductor layer 108 is provided so as to have a region overlapping with the semiconductor layer 108 through the insulating layer 105 inside the opening 141.
  • the insulating layer 106 is provided on the insulating layer 110 so as to cover the insulating layer 105a, the conductive layer 112b, and the semiconductor layer 108.
  • the insulating layer 106 is provided on the semiconductor layer 108 so as to have a region located inside the opening 141 and a region located inside the opening 143.
  • the insulating layer 106 functions as a gate insulating layer for the transistor 100.
  • the insulating layer 105a is provided between the insulating layer 110 and the insulating layer 106. As described above, the insulating layer 105a can have a region that contacts the side of the conductive layer 112b opposite the opening 143.
  • the conductive layer 104 is provided on the insulating layer 106.
  • the conductive layer 104 has a region located inside the opening 141 and a region located inside the opening 143.
  • the conductive layer 104 is provided so as to have a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween inside the opening 141 and inside the opening 143.
  • the conductive layer 104 is provided so as to have a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween inside the opening 141 and the opening 143.
  • the conductive layer 104 functions as a gate electrode of the transistor 100.
  • the semiconductor layer 108 is provided in the opening 141 so as to have a region facing the conductive layer 103 via the insulating layer 105.
  • the conductive layer 104 is provided in the opening 141 so as to have a region facing the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 is provided in the opening 141 so as to have a region facing the conductive layer 103 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106.
  • the conductive layer 103 and the conductive layer 104 have a region overlapping with each other via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106 within the opening 141.
  • the conductive layer 103 can be referred to as a backgate electrode.
  • the conductive layer 104 can be referred to as a front gate electrode.
  • the conductive layer 104 can be referred to as a first gate electrode, and the conductive layer 103 can be referred to as a second gate electrode.
  • the conductive layer 103 can be referred to as a first gate electrode, and the conductive layer 104 can be referred to as a second gate electrode.
  • the conductive layer 103 will be referred to as a backgate electrode.
  • the back gate electrode of the transistor 100 has a region that contacts the upper surface of the conductive layer 112a inside the opening 141. Therefore, the potential of the conductive layer 112a is supplied to the back gate electrode of the transistor 100. As a result, when the conductive layer 112a functions as the source electrode of the transistor 100, the occurrence of the DIBL effect is suppressed. Therefore, the transistor 100 can be a transistor with higher saturation than, for example, a transistor that does not have the conductive layer 103. In addition, by using the highly saturated transistor 100 as a driving transistor of a display device, specifically a light-emitting device, the display device can display a high-quality image. Note that when the conductive layer 112a functions as the drain electrode of the transistor 100, the transistor 100 can function as a diode.
  • a driving transistor of a light-emitting device refers to a transistor that has the function of controlling the current flowing to a light-emitting element of a pixel of a display device.
  • one of the source or drain of the driving transistor can be electrically connected to one electrode of the light-emitting element.
  • the conductive layers 112a, 112b, and 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • An insulating layer 107 is provided on the conductive layer 104 and on the insulating layer 106.
  • the insulating layer 107 is provided so as to cover the conductive layer 104.
  • the insulating layer 107 functions as a protective layer. It is preferable to use a material that does not easily diffuse impurities for the insulating layer 107. By providing the insulating layer 107, it is possible to preferably suppress the diffusion of impurities from the outside into the transistor 100, and to improve the reliability of the semiconductor device. Examples of impurities include water and hydrogen.
  • the insulating layer 107 has one or both of an inorganic insulating film and an organic insulating film.
  • the insulating layer 107 may have a stacked structure of an inorganic insulating film and an organic insulating film.
  • the insulating layer 107 can be made of a material that can be used for the insulating layer 110.
  • inorganic insulating films that can be used for the insulating layer 107 include oxide insulating films and nitride insulating films.
  • the insulating layer 107 can be made of one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.
  • an organic insulating film is used for the insulating layer 107, for example, one or both of acrylic resin and polyimide resin can be used.
  • FIG. 3A is a plan view showing a configuration example of a semiconductor device of one embodiment of the present invention, and shows a configuration example of a transistor 100.
  • the width D143 and the channel width W100 are shown in the plan view shown in FIG. 1A.
  • FIG. 3B is an enlarged view including the configuration shown in FIG. 1B, and shows a configuration example of a transistor 100.
  • the cross-sectional view shown in FIG. 3B corresponds to the dashed dotted line A1-A2 shown in FIG. 3A.
  • the width D143, the channel width W100, the channel length L100, the thickness T110, and the angle ⁇ 110 are shown.
  • the region in contact with the conductive layer 112a functions as one of the source region and the drain region
  • the region in contact with the conductive layer 112b functions as the other of the source region and the drain region
  • the channel length L100 of the transistor 100 is indicated by a dotted double-headed arrow. As shown in FIG. 3B, the channel length L100 can be the shortest distance between the portion of the semiconductor layer 108 that contacts the conductive layer 112a and the portion that contacts the conductive layer 112b in a cross-sectional view.
  • the channel length L100 of the transistor 100 is determined by the thickness T110 of the insulating layer 110 and the angle ⁇ 110 between the side located in the opening 141 of the insulating layer 110 and the surface on which the insulating layer 110 is to be formed (here, the upper surface of the conductive layer 112a). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized with conventional exposure devices for mass production of flat panel displays (for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m). In addition, it is also possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure devices used in cutting-edge LSI technology.
  • the channel length L100 is preferably 0.01 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.05 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Therefore, by applying the semiconductor device of one embodiment of the present invention to a display device, the frame frequency of the display device can be increased.
  • the channel length L100 can be controlled by adjusting the thickness T110 and angle ⁇ 110 of the insulating layer 110. Note that in FIG. 3B, the thickness T110 of the insulating layer 110 is indicated by a dashed double-headed arrow.
  • the thickness T110 of the insulating layer 110 is preferably 0.01 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.05 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.15 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m
  • the channel width W100 is determined by the planar shape of the opening 143.
  • the width D143 of the opening 143 is indicated by a two-dot dashed double arrow.
  • the width D143 indicates the short side of the smallest rectangle that circumscribes the opening 143 in a planar view.
  • the width D143 of the opening 143 is equal to or greater than the limit resolution of the exposure device.
  • the width D143 is, for example, preferably 0.20 ⁇ m or more and less than 5.0 ⁇ m, more preferably 0.20 ⁇ m or more and less than 4.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 4.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.5 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m, even more preferably 0.20 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.5 ⁇ m, even more preferably 0.30 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and less than 1.2 ⁇ m, even more preferably 0.40 ⁇ m or more and
  • the width D143 corresponds to the diameter of the opening 143
  • the channel width W10 can be made equal to the length of the outer periphery of the opening 143 in a planar view, and can be calculated as "D143 x ⁇ ".
  • the width of the opening 141 and the width of the opening 143 may differ from each other. Furthermore, the width of the opening 141 and the width of the opening 143 may each vary in the depth direction.
  • the width of the opening may be, for example, the average value of the width at the highest point of the insulating layer 110 in a cross-sectional view, the width at the lowest point, and the width at the midpoint between these.
  • the width of the opening may be, for example, any of the width at the highest point of the insulating layer 110 in a cross-sectional view, the width at the lowest point, and the width at the midpoint between these.
  • the planar shape of opening 141 and opening 143 are each circular.
  • the processing accuracy when forming the openings can be improved, and openings of fine size can be formed.
  • a circle is not limited to a perfect circle.
  • planar shape of the opening 141 refers to the shape of the upper end of the insulating layer 110 on the opening 141 side.
  • planar shape of the opening 143 refers to the shape of the lower end of the conductive layer 112b on the opening 143 side.
  • the planar shapes of the openings 141 and 143 can be made to match or roughly match each other.
  • the bottom surface end of the conductive layer 112b on the opening 143 side match or roughly match the top surface end of the insulating layer 110 on the opening 141 side.
  • the bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side.
  • the side surface located in the opening 141 of the insulating layer 110 is preferably tapered or vertical.
  • the angle ⁇ 110 between the side surface located in the opening 141 of the insulating layer 110 and the surface on which the insulating layer 110 is to be formed is preferably 90 degrees or less.
  • the coverage of the layer (e.g., the semiconductor layer 108) provided on the insulating layer 110 can be improved.
  • Figures 1B, 1C, and 3B show an example in which the side surface located in the opening 141 of the insulating layer 110 is tapered (angle ⁇ 110 is less than 90 degrees).
  • the top of the conductive layer 103 is portion 121.
  • the upper end of the insulating layer 110 on the opening 141 side is portion 123.
  • portion 121 is located below portion 123. This prevents, for example, the conductive layer 103 and the conductive layer 112b from contacting each other and causing a short circuit.
  • FIG. 3B shows an example in which the conductive layer 103 contacts the side surfaces of the insulating layer 110a and the insulating layer 110b located in the opening 141, but does not contact the side surface of the insulating layer 110c located in the opening 141, but the conductive layer 103 may have an area in contact with the side surface of the insulating layer 110c located in the opening 141.
  • region 125 a region of the semiconductor layer 108 facing the conductive layer 103 is referred to as region 125.
  • Region 125 faces the conductive layer 103 via the insulating layer 105.
  • region 127 a region of the conductive layer 104 functioning as the gate electrode of the transistor 100 facing the conductive layer 103 is referred to as region 127.
  • Region 127 and the conductive layer 103 face each other via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106.
  • the electric field of the conductive layer 103 functioning as a back gate electrode can be applied to the region 125.
  • the electric field of the conductive layer 103 can also be applied to a region near the region 125 in some cases.
  • the conductive layer 103 is supplied with the potential of the conductive layer 112a functioning as one of the source electrode or drain electrode of the transistor 100.
  • the transistor 100 can be a transistor with higher saturation than, for example, a transistor without the conductive layer 103.
  • the shorter the distance between the portion 121 and the portion 123 in other words, the smaller the difference between the height of the portion 123 from the surface of the substrate 102 and the height of the portion 121 from the surface of the substrate 102, the larger the area of the region 125 can be. Therefore, the area of the region to which the electric field of the conductive layer 103 is not supplied in the channel formation region of the semiconductor layer 108 can be reduced. Therefore, the occurrence of the DIBL effect can be suitably suppressed, and the saturation of the transistor 100 can be improved.
  • the longer the distance between the portion 121 and the portion 123 in other words, the larger the difference between the height of the portion 123 from the surface of the substrate 102 and the height of the portion 121 from the surface of the substrate 102, the more it is possible to suppress the conductive layer 103 and the conductive layer 112b from coming into contact with each other and causing a short circuit.
  • the height of the portion 121 from the surface of the substrate 102 is as high as possible within a range in which the conductive layer 103 does not come into contact with the conductive layer 112b.
  • the greater the height of portion 121 from the surface of substrate 102 the larger the area of not only region 125 but also region 127 can be.
  • FIG. 3B shows an example in which the top of the insulating layer 105 and the top of the insulating layer 105a coincide or approximately coincide with the top surface of the conductive layer 112b. Specifically, an example is shown in which the top of the insulating layer 105 coincides or approximately coincides with the top surface end of the conductive layer 112b on the opening 143 side, and the top of the insulating layer 105a coincides or approximately coincides with the top surface end of the conductive layer 112b opposite the opening 143, but one embodiment of the present invention is not limited to this.
  • FIG. 4A is a cross-sectional view showing an example in which the top of the insulating layer 105 and the top of the insulating layer 105a are located between the bottom surface and the top surface of the conductive layer 112b.
  • the top of the insulating layer 105 is located between the bottom surface end and the top surface end of the conductive layer 112b on the opening 143 side.
  • the top of the insulating layer 105a is located between the bottom surface end and the top surface end of the conductive layer 112b opposite the opening 143.
  • Figure 4B is a cross-sectional view showing an example in which the top of insulating layer 105 is located below the bottom surface of conductive layer 112b.
  • the top of insulating layer 105 is located below the bottom surface end of conductive layer 112b on the opening 143 side.
  • the top of insulating layer 105 can be located below portion 123, which is the top surface end of insulating layer 110 on the opening 141 side.
  • the insulating layer 105a When the top of the insulating layer 105 is located below the bottom surface of the conductive layer 112b, the insulating layer 105a may not be provided. Note that even when the top of the insulating layer 105 is located above the bottom surface of the conductive layer 112b, the insulating layer 105a may not be provided.
  • top of the insulating layer 105 is located between the bottom surface and the top surface of the insulating layer 110c, but this is not a limitation of one embodiment of the present invention.
  • the top of the insulating layer 105 may be located between the bottom surface and the top surface of the insulating layer 110b.
  • the semiconductor layer 108 can have a region in contact with not only the top surface of the conductive layer 112b but also the side surface located within the opening 143. This allows the contact area between the semiconductor layer 108 and the conductive layer 112b to be larger than when the transistor 100 has the configuration shown in FIG. 3B, for example. This allows the contact resistance between the semiconductor layer 108 and the conductive layer 112b to be reduced. This makes it possible to prevent defects such as poor contact in the transistor 100. On the other hand, by configuring the transistor 100 as shown in FIG. 3B, it is easier to prevent the semiconductor layer 108 and the conductive layer 103 from coming into contact with each other and causing a short circuit than when the transistor 100 has the configuration shown in FIG. 4A or FIG. 4B.
  • Figure 5 is a cross-sectional view showing an example in which the thickness of the conductive layer 112a shown in Figure 3B in the region in contact with the bottom surface of the semiconductor layer 108 or the bottom surface of the insulating layer 105 is thinner than the thickness in the region overlapping with the conductive layer 103 or the insulating layer 110.
  • a recess 129 is formed in the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 or the bottom surface of the insulating layer 105.
  • height H104 is the height from the surface on which conductive layer 112a is formed (here, the upper surface of substrate 102) to the lowest point on the lower surface of conductive layer 104.
  • Height H112 is the height from the upper surface of substrate 102 to the lower surface of insulating layer 110 or conductive layer 103.
  • Height H112 can be the thickness of conductive layer 112a in the area other than recess 129.
  • the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a can be strengthened, and the on-current of the transistor 100 can be increased.
  • the electric field of the gate electrode applied to the channel formation region can be made uniform. Note that even if the height H104 is equal to or approximately equal to the height H112, the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a can be strengthened. In addition, the electric field of the gate electrode applied to the channel formation region can be made uniform.
  • the electrical characteristics when the conductive layer 112a is the source electrode and the conductive layer 112b is the drain electrode may differ from the electrical characteristics when the conductive layer 112a is the drain electrode and the conductive layer 112b is the source electrode.
  • the transistor 100 can be suitably used in a circuit configuration in which the source and drain are interchanged.
  • region 125 is not limited to the region facing the conductive layer 103 through the insulating layer 105 of the semiconductor layer 108, but also includes the region facing the conductive layer 112a through the insulating layer 105.
  • the thickness of the conductive layer 112a may be adjusted as appropriate so that the height H104 is, for example, lower than the height H112.
  • the configuration of the conductive layer 112a shown in FIG. 5 may also be applied to other configuration examples, for example, configuration examples shown in other drawings.
  • the conductive layer 112a shown in FIG. 4A may have a recess 129.
  • the conductive layer 112a shown in FIG. 4B may have a recess 129.
  • FIGS. 6A, 6B, and 7A are diagrams showing an example in which the conductive layer 112a has a two-layer laminated structure of a conductive layer 112a1 and a conductive layer 112a2 having an area located on the conductive layer 112a1.
  • FIG. 6A is a plan view showing an example of the configuration of the conductive layer 112a1, the conductive layer 112a2, the conductive layer 103, the opening 141, and the opening 143. Note that in FIG. 6A, the conductive layer 103 is not hatched.
  • FIG. 6A the conductive layer 103 is not hatched.
  • FIG. 6B is a cross-sectional view of the conductive layer 112a shown in FIG. 5, corresponding to the plan view shown in FIG. 6A.
  • FIG. 6B is a cross-sectional view between the dashed lines A1-A2 shown in FIG. 6A.
  • FIG. 7A is a cross-sectional view between the dashed lines B1-B2 shown in FIG. 6A.
  • the conductive layer 112a2 is provided so as to cover the side surface of the conductive layer 112a1.
  • the conductive layer 112a2 is removed.
  • the bottom surface of the semiconductor layer 108 has a region in contact with the upper surface of the conductive layer 112a1.
  • the bottom surface of the insulating layer 105 has a region in contact with the upper surface of the conductive layer 112a1, and the side surface of the insulating layer 105 can have a region in contact with the side surface of the conductive layer 112a2.
  • the bottom surface of the conductive layer 103 has a region in contact with the upper surface of the conductive layer 112a2.
  • the thickness of the conductive layer 112a1 in the region overlapping the recess 129 is equal to the thickness of the conductive layer 112a1 in the region not overlapping the recess 129, but one aspect of the present invention is not limited to this.
  • the thickness of the conductive layer 112a1 in the region overlapping the recess 129 may be thinner than the thickness of the conductive layer 112a1 in the region not overlapping the recess 129. That is, in the recess 129, not only the conductive layer 112a2 but also a part of the conductive layer 112a1 may be processed.
  • the conductive layer 112a2 may be provided without exposing the upper surface of the conductive layer 112a1. That is, in the recess 129, the conductive layer 112a2 may not be completely removed and a part may remain. In this case, it can be said that the recess 129 is formed in the conductive layer 112a2.
  • the film thickness of the conductive layer 112a2 in the recess 129 is thinner than the film thickness of the conductive layer 112a2 in the area other than the recess 129.
  • the conductive layer 112a2 has a region extending in the A1-A2 direction. Therefore, it is preferable to use a material with low electrical resistivity for the conductive layer 112a2, for example, a material with electrical resistivity lower than that of the conductive layer 112a1, since this reduces the wiring resistance of the conductive layer 112a.
  • the conductive layer 112a1 can be made of a conductive oxide such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide.
  • the conductive layer 112a2 can be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the metal element.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the metal element.
  • the conductive layer 103 it is preferable to use a material with low electrical resistivity for the conductive layer 103, since the wiring resistance of the conductive layer 103 can be reduced.
  • the conductive layer 103 it is preferable to use a material similar to the material that can be used for the conductive layer 112a2, for example.
  • the conductive layer 112a2 and the conductive layer 103 can be made of the same material.
  • the etching selectivity of the conductive layer 112a to the conductive layer 103 may be lower than when, for example, a metal is used for one of the conductive layers 112a2 and 103 and a conductive oxide is used for the other of the conductive layers 112a2 and 103.
  • a conductive film to be the conductive layer 103 is formed and then processed by an etching method to form the conductive layer 103, as described in detail later.
  • the conductive layer 112a is also processed to form a recess 129 in the conductive layer 112a.
  • a semiconductor device having good transistor electrical characteristics and high reliability can be provided.
  • a semiconductor device having good transistor electrical characteristics and high reliability since it is easy to form the recess 129 in the conductive layer 112a, it is easy to form a transistor having a large on-current as described in FIG. 5.
  • Figures 7B1 and 7B2 are cross-sectional views showing an example in which the conductive layer 112a has a two-layered structure of a conductive layer 112a1 and a conductive layer 112a2 on the conductive layer 112a1, and the end of the conductive layer 112a1 and the end of the conductive layer 112a2 coincide or approximately coincide.
  • Figure 7B1 is a cross-sectional view taken along dashed lines A1-A2 in Figure 1A.
  • Figure 7B2 is a cross-sectional view taken along dashed lines B1-B2 in Figure 1A.
  • the number of manufacturing steps for the conductive layer 112a can be reduced compared to the example shown in Figure 7A.
  • the step of the surface on which the layer (e.g., insulating layer 110) formed on the conductive layer 112a is formed is reduced, and the coverage of the layer can be improved. This makes it possible to prevent defects such as step discontinuities or voids from occurring in the layer.
  • the conductive layer 112a has a two-layer stacked structure, but the conductive layer 112a may have a three-layer or more stacked structure.
  • the conductive layer 112a shown in the figures other than Figs. 6A to 7B2 may have a two-layer stacked structure or a three-layer or more stacked structure.
  • the conductive layer 112a shown in Figs. 6A to 7B2 can be applied to the conductive layer 112a shown in Figs. 1A to 4B.
  • the conductive layer 112a shown in Figs. 6A to 7B2 can also be applied to the conductive layer 112a shown in the subsequent figures.
  • FIG. 8 is a cross-sectional view showing an example in which the conductive layer 112a2 and the conductive layer 103 shown in FIG. 6B are replaced with the conductive layer 116.
  • the boundary between the conductive layer 112a2 and the conductive layer 103 shown in FIG. 6B may not be clearly visible.
  • the boundary between the conductive layer 112a2 and the conductive layer 103 may not be clearly visible.
  • the conductive layer 112a2 and the conductive layer 103 may be visually recognized as one conductive layer 116.
  • the boundary between the conductive layer 112a2 and the conductive layer 103 may not be clearly visible as described above.
  • the conductive layer 112a and the conductive layer 103 may be visually recognized as one conductive layer 116.
  • FIG. 9 is a cross-sectional view showing an example in which the two angles are different for the transistor 100 shown in FIG. 3B.
  • angle ⁇ 112 is smaller than angle ⁇ 110. This makes it possible to reduce the step of the surface on which a layer, such as the semiconductor layer 108, is to be formed so as to cover at least a portion of the opening 143. This makes it possible to improve the coverage of the layer. This makes it possible to suppress the occurrence of defects such as step discontinuities or voids in the layer.
  • the angle ⁇ 110 and the angle ⁇ 112 can be made different by using different methods to form the opening 141 and the opening 143.
  • the angle ⁇ 112 can be made smaller than the angle ⁇ 110 by using a dry etching method to form the opening 141 and a wet etching method to form the opening 143.
  • FIG. 3A shows an example in which the planar shape of the opening 141 and the planar shape of the opening 143 match, but they do not have to match.
  • FIG. 10A is a plan view showing an example in which the planar shape of the opening 141 and the planar shape of the opening 143 do not match, and shows a conductive layer 112a, an insulating layer 110 having an opening 141, and a conductive layer 112b having an opening 143.
  • FIG. 10B is a cross-sectional view in which the opening 143 shown in FIG. 3B corresponds to the plan view shown in FIG. 10A.
  • FIG. 10B is a cross-sectional view between the dashed dotted line A1-A2 shown in FIG. 10A.
  • FIG. 10B shows an example in which the portion 123, which is the upper surface end of the insulating layer 110 on the opening 141 side, does not match the lower surface end of the conductive layer 112b on the opening 143 side.
  • FIG. 10A shows an example in which opening 143 includes opening 141 in plan view.
  • FIG. 10B shows an example in which insulating layer 110 has an area protruding from conductive layer 112b on the opening 141 side in cross-sectional view.
  • semiconductor layer 108 has a shape that conforms to the top surface of conductive layer 112b, insulating layer 105, and the top surface of conductive layer 112a. Note that when opening 141 and opening 143 have a circular planar shape, opening 141 and opening 143 may or may not be concentric.
  • Figures 11A, 11B, and 11C show an example in which the insulating layer 105 shown in Figures 1A, 1B, and 1C has a region located on the insulating layer 110, and a conductive layer 112b is provided on the insulating layer 105.
  • an opening 145 is provided in the insulating layer 105, reaching the conductive layer 112a.
  • the opening 145 is provided inside the opening 141. Note that the insulating layer 105 is not shown in Figure 11A.
  • the opening 145 can be formed by forming the insulating layer 105, then patterning it using, for example, photolithography, and processing the insulating layer 105 based on the pattern.
  • the semiconductor layer 108 By forming the semiconductor layer 108 after forming the opening 145, the conductive layer 112a and the semiconductor layer 108 can be brought into contact with each other.
  • etching is performed only on a part of the insulating layer 105. Therefore, even if the insulating layer 105 is thinned, it is possible to prevent the insulating layer 105 from being formed in a region that is thinner than other regions. This makes it possible to prevent the conductive layer 103 and the semiconductor layer 108 from coming into contact with each other and shorting out while thinning the insulating layer 105. By thinning the insulating layer 105, it becomes easier to apply the electric field of the conductive layer 103, which functions as the back gate electrode of the transistor 100, to the semiconductor layer 108.
  • the transistor 100 can be made a transistor of a fine size. Furthermore, even if the opening 141 is made fine, it is possible to suppress variations in electrical characteristics, for example variations in channel length, between multiple transistors 100.
  • FIG. 11A shows an example in which opening 143 encompasses opening 141 in plan view.
  • FIG. 11B shows an example in which insulating layer 110 has an area protruding from conductive layer 112b on the opening 141 side in cross-sectional view. Note that when openings 141 and 143 have a circular planar shape, openings 141 and 143 may or may not be concentric.
  • planar shapes of the openings 141, 143, and 145 are circular, but the planar shapes of the openings 141, 143, and 145 are not limited to circular.
  • Figures 12A, 12B, 12C, and 12D are plan views showing examples of the shapes of the openings 141, 143, and 145.
  • the planar shapes of the openings 141, 143, and 145 may be elliptical as shown in Figure 12A, rectangular as shown in Figure 12B, or rectangular with curved corners as shown in Figure 12C.
  • the planar shapes of the openings 141, 143, and 145 may be shapes including one or both of a straight line portion and a curved portion as shown in Figure 12D.
  • planar shapes of the openings 141, 143, and 145 may be parallelograms, rhombuses, or squares.
  • the planar shape of openings 141, 143, and 145 may be a triangle, or a polygon such as a pentagon or a star-shaped polygon.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • planar shape of openings 141, 143, and 145 may be a shape with curved corners of the above-mentioned figures.
  • the semiconductor layer 108 includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of the metal oxide used in the semiconductor layer 108 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element that has a high bond energy with oxygen, for example, a metal element or semi-metal element that has a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 108 may be, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tin oxide (In-Sn ...
  • Indium zinc oxide In-Sn-Zn oxide, also referred to as ITZO (registered trademark)
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium zinc oxide In-Ga-Zn oxide, also referred to as IGZO
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also referred to as IGZTO
  • indium tin gallium oxide In-Sn-Ga oxide, also referred to as IGTO
  • Indium gallium aluminum zinc oxide In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO
  • indium tin oxide containing silicon gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.
  • Ga-Sn oxide gallium tin oxide
  • Al-Sn oxide aluminum tin oxide
  • the above oxides having an amorphous structure can be used.
  • indium oxide with an amorphous structure or indium tin oxide with an amorphous structure can be used.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a large period number in the periodic table instead of or in addition to indium.
  • Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the atomic layer deposition (ALD) method or the sputtering method can be suitably used to form the metal oxide.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of the workpiece. Therefore, it is preferable to form the semiconductor layer 108 having the metal oxide by the ALD method, since damage to the semiconductor layer 108 can be reduced.
  • the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the content of zinc in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the semiconductor layer 108 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 108 may have the same or approximately the same composition.
  • the two or more metal oxide layers in the semiconductor layer 108 may have different compositions.
  • gallium, aluminum, or tin as the element M.
  • a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.
  • the semiconductor layer 108 preferably has a crystalline metal oxide layer.
  • the crystalline metal oxide structure include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity.
  • the semiconductor layer 108 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer.
  • the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer.
  • the first metal oxide layer and the second metal oxide layer may have different compositions, or may have the same or approximately the same composition.
  • the thickness of the semiconductor layer 108 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • oxygen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor.
  • a defect ( VOH ) in which hydrogen is introduced into the oxygen vacancy may function as a donor and generate an electron that is a carrier.
  • some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (that is, the threshold voltage has a negative value).
  • hydrogen in an oxide semiconductor is easily mobile due to stress such as heat and an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm -3 or less, more preferably less than 1 ⁇ 10 17 cm -3 , further preferably less than 1 ⁇ 10 16 cm -3 , further preferably less than 1 ⁇ 10 13 cm -3 , and further preferably less than 1 ⁇ 10 12 cm -3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 -9 cm -3 .
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., are highly resistant to radiation, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).
  • semiconductor materials that can be used for the semiconductor layer 108 include, for example, semiconductors made of single elements or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.
  • Silicon that can be used for the semiconductor layer 108 includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon for the semiconductor layer 108 can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer 108 have high field effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the semiconductor layer 108 have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • the semiconductor layer 108 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tellurium
  • an inorganic insulating film for the insulating layer 110.
  • the inorganic insulating film include an oxide insulating film and a nitride insulating film.
  • the oxide insulating film include a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a magnesium oxide film, a gallium oxide film, a gallium oxynitride film, a germanium oxide film, an yttrium oxide film, an yttrium oxynitride film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a hafnium oxynitride film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • the nitride insulating film include a silicon oxide film, a silicon
  • the insulating layer 110a and the insulating layer 110c can each be made of a material through which hydrogen does not easily diffuse. This can prevent hydrogen from diffusing from the outside of the transistor to the semiconductor layer 108 through the insulating layer 110a or the insulating layer 110c. This can reduce the channel length of the transistor 100 and reduce the threshold voltage of the transistor 100, that is, can prevent the threshold voltage from shifting negatively. This can reduce the cutoff current and realize a transistor with normally-off characteristics. This can improve the reliability of the transistor 100 and the reliability of the semiconductor device of one embodiment of the present invention.
  • the insulating layer 110c may contain the same material as the insulating layer 110a.
  • the insulating layer 110c may use the same material as the insulating layer 110a.
  • the insulating layer 110a and the insulating layer 110c may be formed under the same conditions. Note that, for example, by differentiating the film formation time of the insulating layer 110a from the film formation time of the insulating layer 110c, the film thickness of the insulating layer 110a and the film thickness of the insulating layer 110c may be different.
  • the diffusion coefficient can be calculated, for example, by using Thermal Desorption Spectroscopy (TDS). Alternatively, Secondary Ion Mass Spectrometry (SIMS) can be used.
  • TDS Thermal Desorption Spectroscopy
  • SIMS Secondary Ion Mass Spectrometry
  • the oxide insulating film and the nitride insulating film described above it is preferable to use one or more of the oxide insulating film and the nitride insulating film described above, respectively, and it is preferable to use one or more of a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride film, a hafnium oxide film, and a hafnium aluminate film.
  • nitride insulating films for the insulating layer 110a and the insulating layer 110c.
  • a silicon nitride film and a silicon nitride oxide film for the insulating layer 110a and the insulating layer 110c.
  • the silicon nitride film and the silicon nitride oxide film each emit little impurities (e.g., water and hydrogen) from themselves, and can be made into a film that is difficult for hydrogen to permeate, so they can be suitably used as the insulating layer 110a and the insulating layer 110c.
  • impurities e.g., water and hydrogen
  • Insulating layer 110a and insulating layer 110c may be made of, for example, a film containing aluminum as described above.
  • a film containing aluminum for example, it is preferable to use an aluminum oxide film for insulating layer 110a and insulating layer 110c.
  • the insulating layer 110a and the insulating layer 110c may contain hydrogen.
  • hydrogen can be supplied to a region near the conductive layer 112a of the semiconductor layer 108 to reduce the resistance of the region, for example, to n-type.
  • the insulating layer 110c contains hydrogen, hydrogen can be supplied to a region near the conductive layer 112b of the semiconductor layer 108 to reduce the resistance of the region. As a result, a transistor with low on-resistance can be obtained.
  • the thickness of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more, and can be less than 1 ⁇ m, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less.
  • the thickness of the insulating layer 110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.
  • the thickness of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more, and can be 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less.
  • the thickness of the insulating layer 110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.
  • the insulating layer 110b preferably contains very little hydrogen. This can prevent hydrogen from being supplied to the channel formation region of the semiconductor layer 108. Therefore, the transistor 100 can be a highly reliable transistor that exhibits good electrical characteristics. As described above, when the insulating layer 110a and the insulating layer 110c contain hydrogen and the insulating layer 110b contains very little hydrogen, the resistance of the source and drain regions of the transistor 100 can be reduced while preventing hydrogen from being supplied to the channel formation region.
  • the insulating layer 110b can be an insulating layer containing oxygen.
  • any one or more of the oxides and oxynitrides described above can be used for the insulating layer 110b.
  • one or both of silicon oxide and silicon oxynitride can be preferably used.
  • an insulating layer containing nitrogen may be used for the insulating layer 110b.
  • the insulating layer 110b can be made of the same material as the materials that can be used for the insulating layer 110a and the insulating layer 110c described above.
  • an insulating layer containing oxygen is used as the insulating layer 110b
  • oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies (V O ) are repaired and the oxygen vacancies (V O ) can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained.
  • the insulating layer 110b is preferably one in which the substance diffuses easily. In other words, it is preferable that the diffusion coefficient of the substance in the insulating layer 110b is large. For example, when an insulating layer containing oxygen is used as the insulating layer 110b, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110b is large.
  • the oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 via the insulating layer 105. By making the insulating layer 110b one in which oxygen diffuses easily, the oxygen contained in the insulating layer 110b can be efficiently supplied to the channel formation region of the semiconductor layer 108.
  • the oxygen diffusion coefficient of the insulating layer 110b at 350° C. is preferably 5 ⁇ 10 ⁇ 12 cm 2 /sec or more, more preferably 1 ⁇ 10 ⁇ 11 cm 2 /sec or more, further preferably 5 ⁇ 10 ⁇ 11 cm 2 /sec or more, and further preferably 1 ⁇ 10 ⁇ 10 cm 2 /sec or more. This allows oxygen contained in the insulating layer 110b to be efficiently supplied to the semiconductor layer 108. Since a large diffusion coefficient is preferable, no upper limit is particularly set. Note that the oxygen diffusion coefficient of the insulating layer 110b is not limited to the above-mentioned range.
  • the thickness of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 103, and Conductive Layer 104 For the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104, it is preferable to use a metal element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an alloy containing the metal element.
  • a metal element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium,
  • a nitride of the above metal or alloy, or an oxide of the above metal or alloy may be used.
  • a semiconductor with low electrical resistivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104 it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • tantalum nitride titanium nitride, a nitride containing titanium and aluminum
  • a nitride containing tantalum and aluminum ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • a conductive oxide such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide can be used.
  • a conductive oxide containing indium is preferable because of its high conductivity.
  • the conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108.
  • the semiconductor layer 108 is a metal oxide layer
  • a metal that is easily oxidized is used for the conductive layer 112a or the conductive layer 112b
  • an insulating oxide may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, preventing electrical conduction therebetween.
  • the conductive layers 112a, 112b, 103, and 104 may be formed by stacking a plurality of layers containing the above-mentioned conductive materials.
  • the semiconductor layer 108 is a metal oxide layer
  • oxygen may be supplied from the semiconductor layer 108 to the conductive layers 112a and 112b having a region in contact with the semiconductor layer 108. Therefore, it is preferable to use a conductive material that is difficult to oxidize, a conductive material that maintains conductivity even when oxidized, or an oxide conductive material for the layer having a region in contact with the semiconductor layer 108, for example, the layer having the largest contact area with the semiconductor layer 108.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104 may all be made of the same material, or at least one of them may be made of a different material.
  • the insulating layer 106 may have a single-layer structure or a stacked structure of two or more layers.
  • the insulating layer 106 preferably has one or more inorganic insulating films.
  • the inorganic insulating film include an insulating oxide film and an insulating nitride film. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 106 has a portion in contact with the semiconductor layer 108.
  • an oxide semiconductor is used for the semiconductor layer 108, it is preferable to use any of the oxide insulating films described above for at least the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108.
  • the insulating layer 106 has a single-layer structure, it is preferable to use a silicon oxide film or a silicon oxynitride film for the insulating layer 106.
  • the insulating layer 106 can have a stacked structure of an oxide insulating film on the side in contact with the semiconductor layer 108 and a nitride insulating film on the side in contact with the conductive layer 104.
  • oxide insulating film for example, a silicon oxide film or a silicon oxynitride film is preferably used.
  • nitride insulating film a silicon nitride film or a silicon nitride oxide film is preferably used.
  • Silicon nitride films and silicon nitride oxide films have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for hydrogen to permeate, so they can be suitably used as the insulating layer 106.
  • impurities e.g., water and hydrogen
  • the electrical characteristics of the transistor can be improved and the reliability can be increased.
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • the substrate 102 has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI (Silicon On Insulator) substrate can be used as the substrate 102.
  • a semiconductor element may be provided on the substrate 102.
  • a polarizing plate may be used as the substrate 102.
  • the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate may be used as the substrate 102, and the transistor 100, for example, may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The peeling layer can be used to separate the semiconductor device from the substrate 102 after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate.
  • the transistor 100 can be transferred to a substrate with poor heat resistance or a flexible substrate.
  • the substrate 102 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, or cellulose nanofiber.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • PC polycarbonate
  • PES polyethersulfone
  • polyamide resin nylon, aramid, etc.
  • Fig. 13A is a block diagram showing a structural example of a display device 10 which is a display device of one embodiment of the present invention.
  • the display device 10 includes a display portion 20, a scanning line driver circuit 11, and a signal line driver circuit 13.
  • the display portion 20 includes a plurality of pixels 21 arranged in a matrix.
  • the scanning line driving circuit 11 is electrically connected to the pixels 21 via wiring 41.
  • the wiring 41 extends, for example, in the row direction of the matrix.
  • the signal line driving circuit 13 is electrically connected to the pixels 21 via the wiring 43.
  • the wiring 43 extends, for example, in the column direction of the matrix.
  • the pixel 21 has a display element, and can display an image on the display unit 20 by using the display element.
  • a light-emitting element can be used as the display element, and specifically, an organic EL element can be used.
  • a liquid crystal element also called a liquid crystal device
  • the display element can also be used as the display element.
  • the scanning line driving circuit 11 has a function of selecting, for example, the pixels 21 to which image data is to be written, row by row. Specifically, the scanning line driving circuit 11 can select the pixels 21 to which image data is to be written, by outputting a signal to the wiring 41. Here, the scanning line driving circuit 11 can select all the pixels 21 by, for example, outputting the signal to the wiring 41 in the first row, and then outputting the signal to the wiring 41 in the second row, and so on up to the wiring 41 in the final row. Therefore, the signal that the scanning line driving circuit 11 outputs to the wiring 41 is a scanning signal, and the wiring 41 can be called a scanning line.
  • the signal line driving circuit 13 has a function of generating image data.
  • the image data is supplied to the pixels 21 via the wiring 43.
  • the image data can be written to all the pixels 21 included in the row selected by the scanning line driving circuit 11.
  • the image data can be expressed as a signal (image signal). Therefore, the wiring 43 can be called a signal line.
  • FIG. 13B is a plan view showing a configuration example of pixel 21.
  • Pixel 21 has a plurality of sub-pixels 23.
  • FIG. 13B shows an example in which pixel 21 has sub-pixels 23R, 23G, and 23B.
  • the planar shape of the sub-pixel shown in FIG. 13B corresponds to the planar shape of the light-emitting region of the light-emitting element.
  • FIG. 13B shows the aperture ratios (sizes, or sizes of light-emitting regions) of sub-pixels 23R, 23G, and 23B as being equal or approximately equal, but one embodiment of the present invention is not limited to this.
  • the aperture ratios of sub-pixels 23R, 23G, and 23B can be determined appropriately.
  • the aperture ratios of sub-pixels 23R, 23G, and 23B may be different from each other, or two or more may be equal or approximately equal.
  • subpixel 23 when describing matters common to subpixel 23R, subpixel 23G, and subpixel 23B, the letters that distinguish them may be omitted and they may be referred to as subpixel 23. When describing matters common to other elements that are distinguished by letters, they may also be described using symbols without the letters.
  • a stripe arrangement is applied as the arrangement method of the sub-pixels 23.
  • an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as the arrangement method of the sub-pixels 23.
  • planar shape of the sub-pixels and the arrangement of the sub-pixels refer to embodiment 2.
  • the sub-pixels 23R, 23G, and 23B each emit light of a different color.
  • Examples of the sub-pixels 23R, 23G, and 23B include sub-pixels of three colors, red (R), green (G), and blue (B), and sub-pixels of three colors, yellow (Y), cyan (C), and magenta (M).
  • Four or more sub-pixels 23 may be provided in the pixel 21.
  • the pixel 21 may be provided with four sub-pixels of R, G, B, and white (W).
  • the display device 10 can display a full-color image on the display unit 20 by the pixel 21 having a plurality of sub-pixels 23 that emit light of different colors.
  • the pixel 21 may be provided with sub-pixels of R, G, B, and infrared light (IR).
  • the display unit 20 may be provided with a sensor, for example, a sensor may be provided in the pixel 21.
  • a sensor may be provided in the pixel 21.
  • the display unit 20 may have a function as a fingerprint sensor.
  • the display unit 20 may have a function as an optical or ultrasonic fingerprint sensor.
  • Figures 13C, 13D, 14A, 14B, 14C, and 14D are circuit diagrams showing examples of the configuration of a subpixel 23.
  • the subpixel 23 shown in Figure 13C has a pixel circuit 40A and a light-emitting element 60.
  • Pixel circuit 40A has transistor 51, transistor 52, and capacitance 57.
  • pixel circuit 40A is a 2Tr1C type pixel circuit.
  • one of the source and drain of the transistor 51 is electrically connected to the wiring 43.
  • the other of the source and drain of the transistor 51 is electrically connected to the gate of the transistor 52.
  • the gate of the transistor 52 is electrically connected to one electrode of the capacitor 57.
  • the gate of the transistor 51 is electrically connected to the wiring 41.
  • One of the source or drain of the transistor 52 is electrically connected to the wiring 45.
  • the other of the source or drain of the transistor 52 is electrically connected to the other electrode of the capacitor 57.
  • the other electrode of the capacitor 57 is electrically connected to one electrode of the light-emitting element 60.
  • the other electrode of the light-emitting element 60 is electrically connected to the wiring 47.
  • the one electrode of the light-emitting element 60 is also called a pixel electrode.
  • the wiring 47 can be shared, for example, between all the subpixels 23, the other electrode of the light-emitting element 60 can also be called a common electrode.
  • wiring 41 functions as a scanning line
  • wiring 43 functions as a signal line
  • wiring 45 and wiring 47 function as power supply lines. For example, when a high power supply potential is supplied to wiring 45, a low power supply potential is supplied to wiring 47.
  • the transistor 51 functions as a switch and is also called a selection transistor.
  • the transistor 51 has a function of controlling the conductive state or non-conductive state between the wiring 43 and the gate of the transistor 52 based on the potential of the wiring 41. By turning the transistor 51 on, image data is written to the pixel circuit 40A, and by turning the transistor 51 off, the written image data is retained.
  • Transistor 52 has a function of controlling the amount of current flowing to light-emitting element 60 and is also called a driving transistor.
  • Capacitor 57 has a function of holding the gate potential of transistor 52.
  • the light emission luminance of light-emitting element 60 is controlled according to the potential corresponding to image data that is supplied to the gate of transistor 52. Specifically, when a high power supply potential is supplied to wiring 45 and a low power supply potential is supplied to wiring 47, the amount of current flowing from wiring 45 to wiring 47 is controlled according to the gate potential of transistor 52, thereby controlling the light emission luminance of light-emitting element 60.
  • OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as transistors 51 and 52, the display device 10 can be driven at high speed.
  • the leakage current between the source and drain of an OS transistor in an off state (also referred to as off-state current) is extremely small. Therefore, by using an OS transistor as the transistor 51, the charge stored in the capacitor 57 can be held for a long period of time. As a result, the image data written to the subpixel 23 can be held for a long period of time, and therefore the frequency of refresh operations (rewriting image data to the subpixel 23) can be reduced. As a result, the power consumption of the display device 10 can be reduced.
  • the emission luminance of the light-emitting element 60 it is necessary to increase the amount of current flowing through the light-emitting element 60.
  • the source-drain voltage of the transistor 52 which is a driving transistor.
  • OS transistors have a higher withstand voltage between the source and drain, so a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor for the transistor 52, it is possible to increase the amount of current flowing through the light-emitting element 60 and increase the emission luminance of the light-emitting element 60.
  • the OS transistor When the transistor is operated in the saturation region, the OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as transistor 52, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage. This allows for precise control of the amount of current flowing through light-emitting element 60. This allows for precise control of the luminance of the light emitted by subpixel 23. This allows for a greater number of gray levels that can be expressed by subpixel 23.
  • an OS transistor can flow a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as transistor 52, a stable current can be flowed to the light-emitting element 60, even when the current-voltage characteristics of the light-emitting element 60 vary from one light-emitting element 60 to another. In other words, when an OS transistor is operated in the saturation region, the source-drain current hardly changes even when the source-drain voltage is increased, so that the light emission luminance of the light-emitting element 60 can be stabilized.
  • transistors 51 and 52 are n-channel transistors, but one or both of transistors 51 and 52 may be p-channel transistors. The same applies to other transistors shown in this specification.
  • the light-emitting element 60 may be, for example, a self-emitting light-emitting element such as an LED, an OLED (organic LED), or a semiconductor laser.
  • the LED may be, for example, a mini LED, a micro LED, or the like.
  • the light-emitting material possessed by the light-emitting element 60 may, for example, be a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (such as a quantum dot material).
  • fluorescent material a material that emits fluorescence
  • phosphorescent material a material that emits phosphorescence
  • TADF thermally activated delayed fluorescence
  • an inorganic compound such as a quantum dot material
  • the light-emitting color of the light-emitting element 60 can be infrared, red, green, blue, cyan, magenta, yellow, or white, etc.
  • the color purity can be improved by providing the light-emitting element with a microcavity structure.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the display device of one embodiment of the present invention may be a top emission type that emits light in a direction opposite to the substrate on which the light-emitting elements are formed, a bottom emission type that emits light toward the substrate on which the light-emitting elements are formed, or a dual emission type that emits light to both sides.
  • the sub-pixel 23 shown in FIG. 13D has a pixel circuit 40B and a light-emitting element 60.
  • the pixel circuit 40B has a configuration in which a transistor 53 is added to the pixel circuit 40A.
  • the pixel circuit 40B is a 3Tr1C type pixel circuit.
  • the gate of transistor 51 is electrically connected to wiring 41a.
  • One of the source and drain of transistor 53 is electrically connected to the other of the source and drain of transistor 52, the other electrode of capacitor 57, and one electrode of light-emitting element 60.
  • the other of the source and drain of transistor 53 is electrically connected to wiring 48.
  • the gate of transistor 53 is electrically connected to wiring 41b.
  • Transistor 53 functions as a switch and controls the conductive state and non-conductive state between wiring 48 and one electrode of light-emitting element 60 based on the potential of wiring 41b.
  • a reference potential for example, is supplied to wiring 48.
  • the reference potential of wiring 48 supplied via transistor 53 can suppress the variation in the gate-source potential of transistor 52 for each transistor 52.
  • the wiring 48 can function as a monitor line for outputting the current flowing through the transistor 52 or the current flowing through the light-emitting element 60 to the outside of the pixel 21.
  • the current output to the wiring 48 can be converted into a potential by, for example, a source follower circuit. Or, it can be converted into a digital signal by, for example, an A-D converter.
  • an OS transistor As described above, an OS transistor has a higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 53, the display device 10 can be driven at high speed.
  • the sub-pixel 23 shown in FIG. 14A has a pixel circuit 40C and a light-emitting element 60.
  • the pixel circuit 40C has a configuration in which a transistor 54 and a capacitance 58 are added to the pixel circuit 40B.
  • the pixel circuit 40C is a 4Tr2C type pixel circuit.
  • one of the source or drain of the transistor 52 is electrically connected to one of the source or drain of the transistor 54.
  • the other of the source or drain of the transistor 54 is electrically connected to the wiring 45.
  • the gate of the transistor 54 is electrically connected to the wiring 41c.
  • One electrode of the capacitor 58 is electrically connected to the other of the source or drain of the transistor 52, one of the source or drain of the transistor 53, the other electrode of the capacitor 57, and one electrode of the light-emitting element 60.
  • the wiring 41c is electrically connected to the scanning line driving circuit 11. That is, when the sub-pixel 23 of the pixel 21 has the configuration shown in FIG. 14A, the wiring 41 includes wiring 41a, wiring 41b, and wiring 41c provided in the display device 10.
  • Transistor 54 functions as a switch and has the function of controlling the conductive state or non-conductive state between wiring 45 and one of the source or drain of transistor 52 based on the potential of wiring 41c.
  • a current having a magnitude corresponding to the gate potential of the transistor 52 flows, for example, from the wiring 45 to the wiring 47. This causes the light-emitting element 60 to emit light with a luminance corresponding to the gate potential of the transistor 52.
  • no current flows through the light-emitting element 60, so that the light-emitting element 60 does not emit light.
  • an OS transistor As described above, an OS transistor has a higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor 54, the display device 10 can be driven at high speed.
  • the sub-pixel 23 shown in FIG. 14B has a pixel circuit 40D and a light-emitting element 60.
  • the pixel circuit 40D has a configuration in which a transistor 54 is added to the pixel circuit 40B.
  • the pixel circuit 40D is a 4Tr1C type pixel circuit.
  • one of the source and drain of transistor 54 is electrically connected to the other of the source and drain of transistor 51, the gate of transistor 52, and one electrode of capacitor 57.
  • the other of the source and drain of transistor 54 is electrically connected to wiring 49.
  • the gate of transistor 54 is electrically connected to wiring 41c.
  • the gate potential of the transistor 52 can be set to the potential of the wiring 49.
  • a low potential can be supplied to the wiring 49.
  • the transistor 100 which is a transistor of one embodiment of the present invention, has high saturation. Therefore, by applying the transistor 100 to the transistor 52, which is a driving transistor shown in Figures 13C, 13D, 14A, and 14B, the current flowing through the light-emitting element 60 is stabilized. This stabilizes the light-emitting luminance of the light-emitting element 60. For example, it is possible to suppress variation over time in the current flowing through the light-emitting element 60. As a result, the display device 10 can display a high-quality image on the display portion 20.
  • the transistor 100 can be a transistor with a minute size. Therefore, by applying the transistor 100 to the transistor included in the subpixel 23, the pixel 21 can be miniaturized. Therefore, the display device 10 can be a high-definition display device. As described above, the display device 10 can display a high-quality image on the display unit 20. For example, the transistor 100 can be applied to the transistors 51 to 54.
  • the transistor 100 can also be used as a transistor in the driver circuit of the display device 10.
  • the transistor 100 can also be used as a transistor in the scanning line driver circuit 11 and the signal line driver circuit 13, for example.
  • the area occupied by the driver circuit can be reduced. Therefore, the display device 10 can be a display device with a narrow frame.
  • the subpixel 23 shown in Figures 14C and 14D has a pixel circuit 40E and a liquid crystal element 69.
  • the pixel circuit 40E has a transistor 51 and a capacitance 57.
  • the pixel circuit 40E is a 1Tr1C type pixel circuit.
  • one of the source and drain of the transistor 51 is electrically connected to the wiring 43.
  • the other of the source and drain of the transistor 51 is electrically connected to one electrode of the capacitor 57.
  • One electrode of the capacitor 57 is electrically connected to one electrode of the liquid crystal element 69.
  • the gate of the transistor 51 is electrically connected to the wiring 41.
  • one electrode of the liquid crystal element 69 is also called a pixel electrode.
  • the other electrode of the capacitance 57 and the other electrode of the liquid crystal element 69 are electrically connected to the same wiring 46.
  • wiring 46a is electrically connected to the other electrode of the capacitance 57 as wiring 46
  • wiring 46b is electrically connected to the other electrode of the liquid crystal element 69 as wiring 46.
  • FIG. 14D shows an example in which the wiring 46 electrically connected to the other electrode of the capacitance 57 and the wiring 46 electrically connected to the other electrode of the liquid crystal element 69 are different.
  • the wiring 46 functions as a power supply line and can supply, for example, a ground potential.
  • the other electrode of the liquid crystal element 69 is sometimes called a common electrode.
  • the transistor 51 functions as a switch and controls the conductive state or non-conductive state between the wiring 43 and one electrode of the liquid crystal element 69 based on the potential of the wiring 41. By turning on the transistor 51, image data is written to the pixel circuit 40E, and by turning off the transistor 51, the written image data is retained.
  • Capacitor 57 has the function of holding the potential of one electrode of liquid crystal element 69.
  • the orientation state of liquid crystal element 69 is controlled according to the potential corresponding to image data that is supplied to one electrode of liquid crystal element 69.
  • the liquid crystal element 69 When the liquid crystal element 69 is used as the display element, various modes can be applied to the display device 10.
  • the modes include, for example, a vertical alignment (VA) mode, a fringe field switching (FFS) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically aligned (OCB) mode, and a symmetrically aligned (OCB) mode.
  • VA vertical alignment
  • FFS fringe field switching
  • IPS in-plane switching
  • TN twisted nematic
  • ASM axially symmetric aligned micro-cell
  • OOB optically aligned
  • OCB symmetrically aligned
  • VA mode examples include the Ally Compensated Birefringence (FLC) mode, the Ferroelectric Liquid Crystal (AFLC) mode, the Anti-Ferroelectric Liquid Crystal (AFLC) mode, the Electrically Controlled Birefringence (ECB) mode, and the Guest Host mode.
  • VA mode examples include the Multi-Domain Vertical Alignment (MVA) mode, the Patterned Vertical Alignment (PVA) mode, and the Advanced Super View (ASV) mode.
  • MVA Multi-Domain Vertical Alignment
  • PVA Patterned Vertical Alignment
  • ASV Advanced Super View
  • Liquid crystal materials that can be used for the liquid crystal element 69 include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PNLC Polymer Network Liquid Crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or a blue phase.
  • either positive type liquid crystal or negative type liquid crystal may be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • the display device 10 can be, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, or a semi-transmissive liquid crystal display device.
  • the transistor 100 can be a transistor of a minute size. Therefore, by applying the transistor 100 to the transistor 51 of the pixel circuit 40E, the pixel 21 can be made minute. Therefore, the display device 10 can be a high-definition display device. As described above, the display device 10 can display a high-quality image on the display unit 20.
  • FIG. 15A is a plan view showing an example of the configuration of transistors 51 and 52.
  • FIG. 15B is a cross-sectional view between dashed lines C1-C2 shown in FIG. 15A.
  • FIGS. 15A and 15B show an example in which transistor 51 is configured by omitting conductive layer 103 and insulating layer 105 from transistor 100 shown in FIGS. 1A to 1C.
  • FIGS. 15A and 15B show an example in which transistor 100 shown in FIGS. 1A to 1C is applied to transistor 52.
  • the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, and the conductive layer 104 of the transistor 51 are respectively referred to as the conductive layer 112a_1, the semiconductor layer 108_1, the conductive layer 112b_1, and the conductive layer 104_1.
  • the opening 141 and the opening 143 provided in the transistor 51 are respectively referred to as the opening 141_1 and the opening 143_1.
  • the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, and the conductive layer 104 of the transistor 52 are respectively referred to as the conductive layer 112a_2, the semiconductor layer 108_2, the conductive layer 112b_2, and the conductive layer 104_2.
  • the opening 141 and the opening 143 provided in the transistor 52 are respectively referred to as the opening 141_2 and the opening 143_2.
  • an insulating layer 109 is provided on the insulating layer 107.
  • An opening 146a reaching the conductive layer 112b_1 is provided in the insulating layer 106, the insulating layer 107, and the insulating layer 109.
  • An opening 146b reaching the conductive layer 104_2 is provided in the insulating layer 107 and the insulating layer 109.
  • a conductive layer 119 is provided so as to have a region located inside the opening 146a, a region located inside the opening 146b, and a region located on the insulating layer 109.
  • the conductive layer 119 has, for example, a region in contact with the conductive layer 112b_1 inside the opening 146a and a region in contact with the conductive layer 104_2 inside the opening 146b.
  • the conductive layer 112b_1 functioning as the source electrode or drain electrode of the transistor 51 and the conductive layer 104_2 functioning as the gate electrode of the transistor 52 are electrically connected.
  • the insulating layer 109 can function as a planarizing layer.
  • the insulating layer 109 can be made of the same material as that which can be used for the insulating layer 107, and can be, for example, an organic insulating film or an inorganic insulating film. In particular, it is preferable to use an organic insulating film as the insulating layer 109, because the insulating layer 109 can be easily planarized. Note that the insulating layer 109 does not necessarily have to be provided.
  • the conductive layer 119 functions as a lead wiring.
  • the conductive layer 119 can be made of a material similar to that which can be used for at least one of the conductive layers 112a, 112b, 103, and 104. In particular, it is preferable to use a metal or an alloy as the conductive layer 119, because the electrical resistance of the conductive layer 119 can be reduced.
  • the planar shape of openings 146a and 146b is a rectangle with curved corners, but the planar shape of openings 146a and 146b is not limited to this.
  • the planar shape of openings 146a and 146b can be, for example, a shape similar to the shape that opening 141 can take.
  • the planar shape of openings 146a and 146b can be, for example, a circle, an ellipse, or a shape that includes one or both of straight and curved portions.
  • FIG. 15A and 15B show an example in which an insulating layer 105a is provided to cover the side of the conductive layer 112b_1 opposite the opening 143_1 and the side of the conductive layer 112b_2 opposite the opening 143_2.
  • the insulating layer 105 can have a region in contact with the side of the conductive layer 112b_1 opposite the opening 143_1 and a region in contact with the side of the conductive layer 112b_2 opposite the opening 143_2. Note that, as shown in FIG. 15A and FIG.
  • the insulating layer 105a covering the side of the conductive layer 112b_1 opposite the opening 143_1 and the insulating layer 105a covering the side of the conductive layer 112b_2 opposite the opening 143_2 can be configured to be separated from each other.
  • the conductive layer 103 is not provided inside the opening 141_1.
  • the insulating layer 105 is not provided inside the opening 141_1 and the opening 143_1.
  • the width D143_1 of the opening 143_1 can be made smaller than the width D143_2 of the opening 143_2. Therefore, the transistor 51 can be made smaller than the transistor 100 shown in FIG. 1A, for example.
  • the transistor 52 can be made to have a higher saturation than the transistor 51.
  • the conductive layer 103 and the insulating layer 105 may be provided in the transistor 51. In this case, the transistors 51 and 52 can be formed in the same process.
  • Transistors 53 and 54 shown in Figures 13D to 14B function as switches, similar to transistor 51. Therefore, it is preferable that transistors 53 and 54 have the same structure as transistor 51. For example, when transistor 51 does not have a conductive layer 103 and an insulating layer 105, it is preferable that transistors 53 and 54 also do not have a conductive layer 103 and an insulating layer 105. Note that one or both of transistors 53 and 54 may have the same structure as transistor 52.
  • 16A to 16I are circuit diagrams illustrating examples of the structure of a semiconductor device of one embodiment of the present invention.
  • the semiconductor device shown in FIG. 16A has a transistor 100 and a transistor 200.
  • One of the source and drain of the transistor 200 is electrically connected to the gate of the transistor 100.
  • the transistors 100 and 200 are illustrated as n-channel transistors; however, one embodiment of the present invention is not limited to this. One or both of the transistors 100 and 200 may be p-channel transistors.
  • Figure 17A is a plan view illustrating a configuration example of a semiconductor device 30, which is a semiconductor device of one embodiment of the present invention.
  • the conductive layer 103, the insulating layer 105, the insulating layer 105a, and the insulating layer 110 are not illustrated. The same applies to the subsequent plan views.
  • Figure 17B is a cross-sectional view taken along dashed lines D1-D2 in Figure 17A.
  • Figure 18A is a cross-sectional view taken along dashed lines E1-E2 in Figure 17A.
  • Figure 18B is a cross-sectional view taken along dashed lines E3-E4 in Figure 17A.
  • the semiconductor device 30 includes a transistor 100 and a transistor 150.
  • the transistor 100 and the transistor 150 are each provided on a substrate 102.
  • transistor 100 can be referred to, so a detailed description will be omitted.
  • the transistor 150 has a conductive layer 202, an insulating layer 110, an insulating layer 120, a semiconductor layer 208, an insulating layer 106, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b.
  • Each layer constituting the transistor 150 may have a single-layer structure or a stacked structure.
  • a conductive layer 202 is provided on the substrate 102.
  • the conductive layer 202 functions as a back gate electrode of the transistor 150.
  • the conductive layer 202 can be formed using the same material as the conductive layer 112a of the transistor 100.
  • the conductive layer 202 can be formed in the same process as the conductive layer 112a.
  • a film that becomes the conductive layer 112a and the conductive layer 202 can be formed by forming the film and processing the film.
  • the conductive layer 202 may be formed in a different process from the conductive layer 112a. By forming the conductive layer 202 in a different process, a material different from the conductive layer 112a can be used for the conductive layer 202.
  • the conductive layer 202 does not have a region in contact with either the semiconductor layer 108 or the semiconductor layer 208, and therefore the material used is not particularly limited.
  • the conductive layer 202 is preferably formed using a material having a lower electrical resistivity than the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 202.
  • In-Sn-Si oxide (ITSO) can be suitably used for the conductive layer 112a, and copper or tungsten can be suitably used for the conductive layer 202.
  • the transistor 150 does not necessarily have a backgate electrode.
  • An insulating layer 110 is provided to cover the conductive layer 202, and an insulating layer 120 is provided over the insulating layer 110.
  • the insulating layer 110 and the insulating layer 120 function as back-gate insulating layers of the transistor 150.
  • the insulating layer 120 is preferably an insulating layer containing oxygen because it is in contact with the channel formation region of the semiconductor layer 208.
  • a material suitable for the insulating layer 110b can be used.
  • the semiconductor layer 208 is provided on the insulating layer 120.
  • the semiconductor layer 208 has a region that overlaps with the conductive layer 202 via the insulating layer 110 and the insulating layer 120.
  • the semiconductor layer 208 can be made of the same material as the semiconductor layer 108.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108.
  • An insulating layer 106 is provided to cover the insulating layer 120 and the semiconductor layer 208.
  • the insulating layer 106 functions as a gate insulating layer for the transistor 150.
  • the insulating layer 106 also has openings 147a and 147b that reach the semiconductor layer 208.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b are provided on the insulating layer 106.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed using the same material as the conductive layer 104.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process as the conductive layer 104.
  • the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by forming a film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, and processing the film.
  • the conductive layer 212a is provided so as to cover at least a portion of the opening 147a, and the conductive layer 212b is provided so as to cover at least a portion of the opening 147b.
  • the conductive layer 212a and the conductive layer 212b each have a region in contact with the semiconductor layer 208.
  • the conductive layer 212a is electrically connected to the semiconductor layer 208 through the opening 147a.
  • the conductive layer 212b is electrically connected to the semiconductor layer 208 through the opening 147b.
  • the conductive layer 212a functions as one of the source electrode and drain electrode of the transistor 150.
  • the conductive layer 212b functions as the other of the source electrode and drain electrode of the transistor 150.
  • the conductive layer 204 has a region that overlaps with the semiconductor layer 208 via the insulating layer 106.
  • the conductive layer 204 functions as a gate electrode of the transistor 150.
  • the conductive layer 204 may be in contact with the conductive layer 202, and the conductive layer 204 and the conductive layer 202 may be electrically connected. This allows the conductive layer 204 and the conductive layer 202 to be given the same potential. By giving the conductive layer 204 and the conductive layer 202 the same potential, it is possible to increase the current that can flow when the transistor 150 is in an on state.
  • the conductive layer 204 may be electrically connected to the conductive layer 202 through the insulating layer 106 and the opening 149 provided in the insulating layer 110.
  • the conductive layer 212a or the conductive layer 212b may be electrically connected to the conductive layer 202. By applying the same potential to the source and the back gate, the DIBL effect in the transistor 150 can be suppressed. This can increase the saturation of the transistor 100.
  • the conductive layer 212a or the conductive layer 212b can be configured to be in contact with the conductive layer 202 through an opening provided in the insulating layer 106 and the insulating layer 110.
  • the conductive layer 202 may be electrically connected to none of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b.
  • a constant potential can be supplied to the back gate, and a signal for driving the transistor 150 can be supplied to the gate. In this way, the threshold voltage when driving the transistor 150 can be controlled by the potential supplied to the back gate.
  • the entire region of the semiconductor layer 208 that overlaps with the gate electrode via the gate insulating layer between the source electrode and drain electrode functions as a channel formation region.
  • the semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region, and a pair of regions 208D on the outside of the pair.
  • the region 208D can also be said to be a region with a higher carrier concentration than the channel formation region, or a region with low resistance.
  • the region in contact with the conductive layer 212a and the region 208D adjacent to this region function as one of the source region and the drain region.
  • the region in contact with the conductive layer 212b and the region 208D adjacent to this region function as the other of the source region and the drain region.
  • Region 208L can also be said to be a region with the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen defect density, and the same or higher impurity concentration compared to the channel formation region. Furthermore, region 208L can also be said to be a region with the same or higher resistance, the same or lower carrier concentration, the same or lower oxygen defect density, and the same or lower impurity concentration compared to region 208D.
  • Region 208L functions as a buffer region for alleviating the drain electric field.
  • Region 208L does not overlap with conductive layer 204, and therefore is a region in which a channel is hardly formed even when a gate voltage is applied to conductive layer 204.
  • Region 208L preferably has a higher carrier concentration than the channel formation region. This allows region 208L to function as an LDD (Lightly Doped Drain) region.
  • LDD Lightly Doped Drain
  • impurity elements can be added to the semiconductor layer 208 using these conductive layers as a mask to form the regions 208L and 208D.
  • the region 208L is a region of the semiconductor layer 208 that overlaps with the insulating layer 106 but does not overlap with the conductive layer 204.
  • the region 208D is a region of the semiconductor layer 208 that overlaps with neither the insulating layer 106 nor the conductive layer 204.
  • the conductive layer 212a and the conductive layer 212b are located inside the opening 147a and the opening 147b. In other words, it is preferable that some ends of the conductive layer 212a and the conductive layer 212b are in contact with the semiconductor layer 208 in the opening 147a and the opening 147b. This allows the region in contact with the conductive layer 212a to be adjacent to one of the pair of regions 208D, and similarly, the region in contact with the conductive layer 212b to be adjacent to the other of the pair of regions 208D. Note that the planar shapes of the opening 147a and the opening 147b are not particularly limited.
  • Region 208L and region 208D contain an impurity element.
  • the impurity element may be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and a noble gas.
  • noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity element.
  • the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask. As a result, a region containing the impurity element is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104.
  • a region in contact with the conductive layer 112b of the semiconductor layer 108 functions as a source region or a drain region. Therefore, the region containing the impurity element is formed in a part of the source region or the drain region.
  • the transistor 150 is a so-called top-gate transistor that has a gate electrode above the semiconductor layer 208. For example, by adding an impurity element to the semiconductor layer 208 using the conductive layer 204 that functions as the gate electrode as a mask, the source region and the drain region can be formed in a self-aligned manner.
  • the transistor 150 can be called a TGSA (Top Gate Self-Aligned) type transistor.
  • the channel length of the transistor 150 can be controlled by the width of the conductive layer 204 in the channel length direction. Therefore, the channel length of the transistor 150 is equal to or greater than the resolution limit of the exposure device used to manufacture the transistor. By increasing the channel length, a transistor with high saturation properties can be obtained.
  • An insulating layer 107 is provided to cover the transistor 100 and the transistor 150.
  • the insulating layer 107 functions as a protective layer as described above.
  • the transistor 100 with a short channel length and the transistor 150 with a long channel length can be formed on the same substrate by sharing some of the processes.
  • a high-performance semiconductor device can be obtained by applying the transistor 100 to a transistor that requires a large on-current and the transistor 150 to a transistor that requires high saturation.
  • 17B shows an example in which the conductive layer 212a and the conductive layer 212b are formed in the same process as the conductive layer 104 and the conductive layer 204, but one embodiment of the present invention is not limited thereto.
  • the conductive layer 212a and the conductive layer 212b may be formed after the insulating layer 107 is formed.
  • an opening reaching the semiconductor layer 208 may be provided in the insulating layer 107 and the insulating layer 106, and the conductive layer 212a and the conductive layer 212b may be provided so as to cover the opening, so that the conductive layer 212a and the conductive layer 212b are electrically connected to the semiconductor layer 208.
  • an impurity element may be added to the semiconductor layer 208 using the conductive layer 204 as a mask to form a low-resistance region in the semiconductor layer 208.
  • semiconductor device 30A semiconductor device 30B, semiconductor device 30C, semiconductor device 30D, and semiconductor device 30E will be described as modified examples of semiconductor device 30.
  • FIG. 17A and 19B are cross-sectional views showing a configuration example of the semiconductor device 30A.
  • FIG. 17A can be referred to for a planar configuration example of the semiconductor device 30A.
  • FIG. 19A is a cross-sectional view taken along dashed lines D1-D2 shown in FIG. 17A.
  • FIG. 19B is a cross-sectional view taken along dashed lines E3-E4 shown in FIG. 17A.
  • FIG. 18A can be referred to for a cross-sectional configuration example taken along dashed lines E1-E2 shown in FIG. 17A.
  • the semiconductor device 30A includes a transistor 100 and a transistor 150A.
  • the transistor 150A differs from, for example, the transistor 150 shown in FIG. 17B mainly in that the conductive layer 202 is provided between the insulating layer 110 and the insulating layer 120.
  • a conductive layer 202 is provided on the insulating layer 110.
  • the conductive layer 202 can be made of the same material as the conductive layer 112b.
  • the conductive layer 202 can be formed in the same process as the conductive layer 112b.
  • An insulating layer 120 is provided on the conductive layer 202.
  • the insulating layer 120 is provided so as to cover a portion of the upper surface and side surface of the conductive layer 202.
  • the insulating layer 120 is provided in at least a region where the semiconductor layer 208 and the conductive layer 204 overlap.
  • a portion of the insulating layer 120 functions as a back-gate insulating layer.
  • the insulating layer 120 preferably has a laminated structure.
  • the insulating layer 120 can have, for example, a two-layer laminated structure.
  • the lower layer of the insulating layer 120 can have a region in contact with the conductive layer 202
  • the upper layer of the insulating layer 120 can have a region in contact with the channel formation region of the semiconductor layer 208.
  • the lower layer of the insulating layer 120 is preferably made of a material that is difficult for the metal elements contained in the conductive layer 202 to diffuse into. This can prevent the metal elements contained in the conductive layer 202 from diffusing into the channel formation region of the semiconductor layer 208.
  • the lower layer of the insulating layer 120 can be preferably made of a material that can be used for the insulating layers 110a and 110c. For example, silicon nitride can be preferably used for the lower layer of the insulating layer 120.
  • the upper layer of the insulating layer 120 is preferably an insulating layer containing oxygen.
  • the upper layer of the insulating layer 120 can be made of a material suitable for the insulating layer 110b.
  • silicon oxynitride can be suitably used for the upper layer of the insulating layer 120.
  • transistor 100 For information about transistor 100, please refer to the above description, so a detailed explanation will be omitted.
  • Fig. 16B is a circuit diagram showing a configuration example of the semiconductor device 30B.
  • Fig. 20A is a plan view showing a configuration example of the semiconductor device 30B.
  • Fig. 20B is a cross-sectional view taken along dashed lines D1-D2 in Fig. 20A.
  • Fig. 21A is a cross-sectional view taken along dashed lines E1-E2 in Fig. 20A.
  • Fig. 21B is a cross-sectional view taken along dashed lines E3-E4 in Fig. 20A.
  • the semiconductor device 30B has a transistor 100 and a transistor 200.
  • the other of the source and drain of the transistor 200 is electrically connected to the other of the source and drain of the transistor 100.
  • Transistor 100 and transistor 200 are each provided on a substrate 102.
  • transistor 100 can be referred to, so a detailed description will be omitted.
  • the transistor 200 has a conductive layer 112b, a conductive layer 112c, a conductive layer 203, an insulating layer 205, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204.
  • the transistor 200 can have a similar structure to the transistor 100.
  • the conductive layer 112c functions as one of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100 and also functions as the other of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 203 functions as a back gate electrode of the transistor 200.
  • the insulating layer 205 functions as a back gate insulating layer of the transistor 200.
  • a part of the insulating layer 106 functions as a gate insulating layer of the transistor 200.
  • the conductive layer 204 functions as a gate electrode of the transistor 200.
  • the conductive layer 112c can be formed using the same material as the conductive layer 112a.
  • the conductive layer 112c can be formed in the same process as the conductive layer 112a.
  • the insulating layer 110 has an opening 241 that reaches the conductive layer 112c.
  • the opening 241 can be formed in the same process as the opening 141.
  • the conductive layer 112b has an opening 243 in a region that overlaps with the opening 241.
  • the opening 243 can be formed in the same process as the opening 143.
  • the opening 241 can have a shape similar to the shape that the opening 141 can have.
  • the opening 243 can have a shape similar to the shape that the opening 143 can have.
  • the width of opening 141 and the width of opening 241 may be different. By making the widths of the openings different, it is also possible to fabricate two transistors with different channel widths.
  • the conductive layer 203 is located inside the opening 241 and is provided so as to be electrically connected to the conductive layer 112c.
  • the conductive layer 203 has, for example, a region in contact with the conductive layer 112c and a region in contact with the side surface of the insulating layer 110 located inside the opening 241. Note that when the conductive layer 203 and the conductive layer 112c have a region in contact with each other, the boundary between the conductive layer 203 and the conductive layer 112c may not be clearly visible.
  • the conductive layer 203 can be formed using the same material as the conductive layer 103.
  • the conductive layer 203 can be formed in the same process as the conductive layer 103.
  • the conductive layer 103 and the conductive layer 203 can be formed, for example, by forming a conductive film to cover the openings 141, 143, 241, and 243, and then performing anisotropic etching on the conductive film.
  • the transistor 200 can be a transistor with a fine size.
  • the insulating layer 205 is provided so as to cover the conductive layer 203 inside the opening 241.
  • the insulating layer 205 has, for example, a region in contact with the conductive layer 203 inside the opening 241 and a region in contact with the conductive layer 112c.
  • the insulating layer 205 can be made of the same material as the insulating layer 105.
  • the insulating layer 205 can be formed in the same process as the insulating layer 105.
  • the insulating layer 105 and the insulating layer 205 can be formed, for example, by forming an insulating film so as to cover the openings 141, 143, 241, and 243, and then performing anisotropic etching on the insulating film.
  • a semiconductor layer 208 is provided so as to cover the openings 241 and 243.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108.
  • An insulating layer 106 is provided on the semiconductor layer 208, and a conductive layer 204 is provided on the insulating layer 106.
  • the conductive layer 204 can be formed in the same process as the conductive layer 104.
  • 20A and 20B show an example in which the semiconductor layer in the transistor 100 is separated into the semiconductor layer 108 and the semiconductor layer 208 in the transistor 200; however, one embodiment of the present invention is not limited to this.
  • the transistor 100 and the transistor 200 may share a semiconductor layer.
  • Fig. 16C is a circuit diagram showing a configuration example of the semiconductor device 30C.
  • Fig. 22A is a plan view showing a configuration example of the semiconductor device 30C.
  • Fig. 22B is a cross-sectional view taken along dashed lines D1-D2 in Fig. 22A.
  • Fig. 21A can be referred to for a cross-sectional configuration example taken along dashed lines E1-E2 in Fig. 22A.
  • Fig. 21B can be referred to for a cross-sectional configuration example taken along dashed lines E3-E4 in Fig. 22A.
  • the semiconductor device 30C has a transistor 100 and a transistor 200.
  • One of the source and drain of the transistor 200 is electrically connected to one of the source and drain of the transistor 100.
  • Transistor 100 and transistor 200 are each provided on a substrate 102.
  • transistor 100 can be referred to, so a detailed description will be omitted.
  • the transistor 200 has a conductive layer 112a, a conductive layer 112c, a conductive layer 203, an insulating layer 205, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 112c functions as the other of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 112c can be made of the same material as the conductive layer 112b.
  • the conductive layer 112c can be formed in the same process as the conductive layer 112b.
  • an opening 241 is formed in the insulating layer 110, reaching the conductive layer 112a.
  • an opening 243 is formed in the conductive layer 112c.
  • Fig. 16D is a circuit diagram showing a configuration example of a semiconductor device 30D.
  • Fig. 23A is a plan view showing a configuration example of a semiconductor device 30D.
  • Fig. 23B is a cross-sectional view taken along dashed line D1-D2 shown in Fig. 23A.
  • the semiconductor device 30D has a transistor 100 and a transistor 250.
  • One of the source and drain of the transistor 250 is electrically connected to one of the source and drain of the transistor 100.
  • Transistor 100 and transistor 250 are each provided on a substrate 102.
  • the semiconductor device 30D has a conductive layer 259 on the substrate 102, an insulating layer 252 on the substrate 102 and the conductive layer 259, and a semiconductor layer 253 on the insulating layer 252.
  • the semiconductor layer 253 and the conductive layer 255 have an insulating layer 254 on the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 on the insulating layer 254.
  • the semiconductor layer 253 and the conductive layer 255 have an overlapping region.
  • the conductive layer 259 functions as a back gate electrode of the transistor 250, and the insulating layer 252 functions as a back gate insulating layer.
  • the insulating layer 254 functions as a gate insulating layer, and the conductive layer 255 functions as a gate electrode.
  • An insulating layer 256 is provided over the insulating layer 254 and the conductive layer 255.
  • An opening 257a is provided in the insulating layer 254 and the insulating layer 256 in a region that overlaps with a part of the semiconductor layer 253.
  • An opening 257b is provided in the insulating layer 254 and the insulating layer 256 in a region that overlaps with another part of the semiconductor layer 253.
  • the conductive layer 258a is provided so as to have a region located on the insulating layer 256 and a region located inside the opening 257a.
  • the conductive layer 258b is provided so as to have a region located on the insulating layer 256 and a region located inside the opening 257b.
  • the conductive layer 258a has a region in contact with the semiconductor layer 253 inside the opening 257a.
  • the conductive layer 258b has a region in contact with the semiconductor layer 253 inside the opening 257b.
  • a region that overlaps with the conductive layer 255 functions as a channel formation region.
  • the semiconductor layer 253 has a pair of regions 253D that sandwich the channel formation region.
  • One of the pair of regions 253D functions as one of the source region and drain region, and is electrically connected to the conductive layer 258a.
  • the other of the pair of regions 253D functions as the other of the source region and drain region, and is electrically connected to the conductive layer 258b.
  • An insulating layer 110 is provided on insulating layer 256, conductive layer 258a, and conductive layer 258b, and a conductive layer 112b is provided on insulating layer 110.
  • the conductive layer 259 preferably overlaps with the channel formation region of the transistor 250 and extends beyond the edge of the channel formation region of the transistor 250. That is, the conductive layer 259 is preferably larger than the channel formation region of the transistor 250. In addition, the conductive layer 259 preferably extends beyond the edge of the semiconductor layer 253. That is, the conductive layer 259 is preferably larger than the semiconductor layer 253.
  • the gate electrode and the back gate electrode are arranged to sandwich the channel formation region of the semiconductor layer.
  • the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode.
  • the potential of the back gate electrode may be the ground potential or any potential.
  • the backgate electrode can be formed by the same material and method as the gate electrode, source electrode, drain electrode, etc.
  • the gate electrode and the backgate electrode are conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly an electric field shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.
  • a backgate electrode it is possible to reduce the amount of change in the threshold voltage of the transistor before and after a BT (Bias Temperature) stress test. By providing a backgate electrode, the variation in the characteristics of the transistor is reduced, and the reliability of the semiconductor device can be improved.
  • the back gate and the gate of the transistor 250 may be electrically connected. Also, as shown in FIG. 16F, the back gate and the source or the drain of the transistor 250 may be electrically connected. Also, as shown in FIG. 16G, the transistor 250 may not have a back gate.
  • the transistor 100 is shown as an n-channel type and the transistor 250 is shown as a p-channel type, but one embodiment of the present invention is not limited to this. Both the transistor 100 and the transistor 250 may be n-channel types or p-channel types. Alternatively, the transistor 100 may be a p-channel type and the transistor 250 may be an n-channel type.
  • Transistor 250 may be an OS transistor, as in transistor 100.
  • the semiconductor layer 108 and the semiconductor layer 253 may be made of the same material or different materials.
  • the description of the semiconductor layer 108 and the semiconductor layer 208 in the semiconductor device 30 can also be referred to.
  • Transistor 250 may be a transistor that uses silicon in the channel formation region (hereinafter also referred to as a Si transistor).
  • Silicon can be single crystal silicon, polycrystalline silicon, amorphous silicon, etc.
  • a transistor having an LTPS semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used.
  • LTPS transistors have high field effect mobility and good frequency characteristics.
  • the transistor 100 in the semiconductor device 30D has the same configuration as described above, except that it has a conductive layer 258a instead of the conductive layer 112a.
  • the conductive layer 258a functions as one of the source electrode and drain electrode of the transistor 100 and also functions as one of the source electrode and drain electrode of the transistor 250. By sharing the conductive layer 258a between the transistor 100 and the transistor 250, the occupation area of the semiconductor device can be reduced.
  • the transistor 100 is a vertical channel transistor.
  • the current flowing through the semiconductor layer flows in the horizontal direction, that is, in a direction parallel or approximately parallel to the surface of the substrate 102.
  • Such a transistor is also called a horizontal transistor, a horizontal channel transistor, or a horizontal channel transistor.
  • a semiconductor device may have not only vertical channel transistors but also horizontal channel transistors.
  • the transistor 100 may be formed in a region overlapping with the opening 257a.
  • openings 141 and 143 may be provided in the region overlapping with the opening 257a, and the conductive layer 258a may be in contact with the semiconductor layer 108 and the conductive layer 103 in the opening 257a.
  • the conductive layer 258a may not be provided, and the region 253D may be in contact with the semiconductor layer 108 and the conductive layer 103 in the opening 257a. With such a configuration, a semiconductor device with a smaller occupation area can be obtained.
  • Fig. 16H is a circuit diagram showing a configuration example of a semiconductor device 30E.
  • Fig. 24A is a plan view showing a configuration example of a semiconductor device 30E.
  • Fig. 24B is a cross-sectional view taken along dashed line D1-D2 shown in Fig. 24A.
  • the semiconductor device 30E has a transistor 100 and a transistor 250.
  • the gate of the transistor 250 is electrically connected to one of the source and drain of the transistor 100.
  • the semiconductor device 30E is different from the semiconductor device 30D mainly in that the opening 141 and the opening 143 are provided so as to overlap the conductive layer 255 that functions as the gate electrode of the transistor 250. Therefore, in the semiconductor device 30D, the transistor 100 is provided so as to overlap the gate electrode of the transistor 250.
  • the opening 141 and the opening 143 are provided overlapping the channel formation region of the transistor 250, but this is not limited thereto.
  • the opening 141 and the opening 143 may be provided not overlapping the channel formation region of the transistor 250 and overlapping the conductive layer 255.
  • the conductive layer 255 functions as the gate electrode of the transistor 250 and also functions as one of the source electrode and drain electrode of the transistor 100.
  • transistor 100 By stacking transistor 100 and transistor 250, a semiconductor device with a reduced occupied area can be realized.
  • opening 257a, opening 257b, conductive layer 258a, and conductive layer 258b of semiconductor device 30E are different from those of semiconductor device 30D.
  • Opening 257a and opening 257b are formed by selectively removing a portion of insulating layer 254 and insulating layer 110 in a region overlapping with region 253D of semiconductor layer 253.
  • Conductive layer 258a and conductive layer 258b are provided on insulating layer 110 and are electrically connected to region 253D via opening 257a and opening 257b.
  • the conductive layer 258a and the conductive layer 258b can be formed in the same process as the conductive layer 112b. Since it is not necessary to form the conductive layer 258a and the conductive layer 258b in a separate process from the conductive layer 112b, the manufacturing process of the semiconductor device can be shortened, and the productivity of the semiconductor device can be increased.
  • a semiconductor device includes at least one transistor and at least one capacitor, and has a structure in which the source or drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor.
  • Figure 16I shows an example in which the source or drain of the transistor 100 is electrically connected to one electrode of the capacitor 190.
  • the transistor according to one embodiment of the present invention is a type of vertical transistor, and since the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner, the area occupied can be significantly reduced compared to a planar transistor.
  • a CMOS Complementary Metal Oxide Semiconductor
  • Example 1 of manufacturing method of semiconductor device An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described below with reference to the drawings.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, pulsed laser deposition (PLD: Pulsed Laser Deposition), or ALD.
  • CVD methods include PECVD and thermal CVD.
  • One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the above-mentioned thin film can be processed, for example, by forming a resist mask by photolithography, and then etching the thin film according to the pattern of the resist mask.
  • the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • a photosensitive thin film can be processed by exposure and development. In other words, a photosensitive thin film can be processed by photolithography.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Dry etching or wet etching can be used to etch the thin film.
  • FIG. 25A to FIG. 29B show a cross-sectional view between dashed dotted lines A1-A2 shown in FIG. 1B and a cross-sectional view between dashed dotted lines B1-B2 shown in FIG. 1C side by side.
  • a conductive layer 112a is formed on the substrate 102 (FIG. 25A).
  • a conductive film that will become the conductive layer 112a is formed on the substrate 102, and the conductive film is processed to form the conductive layer 112a.
  • the conductive film that will become the conductive layer 112a can be formed by, for example, a sputtering method.
  • the metal film can be processed by, for example, one or both of a wet etching method and a dry etching method to form the conductive layer 112a.
  • the conductive layer 112a can be formed by, for example, using a conductive oxide such as In-Sn oxide, a metal element such as titanium, or an alloy containing multiple metal elements.
  • a conductive film that will become the conductive layer 112a1 is first formed on the substrate 102, and the conductive film is processed to form the conductive layer 112a1.
  • a conductive film that will become the conductive layer 112a2 is formed on the conductive layer 112a1 and on the substrate 102, and the conductive film is processed to form the conductive layer 112a2.
  • the conductive layer 112a1 and the conductive layer 112a2 that covers the conductive layer 112a1 can be formed.
  • a conductive film that will become the conductive layer 112a1 and a conductive film that will become the conductive layer 112a2 are formed in order on the substrate 102, and the conductive layers 112a2 and 112a1 can be formed by processing these conductive films.
  • the conductive layer 112a1 can be formed, for example, using a conductive oxide.
  • the conductive layer 112a2 can be formed using a metal element such as titanium, or an alloy containing multiple metal elements.
  • the insulating layer 110 is formed on the conductive layer 112a and on the substrate 102.
  • the insulating layer 110 for example, an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b are formed in this order (FIG. 25B).
  • the insulating layers 110a, 110b, and 110c can be formed, for example, by PECVD or sputtering. It is preferable to form the insulating layers 110a, 110b, and 110c successively, for example, in a vacuum, since this can prevent impurities from the atmosphere from adhering to the surfaces of the insulating layers 110a and 110b. Examples of such impurities include water and organic matter.
  • the insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen.
  • the insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen.
  • the insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen.
  • the insulating layer 110a and the insulating layer 110c can contain hydrogen. This can reduce the resistance of the source region and the drain region of the semiconductor layer 108 formed in a later process. Therefore, a transistor with low on-resistance can be formed.
  • the insulating layer 110b is preferably formed by a method that does not use a gas containing hydrogen.
  • a gas containing hydrogen For example, when an oxide insulating film is formed as the insulating layer 110b by a PECVD method, the insulating layer 110b can be formed without using a gas containing hydrogen. As a result, a film with an extremely low hydrogen content can be formed as the insulating layer 110b. This can prevent hydrogen from being supplied to the channel formation region of the semiconductor layer 108 to be formed in a later step. Therefore, a transistor that exhibits good electrical characteristics and is highly reliable can be manufactured. Note that even when an oxide insulating film is formed as the insulating layer 110b by a sputtering method, the insulating layer 110b can be formed without using a gas containing hydrogen.
  • insulating layer 110a and insulating layer 110c in an atmosphere containing hydrogen, and forming insulating layer 110b by a method that does not use a gas containing hydrogen, it is possible to reduce the resistance of the source region and drain region of semiconductor layer 108, which will be formed in a later process, while suppressing the supply of hydrogen to the channel formation region.
  • the substrate temperature during the formation of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower.
  • the transistor included in the semiconductor device of one embodiment of the present invention can be a transistor that exhibits good electrical characteristics and is highly reliable.
  • the insulating layers 110a, 110b, and 110c are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to the heat applied during the formation of the insulating layers 110a, 110b, and 110c.
  • the plasma treatment may be performed without exposing the surface of the insulating layer 110b to the air.
  • a PECVD apparatus is used to form the insulating layer 110b, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity.
  • an N 2 O plasma treatment can be performed continuously.
  • oxygen can be supplied to the insulating layer 110b by forming a film such as an insulating film, a semiconductor film, or a conductive film on the insulating layer 110b in an atmosphere containing oxygen.
  • a film such as an insulating film, a semiconductor film, or a conductive film
  • oxygen can be supplied to the insulating layer 110b by forming a film such as an insulating film, a semiconductor film, or a conductive film on the insulating layer 110b in an atmosphere containing oxygen.
  • a film such as an insulating film, a semiconductor film, or a conductive film on the insulating layer 110b in an atmosphere containing oxygen.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used as the film.
  • the oxygen flow ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% and the oxygen partial pressure as close to 100% as possible.
  • oxygen can be supplied to the insulating layer 110b during the formation of the film, and oxygen can be prevented from being released from the insulating layer 110b.
  • a large amount of oxygen can be trapped in the insulating layer 110b.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, and even more preferably 350°C or higher and 400°C or lower.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) may be used as the atmosphere containing nitrogen or the atmosphere containing oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere is as small as possible.
  • a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere.
  • a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere.
  • Heat treatment can be performed using an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.
  • the film is removed.
  • a wet etching method can be preferably used. By using a wet etching method, etching of the insulating layer 110b during the removal can be suppressed. This can suppress the thickness of the insulating layer 110b from becoming thin, and the thickness of the insulating layer 110b can be made uniform.
  • a conductive film 112f that will become the conductive layer 112b is formed on the insulating layer 110 (FIG. 25C).
  • the conductive film 112f is formed so as to have a region in contact with the upper surface of the insulating layer 110c.
  • the conductive film 112f can be formed, for example, by using a sputtering method.
  • the conductive film 112f is processed into a desired shape to form the conductive layer 112b on the insulating layer 110 (FIG. 26A).
  • the conductive layer 112b is formed so as to have a region in contact with the upper surface of the insulating layer 110c.
  • the conductive layer 112b is processed to form an opening 143 (FIG. 26B).
  • the opening 143 is formed to have an area that overlaps with the conductive layer 112a.
  • the conductive film 112f may be processed into a desired shape to form the conductive layer 112b in which the opening 143 is provided. In other words, the process shown in FIG. 26A and the process shown in FIG. 26B may be interchanged.
  • the opening 141 has an area that overlaps with the opening 143, and is formed to reach the conductive layer 112a. By forming the opening 141, the area of the conductive layer 112a that overlaps with the opening 141 and the opening 143 is exposed.
  • the opening 143 and the opening 141 can be formed by one or both of a wet etching method and a dry etching method.
  • the opening 143 can be formed by, for example, a wet etching method.
  • the opening 141 can be formed by, for example, a dry etching method.
  • the wet etching method can be a processing method with higher isotropy than the dry etching method. Therefore, when the opening 143 is formed by the wet etching method and the opening 141 is formed by the dry etching method, the lower end of the conductive layer 112b on the opening 143 side may not coincide with the portion 123 as shown in FIG. 10A and FIG. 10B.
  • the insulating layer 110 may have a region protruding from the conductive layer 112b on the opening 141 side in a cross-sectional view.
  • the opening 141 can be formed, for example, by using the resist mask used to form the opening 143.
  • a resist mask is formed on the conductive layer 112b.
  • a part of the conductive layer 112b is removed using the resist mask to form the opening 143.
  • a part of the insulating layer 110 is removed using the resist mask to form the opening 141.
  • the opening 141 and the opening 143 may be formed using different resist masks.
  • a conductive film 103f that will become the conductive layer 103 is formed so as to cover the opening 141 and the opening 143 (FIG. 27A).
  • the conductive film 103f is formed on the insulating layer 110 so as to cover the side surface of the insulating layer 110 located within the opening 141 and the upper surface of the conductive layer 112a exposed by the opening 141.
  • the conductive film 103f can be formed to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112b, a region in contact with the upper surface of the conductive layer 112b, and a region in contact with the upper surface of the insulating layer 110.
  • the conductive film 103f can be formed, for example, by using a sputtering method, a thermal CVD method (including a MOCVD method), or an ALD method.
  • the conductive layer 103 is formed inside the opening 141 so as to be electrically connected to the conductive layer 112a (FIG. 27B).
  • the conductive layer 103 is formed along the side surface located within the opening 141 of the insulating layer 110 so as to have an area in contact with the conductive layer 112a inside the opening 141.
  • the conductive layer 103 can also be formed so as to have an area in contact with the side surface located within the opening 141 of the insulating layer 110.
  • anisotropic etching it is preferable to perform anisotropic etching on the conductive film 103f so that the top of the conductive layer 103 is located below the upper end of the insulating layer 110 on the opening 141 side. In other words, it is preferable to perform anisotropic etching on the conductive film 103f so that the conductive layer 103 is not provided inside the opening 143. For example, it is preferable to adjust the speed and time of the anisotropic etching so that the conductive layer 103 is provided inside the opening 141 but not inside the opening 143. As a result, for example, it is possible to prevent the conductive layer 103 and the conductive layer 112b from coming into contact with each other and causing a short circuit.
  • the anisotropic etching of the conductive film 103f is preferably performed under conditions where the selectivity is high with respect to the conductive layer 112a and the conductive layer 112b.
  • the anisotropic etching is preferably performed under conditions where the etching rate of the conductive film 103f is faster than the etching rate of the conductive layer 112a and the conductive layer 112b. This can prevent the conductive layer 112a and the conductive layer 112b from being unintentionally etched during the anisotropic etching of the conductive film 103f. Therefore, the manufacturing yield of the semiconductor device can be increased. Furthermore, a highly reliable semiconductor device can be manufactured.
  • the conductive film 103f is preferably made of a metal element such as titanium or an alloy containing multiple metal elements. This allows the conductive layer 103 to have low electrical resistance, for example.
  • a metal such as titanium for the conductive film 103f and a conductive oxide such as In-Sn oxide for the conductive layers 112a and 112b the etching selectivity between the conductive film 103f and the conductive layers 112a and 112b can be increased.
  • a recess 129 may be formed in the conductive layer 112a, for example, as shown in FIG. 5.
  • the recess 129 may be formed.
  • the conductive layer 112a has a structure as shown in, for example, FIG. 6B to FIG. 7B2
  • the conductive layer 112a1 can be prevented from being processed when the recess 129 is formed in the conductive layer 112a. Therefore, the conductive layer 112a can be prevented from being completely removed in the region that overlaps with the opening 141 and does not overlap with the conductive layer 103. This can prevent the bottom surface of the semiconductor layer 108 formed in a later process from coming into contact with the conductive layer 112a.
  • the conductive layer 112a2 that has a lower etching selectivity to the conductive film 103f than the conductive layer 112a1, it is easier to form the recess 129 in the conductive layer 112a. Therefore, as described above, it is easier to form a transistor with a large on-current.
  • the conductive layer 112a1 can be made of, for example, a conductive oxide.
  • the conductive layer 112a2 can be made of, for example, a material similar to that which can be used for the conductive film 103f.
  • the conductive layer 112a2 and the conductive film 103f can be made of the same material.
  • the conductive layer 103 When the conductive layer 103 is formed by performing anisotropic etching on the conductive film 103f, there is no need to use a mask, unlike when the conductive layer 103 is formed by processing the conductive film 103f after patterning by photolithography, for example. Therefore, in the method for manufacturing a semiconductor device of one embodiment of the present invention, the conductive layer 103 can be formed without considering the accuracy of mask alignment, for example. As described above, even if the opening 141 in which the conductive layer 103 is formed is miniaturized, it is possible to prevent, for example, the conductive layer 103 from not being formed inside the opening 141. Therefore, in the method for manufacturing a semiconductor device of one embodiment of the present invention, a transistor with a fine size can be manufactured.
  • Insulating film 105f is formed so as to cover conductive layer 103 and conductive layer 112b (FIG. 27C).
  • Insulating film 105f can be formed to have a region in contact with the upper surface of conductive layer 112a, a region in contact with conductive layer 103, a region in contact with the side of insulating layer 110, a region in contact with the upper surface of insulating layer 110, a region in contact with the side of conductive layer 112b, and a region in contact with the upper surface of conductive layer 112b.
  • Insulating film 105f can be formed, for example, by using a PECVD method or an ALD method.
  • anisotropic etching is performed on the insulating film 105f.
  • anisotropic etching is performed on the insulating film 105f until at least a portion of the upper surface of the conductive layer 112b is exposed.
  • an insulating layer 105 is formed so as to cover the conductive layer 103 ( Figure 28A).
  • the insulating layer 105 can be formed to have a region that contacts the conductive layer 103 inside the opening 141 and a region that contacts the conductive layer 112a.
  • the insulating layer 105 can also be formed to have a region that contacts the side of the conductive layer 112b inside the opening 143.
  • the top of the insulating layer 105 can be aligned or approximately aligned with the top surface of the conductive layer 112b. Also, as shown in FIG. 4A, the top of the insulating layer 105 and the top of the insulating layer 105a may be located between the bottom and top surfaces of the conductive layer 112b. Furthermore, as shown in FIG. 4B, the top of the insulating layer 105 may be located below the bottom surface of the conductive layer 112b. The position of the top of the insulating layer 105 can be changed, for example, by the rate and time of the anisotropic etching.
  • an insulating layer 105a may be formed so as to cover at least a portion of the side of the conductive layer 112b, specifically, the side opposite the opening 143.
  • the insulating layer 105a is formed as a residue when the insulating layer 105 is formed.
  • the insulating layer 105a can be formed to have an area in contact with the side of the conductive layer 112b opposite the opening 143.
  • the insulating layer 105a may be formed.
  • the insulating layer 105a may be formed. Note that the insulating layer 105a may not be formed.
  • the insulating layer 105 When the insulating layer 105 is formed so that the top coincides with the top surface of the insulating layer 110, for example, the top end of the insulating layer 110 on the opening 141 side, or is located below the top surface of the insulating layer 110, the insulating layer 105a may not be formed. Furthermore, even if the insulating layer 105 is formed so that its uppermost portion is located above the upper surface of the insulating layer 110, for example, the upper end of the insulating layer 110 on the opening 141 side, the insulating layer 105a may not be formed.
  • the conductive layer 103 can be prevented from being exposed.
  • the insulating layer 105 can be formed so as to prevent the conductive layer 103 from being exposed. This makes it possible to prevent the semiconductor layer 108 formed in a later step from coming into contact with the conductive layer 103 and causing a short circuit. This can increase the manufacturing yield of the semiconductor device of one embodiment of the present invention.
  • slowing down the rate of anisotropic etching on the insulating film 105f reduces the throughput, and therefore it is preferable to adjust the rate of anisotropic etching in consideration of the manufacturing yield and throughput of the semiconductor device.
  • a part of the insulating layer 110 may be processed.
  • the film thickness in the region of the insulating layer 110 that does not overlap with either the conductive layer 112b or the insulating layer 105a may be thinner than the film thickness in the region of the insulating layer 110 that overlaps with the conductive layer 112b or the insulating layer 105a.
  • a recess may be formed in the region of the insulating layer 110 that does not overlap with either the conductive layer 112b or the insulating layer 105a.
  • a recess may be formed in the insulating layer 110.
  • the insulating layer 110 has a three-layered structure of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, if the etching selectivity of the insulating film 105f and the insulating layer 110c is high, the formation of a recess in the insulating layer 110 can be suppressed even if the etching selectivity of the insulating film 105f and the insulating layer 110b is low.
  • the insulating film 105f can be made of the same material as the insulating layer 110b.
  • one or both of a part of the conductive layer 112a and a part of the conductive layer 112b may be processed.
  • a recess may be formed in the conductive layer 112a in a region that overlaps with the opening 141 and does not overlap with the conductive layer 103.
  • a recess may be formed in the conductive layer 112a.
  • the film thickness of the conductive layer 112b may be thinned.
  • the film thickness of the conductive layer 112b after the insulating layer 105 is formed may be thinner than the film thickness of the conductive layer 112b before the insulating layer 105 is formed.
  • the film thickness of the conductive layer 112b may be thinned.
  • a semiconductor film 108f that will become the semiconductor layer 108 is formed so as to cover the openings 141 and 143 (FIG. 28B).
  • the semiconductor film 108f is formed so as to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the insulating layer 105, a region in contact with the insulating layer 105a, a region in contact with the upper surface of the conductive layer 112b, and a region in contact with the upper surface of the insulating layer 110.
  • the semiconductor film 108f is preferably formed using the ALD method.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of the workpiece. Therefore, when the semiconductor film 108f is formed by the ALD method, damage to the semiconductor film 108f can be reduced.
  • oxygen vacancies may occur in the semiconductor film 108f.
  • oxygen can be supplied to the semiconductor layer 108 by making one or both of the insulating layer 105 and the insulating layer 106 formed in a later process contain excess oxygen and performing heat treatment or the like.
  • the insulating layer 105 contains excess oxygen
  • the conductive layer 103, the conductive layer 112a, and the conductive layer 112b may be oxidized, and the electrical resistance of the conductive layer 103, the conductive layer 112a, and the conductive layer 112b may be increased.
  • the insulating layer 106 contains excess oxygen
  • the conductive layer 104 and the conductive layer 112b may be oxidized, and the electrical resistance of the conductive layer 104 and the conductive layer 112b may be increased.
  • excess oxygen refers to oxygen that is present in a layer but is not bonded to the layer (free oxygen), or oxygen that has low bond energy with the layer.
  • the semiconductor film 108f is formed by a deposition method that causes less damage, such as the ALD method
  • the occurrence of oxygen vacancies can be suppressed compared to when the semiconductor film 108f is formed by a deposition method that causes more damage. This eliminates the need to perform processing to repair oxygen vacancies in the semiconductor layer 108.
  • the ALD method When the ALD method is used to form the semiconductor film 108f, it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • the thermal ALD method is preferable because it exhibits extremely high step coverage.
  • the PEALD method is preferable because it exhibits high step coverage and allows low-temperature film formation.
  • the semiconductor film 108f can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • precursors containing indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.
  • precursors containing gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.
  • precursors containing tin include tetramethyltin, tetraethyltin, tetraethenyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tributylstannylacetylene, tributylphenyltin, chlorotrimethyltin, chlorotriethyltin, and tin(IV) chloride.
  • Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • Methods for controlling the composition of the resulting film include adjusting the flow ratio of the source gases, the time for which the source gases are flowed, or the order in which the source gases are flowed. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions continuously.
  • a film formation method other than the ALD method may be used to form the semiconductor film 108f.
  • the semiconductor film 108f may be formed by a sputtering method.
  • all layers may be formed by the same film formation method, or each layer may be formed by a different film formation method.
  • the semiconductor film 108f has a two-layer stacked structure, one layer may be formed by the ALD method, and the other layer may be formed by the sputtering method.
  • the semiconductor film 108f is formed by a film formation method other than the ALD method, it is preferable to supply oxygen to the insulating layer 110b by the above-mentioned method after the insulating layer 110b is formed and before the insulating layer 110c is formed. This allows oxygen vacancies in the semiconductor film 108f to be repaired.
  • a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110.
  • heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere.
  • plasma treatment in an atmosphere containing oxygen may be performed.
  • oxygen may be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N 2 O).
  • nitrous oxide N 2 O
  • plasma treatment containing nitrous oxide gas oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to form the semiconductor film 108f continuously without exposing the surface of the insulating layer 110 to the air.
  • the semiconductor layer 108 has a laminated structure, it is preferable to form a next metal oxide film in succession after forming a first metal oxide film without exposing the surface to the air.
  • the semiconductor film 108f is processed into an island shape to form the semiconductor layer 108 (FIG. 29A).
  • the semiconductor layer 108 can be formed to have a region located inside the opening 141 and a region located inside the opening 143.
  • the semiconductor layer 108 can be formed to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the insulating layer 105, and a region in contact with the top surface of the conductive layer 112b.
  • the semiconductor layer 108 can be formed by using either or both of a wet etching method and a dry etching method.
  • a wet etching method is preferable.
  • a part of the conductive layer 112b in a region that does not overlap with the semiconductor layer 108 may be etched and thinned.
  • a part of the insulating layer 105a may be etched and thinned.
  • a part of the insulating layer 110 in a region that does not overlap with any of the semiconductor layer 108, the conductive layer 112b, and the insulating layer 105a may be etched and thinned.
  • the heat treatment can remove hydrogen or water contained in the semiconductor film 108f or the semiconductor layer 108 or adsorbed on the surface.
  • the heat treatment may improve the film quality of the semiconductor film 108f or the semiconductor layer 108 (for example, reduce defects or improve crystallinity). It is more preferable to perform the heat treatment before processing into the semiconductor layer 108.
  • the temperature of the heat treatment is preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and more preferably 300°C or higher and 400°C or lower, typically 350°C.
  • For other conditions of the heat treatment refer to the description of the heat treatment after the formation of the metal oxide layer 149.
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it may be performed in the same manner as a heat treatment performed in a later process. Also, a high-temperature process in a later process (e.g., a film formation process) may also serve as the heat treatment.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, the insulating layer 105a, and the insulating layer 110 (FIG. 29B).
  • the insulating layer 106 can be formed on the semiconductor layer 108 so as to have a region located inside the opening 141 and a region located inside the opening 143.
  • the insulating layer 106 can be formed along the sidewalls of the opening 141 and the sidewalls of the opening 143 through the semiconductor layer 108.
  • the insulating layer 106 can be formed, for example, by using a PECVD method or an ALD method.
  • the insulating layer 106 preferably functions as a barrier film that suppresses the diffusion of oxygen. Since the insulating layer 106 has the function of suppressing the diffusion of oxygen, the diffusion of oxygen from above the insulating layer 106 to the conductive layer 104 can be suppressed, and the conductive layer 104 can be suppressed from being oxidized. As a result, a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.
  • a barrier film refers to a film having barrier properties.
  • an insulating layer having barrier properties can be called a barrier insulating layer.
  • barrier properties refer to one or both of the function of suppressing the diffusion of the corresponding substance (also called low permeability) and the function of capturing or fixing the corresponding substance (also called gettering).
  • the substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C.
  • the substrate temperature during the formation of the insulating layer 106 By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • plasma treatment may be performed on the surface of the semiconductor layer 108.
  • the plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • the conductive layer 104 is formed on the insulating layer 106. This forms the transistor 100.
  • the conductive layer 104 can be formed to have a region located inside the opening 141 and a region located inside the opening 143, and to have a region facing the semiconductor layer 108 via the insulating layer 106.
  • a conductive film that becomes the conductive layer 104 can be formed on the insulating layer 106 and then processed to form the conductive layer 104.
  • a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method is suitable for forming the conductive film that becomes the conductive layer 104.
  • the conductive film can be processed to form an island-shaped conductive layer 104 that functions as a gate electrode.
  • insulating layer 107 is formed to cover conductive layer 104 and insulating layer 106 (FIGS. 1B and 1C).
  • CVD can be used to form insulating layer 107, and more specifically, PECVD can be used.
  • insulating layer 107 can also be formed by, for example, sputtering.
  • the semiconductor device shown in Figures 1B and 1C can be manufactured.
  • the conductive layer 103 functioning as the back gate electrode of the transistor 100 and the insulating layer 105 functioning as the back gate insulating layer of the transistor 100 are formed by anisotropic etching without using a mask. Therefore, in the above-described method for manufacturing a semiconductor device, the conductive layer 103 and the insulating layer 105 can be formed without considering the accuracy of mask alignment, for example. As described above, even if the opening 141 in which the conductive layer 103 and the insulating layer 105 are formed is miniaturized, it is possible to prevent, for example, the conductive layer 103 and the insulating layer 105 from being not formed inside the opening 141. Therefore, the method for manufacturing a semiconductor device according to one embodiment of the present invention allows a transistor with a fine size to be manufactured.
  • Fig. 30A to Fig. 31C show a cross-sectional view taken along dashed line A1-A2 in Fig. 11B and a cross-sectional view taken along dashed line B1-B2 in Fig. 11C side by side.
  • the conductive layer 112a and the insulating layer 110 are formed in order on the substrate 102 by performing steps similar to those shown in Figures 25A and 25B.
  • an opening 141 is formed in the insulating layer 110, reaching the conductive layer 112a ( Figure 30A).
  • a resist mask is formed on the insulating layer 110, and the opening 141 can be formed by removing the portion of the insulating layer 110 that does not overlap with the resist mask by an etching method.
  • the insulating layer 110 can be removed by an etching method, and for example, a dry etching method can be preferably used.
  • a process similar to that shown in FIG. 27A is performed to form a conductive film 103f so as to cover the opening 141 (FIG. 30A).
  • the conductive film 103f can be formed to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, and a region in contact with the upper surface of the insulating layer 110.
  • steps similar to those shown in Figures 27B and 27C are performed to form the conductive layer 103 and the insulating layer 105 in that order (Figure 30B).
  • the insulating film 105f shown in Figure 27C corresponds to the insulating layer 105 shown in Figure 30B.
  • the conductive layer 112b is not formed at this stage.
  • a process similar to that shown in FIG. 25C is performed to form a conductive film 112f so as to cover the opening 141 (FIG. 30C).
  • the conductive film 112f is formed on the insulating layer 105.
  • the conductive film 112f is processed to form a conductive layer 112b having an opening 143 (FIG. 31A).
  • the opening 143 is formed to have an area overlapping with the opening 141.
  • the conductive layer 112b having the opening 143 can be formed by, for example, photolithography and etching. Specifically, a resist mask is formed on the conductive film 112f, and a portion of the conductive film 112f that does not overlap with the resist mask is removed by etching, thereby forming the conductive layer 112b having the opening 143.
  • the conductive layer 112b can be formed by processing the conductive film 112f, and the opening 143 can be formed in the conductive layer 112b in the same process. That is, the conductive layer 112b can be formed and the opening 143 can be formed in the conductive layer 112b using the same resist mask.
  • the conductive layer 112b can be formed and the opening 143 can be formed in the conductive layer 112b in different processes. For example, a resist mask is formed, and the conductive film 112f is processed based on the resist mask to form the conductive layer 112b, and the resist mask is removed, and then a resist mask is formed again. The conductive layer 112b can then be processed based on the resist mask to form the opening 143. After forming the opening 143 in the conductive film 112f, the conductive film 112f having the opening 143 may be processed to form the conductive layer 112b.
  • the insulating layer 105 is processed to form an opening 145 (FIG. 31B).
  • the opening 145 is located inside the opening 141 and is formed so as to reach the conductive layer 112a. By forming the opening 145, the area of the conductive layer 112a that overlaps with the opening 145 is exposed.
  • the opening 145 can be formed by, for example, photolithography and etching. Specifically, a resist mask is formed on the insulating layer 105, and the portion of the insulating layer 105 that does not overlap with the resist mask is removed by etching to form the opening 145. In particular, if a dry etching method is used to remove the insulating layer 105, the opening 145 can be made fine. This is preferable because it can prevent the semiconductor layer 108 formed in a later process from coming into contact with the conductive layer 103 and causing a short circuit.
  • a process similar to that shown in FIG. 28B is performed to form a semiconductor film 108f so as to cover the openings 141, 143, and 145 (FIG. 31B).
  • the semiconductor film 108f is formed to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the insulating layer 105, a region in contact with the side of the conductive layer 112b, a region in contact with the upper surface of the conductive layer 112b, and a region in contact with the upper surface of the insulating layer 110.
  • the semiconductor layer 108 can be formed to have a region located inside the opening 141, a region located inside the opening 143, and a region located inside the opening 145.
  • the semiconductor layer 108 can be formed to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the insulating layer 105, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surface of the conductive layer 112b.
  • insulating layer 107 is formed to cover conductive layer 104 and insulating layer 106 (FIGS. 11B and 11C).
  • insulating layer 107 can be formed, for example, by CVD, specifically, PECVD. Note that insulating layer 107 can also be formed, for example, by sputtering.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • anisotropic etching is not performed when the insulating layer 105 is formed, and etching is performed only on a part of the insulating layer 105. Therefore, even if the insulating layer 105 is thinned, it is possible to prevent the insulating layer 105 from being formed in a region thinner than other regions. This makes it possible to prevent the conductive layer 103 and the semiconductor layer 108 from contacting each other and causing a short circuit while thinning the insulating layer 105. By thinning the insulating layer 105, it is possible to easily apply an electric field of the conductive layer 103, which functions as a backgate electrode of the transistor 100, to the semiconductor layer 108.
  • Example 3 of manufacturing method of semiconductor device An example of a method for manufacturing the semiconductor device shown in Fig. 15B will be described below with reference to Fig. 32A to Fig. 33B, which show cross-sectional views taken along dashed line C1-C2 shown in Fig. 15B.
  • conductive layers 112a_1 and 112a_2, insulating layer 110, conductive layers 112b_1 and 112b_2 on substrate 102 Figure 32A.
  • conductive layers 112a_1 and 112a_2 can be formed by processing the same conductive film.
  • conductive layers 112b_1 and 112b_2 can be formed by processing the same conductive film.
  • the conductive layer 112b_2 is processed to form the opening 143_2 (FIG. 32A).
  • the opening 143_2 can be formed in the same manner as the opening 143 shown in FIG. 26B.
  • the insulating layer 110 is processed to form the opening 141_2 (FIG. 32A).
  • the opening 141_2 can be formed in the same manner as the opening 141 shown in FIG. 26C.
  • 27A to 28A are performed to form the conductive layer 103 and the insulating layer 105 inside the opening 141_2 (FIG. 32B).
  • a recess 129 as shown in FIG. 5 may be formed in the conductive layer 112a_2.
  • the insulating layer 105 may be formed to have a region located inside the opening 143_2.
  • the insulating layer 105a may be formed to cover at least a portion of the side of the conductive layer 112b_1 and at least a portion of the side of the conductive layer 112b_2 opposite the opening 143_2.
  • the insulating layer 105a may be formed to have a region in contact with the side of the conductive layer 112b_1 and a region in contact with the side of the conductive layer 112b_2 opposite the opening 143_2.
  • the conductive layer 112b_1 is processed to form an opening 143_1, and the insulating layer 110 is processed to form an opening 141_1 (FIG. 32C).
  • the opening 143_1 can be formed in the same manner as the opening 143 shown in FIG. 26B.
  • the opening 141_1 can be formed in the same manner as the opening 141 shown in FIG. 26C.
  • the same steps as those shown in FIG. 28B to FIG. 29B are performed to sequentially form the semiconductor layer 108_1 and the semiconductor layer 108_2, the insulating layer 106, and the conductive layer 104_1 and the conductive layer 104_2 (FIG. 33A).
  • the semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed by processing the semiconductor film 108f shown in FIG. 28B.
  • the conductive layer 104_1 and the conductive layer 104_2 can be formed by processing the same conductive film.
  • insulating layer 107 is formed to cover conductive layer 104 and insulating layer 106 (FIG. 33A).
  • insulating layer 107 can be formed, for example, by CVD, specifically, by PECVD. Note that insulating layer 107 can also be formed, for example, by sputtering.
  • insulating layer 109 is formed on insulating layer 107 (FIG. 33A).
  • the insulating layer 109 can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the insulating layer 109 can be formed by a CVD method or a sputtering method.
  • an opening 146a is formed in the insulating layer 109, the insulating layer 107, and the insulating layer 106, reaching the conductive layer 112b_1.
  • an opening 146b is formed in the insulating layer 109 and the insulating layer 107, reaching the conductive layer 112b_2 (FIG. 33B).
  • the opening 146a and the opening 146b can be formed in parallel.
  • the openings 146a and 146b can be formed by, for example, photolithography and etching. Specifically, a resist mask is formed on the insulating layer 109, and the portions of the insulating layer 109, the insulating layer 107, and the insulating layer 105 that do not overlap with the resist mask are removed by etching to form the openings 146a and 146b. In particular, it is preferable to use a dry etching method to remove the insulating layer 109, the insulating layer 107, and the insulating layer 105, since this allows the openings 146a and 146b to be miniaturized.
  • Conductive layer 119 is formed so as to have a region located inside opening 146a and a region located inside opening 146b (FIG. 15B). Conductive layer 119 can be formed so as to have a region in contact with conductive layer 112b_1 inside opening 146a and a region in contact with conductive layer 104_2 inside opening 146b.
  • a conductive film that will become the conductive layer 119 is formed on the insulating layer 109 so as to have a region located inside the opening 146a and a region located inside the opening 146b, and the conductive film is processed to form the conductive layer 119.
  • a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method is suitable for forming the conductive film that will become the conductive layer 119.
  • the conductive film is processed to form the conductive layer 119 that functions as a lead wiring.
  • the semiconductor device shown in FIG. 15B can be manufactured.
  • the conductive layer 103 is not formed inside the opening 141_1, and the conductive layer 103 is formed inside the opening 141_2. Therefore, even if a recess is formed in the conductive layer 112a_2, there are cases where a recess is not formed in the conductive layer 112a_1.
  • the arrangement of the sub-pixels there are no particular limitations on the arrangement of the sub-pixels, and various methods can be applied. Examples of the arrangement of the sub-pixels include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.
  • planar shape of the subpixels shown in the figures in this embodiment corresponds to the planar shape of the display area (or light receiving area).
  • the planar shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, or a polygon with rounded corners, an ellipse, or a circle.
  • the circuit layout constituting the subpixel is not limited to the area of the subpixel shown in the figure, but may be arranged outside of it.
  • the pixel 21 shown in FIG. 34A has an S-stripe arrangement.
  • the pixel 21 shown in FIG. 34A is composed of three types of subpixels: subpixel 23a, subpixel 23b, and subpixel 23c.
  • Pixel 21 shown in FIG. 34B has subpixels 23a and 23b that have a planar shape of a roughly trapezoid or triangle with rounded corners, and subpixel 23c that has a planar shape of a roughly rectangular or hexagon with rounded corners.
  • Subpixel 23b has a larger display area than subpixel 23a. In this way, the shape and size of each subpixel can be determined independently. For example, the size of a subpixel that has a display element with higher reliability can be made smaller.
  • FIG. 34C shows an example in which pixel 21a having sub-pixels 23a and 23b and pixel 21b having sub-pixels 23b and 23c are arranged alternately.
  • Pixels 21a and 21b shown in Figures 34D to 34F are arranged in a delta arrangement.
  • Pixel 21a has two subpixels (subpixels 23a and 23b) in the top row (first row) and one subpixel (subpixel 23c) in the bottom row (second row).
  • Pixel 21b has one subpixel (subpixel 23c) in the top row (first row) and two subpixels (subpixel 23a and subpixel 23b) in the bottom row (second row).
  • Figure 34D shows an example in which each subpixel has a generally rectangular planar shape with rounded corners
  • Figure 34E shows an example in which each subpixel has a circular planar shape
  • Figure 34F shows an example in which each subpixel has a generally hexagonal planar shape with rounded corners.
  • each subpixel is arranged inside a close-packed hexagonal region.
  • Each subpixel is arranged so that when focusing on one subpixel, it is surrounded by six other subpixels.
  • subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on subpixel 23a, three subpixels 23b and three subpixels 23c are arranged alternately around it.
  • Figure 34G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, in a plan view, the positions of the top sides of two subpixels (e.g., subpixels 23a and 23b, or subpixels 23b and 23c) aligned in the row direction are misaligned.
  • two subpixels e.g., subpixels 23a and 23b, or subpixels 23b and 23c
  • subpixel 23a is subpixel R that emits red light
  • subpixel 23b is subpixel G that emits green light
  • subpixel 23c is subpixel B that emits blue light.
  • the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately.
  • subpixel 23b may be subpixel R that emits red light
  • subpixel 23a may be subpixel G that emits green light.
  • the finer the pattern to be processed the more the effects of light diffraction cannot be ignored, and this causes a loss of fidelity when the photomask pattern is transferred by exposure, making it difficult to process the resist mask into the desired shape.
  • the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed.
  • the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.
  • OPC Optical Proximity Correction
  • a pixel can be configured to have four types of subpixels.
  • the pixels 21 shown in Figures 35A to 35C are arranged in a stripe pattern.
  • Figure 35A shows an example where each subpixel has a rectangular planar shape
  • Figure 35B shows an example where each subpixel has a planar shape that combines two semicircles and a rectangle
  • Figure 35C shows an example where each subpixel has an elliptical planar shape.
  • the pixels 21 shown in Figures 35D to 35F are arranged in a matrix.
  • Figure 35D shows an example where each subpixel has a square planar shape
  • Figure 35E shows an example where each subpixel has a roughly square planar shape with rounded corners
  • Figure 35F shows an example where each subpixel has a circular planar shape.
  • Figures 35G and 35H show an example in which one pixel 21 is configured with two rows and three columns.
  • Pixel 21 shown in FIG. 35G has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and one subpixel (subpixel 23d) in the bottom row (second row).
  • pixel 21 has subpixel 23a in the left column (first column), subpixel 23b in the center column (second column), subpixel 23c in the right column (third column), and subpixel 23d across these three columns.
  • the pixel 21 shown in FIG. 35H has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and three subpixels 23d in the bottom row (second row).
  • the pixel 21 has subpixels 23a and 23d in the left column (first column), subpixels 23b and 23d in the center column (second column), and subpixels 23c and 23d in the right column (third column).
  • FIG. 35H by aligning the arrangement of the subpixels in the top row and the bottom row, it is possible to efficiently remove dust that may occur during the manufacturing process, for example. Therefore, a display device with high display quality can be provided.
  • Figure 35I shows an example in which one pixel 21 is configured with three rows and two columns.
  • the pixel 21 shown in FIG. 35I has subpixel 23a in the top row (first row), subpixel 23b in the center row (second row), subpixel 23c from the first row to the second row, and one subpixel (subpixel 23d) in the bottom row (third row).
  • pixel 21 has subpixel 23a and subpixel 23b in the left column (first column), subpixel 23c in the right column (second column), and subpixel 23d across these two columns.
  • the pixel 21 shown in Figures 35A to 35I is composed of four subpixels: subpixel 23a, subpixel 23b, subpixel 23c, and subpixel 23d.
  • Subpixels 23a, 23b, 23c, and 23d can each be configured to emit light of a different color.
  • Examples of subpixels 23a, 23b, 23c, and 23d include subpixels of four colors: R, G, B, and white (W), subpixels of four colors: R, G, B, and Y, or subpixels of R, G, B, and infrared light (IR).
  • subpixel 23a is a subpixel R that emits red light
  • subpixel 23b is a subpixel G that emits green light
  • subpixel 23c is a subpixel B that emits blue light
  • subpixel 23d is any one of subpixels W that emit white light
  • subpixel Y that emits yellow light
  • subpixel IR that emits near-infrared light
  • the pixel 21 shown in Figures 35G and 35H has a layout of R, G, and B in a stripe arrangement, which can improve the display quality.
  • the pixel 21 shown in Figure 35I has a layout of R, G, and B in a so-called S-stripe arrangement, which can improve the display quality.
  • Pixel 21 may have a sub-pixel having a light receiving element.
  • any one of subpixels 23a to 23d may be a subpixel having a light receiving element.
  • subpixel 23a is a subpixel R that emits red light
  • subpixel 23b is a subpixel G that emits green light
  • subpixel 23c is a subpixel B that emits blue light
  • subpixel 23d is a subpixel S that has a light receiving element.
  • the pixel 21 shown in Figures 35G and 35H has a layout of R, G, and B in a stripe arrangement, which can improve the display quality.
  • the pixel 21 shown in Figure 35I has a layout of R, G, and B in a so-called S-stripe arrangement, which can improve the display quality.
  • the wavelength of light detected by the subpixel S having a light receiving element is not particularly limited.
  • the subpixel S can be configured to detect either or both of visible light and infrared light.
  • a pixel can be configured to have five types of subpixels.
  • Figure 35J shows an example in which one pixel 21 is configured with two rows and three columns.
  • Pixel 21 shown in FIG. 35J has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and two subpixels (subpixels 23d and 23e) in the bottom row (second row).
  • pixel 21 has subpixels 23a and 23d in the left column (first column), subpixel 23b in the center column (second column), subpixel 23c in the right column (third column), and subpixel 23e from the second column to the third column.
  • Figure 35K shows an example in which one pixel 21 is configured with three rows and two columns.
  • Pixel 21 shown in FIG. 35K has subpixel 23a in the top row (first row), subpixel 23b in the center row (second row), subpixel 23c from the first row to the second row, and two subpixels (subpixel 23d and subpixel 23e) in the bottom row (third row).
  • pixel 21 has subpixel 23a, subpixel 23b, and subpixel 23d in the left column (first column), and subpixel 23c and subpixel 23e in the right column (second column).
  • subpixel 23a is a subpixel R that emits red light
  • subpixel 23b is a subpixel G that emits green light
  • subpixel 23c is a subpixel B that emits blue light.
  • the pixel 21 shown in Figure 35J has a layout of R, G, and B in a stripe arrangement, which can improve display quality.
  • the pixel 21 shown in Figure 35K has a layout of R, G, and B in a so-called S-stripe arrangement, which can improve display quality.
  • each pixel 21 shown in Figures 35J and 35K it is preferable to apply a subpixel S having a light receiving element to at least one of subpixels 23d and 23e.
  • the configurations of the light receiving elements may be different from each other.
  • the wavelength ranges of light detected may differ at least in part from each other.
  • one of subpixels 23d and 23e may have a light receiving element that mainly detects visible light, and the other may have a light receiving element that mainly detects infrared light.
  • each pixel 21 shown in Figures 35J and 35K for example, it is preferable to use a subpixel S having a light receiving element as one of subpixels 23d and 23e, and a subpixel having a light emitting element that can be used as a light source as the other.
  • a subpixel IR that emits infrared light
  • a subpixel S having a light receiving element that detects infrared light as the other.
  • an image can be displayed using the sub-pixels R, G, B, IR, and S, while the sub-pixel IR can be used as a light source to detect reflected infrared light emitted by the sub-pixel IR at the sub-pixel S.
  • the display device of one embodiment of the present invention can apply various layouts to pixels configured with subpixels having display elements. Furthermore, the display device of one embodiment of the present invention can apply a configuration in which the pixel has both a light-emitting element and a light-receiving element. Even in this case, various layouts can be applied.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • the display device of this embodiment may have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include a surface capacitance type and a projected capacitance type.
  • Examples of the projected capacitance type include a self-capacitance type and a mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.
  • FIG. 36 is a perspective view showing a configuration example of a display device 10A.
  • Display device 10A has a configuration in which substrate 152 and substrate 102 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 10A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, and the like.
  • FIG. 36 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 10A. Therefore, the configuration shown in FIG. 36 can also be said to be a display module having the display device 10A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140.
  • FIG. 36 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164.
  • the signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.
  • FIG. 36 shows an example in which an IC 173 is provided on a substrate 102 by a COG method or a COF method.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 10A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by, for example, a COF method.
  • the semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 10A.
  • An oxide semiconductor (OS) can be preferably used for a channel formation region of a transistor included in the display device.
  • OS oxide semiconductor
  • the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this manner, an effect of keeping manufacturing costs low can be obtained.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device, the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using the semiconductor device in the display device.
  • the display unit 162 is an area in the display device 10A that displays an image, and has a number of periodically arranged pixels 21.
  • Figure 36 shows an enlarged view of one pixel 21.
  • the pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied.
  • Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • the pixel 21 shown in FIG. 36 has a sub-pixel 23R that emits red light, a sub-pixel 23G that emits green light, and a sub-pixel 23B that emits blue light. Note that the number of sub-pixels that one pixel has is not particularly limited.
  • Subpixel 23R, subpixel 23G, and subpixel 23B each have a display element and a circuit that controls the driving of the display element.
  • the display element including, for example, a light-emitting element and a liquid crystal element.
  • a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type, etc., can also be used.
  • a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may be used.
  • Figure 37A shows an example of a cross section of the display device 10A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.
  • the display device 10A shown in FIG. 37A has transistors 205D, 205R, 205G, and 205B, light-emitting elements 60R, 60G, and 60B between the substrate 102 and the substrate 152.
  • the light-emitting element 60R is a display element included in the subpixel 23R that emits red light
  • the light-emitting element 60G is a display element included in the subpixel 23G that emits green light
  • the light-emitting element 60B is a display element included in the subpixel 23B that emits blue light.
  • the description of the light-emitting element 60 in the first embodiment can be applied to the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.
  • the display device 10A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 10A is a top emission type.
  • a transistor in a top emission type, for example, can be arranged so as to overlap the light emitting region of a light emitting element, so that the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • Transistor 205D, transistor 205R, transistor 205G, and transistor 205B are all formed on substrate 102. These transistors can be manufactured using the same material and in the same process. Note that transistors 205D, transistor 205R, transistor 205G, and transistor 205B may have different structures.
  • the display device 10A includes the transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the transistors of one embodiment of the present invention in the display portion 162 the pixel size can be reduced and high definition can be achieved.
  • the transistors of one embodiment of the present invention in the circuit portion 164 the area occupied by the circuit portion 164 can be reduced and a narrower frame can be achieved.
  • the description of the previous embodiment can be referred to.
  • the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each have a conductive layer 104 functioning as a gate, an insulating layer 106 functioning as a gate insulating layer, a conductive layer 103 functioning as a back gate, an insulating layer 105 functioning as a back gate insulating layer, a conductive layer 112a and a conductive layer 112b functioning as a source and a drain, a semiconductor layer 108 having a metal oxide, and an insulating layer 110.
  • the insulating layer 105a may be provided so as to cover at least a part of the side surface of the conductive layer 112b.
  • the insulating layer 105a may have a region in contact with the side surface of the conductive layer 112b.
  • FIG. 37A shows an example in which the insulating layer 110 has a three-layer stacked structure of the insulating layer 110a, the insulating layer 110b on the insulating layer 110a, and the insulating layer 110c on the insulating layer 110b.
  • the following drawings also show an example in which the insulating layer 110 has a three-layer stacked structure.
  • Insulating layer 110 is provided so as to cover the end of conductive layer 112a.
  • Conductive layer 112b is provided on insulating layer 110.
  • Insulating layer 106 is provided between conductive layer 104 and semiconductor layer 108.
  • the transistors included in the display device of this embodiment are not limited to the transistors of one embodiment of the present invention.
  • the display device may include a combination of a transistor of one embodiment of the present invention and a transistor having another structure.
  • the display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors of the display device of this embodiment may be either a top-gate type or a bottom-gate type. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.
  • the display device of this embodiment may also have a Si transistor.
  • the transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures.
  • the transistors in the circuit unit 164 may all have the same structure or may have two or more types.
  • the transistors in the display unit 162 may all have the same structure or may have two or more types.
  • An insulating layer 107 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on insulating layer 107.
  • the insulating layer 107 preferably functions as a protective layer for the transistor.
  • the insulating layer 107 is preferably made of a material through which impurities such as water and hydrogen are unlikely to diffuse. This allows the insulating layer 107 to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing from the outside into the transistor, and the reliability of the display device can be improved.
  • the insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film.
  • Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film.
  • the outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 235 when processing the pixel electrodes 111R, 111G, and 111B. Alternatively, recesses may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, and 111B.
  • Light-emitting elements 60R, 60G, and 60B are provided on insulating layer 235.
  • the light-emitting element 60R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 60R shown in FIG. 37A emits red light (R).
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 60G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light-emitting element 60G shown in FIG. 37A emits green light (G).
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 60B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light-emitting element 60B shown in FIG. 37A emits blue light (B).
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • EL layers 113R, 113G, and EL layers 113B are all shown to have the same thickness, but this is not limited to the above.
  • EL layers 113R, 113G, and EL layers 113B may each have a different thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layers 106, 107, and 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the ends of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall.
  • the insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 107 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode.
  • the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the insulating layer 237 is provided at least in the display section 162.
  • the insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164.
  • the insulating layer 237 may also be provided up to the edge of the display device 10A.
  • the common electrode 115 is a continuous film that is provided in common to the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.
  • the common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 183 provided in the connection portion 140.
  • a conductive layer 183 it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light is used for the pixel electrode and the common electrode, which is the electrode from which light is extracted. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these in appropriate combinations.
  • Examples of the material include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • Examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), as well as alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive/semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 37A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • the EL layer 113R, the EL layer 113G, and the EL layer 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting material.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably has, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • the light-emitting element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers constituting the light-emitting element can be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units) may be applied to the light-emitting element.
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure can be used to make a light-emitting element capable of emitting high-luminance light.
  • the tandem structure can reduce the current required to obtain the same luminance compared to the single structure, and therefore can improve reliability.
  • the tandem structure may also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting element.
  • the space between the substrate 152 and the substrate 102 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (nitrogen, argon, etc.) and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting element.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162.
  • the protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164.
  • the protective layer 131 is also preferably provided up to the end of the display device 10A.
  • the connection unit 197 there are portions where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light-emitting element can be improved.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 115 and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.
  • the protective layer 131 preferably has one or more inorganic insulating layers.
  • the protective layer 131 can be made of a material that can be used for the insulating layer 110.
  • the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.
  • the protective layer 131 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, specifically, a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 can be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using such a laminated structure, it is possible to prevent impurities (water, oxygen, etc.) from entering the EL layer side.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.
  • a connection portion 197 is provided in an area of the substrate 102 where the substrate 152 does not overlap.
  • the conductive layer 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242.
  • the conductive layer 165 can be a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 can be a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the connection portion between the conductive layer 165 and the conductive layer 166 can be configured similarly to the connection portion between the pixel electrodes 111R, 111G, and 111B and the conductive layer 112b. Specifically, FIG.
  • connection portion 197 shows an example in which an opening is provided in the upper layer of the conductive layer 165, and the conductive layer 166 contacts the upper surface of the conductive layer 165 through the opening.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 10A is a top emission type. Light emitted by the light emitting elements is emitted toward the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of the substrate 152 facing the substrate 102 or on the protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • the colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • a metal material a resin material, a pigment, and a dye
  • the colored layers are formed at the desired positions by a printing method, an inkjet method, or an etching method using photolithography.
  • optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 102).
  • optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light collecting film.
  • a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, or an impact absorbing layer may be arranged on the outside of the substrate 152.
  • a glass layer or a silica layer As the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • a polyester-based material a polycarbonate-based material, or the like
  • the substrate 102 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like.
  • a material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted.
  • a flexible material is used for the substrate 102 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized.
  • a polarizing plate may be used for at least one of the substrates 102 and 152.
  • the substrate 102 and the substrate 152 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, or the like. At least one of the substrates 102 and 152 may be made of glass having a thickness sufficient to provide flexibility.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • various curing adhesives can be used, such as a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, or an anaerobic adhesive.
  • a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, or an anaerobic adhesive.
  • these adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin are preferable.
  • a two-part mixed resin may also be used.
  • an adhesive sheet may also be used.
  • connection layer 242 may be an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP), etc.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • FIG. 37B shows an example of a cross section of the display unit 162 of the display device 10B.
  • the display device 10B is mainly different from the display device 10A in that a light-emitting element having a common EL layer 113 and a colored layer (color filter) are used in each subpixel of each color.
  • the configuration shown in FIG. 37B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 102 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 37A.
  • the description of the same parts as those of the display device described above will be omitted as appropriate.
  • the display device 10B shown in FIG. 37B has light-emitting elements 60R, 60G, and 60B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light-emitting element 60R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 60R is extracted as red light to the outside of the display device 10B via the colored layer 132R.
  • the light-emitting element 60G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 60G is extracted as green light to the outside of the display device 10B via the colored layer 132G.
  • the light-emitting element 60B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 60B is extracted as blue light to the outside of the display device 10B via the colored layer 132B.
  • Light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B each share an EL layer 113 and a common electrode 115.
  • a configuration in which a common EL layer 113 is provided for subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.
  • the light-emitting elements 60R, 60G, and 60B shown in FIG. 37B emit white light.
  • the white light emitted by the light-emitting element 60R passes through the colored layer 132R
  • the white light emitted by the light-emitting element 60G passes through the colored layer 132G
  • the white light emitted by the light-emitting element 60B passes through the colored layer 132B. This makes it possible to obtain light of the desired color.
  • a light-emitting element that emits white light preferably includes two or more light-emitting layers.
  • light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting element as a whole emits white light.
  • the emission colors of the three or more light-emitting layers can be combined to obtain a configuration in which the light-emitting element as a whole emits white light.
  • the EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, red light, and a light-emitting unit that emits blue light, etc.
  • the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B.
  • the number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B shown in FIG. 37B emit blue light.
  • the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 23B that emits blue light, the blue light emitted by the light-emitting element 60B can be extracted.
  • a color conversion layer is provided between the light-emitting element 60R or the light-emitting element 60G and the substrate 152, so that the blue light emitted by the light-emitting element 60R or the light-emitting element 60G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • a part of the light emitted by the light-emitting element may be transmitted as it is without being converted by the color conversion layer.
  • the color conversion layer By extracting the light that has passed through the color conversion layer via the colored layer, light other than the desired color is absorbed by the colored layer, and the color purity of the light emitted by the subpixel can be increased.
  • Display device 10C A display device 10C shown in FIG. 38 differs from the display device 10B mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 102. It is preferable to use a material that is highly transparent to visible light for the substrate 102. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.
  • FIG. 38 shows an example in which the light-shielding layer 117 is provided on the substrate 102, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 107, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the light-emitting element 60R which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.
  • the light-emitting element 60G which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.
  • the light-emitting element 60B which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.
  • the pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115.
  • the common electrode 115 can be made of, for example, a metal with low electrical resistivity, so that voltage drops caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.
  • a display device 10D shown in FIG. 39A differs from the display device 10A mainly in that a light receiving element 61 is included.
  • the display device 10D has a light-emitting element and a light-receiving element in each pixel.
  • the organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device that uses an organic EL element.
  • the pixels In the display device 10D, in which the pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, and therefore it is possible to detect the contact or proximity of an object while displaying an image. Therefore, in addition to the image display function, the display unit 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all of the sub-pixels of the display device 10D, some of the sub-pixels can emit light as a light source, some other sub-pixels can perform light detection, and the remaining sub-pixels can display the image.
  • the display device 10D it is not necessary to provide a light receiving unit and a light source separately from the display device 10D, and the number of parts in the electronic device can be reduced. For example, it is not necessary to provide a separate biometric authentication device in the electronic device, or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 10D, it is possible to provide an electronic device with reduced manufacturing costs.
  • the display device 10D can capture an image using the light receiving element.
  • the image sensor can be used to capture images for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.
  • the light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor).
  • a touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object are in direct contact with each other.
  • a non-contact sensor can detect an object even if the object does not touch the display device.
  • the light receiving element 61 has a pixel electrode 111S on the insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S.
  • Light Lin is incident on the functional layer 113S from outside the display device 10D.
  • the pixel electrode 111S is electrically connected to the conductive layer 112b of the transistor 205S through openings provided in the insulating layers 106, 107, and 235.
  • the ends of the pixel electrode 111S are covered by an insulating layer 237.
  • the common electrode 115 is a continuous film provided in common to the light receiving element 61, the light emitting element 60R (not shown), the light emitting element 60G, and the light emitting element 60B.
  • the common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 183 provided in the connection portion 140.
  • the functional layer 113S has at least an active layer (also called a photoelectric conversion layer).
  • the active layer includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds.
  • an organic semiconductor is used as the semiconductor of the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition method), which is preferable because the manufacturing equipment can be shared.
  • the functional layer 113S may further include a layer containing a material with high hole transport properties, a material with high electron transport properties, or a bipolar material, as a layer other than the active layer.
  • the functional layer 113S may further include a layer containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material.
  • the materials that can be used in the light-emitting element described above can be used for the functional layer 113S.
  • the light receiving element may be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers constituting the light receiving element may be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the display device 10D shown in Figures 39B and 39C has a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element between the substrate 102 and the substrate 152.
  • Layer 353 has, for example, a light receiving element 61.
  • Layer 357 has, for example, a light emitting element 60R, a light emitting element 60G, and a light emitting element 60B.
  • the circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element.
  • the circuit layer 355 has, for example, a transistor 205R, a transistor 205G, and a transistor 205B.
  • the circuit layer 355 may be provided with one or more of a switch, a capacitance, a resistance, a wiring, a terminal, and the like.
  • Figure 39B shows an example in which the light receiving element 61 is used as a touch sensor. As shown in Figure 39B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 10D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 10D.
  • Figure 39C shows an example in which the light receiving element 61 is used as a non-contact sensor. As shown in Figure 39C, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 10D, and the light receiving element in layer 353 detects the reflected light.
  • Display device 10E] 40A is an example of a display device to which an MML (metal maskless) structure is applied, that is, the display device 10E has light-emitting elements fabricated without using a fine metal mask.
  • MML metal maskless
  • the island-shaped light-emitting layer in the light-emitting element of a display device to which the MML structure is applied is formed by depositing a light-emitting layer on one surface and then processing it using a photolithography method. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • the deposition of the light-emitting layer and processing by photolithography can be repeated three times to form three types of island-shaped light-emitting layers.
  • Devices with an MML structure can be manufactured without using a metal mask, and therefore can exceed the upper limit of resolution resulting from the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the process of cleaning the metal mask can be eliminated. Furthermore, since the same or similar equipment as that used to manufacture transistors can be used for photolithography processing, there is no need to introduce special equipment to manufacture devices with an MML structure. In this way, the MML structure makes it possible to keep manufacturing costs low, and is therefore suitable for mass production of devices.
  • a display device to which the MML structure is applied there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, so it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) with a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.
  • the layered structure from the substrate 102 to the insulating layer 235, and the layered structure from the protective layer 131 to the substrate 152 are similar to those of the display device 10A, and therefore will not be described.
  • light-emitting elements 60R, 60G, and 60B are provided on insulating layer 235.
  • the light-emitting element 60R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 60R shown in FIG. 40A emits red light (R).
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layers 124R and 126R can be referred to as a pixel electrode.
  • the light-emitting element 60G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114.
  • the light-emitting element 60G shown in FIG. 40A emits green light (G).
  • the layer 133G has a light-emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.
  • the light-emitting element 60B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114.
  • the light-emitting element 60B shown in FIG. 40A emits blue light (B).
  • the layer 133B has a light-emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as a common layer 114.
  • the layers 133R, 133G, and 133B may be referred to as island-shaped EL layers, EL layers formed in an island shape, etc., without including the common layer 114.
  • a light-emitting element manufactured without using a metal mask may not have a common layer, and all layers constituting the EL layer may be formed in an island shape.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the EL layer in an island shape for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission caused by crosstalk, and to realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited to this. Layers 133R, 133G, and 133B may each have a different thickness.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layers 106, 107, and 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • the layer 128 has a function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • the conductive layer 126R, the conductive layer 126G, and the conductive layer 126B, which are electrically connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, are provided on the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B and the layer 128.
  • the region overlapping with the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B can also be used as a light-emitting region, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be applied to layer 128.
  • FIG. 40A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • Conductive layers 124G, 126G, 124B, and 126B are similar to conductive layers 124R and 126R, so detailed descriptions are omitted.
  • conductive layer 126R The upper surface and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper surface and side surfaces of conductive layer 126G are covered by layer 133G, and the upper surface and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layer 126R, conductive layer 126G, and conductive layer 126B are provided can be used as the light-emitting area of light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B, thereby increasing the aperture ratio of the pixel.
  • a common layer 114 is provided on layers 133R, 133G, and 133B, and insulating layers 185 and 187, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each continuous films provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 37A is not provided between the conductive layer 126R and the layer 133R.
  • the display device 10E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This makes it possible to provide a high-definition or high-resolution display device.
  • a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.
  • Insulating layer 187 covers the sides of layers 133R, 133G, and 133B via insulating layer 185.
  • the insulating layer 185 is preferably in contact with the side surfaces of the layers 133R, 133G, and 133B. By configuring the insulating layer 185 to be in contact with the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.
  • the insulating layer 187 is provided on the insulating layer 185 so as to fill the recesses in the insulating layer 185. It is preferable that the insulating layer 187 covers at least a portion of the side surface of the insulating layer 185.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (e.g., the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. Therefore, the coverage of the carrier injection layer, the common electrode, etc. can be improved.
  • layers e.g., the carrier injection layer and the common electrode
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, 133B, the insulating layer 185, and the insulating layer 187. Before the insulating layer 185 and the insulating layer 187 are provided, there is a step due to the region where the pixel electrode and the island-shaped EL layer are provided and the region where the pixel electrode and the island-shaped EL layer are not provided (the region between the light-emitting elements). In the display device of one embodiment of the present invention, the step can be flattened by having the insulating layer 185 and the insulating layer 187, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, it is possible to suppress an increase in electrical resistance due to local thinning of the common electrode 115 due to the step.
  • the upper surface of the insulating layer 187 preferably has a shape with high flatness.
  • the upper surface of the insulating layer 187 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 187 preferably has a convex curved shape with a large radius of curvature.
  • the insulating layer 185 may have a single layer structure or a laminated structure of two or more layers.
  • the insulating layer 185 preferably has one or more inorganic insulating layers.
  • the insulating layer 185 may be made of a material that can be used for the insulating layer 110.
  • aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 187.
  • an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method to the insulating layer 185, it is possible to form an insulating layer 185 that has few pinholes and has an excellent function of protecting the EL layer.
  • the insulating layer 185 may also have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 185 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 185 preferably functions as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 185 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 185 preferably has a function of capturing or fixing (gettering) at least one of water and oxygen.
  • the insulating layer 185 functions as a barrier insulating layer, making it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and further a highly reliable display device.
  • impurities typically at least one of water and oxygen
  • the insulating layer 185 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 185 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 185, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 185 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, preferably both.
  • the insulating layer 187 provided on the insulating layer 185 has the function of flattening the unevenness of the insulating layer 185 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 187 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 187 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 187 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • a photoresist may be used as the photosensitive resin.
  • Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.
  • the insulating layer 187 may be made of a material that absorbs visible light. By having the insulating layer 187 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 187 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • FIG. 40B shows an example of a cross section of the display unit 162 of the display device 10F.
  • the display device 10F is different from the display device 10E mainly in that a light-emitting element having a layer 133 and a colored layer (color filter) are used in each subpixel of each color.
  • the configuration shown in Fig. 40B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 102 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Fig. 40A.
  • the display device 10F shown in FIG. 40B has light-emitting elements 60R, 60G, and 60B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light emitted by the light-emitting element 60R is extracted as red light to the outside of the display device 10F through the colored layer 132R.
  • the light emitted by the light-emitting element 60G is extracted as green light to the outside of the display device 10F through the colored layer 132G.
  • the light emitted by the light-emitting element 60B is extracted as blue light to the outside of the display device 10F through the colored layer 132B.
  • Each of the light-emitting elements 60R, 60G, and 60B has a layer 133. These three layers 133 are formed using the same material and in the same process. In addition, these three layers 133 are separated from each other. By providing an island-shaped EL layer for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.
  • the light-emitting elements 60R, 60G, and 60B shown in FIG. 40B emit white light.
  • the white light emitted by the light-emitting element 60R passes through the colored layer 132R
  • the white light emitted by the light-emitting element 60G passes through the colored layer 132G
  • the white light emitted by the light-emitting element 60B passes through the colored layer 132B. This makes it possible to obtain light of the desired color.
  • the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B shown in FIG. 40B emit blue light.
  • the layer 133 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 60B can be extracted.
  • a color conversion layer is provided between the light-emitting element 60R or the light-emitting element 60G and the substrate 152, so that the blue light emitted by the light-emitting element 60R or the light-emitting element 60G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • Display device 10G A display device 10G shown in FIG. 41 differs from the display device 10F mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 102. It is preferable to use a material that is highly transparent to visible light for the substrate 102. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.
  • FIG. 41 shows an example in which the light-shielding layer 117 is provided on the substrate 102, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 107, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the light-emitting element 60R which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 60G which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 60B which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.
  • Conductive layer 124R, conductive layer 124G, conductive layer 124B, conductive layer 126R, conductive layer 126G, and conductive layer 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for common electrode 115. In a bottom emission type display device, for example, a metal with low electrical resistivity can be used for common electrode 115, so that voltage drop caused by the resistance of common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.
  • a display device 10H shown in FIG. 42 is a VA mode liquid crystal display device.
  • Substrate 102 and substrate 152 are bonded together by adhesive layer 144.
  • Liquid crystal 262 is sealed in the area surrounded by substrate 102, substrate 152, and adhesive layer 144.
  • Polarizing plate 260a is located on the outer surface of substrate 152
  • polarizing plate 260b is located on the outer surface of substrate 102.
  • a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.
  • Transistors 205D, 205R, and 205G, a connection portion 197, and a spacer 224 are provided on the substrate 102.
  • the transistor 205D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162.
  • the conductive layer 112b of the transistors 205R and 205G functions as a pixel electrode of the liquid crystal element 69.
  • the substrate 152 is provided with a colored layer 132R, a colored layer 132G, a light-shielding layer 117, an insulating layer 225, and a conductive layer 263.
  • the conductive layer 263 functions as a common electrode for the liquid crystal element 69.
  • the display device 10H includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the transistors of one embodiment of the present invention in the display portion 162 the pixel size can be reduced and high definition can be achieved.
  • the transistors of one embodiment of the present invention in the circuit portion 164 the area occupied by the circuit portion 164 can be reduced and a narrower frame can be achieved.
  • the transistors of one embodiment of the present invention refer to the description of the previous embodiment.
  • Transistor 205D, transistor 205R, and transistor 205G are covered with insulating layer 107.
  • Insulating layer 107 functions as a protective layer for transistor 205D, transistor 205R, and transistor 205G.
  • the subpixels in the display unit 162 each have a transistor, a liquid crystal element 69, and a colored layer.
  • a subpixel that emits red light has a transistor 205R, a liquid crystal element 69, and a colored layer 132R that transmits red light.
  • a subpixel that emits green light has a transistor 205G, a liquid crystal element 69, and a colored layer 132G that transmits green light.
  • a subpixel that emits blue light similarly has a transistor, a liquid crystal element 69, and a colored layer that transmits blue light.
  • the liquid crystal element 69 has a conductive layer 112b, a conductive layer 263, and a liquid crystal 262 sandwiched between them.
  • a conductive layer 264 is provided on the substrate 102 and is located on the same plane as the conductive layer 112a.
  • the conductive layer 264 has a portion that overlaps with the conductive layer 112b via the insulating layer 110.
  • a storage capacitor is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 between them. Note that it is sufficient that there is one or more insulating layers between the conductive layer 112b and the conductive layer 264, and one or two of the insulating layers 110 may be removed by etching.
  • an insulating layer 225 is provided to cover the colored layer 132R, the colored layer 132G, and the light-shielding layer 117.
  • the insulating layer 225 may function as a planarizing film.
  • the insulating layer 225 can make the surface of the conductive layer 263 roughly flat, so that the orientation state of the liquid crystal 262 can be made uniform.
  • an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surfaces of the conductive layer 263 and the insulating layer 107, etc. that come into contact with the liquid crystal 262 (see the alignment film 265 in Figures 44A and 44B).
  • the conductive layer 112b and the conductive layer 263 transmit visible light.
  • a transmissive liquid crystal device can be used.
  • the orientation of the liquid crystal 262 can be controlled by the voltage applied between the conductive layer 112b and the conductive layer 263, and the optical modulation of the light can be controlled.
  • the intensity of the light emitted through the polarizing plate 260b can be controlled.
  • the colored layer absorbs light other than a specific wavelength range of the incident light, so that the extracted light is, for example, red light.
  • a linear polarizing plate may be used as polarizing plate 260b, but a circular polarizing plate may also be used.
  • a circular polarizing plate for example, a linear polarizing plate and a quarter-wave retardation plate stacked together may be used.
  • polarizer 260b When a circular polarizer is used as polarizer 260b, a circular polarizer may also be used as polarizer 260a, or a normal linear polarizer may be used. Depending on the type of polarizer used for polarizers 260a and 260b, the cell gap, orientation, driving voltage, etc. of the liquid crystal element used in liquid crystal element 69 can be adjusted to achieve the desired contrast.
  • the conductive layer 263 is electrically connected to the conductive layer 166b provided on the substrate 102 side by the connector 223 at the connection portion 140.
  • the conductive layer 166b is connected to the conductive layer 165b through an opening provided in the insulating layer 110 and the insulating layer 105. This allows a potential or signal to be supplied to the conductive layer 263 from an FPC or IC arranged on the substrate 102 side.
  • the conductive layer 165b is formed to the same extent using the same material as the conductive layer 112a, and the conductive layer 166b is formed in the same process using the same material as the conductive layer 104.
  • conductive particles can be used as the connector 223.
  • the conductive particles particles of organic resin or silica, etc., whose surfaces are coated with a metal material can be used.
  • Nickel or gold is preferably used as the metal material because it can reduce the contact resistance.
  • particles coated with two or more metal materials in layers, such as nickel further coated with gold It is also preferable to use a material that undergoes elastic deformation or plastic deformation as the connector 223. In this case, the conductive particles may be crushed in the vertical direction as shown in FIG. 42. This increases the contact area between the connector 223 and the conductive layer electrically connected thereto, thereby reducing the contact resistance and suppressing the occurrence of problems such as poor connection.
  • connection portion 197 is provided in a region near the end of the substrate 102.
  • the conductive layer 166a is electrically connected to the FPC 172 via the connection layer 242.
  • the conductive layer 166a is connected to the conductive layer 165a via an opening provided in the insulating layer 110 and the insulating layer 105.
  • the conductive layer 165a is formed in the same process using the same material as the conductive layer 112a, and the conductive layer 166a is formed in the same process using the same material as the conductive layer 104.
  • Display device 10I] 43 is a liquid crystal display device in the FFS mode.
  • the display device 10I differs from the display device 10H mainly in the configuration of the liquid crystal element 69.
  • a conductive layer 263 that functions as a common electrode of the liquid crystal element 69 is provided on the insulating layer 110, and an insulating layer 261 is provided on the conductive layer 263.
  • a conductive layer 112b that functions as the other of the source and drain electrodes of the transistor and as a pixel electrode of the liquid crystal element 69 is provided on the insulating layer 261.
  • An insulating layer 107 is provided on the conductive layer 112b.
  • the conductive layer 112b has a comb-like shape or a shape with slits in a plan view.
  • the conductive layer 263 is arranged to overlap the conductive layer 112b. In the area overlapping the colored layer, there is a portion on the conductive layer 263 where the conductive layer 112b is not arranged.
  • a capacitance is formed by stacking the conductive layer 112b and the conductive layer 263 with the insulating layer 261 interposed therebetween. This eliminates the need to form a separate capacitive element, and allows the aperture ratio of the pixel to be increased.
  • both the conductive layer 112b and the conductive layer 263 may have a comb-like planar shape.
  • the conductive layer 112b and the conductive layer 263 partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 263 to be used as a storage capacitance, making it unnecessary to provide a separate capacitance element, and increasing the aperture ratio of the display device.
  • Display device 10J In the display device 10J shown in Fig. 44A, a portion of the insulating layer 110b that overlaps with the liquid crystal element 69 is removed by etching.
  • the liquid crystal element 69 of the display device 10J has a portion in which a conductive layer 112b, an insulating layer 110a, an insulating layer 110c, and a conductive layer 112b are stacked in this order.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 69.
  • the conductive layer 112m functions as a common electrode of the liquid crystal element 69.
  • the conductive layer 112m is formed from the same conductive film as the conductive layer 112a.
  • either one of the insulating layers 106 and 107, or both, may have a portion that overlaps with the liquid crystal element 69 removed by etching.
  • the insulating layer 107 may not be provided. This allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262, enabling high-speed operation of the liquid crystal element 69.
  • the light transmittance in the portion that overlaps with the liquid crystal element 69 increased, but the effects of interface reflection and interface scattering can be suppressed.
  • either one of the insulating layers 110a and 110c may have a portion that overlaps with the liquid crystal element 69 removed by etching. This also allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262.
  • the capacitance between the conductive layer 112b and the conductive layer 112m may be increased in some cases.
  • both the conductive layer 112b and the conductive layer 112m may have a comb-tooth planar shape.
  • the conductive layer 112b and the conductive layer 112m are configured to partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 112m to be used as a storage capacitance, eliminating the need to provide a separate capacitive element and increasing the aperture ratio of the display device.
  • Display device 10K] 44B is different from the display device 10I mainly in that a pixel electrode is provided over a common electrode.
  • a conductive layer 112b included in the transistor 100 functions as a pixel electrode in a liquid crystal element 69.
  • An insulating layer 106 and an insulating layer 107 are provided over the conductive layer 112b, and a conductive layer 263 is provided over the insulating layer 107.
  • the conductive layer 263 functions as a common electrode in the liquid crystal element 69.
  • the conductive layer 263 has a comb-like shape or a shape provided with slits in a plan view.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can be applied to portions other than the display portion of electronic devices.
  • portions other than the display portion of electronic devices For example, by using the semiconductor device of one embodiment of the present invention in a control portion of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Examples of electronic devices include electronic devices with relatively large screens such as television devices, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display unit, since it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 45A to 45D An example of a wearable device that can be worn on the head will be described using Figures 45A to 45D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content
  • Electronic device 700A shown in FIG. 45A and electronic device 700B shown in FIG. 45B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device can be applied to the display panel 751. Therefore, the electronic device can display high-quality images.
  • Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply, for example, a video signal through the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are equipped with batteries and can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation, a slide operation, or the like by the user, and perform various processes. For example, a tap operation can perform processes such as pausing or resuming a video, and a slide operation can perform processes such as fast-forwarding or rewinding.
  • a tap operation can perform processes such as pausing or resuming a video
  • a slide operation can perform processes such as fast-forwarding or rewinding.
  • the range of operations can be expanded.
  • Various touch sensors can be applied as the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, or an optical type.
  • a capacitance type or an optical type sensor it is preferable to apply to the touch sensor module.
  • a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 45C and electronic device 800B shown in FIG. 45D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • the display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, the electronic device can display high-quality images. In addition, the electronic device can display images with extremely high resolution, which allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Electrical device 800A and electronic device 800B can each be considered electronic devices for VR.
  • a user wearing electronic device 800A or electronic device 800B can view the image displayed on display unit 820 through lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head. Note that, for example, in FIG. 45C, the mounting unit 823 is shown shaped like the temples of glasses, but is not limited to this. The mounting unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies, for example, a video signal from a video output device and power for charging a battery provided in the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 45A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 45C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 45B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • electronic device 800B shown in FIG. 45D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • electronic devices according to one aspect of the present invention are suitable for both glasses-type devices (such as electronic device 700A and electronic device 700B) and goggle-type devices (such as electronic device 800A and electronic device 800B).
  • An electronic device can transmit information to an earphone via a wired or wireless connection.
  • the electronic device 6500 shown in FIG. 46A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502. Therefore, the electronic device 6500 can be an electronic device that can display high-quality images.
  • Figure 46B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 46C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the television device 7100 can be an electronic device that can display high-quality images.
  • the television device 7100 shown in FIG. 46C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG 46D shows an example of a notebook computer.
  • the notebook computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214.
  • the display unit 7000 is built into the housing 7211.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the notebook computer 7200 can be an electronic device that can display high-quality images.
  • Figures 46E and 46F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 46E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 46F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the digital signage 7300 and the digital signage 7400 can be electronic devices that can display high-quality images.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 47A to 47G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001. Therefore, the electronic devices illustrated in Figures 47A to 47G can be electronic devices that can display high-quality images.
  • the electronic devices shown in Figures 47A to 47G have various functions. For example, they may have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic device are not limited to these, and the electronic device may have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a function of, for example, providing a camera, taking still images or videos, storing them on a recording medium (external or built into the camera), and displaying the taken images on the display unit.
  • FIG. 47A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 47A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notification of an incoming email, SNS, or telephone call, the title of the email or SNS, the sender's name, the date and time, the time, the remaining battery level, and the radio wave intensity.
  • the icon 9050, etc. may be displayed at the position where the information 9051 is displayed.
  • FIG 47B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.
  • FIG 47C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG 47D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself through the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • Figures 47E to 47G are perspective views showing a foldable mobile information terminal 9201.
  • Figure 47E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • Figure 47G is a perspective view of the mobile information terminal 9201 in a folded state
  • Figure 47F is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of Figures 47E and 47G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

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US20220149166A1 (en) * 2020-11-11 2022-05-12 Samsung Electronics Co., Ltd. Field-effect transistor, field-effect transistor array structure and method of manufacturing field-effect transistor
JP2022159517A (ja) * 2017-05-01 2022-10-17 株式会社半導体エネルギー研究所 半導体装置

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JP2022159517A (ja) * 2017-05-01 2022-10-17 株式会社半導体エネルギー研究所 半導体装置
US20220149166A1 (en) * 2020-11-11 2022-05-12 Samsung Electronics Co., Ltd. Field-effect transistor, field-effect transistor array structure and method of manufacturing field-effect transistor

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