WO2024198643A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2024198643A1
WO2024198643A1 PCT/CN2024/072250 CN2024072250W WO2024198643A1 WO 2024198643 A1 WO2024198643 A1 WO 2024198643A1 CN 2024072250 W CN2024072250 W CN 2024072250W WO 2024198643 A1 WO2024198643 A1 WO 2024198643A1
Authority
WO
WIPO (PCT)
Prior art keywords
island
circuit
line
sub
islands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/072250
Other languages
English (en)
French (fr)
Inventor
陈龙
刘胜优
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Publication of WO2024198643A1 publication Critical patent/WO2024198643A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the technical field of display equipment, and in particular to a display panel and a display device.
  • OLED display panels are popular because of their wide viewing angle, ultra-high contrast and fast response.
  • One of the advantages of OLED display substrates is that they can be made flexible. By making OLED devices on flexible substrates, bendable display devices can be realized. However, with the increasing popularity of wearable devices, higher requirements are placed on the stretchability of OLED flexible panels.
  • Embodiments of the present application provide a display panel and a display device, aiming to improve the stretchability of the display panel.
  • An embodiment of the first aspect of the present application provides a display panel, the display panel having a first area and a second area arranged around at least part of the first area, the first area and the second area both including an island area and a stretching area, a plurality of island areas are distributed in an array in the first area and the second area, the stretching area is located between two adjacent rows and/or two adjacent columns of island areas, the display panel comprises: a plurality of functional islands, each functional island is located in each island area and functional parts are arranged on the functional island, the plurality of functional islands include a plurality of pixel islands located in the first area and a plurality of circuit islands located in the second area, the functional parts include a first pixel circuit structure arranged on the pixel island, a first light-emitting unit and a driving circuit structure arranged on the circuit island, the first pixel circuit structure is used to drive the first light-emitting unit to emit light; a stretching portion, arranged in the stretching area and connected between two adjacent functional islands, and in the second area, at
  • the plurality of circuit islands include a first island component, and the first island component includes:
  • the first circuit island, the driving circuit structure includes a shift register unit arranged in the first circuit island,
  • a second circuit island is arranged side by side with the first circuit island, and the driving circuit structure includes a connecting portion arranged on the second circuit island;
  • the signal line includes a first signal line connected to the shift register unit and a second signal line connected to the connecting part.
  • Multiple shift register units are connected to the first pixel circuit structure through at least part of the second signal line, the connecting part and the first signal line to provide a scanning signal to the first pixel circuit structure.
  • a plurality of circuit islands and a plurality of pixel islands are arranged in rows and columns along a first direction and a second direction, and in the circuit islands and pixel islands in the same row, the shift register units on the circuit islands are used to A first pixel circuit structure driving the pixel island along the same line.
  • the first circuit island and the second circuit island of the first island component are arranged side by side along the first direction, and multiple first island components are arranged at intervals along the second direction, the first signal lines of the multiple first circuit islands arranged side by side along the second direction are connected to each other, and the second signal lines of the multiple second circuit islands arranged side by side along the second direction are connected to each other.
  • the first circuit islands of the plurality of first island assemblies spaced apart along the second direction are aligned along the second direction.
  • the second circuit islands of the plurality of first island assemblies spaced apart along the second direction are aligned along the second direction.
  • the functional component also includes a second pixel circuit structure and a second light-emitting unit arranged on at least one of the first circuit island and the second circuit island, and the second pixel circuit structure is used to drive the second light-emitting unit to emit light.
  • a second pixel circuit structure and a second light-emitting unit are provided on the circuit island close to the first area in the first circuit island and the second circuit island of the first island assembly.
  • the first island component includes a first circuit island and two second circuit islands, the two second circuit islands are arranged on both sides of the first circuit island, and the second pixel circuit structure is arranged on the second circuit island located on the first circuit island facing the first area.
  • second light-emitting units are provided on the first circuit island and the second circuit island in the same first island component, and a second pixel circuit structure is provided on one of the first circuit island and the second circuit island in the same first island component, and the second pixel circuit structure is used to drive multiple second light-emitting units in the same first island component to emit light.
  • a virtual pixel circuit is provided on at least one second circuit island.
  • virtual pixel circuits are provided on both second circuit islands, and the sum of the number of second pixel circuit structures and virtual pixel circuits on one of the second circuit islands is equal to the sum of the number of virtual pixel circuits on the other second circuit island.
  • the second light-emitting unit includes a first electrode
  • the signal line includes:
  • a first connecting line used to connect two adjacent first electrodes in the same first island assembly
  • a second connecting line is a scanning line and is used to connect the driving circuit structure and the second pixel circuit structure, or to connect the adjacent first pixel circuit structure and the second pixel circuit structure;
  • a third connecting line is a power signal line and is used to connect the first pixel circuit structure and the second pixel circuit structure;
  • the second connection line connected between two adjacent circuit islands and the first connection line are stacked along the thickness direction of the display panel; and/or the second connection line connected between two adjacent circuit islands and the third connection line are stacked along the thickness direction of the display panel.
  • the second light-emitting unit also includes a second electrode
  • the first signal line also includes a fourth connecting line, which is used to connect the second electrodes on two adjacent circuit islands, and the fourth connecting line and the second connecting line are stacked along the thickness direction.
  • the fourth connecting line and the first electrode are arranged in the same layer and are insulated from each other, and the fourth connecting line is connected to the second electrode via a via.
  • the second connecting line includes a first scanning line and a second scanning line, the first scanning line and the second scanning line are arranged at intervals along the second direction, the first scanning line and the fourth connecting line are arranged in a stacked manner along the thickness direction, the second scanning line and the first connecting line are arranged in a stacked manner along the thickness direction, or the second scanning line and the third connecting line are arranged in a stacked manner along the thickness direction.
  • the signal line includes a line connecting the pixel islands and extending along the second direction.
  • the extended seventh connection line, at least one fourth connection line connects the second circuit island and the pixel island, and the seventh connection line is connected to the pixel island.
  • the signal line includes a data line and a sixth connecting line connected to a second circuit island provided with a second pixel circuit structure, the data line and the sixth connecting line are arranged side by side along a first direction, and the sixth connecting line and the first scanning line are electrically connected to each other.
  • the signal line includes:
  • a clock signal line connected to a second circuit island located away from the first area of the first circuit structure
  • the fifth connecting line connects the clock signal line and the driving circuit structure, and the fifth connecting line connected between two adjacent circuit islands is stacked with the first connecting line along the thickness direction; and/or the fifth connecting line connected between two adjacent circuit islands is stacked with the fourth connecting line along the thickness direction.
  • the clock signal line includes a first clock signal line and a second clock signal line
  • the fifth connecting line includes a first sub-connecting line connected to the first clock signal line and a second sub-connecting line connected to the second clock signal line
  • the first sub-connecting line and the second sub-connecting line are spaced apart along the second direction
  • the first sub-connecting line and the fourth connecting line are stacked along the thickness direction
  • the second sub-connecting line and the first connecting line are stacked along the thickness direction.
  • the signal line also includes redundant routing lines located in the first area and signal routing lines for connecting adjacent first pixel circuit structures, and at least part of the redundant routing lines and the signal routing lines are stacked along the thickness direction.
  • the sum of the number of redundant routing lines and signal routing lines between two adjacent pixel islands is the same as the number of signal lines between two adjacent circuit islands.
  • the redundant wiring between two adjacent pixel islands and at least one of the first connecting line, the second connecting line, the third connecting line and the fourth connecting line are arranged in the same layer and the same material.
  • the first signal line includes a first sub-line, and the first sub-line extends from both sides of the first circuit island in the second direction;
  • the second signal line includes a second sub-line, and the second sub-line extends from both sides of the second circuit island in the second direction.
  • the number of first sub-lines corresponding to each first circuit island is the same as the number of second sub-lines corresponding to each second circuit island.
  • the signal line also includes a driving signal line connected to the first pixel circuit structure, the driving signal line includes a third sub-line, the third sub-line extends from both sides of the pixel island in the second direction, and the number of third sub-lines corresponding to each pixel island is the same as the number of first sub-lines corresponding to each first circuit island.
  • the first signal line includes a fourth sub-line, and the fourth sub-line extends from both sides of the first circuit island in the first direction;
  • the second signal line includes a fifth sub-line, and the fifth sub-line extends from both sides of the second circuit island in the first direction.
  • the number of fourth sub-lines corresponding to each first circuit island is the same as the number of fifth sub-lines corresponding to each second circuit island.
  • the driving signal line includes a sixth sub-line, which extends from both sides of the pixel island in the first direction, and the number of sixth sub-lines corresponding to each pixel island is the same as the number of fourth sub-lines corresponding to each first circuit island.
  • the number of first sub-lines and the number of third sub-lines corresponding to the same first circuit island are the same.
  • the number of second sub-lines and the number of fifth sub-lines corresponding to the same second circuit island are the same.
  • the number of third sub-lines and the number of sixth sub-lines corresponding to the same pixel island are the same.
  • the first pixel circuit structure is electrically connected to each other through the sixth sub-line, the third sub-line and the shift register unit.
  • At least part of the fourth sub-line and at least or part of the sixth sub-line are interconnected, so that the first pixel circuit structure can be electrically connected to each other through the sixth sub-line, the fourth sub-line and the connecting portion.
  • the number of the second circuit island is one, and the second circuit island is arranged on a side of the first circuit island facing toward or away from the first area;
  • the second signal line includes at least one of a clock signal line, a scan line, and a first power signal line.
  • the multiple second circuit islands are arranged on both sides of the first circuit island, or the multiple second circuit islands are arranged on the side of the first circuit island facing or away from the first area.
  • the second region includes a first sub-region extending along the first direction and a second sub-region extending along the second direction, the first island component is located in the second sub-region, and the display panel also includes binding pins, which are located in the first sub-region.
  • At least a portion of the stretching portion is arranged along the first direction and penetrates the second sub-region.
  • the two second sub-areas are arranged on both sides of the first area in the first direction, and the first island component is arranged in each second sub-area.
  • a plurality of binding pins are distributed in the first sub-area at intervals along the second direction.
  • the two first sub-areas are arranged on both sides of the first area in the second direction, and each first sub-area is provided with a binding pin.
  • an extension dimension of the first sub-region in the first direction is smaller than an extension dimension of the second sub-region in the second direction.
  • At least two of the pixel island, the first circuit island, and the second circuit island have the same size.
  • the number of the second circuit islands is two, wherein the second signal lines corresponding to one of the second circuit islands include a first clock signal line and a second clock signal line, and the second signal lines corresponding to the other second circuit island include a scan line and a first power signal line, and the first signal line includes a high-level power line and a low-level power line;
  • the number of the second circuit islands is three or more, and the second signal line corresponding to at least one second circuit island includes a virtual signal line.
  • the second signal line includes virtual signal lines, and the number of the virtual signal lines is symmetrical to the signal lines connected to the same second circuit island.
  • At least a portion of the signal line is arc-shaped.
  • the signal line includes arc segments.
  • two signal lines connected to the same functional island and extending from the same side of the functional island are symmetrically arranged.
  • the embodiment of the first aspect of the present application further provides a display panel, the display panel having a first area and a second area located around the first area, the first area and the second area both including an island area and a stretching area, a plurality of island areas are distributed in an array in the first area and the second area, the stretching area is located between two adjacent rows and/or two adjacent columns of island areas, the display panel comprises: a plurality of functional islands, each functional island is located in each island area and functional parts are arranged on the functional islands, the plurality of functional islands include a plurality of pixel islands located in the first area and a plurality of circuit islands located in the second area, the functional parts include a first pixel circuit structure arranged on the pixel island, a first light-emitting unit and a driving circuit structure arranged on the circuit island, the first pixel circuit structure is used to drive the first light-emitting unit to emit light; a stretching portion is arranged in the stretching area and connected between two adjacent functional islands, and in the second area, to A small part of
  • An embodiment of the second aspect of the present application further provides a display device, comprising a display panel of any of the above-mentioned embodiments of the first aspect.
  • the display panel has a first area and a second area, the first area can be used to set the light-emitting unit to realize the display of the display panel, and the second area can be used to set the signal line and controller for driving the display panel to emit light.
  • the display panel includes a functional island, a stretching portion and a signal line. Functional parts are arranged on the functional island, and the functional island includes a pixel island and a circuit island. The functional parts include a first pixel circuit structure and a driving circuit structure. The first pixel circuit structure is arranged in the pixel island, which can improve the problem that the first pixel circuit structure is easily damaged during the stretching process of the display panel.
  • the driving circuit structure is arranged in the circuit island, which can also improve the problem that the driving circuit structure is easily damaged during the stretching process of the display panel.
  • a stretching portion is arranged between the functional islands, which can improve the stretching performance of the display panel, and at least part of the stretching portion of the second area is arranged through the second area, forming a non-display stretching area, which can further improve the stretching performance of the second area.
  • the signal line is arranged in the stretching portion and connects the functional parts of the adjacent functional islands to realize signal transmission between different functional parts.
  • FIG1 is a schematic diagram of a display panel provided by an embodiment of the first aspect of the present application.
  • FIG2 is a schematic structural diagram of a display panel provided by an embodiment of the first aspect of the present application.
  • FIG. 3 is a schematic structural diagram of a first island component of a display panel provided by an embodiment of the first aspect of the present application.
  • Fig. 4 is a cross-sectional view of the A-A position in Fig. 2;
  • FIG. 5 is a schematic structural diagram of a first island assembly of a display panel provided by another embodiment of the first aspect of the present application.
  • Fig. 6 is a cross-sectional view at B-B in Fig. 2;
  • FIG. 7 is a schematic structural diagram of a first island assembly and a pixel island of a display panel provided by yet another embodiment of the first aspect of the present application;
  • FIG8 is a partial cross-sectional view of FIG7;
  • FIG9 is a partial cross-sectional view of another position of FIG7;
  • FIG. 10 is a schematic structural diagram of a pixel island of a display panel provided by an embodiment of the first aspect of the present application.
  • FIG11 is a schematic structural diagram of a display panel provided by another embodiment of the first aspect of the present application.
  • FIG. 12 is a schematic structural diagram of a first island assembly of a display panel provided by yet another embodiment of the first aspect of the present application.
  • FIG. 13 is a schematic structural diagram of a first island component of a display panel provided in yet another embodiment of the first aspect of the present application.
  • the display panel and the display device according to the embodiment of the present application are described in detail below with reference to FIGS. 1 to 13 .
  • an embodiment of the first aspect of the present application provides a display panel, the display panel having a first area AA and a second area NA arranged around at least a portion of the first area AA, the first area AA and the second area NA both including an island area and a stretching area, a plurality of island areas are distributed in an array in the first area AA and the second area NA, the stretching area is located between two adjacent rows and/or two adjacent columns of island areas, the display panel includes a functional island 100, a stretching portion 300 and a signal line 400, each functional island 100 is located in each island area and a functional part 200 is arranged on the functional island 100, and the plurality of functional islands 100 include a plurality of island areas 100 located in each island area and a plurality of functional parts 200 are ...
  • the functional component 200 includes a first pixel circuit structure 210 arranged on the pixel island 110 and a driving circuit structure 220 arranged on the circuit island 120;
  • the stretching portion 300 is arranged in the stretching area and connected between two adjacent functional islands 100, and in the second area NA, at least part of the stretching area is arranged along the direction from the first area AA to the second area NA and penetrates the second area NA;
  • at least part of the signal line 400 is arranged in the stretching portion 300 and is used to connect the functional components 200 of two adjacent functional islands 100.
  • the stretching zone is arranged along the direction from the first zone AA to the second zone NA, passing through the second zone NA; that is, the second zone NA is divided into multiple sub-zones by the stretching zone, and a stretching zone for disconnecting the second zone NA is formed between adjacent sub-zones, and the stretching zone is the area where the stretching portion 300 is arranged.
  • the display panel has a first area AA and a second area NA
  • the first area AA can be used to set the light-emitting unit to realize the display of the display panel
  • the second area NA can be used to set the signal line 400 and the controller for driving the display panel to emit light.
  • the display panel includes a functional island 100, a stretching portion 300 and a signal line 400.
  • a functional part 200 is arranged on the functional island 100, and the functional island 100 includes a pixel island 110 and a circuit island 120.
  • the functional part 200 includes a first pixel circuit structure 210 and a driving circuit structure 220.
  • the first pixel circuit structure 210 is arranged on the pixel island 110, which can improve the problem that the first pixel circuit structure 210 is easily damaged during the stretching process of the display panel.
  • the driving circuit structure 220 is arranged on the circuit island 120, which can also improve the problem that the driving circuit structure 220 is easily damaged during the stretching process of the display panel.
  • a stretching portion 300 is arranged between the functional islands 100, which can improve the stretching performance of the display panel, and at least part of the stretching portion 300 of the second area NA is arranged through the second area NA, which can further improve the stretching performance of the second area.
  • the signal line 400 is disposed in the stretching portion 300 and connects the functional components 200 of adjacent functional islands 100 to achieve signal transmission between different functional components 200 .
  • multiple islands are distributed in rows and columns along the first direction X and the second direction Y, and multiple islands are arranged at intervals, and the stretching zone is located between two adjacent rows of islands along the second direction Y, and/or, the stretching zone is located between two adjacent columns of islands along the first direction X.
  • stretching zones are arranged between two adjacent rows and two columns of islands, so that the first area AA can be stretched in both the first direction X and the second direction Y.
  • the island area can be considered as the area where the functional island 100 is arranged, and the stretching zone can be considered as the area where the stretching portion 300 is arranged.
  • a stretching zone is arranged between two adjacent rows or two adjacent columns of islands in a part of the second area NA.
  • stretching zones are arranged between two adjacent rows and two columns of islands, and the islands in this part of the area are arranged at intervals, so that this part of the second area NA can be stretched in the first direction and the second direction.
  • the stretching zone is not arranged through the second area along the second direction Y.
  • At least part of the stretching portion 300 is arranged along the direction from the first area AA to the second area NA and through the second area NA. That is, the second area NA includes two parts, one part is used to set the circuit island 120, and the other part is used to set the stretching portion 300, and the stretching portion 300 is arranged along the direction from the first area AA to the second area NA and through the second area NA. That is, at least part of the second area NA is not a continuous structure surrounding the first area AA, and at least part of the second area NA surrounding the first area AA is divided into a plurality of structures for setting the circuit island 120 by the stretching portion 300.
  • the functional island 100 is a rigid area, and the functional island 100 includes a substrate (PI), a buffer layer (not shown in the figure), a semiconductor layer (P-Si), multiple metal layers (M), a planarization layer (PLN), a pixel definition layer (PDL), a support column layer, and an insulating layer located between two adjacent metal layers, which are stacked in sequence.
  • PI substrate
  • P-Si semiconductor layer
  • M multiple metal layers
  • PNL planarization layer
  • PDL pixel definition layer
  • support column layer an insulating layer located between two adjacent metal layers, which are stacked in sequence.
  • the stretching portion 300 is a flexible region, and the number of functional layer structures of the stretching portion 300 is less than the number of functional layer structures of the functional island 100, so that the stretching portion 300 is easily deformed to achieve the stretchability of the display panel.
  • the stretching portion 300 includes a metal layer 301 and a protective layer 302 located on both sides of the metal layer 301, the signal line 400 is disposed on the metal layer 301, and the protective layer 302 is used to provide protection for the signal line 400 and to prevent the signal line 400 from being short-circuited with other circuits.
  • the stretching part 300 further includes an elastic filling layer 600, which is elastic to improve the stretching performance of the display panel.
  • the elastic filling layer 600 can be located on one side or both sides of the metal layer used to set the signal line 400 in the thickness direction Z.
  • the light transmittance of the elastic filling layer 600 is greater than 15%, for example, the light transmittance of the elastic filling layer 600 is greater than 20%, or the light transmittance of the elastic filling layer 600 is greater than 80%, or even the light transmittance of the elastic filling layer 600 is greater than 95%.
  • the elastic filling layer 600 has good light transmittance, which improves the display effect of the display panel.
  • the signal line 400 extends along a straight path in the stretching portion 300 , and the material properties of the signal line 400 itself are used to overcome the stretching force generated when the display panel is stretched.
  • At least part of the signal line 400 is extended along a curved path.
  • the signal line 400 is deformed to overcome the stretching force, thereby improving the problem that the signal line 400 is easily broken under stress.
  • the plurality of circuit islands 120 include a first island assembly 100a, the first island assembly 100a includes a first circuit island 121 and a second circuit island 122, the driving circuit structure 220 includes a shift register unit 221 disposed on the first circuit island 121, the second circuit island 122 and the first circuit island 121 are disposed side by side, and the driving circuit structure 220 includes a connecting portion 222 disposed on the second circuit island 122.
  • the signal line 400 includes a first signal line 410 connected to the shift register unit 221 and a second signal line 420 connected to the connecting portion 222.
  • the plurality of shift register units 221 are connected to the first pixel circuit structure 210 through at least part of the second signal line 420, the connecting portion 222 and the first signal line 410 to provide a scanning signal to the first pixel circuit structure 210.
  • the location of the first island assembly 100a is framed by a dotted line in FIG. 2, and the dotted line frame does not constitute a structural limitation on the embodiment of the present application.
  • the first island assembly 100a includes a first circuit island 121 and a second circuit island 122 that are spaced apart and arranged side by side. Since the first circuit island 121 and the second circuit island 122 are spaced apart from each other, a gap can be formed between the first circuit island 121 and the second circuit island 122. The gap can be used to set a stretching portion 300 to increase the stretching properties of the second area NA, thereby increasing the stretching properties of the entire display panel.
  • the signal line 400 is divided into a first signal line 410 and a second signal line 420 , so that the shift register unit 221 can be connected to the first pixel circuit structure 210 through the first signal line 410 and the second signal line 420 , thereby providing a scanning signal to the first pixel circuit structure 210 .
  • two different circuit islands 120 are arranged in the second area NA, namely, a first circuit island 121 and a second circuit island 122, so that the shift register unit 221 and the connecting portion 222 connecting the signal line 400 in the second area NA can be arranged on the first circuit island 121 and the second circuit island 122 respectively.
  • sufficient arrangement area can be provided for the shift register unit 221 and the signal line 400; on the other hand, the problem of mutual interference between the wiring of the shift register unit 221 and the signal line 400 can be improved.
  • the difference between the connecting portion 222 and the second signal line 420 lies in their positions.
  • the connecting portion 222 is arranged on the second circuit island 122, and the second signal line 420 is arranged on the stretching portion 300.
  • the connecting portion 222 and the second signal line 420 can be used to transmit the same signal
  • the connecting portion 222 and the second signal line 420 can also be arranged on the same conductive layer
  • the extension directions of the connecting portion 222 and the second signal line 420 can also be the same or different.
  • the plurality of circuit islands 120 are divided into a first circuit island 121 and a second circuit island 122.
  • the difference between the first circuit island 121 and the second circuit island 122 is that the functional parts 200 arranged thereon are different.
  • the first circuit island 121 is provided with a shift register unit 221, and the second circuit island 122 is provided with a connecting portion 222.
  • the shift register unit 221 is used to transmit a scanning signal, and the connecting portion 222 is used to realize the connection between different signal lines 400.
  • the connecting portion 222 is arranged on the second circuit island 122, which can improve the connection position between different signal lines 400, which is easy to break during the stretching process of the display panel. problem.
  • first circuit island 121 and the second circuit island 122 are combined side by side to form a first island assembly 100 a
  • the first island assembly 100 a includes the first circuit island 121 and one or more second circuit islands 122 .
  • multiple circuit islands 120 and multiple pixel islands 110 are arranged in rows and columns along the first direction X and the second direction Y.
  • the shift register unit 221 on the circuit island 120 is used to drive the first pixel circuit structure 210 of the pixel island 110 in the same row.
  • the shift register unit 221 and the first pixel circuit structure 210 connected to each other are located on the circuit island 120 and the pixel island 110 arranged in the same row, which can simplify the layout path of the signal line 400 .
  • the first signal line 410 may include at least one of a high level power line (VGH) and a low level power line (VGL).
  • VGH high level power line
  • VGL low level power line
  • the first signal line 410 includes a high level power line and a low level power line, and the high level power line and the low level power signal line are arranged side by side along the first direction X.
  • the first circuit island 121 and the second circuit island 122 in the same first island component 100a are arranged at intervals along the first direction X, and multiple first island components 100a are arranged at intervals along the second direction Y in the second area NA, and the first signal lines 410 connected to the multiple first circuit islands 121 arranged along the second direction Y are connected to each other, that is, the first signal line 410 is used to connect the shift register unit 221 arranged along the second direction Y; the second signal lines 420 connected to the multiple second circuit islands 122 arranged along the second direction Y are connected to each other, that is, the second signal line 420 is used to connect the connection portion 222 arranged along the second direction Y.
  • first circuit islands 121 and second circuit islands 122 are arranged in an array along the first direction X and the second direction Y. There are gaps between adjacent first circuit islands 121 and second circuit islands 122 along the first direction X. There are also gaps between adjacent first circuit islands 121 or second circuit islands 122 along the second direction Y. Stretching portions 300 may be provided in these gaps, thereby improving the stretching performance of the display panel in the first direction X and the second direction Y.
  • the first circuit islands 121 of the multiple first island assemblies 100a spaced apart along the second direction Y are aligned along the second direction Y, that is, the first circuit islands 121 of the multiple first island assemblies 100a are located in the same column, and the column direction is the second direction Y, so that the arrangement of the multiple first circuit islands 121 is more regular, and it is convenient for the first signal line 410 to connect adjacent gate drive circuits.
  • the second circuit islands 122 of the plurality of first island assemblies 100a spaced apart along the second direction Y are aligned along the second direction Y. That is, the second circuit islands 122 of the plurality of first island assemblies 100a are located in the same column, and the column direction is the second direction Y, so that the arrangement of the plurality of second circuit islands 122 is more regular, and the second signal lines 420 are conveniently connected to each other along the second direction Y.
  • the multiple second circuit islands 122 are arranged side by side along the first direction X, the second circuit islands 122 of the multiple first island components 100a are distributed in multiple columns, and the multiple second circuit islands 122 in the same column are aligned along the second direction Y.
  • the second area NA may not be provided with a light emitting unit, and the second area NA is used to provide the shift register unit 221 and the related signal line 400 and constitute a non-display area of the display panel.
  • the functional component 200 further includes a second pixel circuit structure 230 and a second light-emitting unit disposed on at least one of the first circuit island 121 and the second circuit island 122 , and the second pixel circuit structure 230 is used to drive the second light-emitting unit to emit light.
  • the second pixel circuit structure 230 can drive the second light-emitting unit to emit light, so that the second area NA can also be displayed, thereby expanding the display area of the display panel and improving the screen-to-body ratio of the display panel.
  • the second light-emitting unit includes a first electrode 240, a second electrode 250 and a light-emitting structure arranged between the first electrode 240 and the second electrode 250.
  • the first electrode 240 can be connected to the second pixel circuit structure 230, so that the second pixel circuit structure 230 drives the light-emitting structure to emit light through the first electrode 240.
  • the second pixel circuit structure 230 and the second light emitting unit may be connected to each other and disposed on one of the first circuit islands 121 or the second circuit islands 122.
  • the first circuit island 121 and the second circuit island 122 are both provided with the second light emitting unit and the second pixel circuit structure 230 connected to each other.
  • a second pixel circuit structure 230 and a second light-emitting unit are provided on the circuit island 120 close to the first area AA in the first circuit island 121 and the second circuit island 122 of the first island assembly 100a, so that part of the second area NA close to the first area AA can be displayed, thereby expanding the display area of the display panel and achieving the purpose of a narrow frame.
  • the first circuit island 121 and the second circuit island 122 in the same first island component 100a are both provided with a first electrode 240, so that the corresponding positions of the first circuit island 121 and the second circuit island 122 in the first island component 100a can be provided with a second light-emitting unit to realize the light-emitting display of the display panel.
  • a second pixel circuit structure 230 is provided on a circuit island 120 in the same first island component 100a, and the second pixel circuit structure 230 is used to drive multiple first electrodes 240 in the same first island component 100a.
  • the second pixel circuit structure 230 and the first electrode 240 are in a one-to-many relationship, which can reduce the number of signal lines 400 arranged in the second area NA, thereby improving the stretchability of the second area NA.
  • the second pixel circuit structure 230 can be set on the second circuit island 122 to improve the mutual interference between the positions of the second pixel circuit structure 230 and the shift register unit 221, and there is enough setting space on the second circuit island 122 to set the second pixel circuit structure 230.
  • the first island assembly 100a includes a first circuit island 121 and two second circuit islands 122, the two second circuit islands 122 are disposed on both sides of the first circuit island 121, and the second pixel circuit structure 230 is disposed on the second circuit island 122 located on the first circuit island 121 facing the first area AA.
  • the first three circuit islands 120 from the left constitute the first island assembly 100a, and the first and third from the left are the second circuit islands 122, the second from the left is the first circuit island 121, and the rightmost functional island 100 is the pixel island 110.
  • the second pixel circuit structure 230 is arranged close to the first area AA, which can reduce the distance between the second pixel circuit structure 230 and the first pixel circuit structure 210, facilitate the introduction of other signal transmission lines from the first pixel circuit structure 210 to the second pixel circuit structure 230, and simplify the arrangement of the signal lines 400 of the display panel.
  • virtual pixel circuits 260 are disposed on both second circuit islands 122, and the sum of the number of second pixel circuit structures 230 and virtual pixel circuits 260 on one second circuit island 122 is equal to the sum of the number of virtual pixel circuits 260 on the other second circuit island 122.
  • three virtual pixel circuits 260 are disposed on the second circuit island 122 located on the side of the first circuit island 121 away from the first area AA, and two virtual pixel circuits 260 and one second pixel circuit structure 230 are disposed on the second circuit island 122 located on the side of the first circuit island 121 facing the first area AA, so that the consistency of the metal wiring density on the two second circuit islands 122 can be ensured.
  • the signal line 400 includes a first connection line 401, a second connection line 402, and a third connection line 403.
  • the first connection line 401 is used to connect two adjacent first electrodes 240 in the same first island component 100a;
  • the second connection line 402 is a scan line and is used to connect the drive circuit structure 220 and the second image
  • the third connection line 403 is a power signal line and is used to connect the first pixel circuit structure 210 and the second pixel circuit structure 230; wherein the second connection line 402 connected between two adjacent circuit islands 120 and the first connection line 401 are stacked along the thickness direction Z of the display panel; and/or the second connection line 402 connected between two adjacent circuit islands 120 and the third connection line 403 are stacked along the thickness direction Z of the display panel.
  • the first connection lines 401 connect the first electrodes 240 adjacent to each other along the first direction X, so that the same second pixel circuit structure 230 can drive more than two first electrodes 240 connected by the first connection lines 401.
  • there are two first connection lines 401 and the two first connection lines 401 are disposed on both sides of the first circuit island 121.
  • the two first connection lines 401 respectively connect the first electrode 240 on the second circuit island 122 and the first electrode 240 on the first circuit island 121, so that the three first electrodes 240 are connected to each other, and the second pixel circuit structure 230 can drive the three first electrodes 240 simultaneously.
  • Fig. 8 may be a schematic cross-sectional view of one group of signal lines 400 stacked on each other between the first second circuit island 122 from the left and the second first circuit island 121 from the left in Fig. 7.
  • Fig. 8 is a schematic cross-sectional view of the first group from the top of the two groups of signal lines 400 stacked on each other.
  • the second connection line 402 is a scan line.
  • the second connection line 402 may be located between the first circuit island 121 and the second circuit island 122 to connect the shift register unit 221 and the second pixel circuit structure 230, and/or, the second connection line 402 may also be located between the second circuit island 122 and the pixel island 110 to connect the first pixel circuit structure 210 and the second pixel circuit structure 230.
  • the second connection line 402 and the first connection line 401 also located between the first circuit island 121 and the second circuit island 122 may be used to connect the same circuit island 120.
  • the second connection line 402 and the first connection line 401 may be stacked along the thickness direction Z to reduce the distribution area of the metal wiring and ensure the light transmittance and stretchability of the display panel.
  • the display panel also includes a second electrode 250, the second electrode 250 is arranged on the first circuit island 121 and the second circuit island 122, the signal line 400 also includes a fourth connecting line 404, the fourth connecting line 404 is used to connect the second electrodes 250 on two adjacent circuit islands 120, and the fourth connecting line 404 and the second connecting line 402 are stacked along the thickness direction of the second electrode 250.
  • the first circuit island 121 and the second circuit island 122 are both provided with a second electrode 250, and the second electrode 250 and the first electrode 240 interact with each other to drive the first light-emitting structure to emit light.
  • the fourth connection line 404 and the second connection line 402 can be stacked along the thickness direction Z to reduce the distribution area of the metal wiring and ensure the light transmittance and stretchability of the display panel.
  • the fourth connection line 404 may be disposed in the same layer as the second electrode 250. Alternatively, the fourth connection line 404 may be disposed in the same layer as the first electrode 240.
  • the second connecting line 402 includes a first scanning line 4021 and a second scanning line 4022, the first scanning line 4021 and the second scanning line 4022 are arranged at intervals along the second direction Y, the first scanning line 4021 and the fourth connecting line 404 are arranged in a stacked manner along the thickness direction Z, the second scanning line 4022 and the first connecting line 401 are arranged in a stacked manner along the thickness direction Z, or the second scanning line 4022 and the third connecting line 403 are arranged in a stacked manner along the thickness direction Z.
  • the first scan line 4021 When the second connection line 402 includes a first scan line 4021 and a second scan line 4022, the first scan line 4021
  • the first scan line 4021 and the second scan line 4022 can both be connected to the shift register unit 221, one of the first scan line 4021 and the second scan line 4022 is connected to the shift register unit 221 as an input signal, and the other is connected to the shift register unit 221 as an output.
  • the embodiment of the present application is described by taking the first scan line 4021 as an input signal connected to the shift register unit 221, and the second scan line 4022 as an output connected to the shift register unit 221 as an example.
  • the first circuit island 121 may also be provided with the first connecting line 401 and the fourth connecting line 404 on this side, and one of the first scan line 4021 and the second scan line 4022 is stacked with the first connecting line 401 along the thickness direction Z, and the other is stacked with the fourth connecting line 404 along the thickness direction Z.
  • the fourth connection line 404 and the third connection line 403 may also be provided on this side of the second circuit island 122, and one of the first scan line 4021 and the second scan line 4022 is stacked with the third connection line 403 along the thickness direction Z, and the other is stacked with the fourth connection line 404 along the thickness direction Z.
  • the fourth connection line 404 is connected to the second electrode 250, and the fourth connection line 404 can be used to transmit a negative voltage signal (VSS).
  • the first area AA can be provided with a negative voltage signal line, and the negative voltage signal line of the first area AA can be directly led to the second area NA to reduce the number of signal lines 400 arranged in the second area NA.
  • the signal line 400 includes a seventh connection line 40a connected to the pixel island 110 and extending along the second direction, and at least one fourth connection line 404 connects the second circuit island 122 and the pixel island 110 and connects the seventh connection line 40a at the pixel island 110.
  • the signal line 400 includes a seventh connection line 40a located in the first area AA and connected to the pixel island 110, and the seventh connection line 40a extends along the second direction Y.
  • the fourth connection line 404 for connecting the second electrode 250 is connected to the seventh connection line 40a on the pixel island 110, thereby introducing the negative voltage signal line of the first area AA into the second electrode 250 of the second area NA.
  • the signal line 400 includes a data line (Data) connected to the second circuit island 122 provided with the second pixel circuit structure 230 and a sixth connection line 406, the data line and the sixth connection line 406 are arranged side by side along the first direction X, and the sixth connection line 406 and the first scan line 4021 are electrically connected to each other.
  • Data data line
  • the sixth connection line 406 and the first scan line 4021 are electrically connected to each other.
  • the sixth connection line 406 can be connected to the scan output line of the previous row of circuit islands (for example, the second scan line 4022 of the previous row of first island components 100a), and the scan output line of the previous row of circuit islands 120 serves as the scan input line of the next row of circuit islands 120.
  • the second scan line 4022 can be connected to the first scan line 4021 of the next row through the sixth connection line 406.
  • the data line is used to input a data signal to the second pixel circuit structure 230 on the second circuit island 122.
  • the signal line 400 also includes a clock signal line and a fifth connecting line 405, the clock signal line is connected to the second circuit island 122 located away from the first area AA of the first circuit island 121; the fifth connecting line 405 connects the clock signal line and the driving circuit structure 220, the fifth connecting line 405 connected between two adjacent circuit islands is stacked with the first connecting line 401 along the thickness direction Z; and/or, the fifth connecting line 405 connected between two adjacent circuit islands 120 is stacked with the fourth connecting line 404 along the thickness direction Z.
  • the fifth connection line 405 can be used to connect the clock signal line and the driving circuit structure 220, that is, the fifth connection line 405 can be used to connect the clock signal line and the shift register unit 221, then the fifth connection line 405 is connected between the first circuit island 121 and the second circuit island 122, the fifth connection line 405 and the first connection line 401, and the fourth connection line 404 may be connected between the same two circuit islands 120, the fifth connection line 405 and the fourth connection line 404 connected between two adjacent circuit islands 120, and/or the fifth connection line 405 and the first connection line 401 are stacked along the thickness direction Z to reduce the distribution area of the metal wiring and ensure the transmittance and elongation of the display panel.
  • the clock signal line may include a first clock signal line CLK1 and a second clock signal line CLK2
  • the fifth connection line 405 may include a first sub-connection line 4051 and a second sub-connection line 4052, wherein the first sub-connection line 4051 connects the first clock signal line CLK1 and the driving circuit structure 220, and the second sub-connection line 4052 connects the second clock signal line CLK2 and the driving circuit structure 220.
  • one of the first sub-connection line 4051 and the second sub-connection line 4052 may be stacked with the fourth connection line 404 in the thickness direction, and the other may be stacked with the first connection line 401 in the thickness direction. Cascade settings.
  • the signal line 400 of the second area NA may include a first clock signal line CLK1, a second clock signal line CLK2, a first scan line Sn, and a second scan line Sn+1, and the first clock signal line CLK1 and the second clock signal line CLK2 may be connected to one of the second circuit islands 122 and extend between the second circuit island 122 and the first circuit island 121 to connect the shift register unit 2 21, the first scan line Sn and the second scan line Sn+1 can be connected to another second circuit island 122 and extend between the second circuit island 122 and the first circuit island 121 to connect the shift register unit 221, so two connecting lines arranged side by side are arranged between two adjacent circuit islands 120, that is, part of the first clock signal line CLK1 and the second clock signal line CLK2 are arranged side by side
  • the first island assembly 100a includes two second circuit islands 122 and a first circuit island 121, and the two second circuit islands 122 are arranged on both sides of the first circuit island 121
  • a second light-emitting unit is arranged on the first circuit island 121 and the two second circuit islands 122, and the second light-emitting unit includes a first electrode 240 and a second electrode 250
  • the same second pixel circuit structure 230 drives the three second light-emitting units in the same first island assembly 100a.
  • This requires a connecting line to connect the first electrode 240 and the second electrode 250 of two adjacent circuit islands 120, so a first connecting line 401 and a fourth connecting line 404 are added between two adjacent circuit islands 120.
  • the first connecting line 401 is used to connect the first electrode 240 of the adjacent circuit islands 120
  • the fourth connecting line 404 is used to connect the second electrode 250 of the two adjacent circuit islands 120. Since the first connecting line 401 and the fourth connecting line 404 are added, the first connecting line 401 can be stacked with one of the two connecting lines between the original two adjacent circuit islands 120 (for example, the first scanning line Sn or the first clock signal line CLK1), and the fourth connecting line 404 can be stacked with the other of the two connecting lines between the original two adjacent circuit islands 120 (for example, the second scanning line Sn+1 or the second clock signal line CLK2).
  • the signal line 400 further includes a redundant routing line 407 located in the first area AA and a signal routing line 408 for connecting the adjacent first pixel circuit structure 210, and at least part of the redundant routing line 407 and the signal routing line 408 are stacked in the thickness direction.
  • a redundant routing line 407 is provided in the first area AA, and the redundant routing line 407 and the signal routing line 408 are stacked in the thickness direction, so that the arrangement of the signal line 400 in the first area AA and the second area NA is similar, which can improve the difference in stretching rate between the first area AA and the second area NA.
  • the sum of the number of redundant wirings 407 and signal wirings 408 between two adjacent pixel islands 110 is the same as the number of first signal lines 410 between two adjacent circuit islands 120.
  • the stretching rate difference between the first area AA and the second area NA is further improved.
  • the redundant wiring 407 between two adjacent pixel islands 110 is arranged in the same layer and material as at least one of the first connection line 401, the second connection line 402, the third connection line 403 and the fourth connection line 404.
  • the redundant wiring 407 can be arranged in the same layer and material as one of the first connection line 401 and the first scan line Sn, and the signal wiring 408 can be arranged in the same layer and material as the other one, so as to simplify the manufacturing process of the display panel.
  • the first signal line 410 includes a first sub-line 411, which extends from the first circuit island 121 on both sides in the second direction Y;
  • the second signal line 420 includes a second sub-line 421, which extends from the second circuit island 122 on both sides in the second direction Y, wherein the number of first sub-lines 411 corresponding to each first circuit island 121 is the same as the number of second sub-lines 421 corresponding to each second circuit island 122.
  • the first sub-line 411 corresponding to the first circuit island 121 refers to the first sub-line 411 extending from the first circuit island 121 on both sides in the second direction Y.
  • the second sub-line 421 corresponding to the second circuit island 122 refers to the second sub-line 421 extending from the second circuit island 122 on both sides in the second direction Y.
  • the first sub-line extending from the first circuit island 121 and the second circuit island 122 on the same side The number of the second sub-lines 411 and 421 is the same, so that the stretching rates of the first circuit island 121 and the second circuit island 122 in the second direction Y tend to be consistent, which can well improve the stretching performance of the second area NA of the display panel in the second direction Y.
  • the first circuit island 121 has first sub-lines 411 extending on both sides of the second direction Y, and the first sub-lines 411 correspondingly arranged along the second direction Y can be used to transmit the same signal.
  • the first sub-line 411 for example, includes at least one of a high-level power line (VGH) and a low-level power line (VGL).
  • the second circuit island 122 has second sub-lines 421 extending from both sides of the second direction Y, and the second sub-lines 421 correspondingly arranged along the second direction Y are used to transmit the same signal, and the second sub-lines 421, for example, include at least one of the first clock signal line (CLK1), the second clock signal line (CLK2), the first power signal line (VSS), the scan line (Sn), the data line (data), and the sixth connection line (Vin).
  • CLK1 first clock signal line
  • CLK2 the second clock signal line
  • VSS sixth connection line
  • the second sub-line 421 can be used as a scan line to connect the shift register units 221 of two adjacent rows, or the second sub-line 421 can be used as a scan line to connect the scan lines extending along the second direction Y of two adjacent rows, so that when the pixel driving unit of the i-th row is driven, the pixel driving unit of the i+1-th row can be reset.
  • the second sub-line 421 may include at least one of a first clock signal line, a second clock signal line, a scan line, a data line, and a sixth connection line.
  • the second sub-line 421 may include at least one of a first clock signal line (CLK1), a second clock signal line (CLK2), a first power signal line (VSS), and a scan line (Sn).
  • the driving signal line 430 includes a third sub-line 431, and the third sub-line 431 extends from both sides of the pixel island 110 in the second direction Y.
  • the number of the third sub-lines 431 corresponding to each pixel island 110 is the same as the number of the first sub-lines 411 in each first circuit island 121.
  • the third sub-line 431 corresponding to each pixel island 110 is the third sub-line 431 extending from the pixel island 110.
  • the number of third sub-lines 431 of a single pixel island 110 is the same as the number of first sub-lines 411 of a single first circuit island 121, so that the stretching rates of the first area AA and the second area NA in the second direction Y tend to be consistent, which can greatly improve the overall stretching performance of the display panel in the second direction Y.
  • the third sub-line 431 may include a data line, a first power signal line, a second power signal line, etc.
  • the first signal line 410 includes a fourth sub-line 412, which extends from the first circuit island 121 on both sides of the first direction X;
  • the second signal line 420 includes a fifth sub-line 422, which extends from the second circuit island 122 on both sides of the first direction X, wherein the number of fourth sub-lines 412 corresponding to each first circuit island 121 is the same as the number of fifth sub-lines 422 corresponding to each second circuit island 122.
  • the number of fourth sub-lines 412 extending from a single first circuit island 121 is the same as the number of fifth sub-lines 422 extending from a single second circuit island 122, so that the stretching rates of the first circuit island 121 and the second circuit island 122 in the first direction X tend to be consistent, which can greatly improve the stretching performance of the second area NA of the display panel in the first direction X.
  • the fourth sub-line 412 may include at least one of the above-mentioned first connection line 401, second connection line 402, third connection line 403, fourth connection line 404 and fifth connection line 405.
  • at least one of the first connection line 401, second connection line 402, third connection line 403, fourth connection line 404 and fifth connection line 405 used to connect the first circuit island 121 may be the fourth sub-line 412.
  • the fifth sub-line 422 may include at least one of the first connection line 401 , the second connection line 402 , the third connection line 403 , the fourth connection line 404 , and the fifth connection line 405 described above.
  • At least part of the fourth sub-line 412 and at least part of the fifth sub-line 422 are interconnected, so that the shift register unit 221 of the first circuit island 121 can be connected to the connecting part 222 through the fourth sub-line 412 and the fifth sub-line 422, so that the second signal line 420 can be connected to the shift register unit 221.
  • the driving signal line 430 includes a sixth sub-line 432, which extends from the pixel island 110 on both sides in the first direction X, and the number of sixth sub-lines 432 corresponding to each pixel island 110 is the same as the number of fourth sub-lines 412 corresponding to each first circuit island 121.
  • the number of sixth sub-lines 432 extending from a single pixel island 110 is consistent with the number of fourth sub-lines 412 extending from a single first circuit island 121, so that the elongation of the first area AA and the second area NA in the first direction X tends to be consistent, which can improve the overall stretchability of the display panel.
  • the sixth sub-line 432 may include the above-mentioned signal line 408 and redundant line 407 .
  • At least part of the fourth sub-line 412 and at least part of the sixth sub-line 432 are interconnected, so that the shift register unit 221 can be connected to the first pixel circuit structure 210 through the fourth sub-line 412 and the sixth sub-line 432, thereby transmitting a driving signal to the first pixel circuit structure 210.
  • At least part of the fifth sub-line 422 and at least part of the sixth sub-line 432 are connected to each other, so that the first pixel circuit structure 210 can be connected to the connecting portion 222 of the second circuit island 122 through the sixth sub-line 432 and the fifth sub-line 422 .
  • the difference between the first sub-line 411, the second sub-line 421, the third sub-line 431, the fourth sub-line 412, the fifth sub-line 422 and the sixth sub-line 432 lies in their different arrangement positions, at least two of them can be used to transmit the same signal, at least two can be located in the same conductive layer and formed integrally, or at least the extension directions of the two can be the same or different.
  • the number of first sub-lines 411 and the number of third sub-lines 431 corresponding to the same first circuit island 121 are the same, so that the forces on the shift register unit 221 in different directions are more balanced.
  • the number of the second sub-lines 421 and the number of the fifth sub-lines 422 corresponding to the same second circuit island 122 are the same, so that the forces on the connecting portion 222 in different directions are more balanced.
  • the number of the third sub-lines 431 and the number of the sixth sub-lines 432 corresponding to the same pixel island 110 are the same. This makes the forces on the first pixel circuit structure 210 in different directions more balanced.
  • the second sub-line 421 includes a first clock signal line, a second clock signal line, a first scan line and a first negative voltage signal line (i.e., a first power signal line), and the fifth sub-line 422 can be used to connect the first clock signal line and the shift register unit, or the fifth sub-line 422 can be used to connect the second clock signal line and the shift register unit 221, or the fifth sub-line 422 is used to connect the shift register unit 221 and the first scan line.
  • the driving signal line 430 includes a data line, a second scan line, a second negative voltage signal line, and a first positive voltage signal line (i.e., a second power line).
  • the sixth sub-line 432 may also be connected to the shift register unit 221 and the first pixel circuit structure 210 through the fourth sub-line 412.
  • the sixth sub-line 432 may be connected to the first scan line and the second scan line, or the sixth sub-line 432 may also be connected to the first negative voltage signal line and the second negative voltage signal line.
  • the second area NA includes a first sub-area NA1 extending along the first direction X and a second sub-area NA2 extending along the second direction Y
  • the first island component 100a is located in the second sub-area NA2
  • the display panel also includes a binding pin 500, which is located in the first sub-area NA1.
  • the second area NA is divided into a first sub-area NA1 and a second sub-area NA2, the first island component 100a is located in the second sub-area NA2, and the binding pin 500 is located in the first sub-area NA1, so that the arrangement of the first island component 100a and the binding pin 500 does not affect each other.
  • a continuous metal layer or other material layer can be provided for the binding pin 500 in the first sub-area NA1.
  • the stretching portion 300 is located in the second sub-region NA2 , and the stretching portion 300 penetrates the second sub-region NA2 along the first direction X, and the circuit island 120 is disposed between adjacent stretching portions 300 .
  • two second sub-areas NA2 are arranged on both sides of the first area AA in the first direction X, and a first island component 100a is arranged in each second sub-area NA2, that is, a shift register unit 221 is arranged in each second sub-area NA2, so as to facilitate driving the light-emitting units in the first area AA from both sides of the first area AA in the first direction X at the same time, thereby improving the driving hysteresis and improving the display effect of the display panel.
  • the binding pins 500 may be used to bind and connect a scan driver, a display driver, etc.
  • a plurality of binding pins 500 are distributed at intervals along the second direction Y in the first sub-area NA1 , so as to facilitate connection of a plurality of drivers and other components through the binding pins 500 .
  • first sub-areas NA1 are disposed on both sides of the first area AA in the second direction Y, and each first sub-area NA1 is provided with a binding pin 500, so that more binding pins 500 can be arranged in the first sub-area NA1.
  • the extension dimension of the first sub-area NA1 in the first direction X is smaller than the extension dimension of the second sub-area NA2 in the second direction Y. That is, the first direction X may be the width direction of the display panel, and the second direction Y may be the length direction of the display panel.
  • the first island assembly 100a is distributed along the length direction in the second sub-area NA2, which can improve the stretchability of the display panel in its length direction.
  • the binding pins 500 may also be disposed in the second sub-area NA2 , and the first island component 100a may be disposed in the first sub-area NA1 .
  • the stretching portion 300 may be located in the first sub-area NA1 to improve the stretching performance of the first sub-area NA1 .
  • the signal line 400 further includes a driving signal line 430 , the driving signal line 430 is connected to the first pixel circuit structure 210 , and the driving signal line 430 is extended along a bending path.
  • the driving signal line 430 is extended and formed along a bending path, which can improve the stretching performance of the driving signal line 430 and improve the problem that the driving signal line 430 is easily damaged during the stretching of the display panel.
  • the driving signal line 430 may be a data line (Data), a scan line (Scan), a second power line (VSS), etc.
  • the second power line may be connected to the anode of the light emitting unit in the first area AA.
  • At least two of the pixel island 110, the first circuit island 121, and the second circuit island 122 have the same size, so that the stretching rates at different positions of the display panel tend to be consistent, which can well improve the stretching performance of the display panel.
  • the first circuit island 121 and the second circuit island 122 have the same size, so that the gap between two adjacent first circuit islands 121 along the second direction Y is the same as the gap between two adjacent second circuit islands 122 along the second direction Y, thereby making the stretching rates of the first circuit island 121 and the second circuit island 122 in the second area NA tend to be consistent, thereby improving the stretching performance of the second area NA.
  • the sizes of the pixel island 110, the first circuit island 121 and the second circuit island 122 are the same, so that the stretching rate of the second area NA is consistent with the stretching rate of the first area A, which can improve the overall stretching performance of the display panel.
  • the second circuit island 122 can be one, the second circuit island 122 is used to set the connecting part 222, and the first circuit island 121 is used to set the shift register unit 221.
  • the present application increases the distance between the shift register unit 221 and the connecting part 222 by separating the connecting part 222 and the shift register unit 221 in the second area NA in different circuit islands 120, thereby ensuring the insulation performance between the shift register unit 221 and the connecting part 222.
  • the number of the second circuit islands 122 is more than two.
  • the number of the second circuit islands 122 is two, and the second signal line 420 of one of the second circuit islands 122 includes a clock signal line, for example, the second signal line 420 of one of the second circuit islands 122 includes a first clock signal line CLK1 and a second clock signal line (CLK2), and the second signal line 420 of the other second circuit island 122 includes a scan line and a first power signal line (VDD).
  • the two second circuit islands 122 can be arranged on both sides of the first circuit island 121 in the first direction X, or the two second circuit islands 122 can be located on the same side of the first circuit island 121 in the first direction X.
  • two second circuit islands 122 are disposed on both sides of the first circuit island 121 in the first direction X.
  • a first clock signal line CLK1 and a second clock signal line CLK2 are disposed on the second circuit island 122 away from the first area AA, and the first clock signal line CLK1 and the second clock signal line CLK2 extend between the second circuit island 122 and the first circuit island 121 to connect the shift register unit 221 of the first circuit island 121.
  • a scan line and a first power signal line VDD are disposed on the second circuit island 122 close to the first area AA, and the scan line includes a first scan line Sn and a second scan line Sn+1, and the first scan line Sn extends as an input between the second circuit island 122 and the first circuit island 121 to connect the shift register unit 221, and the second scan line Sn+1 extends as an output between the second circuit island 122 and the first circuit island 121 to connect the shift register unit 221.
  • a high-level power line VGH and a low-level power line VGL may be connected to the first circuit island 121, and the high-level power line VGH and the low-level power line VGL extend from both sides of the first circuit island 121 in the second direction Y.
  • the first signal line 410 includes the signal line 400 connected to the shift register unit 221
  • the second signal line 420 includes the signal line 400 connected to the second circuit island 122.
  • the present application divides the signal line 400 into the first signal line 410 and the second signal line 420 according to the setting position and the connection object.
  • the signal line 410 and the second signal line 420 , and parts of the first signal line 410 and the second signal line 420 may be used to transmit the same signal.
  • the number of the second circuit islands 122 is three or more, for example, the number of the second circuit islands 122 is three, and the second signal line 420 includes a clock signal line, a virtual signal line (dum), a scan line, and a first power signal line, and the clock signal line, the virtual signal line, the scan line, and the first power signal line are arranged on three second circuit islands 122.
  • the second signal line 420 includes a clock signal line, a virtual signal line (dum), a scan line, and a first power signal line, and the clock signal line, the virtual signal line, the scan line, and the first power signal line are arranged on three second circuit islands 122.
  • the clock signal line may include a first clock signal line (CLK1) and a second clock signal line (CLK2)
  • the virtual signal line may also include a first virtual signal line and a second virtual signal line, for example, the first clock signal line and the first virtual signal line are arranged on the same second circuit island 122, the second virtual signal line and the second clock signal line are arranged on another second circuit island 122, and the scan line and the first power signal line are arranged on another second circuit island 122.
  • the first clock signal line CLK1 and the second clock signal line CLK2 extend to the two second circuit islands 122, and the second circuit island 122 and the first circuit island 121 to connect the shift register unit 221.
  • the second circuit island 122 near the first area AA is provided with a scan line and a first power signal line VDD, and the arrangement of the scan line and the first power signal line VDD is shown in FIG3 and will not be described in detail here.
  • the first circuit island 121 may also be connected with a high-level power line VGH and a low-level power line VGL, and the arrangement of the high-level power line VGH and the low-level power line VGL is shown in FIG3 and will not be described in detail here.
  • the number of second circuit islands 122 can also be four, each second circuit island 122 includes two second signal lines, the number of virtual signal lines is four, each virtual signal line is respectively arranged in each second circuit island 122, and the first clock signal line, the second clock signal line, the scan line and the first power signal line are respectively arranged in each second circuit island 122.
  • FIG13 there are four second circuit islands 122, and the four second circuit islands 122 are evenly arranged on both sides of the first circuit island 121, that is, two second circuit islands 122 are arranged on one side of the first circuit island 121.
  • the arrangement of the two second circuit islands 122 located on the side of the first circuit island 121 away from the first area AA and the signal lines 400 connected thereto are shown in FIG12 , which will not be described in detail here.
  • the first circuit island 121 can also be connected to a high-level power line VGH and a low-level power line VGL, and its arrangement is shown in FIG3 , which will not be described in detail here.
  • an auxiliary line 409 may also be provided on the signal line 400.
  • the auxiliary line 409 crosses the signal line 400 and is located on the circuit island 120.
  • the auxiliary line 409 is used to increase the contact area between the signal line 400 and the circuit island 120, thereby improving the stability of the position of the signal line 400.
  • the virtual signal line 125 by adding the virtual signal line 125, on the one hand, by reasonably arranging the position of the virtual signal line, the virtual signal line can be arranged close to the side of the second area NA away from the first area AA, so that at least part of the second signal line 420 (for example, the first power signal line) can be arranged away from the edge of the second area NA, thereby improving the effect of static electricity generated by cutting on the second signal line 420; in addition, by reasonably setting the number of virtual signal lines, the number of the second sub-line 421 and the fifth sub-line 422 of the second circuit island 122 and the first sub-line 411 and the fourth sub-line 412 of the first circuit island 121 can be made consistent, thereby improving the stretching performance of the display panel.
  • the signal line 400 is not a straight line.
  • at least part of the signal line 400 is arc-shaped.
  • the signal line 400 includes arc segments, and the signal line 400 includes semi-circular segments.
  • two signal lines 400 extend from the same side of the same functional island 100.
  • the semi-circular segments of the two signal lines 400 connected to the same functional island 100 and extending from the same side of the functional island 100 are symmetrically arranged.
  • the signal line 400 includes a first signal line 410, and two first signal lines 410 are arranged side by side on one side of the first circuit island 121, the arc openings of the two first signal lines 410 are arranged opposite to each other.
  • the arc opening is an opening formed by bending the semicircular first signal line 410.
  • second areas NA are provided on both sides of the first area AA, and a driving circuit structure 220 is provided in each second area NA to realize double-sided driving of the display panel, improve the voltage drop problem, and enhance the display effect of the display panel.
  • the embodiment of the first aspect of the present application also provides another display panel, comprising a first area AA and a second area NA arranged around at least a portion of the first area AA, wherein the first area AA and the second area NA both include an island area and a stretching area, a plurality of island areas are distributed in an array in the first area AA and the second area NA, the stretching area is located between two adjacent rows and/or two adjacent columns of island areas, the display panel comprises a functional island 100, a stretching portion 300 and a signal line 400, each functional island 100 is located in each island area and a functional part 200 is arranged on the functional island, and the plurality of functional islands 100 include a first area AA and a second area NA.
  • the functional part 200 includes a first pixel circuit structure 210 disposed on the pixel island 110 and a driving circuit structure 220 disposed on the circuit island 120;
  • the stretching portion 300 is disposed in the stretching area and connected between two adjacent functional islands 100, and in the second area NA, at least part of the stretching area is disposed along the direction from the first area AA to the second area NA through the second area NA;
  • the signal line 400 is disposed in the stretching portion 300 and is used to connect the functional parts 200 of two adjacent functional islands 100.
  • the plurality of circuit islands 120 include a first island assembly 100a, the first island assembly 100a includes a first circuit island 121 and a second circuit island 122, the driving circuit structure 220 includes a shift register unit 221 disposed on the first circuit island 121, the second circuit island 122 and the first circuit island 121 are disposed side by side, and the shift register unit 221 is connected to the first pixel circuit structure 210 through the signal line 400 to provide a scanning signal to the first pixel circuit structure 210.
  • the first circuit island 121 and the second circuit island 122 in the same first island assembly 100a are arranged at intervals along the first direction X, and the plurality of first island assemblies 100a are arranged at intervals along the second direction Y in the second area NA.
  • the functional part 200 also includes a second pixel circuit structure 230 and a second light-emitting unit arranged on at least one of the first circuit island 121 and the second circuit island 122, and the second pixel circuit structure 230 is used to drive the second light-emitting unit to emit light.
  • the second pixel circuit structure 230 and the second light-emitting unit are arranged on the circuit island 120 close to the first area AA in the first circuit island 121 and the second circuit island 122 of the first island assembly 100a, so that part of the second area NA close to the first area AA can be displayed, thereby expanding the display area of the display panel and achieving the purpose of narrow frame.
  • the display panel is configured as described in any of the above embodiments, which will not be described in detail herein.
  • the embodiment of the second aspect of the present application also provides a display device, including the display panel of any of the above-mentioned embodiments of the first aspect. Since the display device provided by the embodiment of the second aspect of the present application includes the display panel of any of the above-mentioned embodiments of the first aspect, the display device provided by the embodiment of the second aspect of the present application has the beneficial effects of the display panel of any of the above-mentioned embodiments of the first aspect, which will not be repeated here.
  • the display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDA), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles and other devices with display functions.
  • PDA personal digital assistants

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请实施例提供一种显示面板及显示装置，显示面板具有第一区和位于第一区周边的第二区，第一区和第二区均包括岛区和拉伸区，多个岛区在第一区和第二区阵列分布，拉伸区位于相邻两行和/或相邻两列岛区之间，显示面板包括：多个功能岛，各功能岛上设置有功能件，多个功能岛包括位于第一区的多个像素岛和位于第二区的多个电路岛，功能件包括设置于像素岛的第一像素电路结构和设置于电路岛的驱动电路结构；拉伸部，连接于相邻的两个功能岛之间，且在第二区，至少部分拉伸区沿第一区至第二区的方向贯穿第二区设置；信号线，设置于拉伸部并用于连接相邻的两个功能岛的功能件。本申请能够提高显示面板的拉伸性能。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2023年03月29日提交的名称为“显示面板及显示装置”的中国专利申请第202310319700.6号的优先权、及2023年12月29日提交的名称为“显示面板及显示装置”的中国专利申请第202311857627.4号的优先权，该两个申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示设备技术领域，尤其涉及一种显示面板及显示装置。
背景技术
有机发光二极管(Organic light‐emitting diode，OLED)显示面板因具有广视角、超高对比度和响应快速等优点而备受人们的青睐。OLED显示基板的其中一个优势就是可以实现柔性化，其通过将OLED器件制作在柔性衬底上，便可实现可弯曲的显示设备。但随着可穿戴设备的日渐流行，其对于OLED柔性面板的拉伸性能提出了更高的要求。
发明内容
本申请实施例提供一种显示面板及显示装置，旨在提高显示面板的拉伸性能。
本申请第一方面的实施例提供了一种显示面板，显示面板具有第一区和环绕至少部分第一区设置的第二区，第一区和第二区均包括岛区和拉伸区，多个岛区在第一区和第二区阵列分布，拉伸区位于相邻两行和/或相邻两列岛区之间，显示面板包括：多个功能岛，各功能岛位于各岛区且功能岛上设置有功能件，多个功能岛包括位于第一区的多个像素岛和位于第二区的多个电路岛，功能件包括设置于像素岛的第一像素电路结构、第一发光单元和设置于电路岛的驱动电路结构，第一像素电路结构用于驱动第一发光单元发光；拉伸部，设置于拉伸区并连接于相邻的两个功能岛之间，且在第二区，至少部分拉伸区沿第一区至第二区的方向贯穿第二区设置；信号线，设置于拉伸部并用于连接相邻的两个功能岛的功能件。
根据本申请第一方面的实施方式，多个电路岛包括第一岛组件，第一岛组件包括：
第一电路岛，驱动电路结构包括设置于第一电路岛的移位寄存单元，
第二电路岛，和第一电路岛并排设置，驱动电路结构包括设置于第二电路岛的连接部；
信号线包括连接移位寄存单元的第一信号线、连接连接部的第二信号线，多个移位寄存单元通过至少部分第二信号线、连接部和第一信号线与第一像素电路结构连接，以向第一像素电路结构提供扫描信号。
根据本申请第一方面前述任一实施方式，多个电路岛和多个像素岛沿第一方向和第二方向成行成列排布，同一行的电路岛和像素岛中，电路岛上的移位寄存单元用于 驱动与其同行的像素岛的第一像素电路结构。
根据本申请第一方面前述任一实施方式，第一岛组件的第一电路岛和第二电路岛沿第一方向并排设置，且多个第一岛组件沿第二方向间隔设置，沿第二方向并排设置的多个第一电路岛的第一信号线相互连接，沿第二方向并排设置的多个第二电路岛的第二信号线相互连接。
根据本申请第一方面前述任一实施方式，沿第二方向间隔设置的多个第一岛组件的第一电路岛沿第二方向对齐设置。
根据本申请第一方面前述任一实施方式，沿第二方向间隔设置的多个第一岛组件的第二电路岛沿第二方向对齐设置。
根据本申请第一方面前述任一实施方式，功能件还包括设置于第一电路岛和第二电路岛至少一者上的第二像素电路结构和第二发光单元，第二像素电路结构用于驱动第二发光单元发光。
根据本申请第一方面前述任一实施方式，第一岛组件的第一电路岛和第二电路岛中靠近第一区的电路岛上设有第二像素电路结构和第二发光单元。
根据本申请第一方面前述任一实施方式，第一岛组件包括一个第一电路岛和两个第二电路岛，两个第二电路岛分设于第一电路岛的两侧，第二像素电路结构设置于位于第一电路岛朝向第一区的第二电路岛上。
根据本申请第一方面前述任一实施方式，同一第一岛组件中的第一电路岛和第二电路岛上均设置有第二发光单元，且同一第一岛组件中的第一电路岛和第二电路岛中的一者上设置有第二像素电路结构，第二像素电路结构用于驱动同一第一岛组件中的多个第二发光单元发光。
根据本申请第一方面前述任一实施方式，至少一个第二电路岛上设置有虚拟像素电路。
根据本申请第一方面前述任一实施方式，两个第二电路岛上均设置有虚拟像素电路，且其中一个第二电路岛上的第二像素电路结构和虚拟像素电路的数量之和与另一第二电路岛上的虚拟像素电路数量之和相等。
根据本申请第一方面前述任一实施方式，第二发光单元包括第一电极，信号线包括：
第一连接线，用于连接同一第一岛组件内相邻的两个第一电极；
第二连接线，为扫描线并用于连接驱动电路结构和第二像素电路结构，或者，用于连接相邻的第一像素电路结构和第二像素电路结构；
第三连接线，为电源信号线并用于连接第一像素电路结构和第二像素电路结构；
其中，连接于相邻两个电路岛之间的第二连接线与第一连接线沿显示面板的厚度方向层叠设置；和/或，连接于相邻两个电路岛之间的第二连接线与第三连接线沿显示面板的厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，第二发光单元还包括第二电极，第一信号线还包括第四连接线，第四连接线用于连接相邻两个电路岛上的第二电极，第四连接线与第二连接线沿厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，第四连接线和第一电极同层并间隔绝缘设置，第四连接线和第二电极过孔连接。
根据本申请第一方面前述任一实施方式，第二连接线包括第一扫描线和第二扫描线，第一扫描线和第二扫描线沿第二方向间隔设置，第一扫描线和第四连接线沿厚度方向层叠设置，第二扫描线和第一连接线沿厚度方向层叠设置，或者，第二扫描线和第三连接线沿厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，信号线包括连接像素岛的并沿第二方向 延伸的第七连接线，至少一条第四连接线连接第二电路岛和像素岛，且在像素岛连接第七连接线。
根据本申请第一方面前述任一实施方式，信号线包括连接设置有第二像素电路结构的第二电路岛的数据线和第六连接线，数据线和第六连接线沿第一方向并排设置，且第六连接线和第一扫描线相互电连接。
根据本申请第一方面前述任一实施方式，信号线包括：
时钟信号线，时钟信号线连接于位于第一电路结构背离第一区的第二电路岛上；
第五连接线，第五连接线连接时钟信号线和驱动电路结构，连接于相邻两个电路岛之间的第五连接线与第一连接线沿厚度方向层叠设置；和/或，连接于相邻两个电路岛之间的第五连接线与第四连接线沿厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，时钟信号线包括第一时钟信号线和第二时钟信号线，第五连接线包括连接第一时钟信号线的第一子连接线和连接第二时钟信号线的第二子连接线，第一子连接线和第二子连接线沿第二方向间隔设置，第一子连接线和第四连接线沿厚度方向层叠设置，第二子连接线和第一连接线沿厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，信号线还包括位于第一区的冗余走线、用于连接相邻第一像素电路结构的信号走线，至少部分冗余走线和信号走线沿厚度方向层叠设置。
根据本申请第一方面前述任一实施方式，相邻两个像素岛之间的冗余走线和信号走线的数量之和与相邻两个电路岛之间的信号线的数量相同。
根据本申请第一方面前述任一实施方式，相邻两个像素岛之间的冗余走线和第一连接线、第二连接线、第三连接线和第四连接线中的至少一者同层同材料设置。
根据本申请第一方面前述任一实施方式，第一信号线包括第一子线，第一子线由第一电路岛在第二方向的两侧伸出；
第二信号线包括第二子线，第二子线由第二电路岛在第二方向的两侧伸出，
其中，各第一电路岛对应的第一子线的数量和各第二电路岛对应的第二子线的数量相同。
根据本申请第一方面前述任一实施方式，信号线还包括连接第一像素电路结构的驱动信号线，驱动信号线包括第三子线，第三子线由像素岛在第二方向的两侧伸出，各像素岛对应的第三子线的数量和各第一电路岛对应的第一子线的数量相同。
根据本申请第一方面前述任一实施方式，第一信号线包括第四子线，第四子线由第一电路岛在第一方向的两侧伸出；
第二信号线包括第五子线，第五子线由第二电路岛在第一方向的两侧伸出，
其中，各第一电路岛对应的第四子线的数量和各第二电路岛对应的第五子线的数量相同。
根据本申请第一方面前述任一实施方式，驱动信号线包括第六子线，第六子线由像素岛在第一方向的两侧伸出，各像素岛对应的第六子线的数量和各第一电路岛对应的第四子线的数量相同。
根据本申请第一方面前述任一实施方式，同一第一电路岛对应第一子线的数量和第三子线的数量相同。
根据本申请第一方面前述任一实施方式，同一第二电路岛对应第二子线的数量和第五子线的数量相同。
根据本申请第一方面前述任一实施方式，同一像素岛对应第三子线的数量和第六子线的数量相同。
根据本申请第一方面前述任一实施方式，至少部分第三子线和至少部分第六子线 相互连接，以使第一像素电路结构能够通过第六子线、第三子线和移位寄存单元相互电连接。
根据本申请第一方面前述任一实施方式，至少部分第四子线和至少或部分第六子线相互连接，以使第一像素电路结构能够通过第六子线、第四子线和连接部相互电连接。
根据本申请第一方面前述任一实施方式，第二电路岛的个数为一个，第二电路岛设置于第一电路岛朝向或背离第一区的一侧；
第二信号线包括时钟信号线、扫描线和第一电源信号线中的至少一者。
根据本申请第一方面前述任一实施方式，第二电路岛的个数为多个，多个第二电路岛分设于第一电路岛的两侧，或者多个第二电路岛设置于第一电路岛朝向或背离第一区的一侧。
根据本申请第一方面前述任一实施方式，第二区包括沿第一方向延伸的第一子区和沿第二方向延伸的第二子区，第一岛组件位于第二子区，显示面板还包括绑定引脚，绑定引脚位于第一子区。
根据本申请第一方面前述任一实施方式，至少部分拉伸部沿第一方向贯穿第二子区设置。
根据本申请第一方面前述任一实施方式，两个第二子区分设于第一区在第一方向的两侧，各第二子区内均设置有第一岛组件。
根据本申请第一方面前述任一实施方式，多个绑定引脚在第一子区沿第二方向间隔分布。
根据本申请第一方面前述任一实施方式，两个第一子区分设于第一区在第二方向的两侧，各第一子区内均设置有绑定引脚。
根据本申请第一方面前述任一实施方式，第一子区在第一方向上的延伸尺寸小于第二子区在第二方向上的延伸尺寸。
根据本申请第一方面前述任一实施方式，像素岛、第一电路岛和第二电路岛中的至少两者的尺寸相同。
扫描线根据本申请第一方面前述任一实施方式，第二电路岛的个数为两个，其中一个第二电路岛对应的第二信号线包括第一时钟信号线和第二时钟信号线，另一个第二电路岛对应的第二信号线包括扫描线和第一电源信号线，第一信号线包括高电平电源线和低电平电源线；
或者，第二电路岛的个数为三个以上，至少一个第二电路岛对应的第二信号线包括虚拟信号线。
根据本申请第一方面前述任一实施方式，第二信号线包括虚拟信号线，且虚拟信号线的数量和与其连接于同一第二电路岛的信号线对称设置。
根据本申请第一方面前述任一实施方式，至少部分信号线呈弧形。
根据本申请第一方面前述任一实施方式，信号线包括圆弧分段。
根据本申请第一方面前述任一实施方式，连接于同一功能岛、且由功能岛的同侧伸出的两条信号线对称设置。
本申请第一方面的实施例还提供了一种显示面板，显示面板具有第一区和位于第一区周边的第二区，第一区和第二区均包括岛区和拉伸区，多个岛区在第一区和第二区阵列分布，拉伸区位于相邻两行和/或相邻两列岛区之间，显示面板包括：多个功能岛，各功能岛位于各岛区且功能岛上设置有功能件，多个功能岛包括位于第一区的多个像素岛和位于第二区的多个电路岛，功能件包括设置于像素岛的第一像素电路结构、第一发光单元和设置于电路岛的驱动电路结构，第一像素电路结构用于驱动第一发光单元发光；拉伸部，设置于拉伸区并连接于相邻的两个功能岛之间，且在第二区，至 少部分拉伸区沿第一区至第二区的方向贯穿第二区设置；信号线，设置于拉伸区并用于连接相邻的两个功能岛的功能件；多个电路岛包括第一岛组件，第一岛组件包括：第一电路岛，驱动电路结构包括设置于第一电路岛的移位寄存单元；第二电路岛，和第一电路岛并排设置，移位寄存单元通过信号线与第一像素电路结构连接，以向第一像素电路结构提供扫描信号，第一岛组件的第一电路岛和第二电路岛沿第一方向并排设置，且多个第一岛组件沿第二方向间隔设置，功能件还包括设置于第一电路岛和第二电路岛至少一者上的第二像素电路结构和与第二像素电路结构电连接的第二发光单元，第二像素电路结构用于驱动第二发光单元发光，第一岛组件的第一电路岛和第二电路岛中靠近第一区的电路岛上设有第二像素电路结构和第二发光单元。
本申请第二方面的实施例还提供了一种显示装置，包括上述任一第一方面实施例的显示面板。
在本申请实施例提供的显示面板中，显示面板具有第一区和第二区，第一区可以用于设置发光单元实现显示面板的显示，第二区可以设置用于驱动显示面板发光的信号线和控制器等。显示面板包括功能岛、拉伸部和信号线。功能岛上设置有功能件，功能岛包括像素岛和电路岛，功能件包括第一像素电路结构和驱动电路结构，将第一像素电路结构设置于像素岛，能够改善第一像素电路结构在显示面板拉伸过程中易损坏的问题。同样的，将驱动电路结构设置于电路岛，也能够改善驱动电路结构在显示面板拉伸过程中易损坏的问题。功能岛之间设置有拉伸部，能够提高显示面板的拉伸性能，且第二区的至少部分拉伸部贯穿第二区设置，形成了非显示拉伸区，能够进一步提高第二区的拉伸性能。信号线设置于拉伸部内并连接相邻的功能岛的功能件，以实现不同功能件之间的信号传输。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征。
图1是本申请第一方面实施例提供的一种显示面板的示意图；
图2是本申请第一方面实施例提供的一种显示面板的结构示意图；
图3是本申请第一方面实施例提供的一种显示面板的第一岛组件的结构示意图；
图4是图2中A-A处的剖视图；
图5是本申请第一方面另一实施例提供的一种显示面板的第一岛组件的结构示意图；
图6是图2中B-B处的剖视图；
图7是本申请第一方面又一实施例提供的一种显示面板的第一岛组件和像素岛的结构示意图；
图8是图7的局部剖视图；
图9是图7另一位置的局部剖视图；
图10是本申请第一方面实施例提供的一种显示面板的像素岛的结构示意图；
图11是本申请第一方面另一实施例提供的一种显示面板的结构示意图；
图12是本申请第一方面又一实施例提供的一种显示面板的第一岛组件的结构示意图；
图13是本申请第一方面还一实施例提供的一种显示面板的第一岛组件的结构示意图。
具体实施方式
下面结合图1至图13对本申请实施例的显示面板和显示装置进行详细描述。
如图1至图10所示，本申请第一方面的实施例提供了一种显示面板，显示面板具有第一区AA和环绕至少部分第一区AA设置的第二区NA，第一区AA和第二区NA均包括岛区和拉伸区，多个岛区在第一区AA和第二区NA阵列分布，拉伸区位于相邻两行和/或相邻两列岛区之间，显示面板包括功能岛100、拉伸部300和信号线400，各功能岛100位于各岛区且功能岛100上设置有功能件200，多个功能岛100包括位于第一区AA的多个像素岛110和位于第二区NA的多个电路岛120，功能件200包括设置于像素岛110的第一像素电路结构210和设置于电路岛120的驱动电路结构220；拉伸部300设置于拉伸区并连接于相邻的两个功能岛100之间，且在第二区NA，至少部分拉伸区沿第一区AA至第二区NA的方向贯穿第二区NA设置；至少部分信号线400设置于拉伸部300并用于连接相邻的两个功能岛100的功能件200。
可选的，至少部分拉伸区沿第一区AA至第二区NA的方向贯穿第二区NA设置；也就是说，第二区NA被拉伸区分隔为多个子区，相邻的子区之间形成用于将第二区NA断开的拉伸区，拉伸区即设置有拉伸部300的区域。
在本申请实施例提供的显示面板中，显示面板具有第一区AA和第二区NA，第一区AA可以用于设置发光单元实现显示面板的显示，第二区NA可以设置用于驱动显示面板发光的信号线400和控制器等。显示面板包括功能岛100、拉伸部300和信号线400。功能岛100上设置有功能件200，功能岛100包括像素岛110和电路岛120，功能件200包括第一像素电路结构210和驱动电路结构220，将第一像素电路结构210设置于像素岛110，能够改善第一像素电路结构210在显示面板拉伸过程中易损坏的问题。同样的，将驱动电路结构220设置于电路岛120，也能够改善驱动电路结构220在显示面板拉伸过程中易损坏的问题。功能岛100之间设置有拉伸部300，能够提高显示面板的拉伸性能，且第二区NA的至少部分拉伸部300贯穿第二区NA设置，能够进一步提高第二区的拉伸性能。信号线400设置于拉伸部300内并连接相邻的功能岛100的功能件200，以实现不同功能件200之间的信号传输。
可选的，多个岛区沿第一方向X和第二方向Y成行成列分布，多个岛区间隔设置，拉伸区位于沿第二方向Y相邻的两行岛区之间，和/或，拉伸区位于沿第一方向X相邻的两列岛区之间。可选的，在第一区AA，相邻的两行和两列岛区之间均设置有拉伸区，使得第一区AA在第一方向X和第二方向Y上均能够被拉伸。岛区可以认为设置功能岛100的区域，拉伸区可以认为是设置拉伸部300的区域。在第二区NA，一部分第二区NA的相邻的两行或相邻的两列岛区之间设置有拉伸区。例如，如图1所示，位于第一区AA在第一方向两侧的部分第二区NA中，相邻的两行和两列岛区之间均设置有拉伸区，这一部分区域的岛区相互间隔设置，使得这部分第二区NA能够在第一方向和第二方向上被拉伸。而位于第一区AA在第二方向两侧的部分第二区NA中，拉伸区并未沿第二方向Y贯穿第二区设置。
至少部分拉伸部300沿第一区AA至第二区NA的方向贯穿第二区NA设置。也就是说，第二区NA包括两部分，一部分用于设置电路岛120，另一部分设置拉伸部300，拉伸部300沿第一区AA至第二区NA的方向贯穿第二区NA设置。即至少部分第二区NA不是环绕第一区AA呈连续结构，环绕第一区AA的至少部分第二区NA被拉伸部300分隔为多个用于设置电路岛120的结构。
可选的，如图2至图4所示，功能岛100为刚性区域，功能岛100包括依次层叠设置的衬底(PI)、缓冲层(图中未示出)、半导体层(P-Si)、多个金属层(M)、平坦化层(PLN)、像素定义层(PDL)、支撑柱层及位于相邻两个金属层之间的绝缘层等功能层结构。
可选的，如图8所示，拉伸部300为柔性区域，拉伸部300的功能层结构数量少于功能岛100的功能层结构数量，使得拉伸部300易变形以实现显示面板的可拉伸。例如，拉伸部300包括金属层301及位于金属层301两侧的防护层302，信号线400设置于金属层301，防护层302用于向信号线400提供防护，并用于避免信号线400与其他电路短路连接等问题。
可选的，拉伸部300还包括弹性填充层600，弹性填充层600具有弹性，以提高显示面板的拉伸性能。可选的，弹性填充层600可以位于用于设置信号线400的金属层在厚度方向Z上的一侧或两侧。可选的，弹性填充层600的透光率大于15％，例如弹性填充层600的透光率大于20％、或者弹性填充层600的透光率大于80％，甚至弹性填充层600的透光率大于95％。使得弹性填充层600具有良好的透光性能，提高显示面板的显示效果。
可选的，信号线400在拉伸部300内沿直线路径延伸，利用信号线400本身材料特性克服显示面板拉伸时产生的拉伸力。
在另一些可选的实施例中，至少部分信号线400沿弯折路径延伸设置。在显示面板拉伸时，通过信号线400自身的形状变形以克服该拉伸力，能够改善信号线400受力易断裂的问题。
多个电路岛120包括第一岛组件100a，第一岛组件100a包括第一电路岛121和第二电路岛122，驱动电路结构220包括设置于第一电路岛121的移位寄存单元221，第二电路岛122和第一电路岛121并排设置，驱动电路结构220包括设置于第二电路岛122的连接部222。信号线400包括连接移位寄存单元221的第一信号线410、连接连接部222的第二信号线420，多个移位寄存单元221通过至少部分第二信号线420、连接部222和第一信号线410与第一像素电路结构210连接，以向第一像素电路结构210提供扫描信号。图2中以虚线框出了第一岛组件100a的所在位置，虚线框并不构成对本申请实施例结构上的限定。
在这些可选的实施例中，第一岛组件100a包括间隔并排设置的第一电路岛121和第二电路岛122，由于第一电路岛121和第二电路岛122相互间隔设置，因此第一电路岛121和第二电路岛122之间能够形成间隙，该间隙可以设置拉伸部300从而增加第二区NA的拉伸性能，进而增加整个显示面板的拉伸性能。
此外，信号线400分为第一信号线410、第二信号线420，使得移位寄存单元221可以通过第一信号线410和第二信号线420连接第一像素电路结构210，从而向第一像素电路结构210提供扫描信号。
本申请实施例在第二区NA设置了两个不同的电路岛120，即第一电路岛121和第二电路岛122，使得第二区NA内的移位寄存单元221和连接信号线400的连接部222等可以分设在第一电路岛121和第二电路岛122上，一方面能够为移位寄存单元221和信号线400提供足够的设置区域；另一方面还能够改善移位寄存单元221和信号线400布线相互干扰的问题。
在本申请实施例中，连接部222和第二信号线420的不同之处在于所处位置，连接部222设置在第二电路岛122，第二信号线420设置于拉伸部300，但是连接部222和第二信号线420可以用于传输相同的信号，连接部222和第二信号线420也可以设置于同一导电层，连接部222和第二信号线420的延伸方向也可以相同或不同。
可选的，多个电路岛120分为第一电路岛121和第二电路岛122，第一电路岛121和第二电路岛122的不同之处在于其上设置的功能件200不同，第一电路岛121上设置有移位寄存单元221，第二电路岛122上设置有连接部222，移位寄存单元221用于传输扫描信号，连接部222用于实现不同信号线400之间的连接。连接部222设置于第二电路岛122，能够改善不同信号线400之间的连接位置处在显示面板拉伸过程中易断裂 的问题。
可选的，第一电路岛121和第二电路岛122又并排组合形成第一岛组件100a，第一岛组件100a包括第一电路岛121和一个或多个第二电路岛122。
可选的，多个电路岛120和多个像素岛110沿第一方向X和第二方向Y成行成列排布，同一行的电路岛120和像素岛110中，电路岛120上的移位寄存单元221用于驱动与其同行的像素岛110的第一像素电路结构210。
在这些可选的实施例中，相互连接的移位寄存单元221和第一像素电路结构210位于同一行设置的电路岛120和像素岛110上，能够简化信号线400的布置路径。
如图1至图6所示，第一信号线410的设置方式有多种，第一信号线410可以包括高电平电源线(VGH)、低电平电源线(VGL)中的至少一者。例如第一信号线410包括高电平电源线和低电平电源线，且高电平电源线和低电平带能源信号线沿第一方向X并排设置。
第二信号线420的设置方式有多种，例如，第二信号线420包括第一时钟信号线(CLK1)、第二时钟信号线(CLK2)、第一电源信号线400(VSS)和扫描线(Sn)中的至少一者。第一电源信号线可以用于传输负电压，第一电源信号线可以连接第一区AA的阴极。
在一些可选的实施例中，同一第一岛组件100a内的第一电路岛121和第二电路岛122沿第一方向X间隔设置，多个第一岛组件100a在第二区NA内沿第二方向Y间隔设置，沿第二方向Y设置的多个第一电路岛121连接的第一信号线410相互连接，即第一信号线410用于连接沿第二方向Y设置的移位寄存单元221；沿第二方向Y设置的多个第二电路岛122连接的第二信号线420相互连接，即第二信号线420用于连接沿第二方向Y设置的连接部222。
在这些可选的实施例中，多个第一电路岛121和第二电路岛122沿第一方向X和第二方向Y阵列分布，沿第一方向X相邻的第一电路岛121和第二电路岛122之间具有间隙，沿第二方向Y相邻的第一电路岛121或第二电路岛122之间也有间隙，这些间隙内均可以设置拉伸部300，能够提高显示面板在第一方向X和第二方向Y上的拉伸性能。
可选的，沿第二方向Y间隔设置的多个第一岛组件100a的第一电路岛121沿第二方向Y对齐设置，即多个第一岛组件100a的第一电路岛121位于同一列内，列方向为第二方向Y，使得多个第一电路岛121的排布更加规律，同时便于第一信号线410连接相邻的栅极驱动电路。
可选的，沿第二方向Y间隔设置的多个第一岛组件100a的第二电路岛122沿第二方向Y对齐设置。即多个第一岛组件100a的第二电路岛122位于同一列内，列方向为第二方向Y，使得多个第二电路岛122的排布更加规律，同时便于第二信号线420沿第二方向Y相互连接。
可选的，当同一第一岛组件100a内的第二电路岛122的个数为多个时，多个第二电路岛122沿第一方向X并排设置，多个第一岛组件100a的第二电路岛122呈多列分布，且同列的多个第二电路岛122沿第二方向Y对齐设置。
可选的，在上述任一实施例中，第二区NA可以不设置发光单元，第二区NA用于设置移位寄存单元221和相关的信号线400并构成显示面板的非显示区。
在另一些实施例中，如图7所示，功能件200还包括设置于第一电路岛121和第二电路岛122至少一者上的第二像素电路结构230和第二发光单元，第二像素电路结构230用于驱动第二发光单元发光。
在这些实施例中，第二像素电路结构230可以驱动第二发光单元发光，从而使得第二区NA也能够显示，扩大显示面板的显示面积，提高显示面板的屏占比。
可选的，第二发光单元包括第一电极240、第二电极250和设置于第一电极240和第二电极250之间的发光结构，第一电极240可以连接于第二像素电路结构230，使得第二像素电路结构230通过第一电极240驱动发光结构发光。
可选的，第二像素电路结构230和第二发光单元可以相互连接设置于其中一个第一电路岛121或第二电路岛122上。或者，第一电路岛121和第二电路岛122上均设置有相互连接的第二发光单元和第二像素电路结构230。
在还一些实施例中，第一岛组件100a的第一电路岛121和第二电路岛122中靠近第一区AA的电路岛120上设置有第二像素电路结构230和第二发光单元，令部分靠近第一区AA的第二区NA能够显示，进而扩大显示面板的显示区域面积，实现窄边框的目的。
在另一些可选的实施例中，同一第一岛组件100a中的第一电路岛121和第二电路岛122上均设置有第一电极240，且同一第一岛组件100a中的第一电路岛121和第二电路岛122中的一者上设置有第二像素电路结构230，第二像素电路结构230用于驱动同一第一岛组件100a中的多个第一电极240。
在这些可选的实施例中，同一第一岛组件100a中的第一电路岛121和第二电路岛122上均设置有第一电极240，使得第一岛组件100a中的第一电路岛121和第二电路岛122对应位置均可以设置第二发光单元以实现显示面板的发光显示。同一第一岛组件100a中的一个电路岛120上设置第二像素电路结构230，且该一个第二像素电路结构230用于驱动同一第一岛组件100a中的多个第一电极240，第二像素电路结构230和第一电极240为一驱多的关系，能够减少第二区NA内信号线400的布置数量，进而提高第二区NA的拉伸性能。
可选的，第二像素电路结构230可以设置于第二电路岛122，以改善第二像素电路结构230和移位寄存单元221之间位置的相互干扰，第二电路岛122上具有足够的设置空间以设置第二像素电路结构230。
可选的，第一岛组件100a包括一个第一电路岛121和两个第二电路岛122，两个第二电路岛122分设于第一电路岛121的两侧，第二像素电路结构230设置于位于第一电路岛121朝向第一区AA的第二电路岛122上。可选的，如图7所示，左起前三个电路岛120组成第一岛组件100a，且左起第一个和第三个为第二电路岛122，左起第二个为第一电路岛121，最右的功能岛100为像素岛110。
在这些可选的实施例中，第二像素电路结构230靠近第一区AA设置，能够减小第二像素电路结构230和第一像素电路结构210之间的间距，便于从第一像素电路结构210处引入其他信号传输线至第二像素电路结构230，能够简化显示面板的信号线400布置。
可选的，至少一个第二电路岛122上设置有虚拟像素电路260。通过设置虚拟像素电路260结构，能够保证多个功能岛100上金属布线密度的一致性，改善显示面板的显示效果。
可选的，两个第二电路岛122上均设置有虚拟像素电路260，且其中一个第二电路岛122上的第二像素电路结构230和虚拟像素电路260的数量之和与另一第二电路岛122上的虚拟像素电路260数量之和相等。例如，位于第一电路岛121背离第一区AA一侧的第二电路岛122上设置有3个虚拟像素电路260，位于第一电路岛121朝向第一区AA一侧的第二电路岛122上设置有2个虚拟像素电路260和1个第二像素电路结构230，能够保证两个第二电路岛122上金属布线密度的一致性。
在一些可选的实施例中，如图7至图9所示，信号线400包括第一连接线401、第二连接线402和第三连接线403，第一连接线401用于连接同一第一岛组件100a内相邻的两个第一电极240；第二连接线402为扫描线并用于连接驱动电路结构220和第二像 素电路结构230，或者，用于连接相邻的第一像素电路结构210和第二像素电路结构230；第三连接线403为电源信号线并用于连接第一像素电路结构210和第二像素电路结构230；其中，连接于相邻两个电路岛120之间的第二连接线402与第一连接线401沿显示面板的厚度方向Z层叠设置；和/或，连接于相邻两个电路岛120之间的第二连接线402与第三连接线403沿显示面板的厚度方向Z层叠设置。
在这些可选的实施例中，第一连接线401连接沿第一方向X相邻的第一电极240，使得同一第二像素电路结构230能够驱动通过第一连接线401连接的两个以上第一电极240。例如，第一连接线401的个数为两个，两个第一连接线401分设于第一电路岛121的两侧，两个第一连接线401分别连接第二电路岛122上的第一电极240和第一电路岛121上的第一电极240，使得三个第一电极240相互连接，第二像素电路结构230可以同时驱动三个第一电极240。
可选的，图8可以为图7中左起第一个第二电路岛122和左起第二个第一电路岛121之间的其中一组相互层叠设置的信号线400的横截面示意图。例如，图7中左起第一个第二电路岛122和左起第二个第一电路岛121之间具有两组相互层叠设置的信号线400，图8为两组层叠设置的信号线400中上数的第一组的横截面结构示意图。
第二连接线402为扫描线，第二连接线402可以位于第一电路岛121和第二电路岛122之间以连接移位寄存单元221和第二像素电路结构230，和/或，第二连接线402也可以位于第二电路岛122和像素岛110之间以连接第一像素电路结构210和第二像素电路结构230。当第二连接线402位于第一电路岛121和第二电路岛122之间时，第二连接线402与同样位于第一电路岛121和第二电路岛122之间的第一连接线401可能用于连接相同的电路岛120，第二连接线402和第一连接线401可以沿厚度方向Z层叠设置，以减小金属布线的分布面积，保证显示面板的透光率和拉伸率。
第三连接线403为电源信号线并连接第一像素电路结构210和第二像素电路结构230，此时第三连接线403可以位于第二电路岛122和像素岛110之间，当第二连接线402同样位于第二电路岛122和像素岛110之间以连接第一像素电路结构210和第二像素电路结构230时，第三连接线403可以与第二连接线402沿厚度方向Z层叠设置，以减小金属布线的分布面积，保证显示面板的透光率和拉伸率。
在一些可选的实施例中，如上所述，显示面板还包括第二电极250，第二电极250设置于第一电路岛121和第二电路岛122，信号线400还包括第四连接线404，第四连接线404用于连接相邻两个电路岛120上的第二电极250，第四连接线404与第二连接线402沿厚度方向第二电极250层叠设置。
在这些可选的实施例中，第一电路岛121和第二电路岛122上均设置有第二电极250，第二电极250和第一电极240相互作用以驱动第一个发光结构发光。第四连接线404可以为两条，两条第四连接线404可以分设于第一电路岛121的两侧，使得第四连接线404可以连接第一电路岛121上的第二电极250和第二电路岛122上的第二电极250。当第二连接线402位于第一电路岛121和第二电路岛122之间以连接移位寄存单元221和第二像素电路结构230时，第四连接线404和第二连接线402可以沿厚度方向Z层叠设置，以减小金属布线的分布面积，保证显示面板的透光率和拉伸率。
第四连接线404可以与第二电极250同层设置。或者，第四连接线404可以与第一电极240层同层设置。
可选的，第二连接线402包括第一扫描线4021和第二扫描线4022，第一扫描线4021和第二扫描线4022沿第二方向Y间隔设置，第一扫描线4021和第四连接线404沿厚度方向Z层叠设置，第二扫描线4022和第一连接线401沿厚度方向Z层叠设置，或者，第二扫描线4022和第三连接线403沿厚度方向Z层叠设置。
当第二连接线402包括第一扫描线4021和第二扫描线4022时，第一扫描线4021 和第二扫描线4022可以均连接移位寄存单元221，第一扫描线4021和第二扫描线4022中的一者作为输入信号连接于移位寄存单元221，另一者作为输出连接于移位寄存单元221。本申请实施例以第一扫描线4021输入信号连接于移位寄存单元221，第二扫描线4022作为输出连接于移位寄存单元221为例进行举例说明。
当第一扫描线4021和第二扫描线4022连接于第一电路岛121的同侧时，第一电路岛121的这一侧也可能设置有第一连接线401和第四连接线404，第一扫描线4021和第二扫描线4022中的一者与第一连接线401沿厚度方向Z层叠设置，另一者与第四连接线404沿厚度方向Z层叠设置。
当第一扫描线4021和第二扫描线4022连接于设置有第二像素电路结构230的第二电路岛122和像素电路岛之间时，第二电路岛122的这一侧也可能设置有第四连接线404和第三连接线403，第一扫描线4021和第二扫描线4022中的一者与第三连接线403沿厚度方向Z层叠设置，另一者与第四连接线404沿厚度方向Z层叠设置。
可选的，第四连接线404连接第二电极250，第四连接线404可以用于传输负电压信号(VSS)。第一区AA可以设置有负电压信号线，可以直接将第一区AA的负电压信号线引至第二区NA，以减少第二区NA内信号线400的布置数量。例如：信号线400包括连接像素岛110并沿第二方向延伸的第七连接线40a，至少一条第四连接线404连接第二电路岛122和像素岛110且在像素岛110连接第七连接线40a。
在这些可选的实施例中，信号线400包括位于第一区AA并连接像素岛110的第七连接线40a，第七连接线40a沿第二方向Y延伸，用于连接第二电极250的第四连接线404在像素岛110上连接第七连接线40a，从而将第一区AA的负电压信号线引入第二区NA的第二电极250。
可选的，信号线400包括连接设置有第二像素电路结构230的第二电路岛122的数据线(Data)和第六连接线406，数据线和第六连接线406沿第一方向X并排设置，且第六连接线406和第一扫描线4021相互电连接。
在这些可选的实施例中，第六连接线406可以连接于上一行电路岛的扫描输出线(例如上一行第一岛组件100a的第二扫描线4022)，上一行电路岛120的扫描输出线作为下一行电路岛120的扫描输入线。第二扫描线4022可以通过第六连接线406连接下一行的第一扫描线4021。数据线用于向第二电路岛122上的第二像素电路结构230输入数据信号。
在一些可选的实施例中，信号线400还包括时钟信号线和第五连接线405，时钟信号线连接于位于第一电路岛121背离第一区AA的第二电路岛122上；第五连接线405连接时钟信号线和驱动电路结构220，连接于相邻两个电路岛之间的第五连接线405与第一连接线401沿厚度方向Z层叠设置；和/或，连接于相邻两个电路岛120之间的第五连接线405与第四连接线404沿厚度方向Z层叠设置。
可选的，第五连接线405可以用于连接时钟信号线和驱动电路结构220，即第五连接线405可用于连接时钟信号线和移位寄存单元221，那么第五连接线405连接于第一电路岛121和第二电路岛122之间，第五连接线405与第一连接线401、第四连接线404可能连接于相同的两个电路岛120之间，连接于相邻两个电路岛120之间的第五连接线405与第四连接线404、和/或第五连接线405和第一连接线401沿厚度方向Z层叠设置，以减小金属布线的分布面积，保证显示面板的透光率和拉伸率。
可选的，时钟信号线可以包括第一时钟信号线CLK1和第二时钟信号线CLK2，第五连接线405可以包括第一子连接线4051和第二子连接线4052，第一子连接线4051连接第一时钟信号线CLK1和驱动电路结构220，第二子连接线4052连接第二时钟信号线CLK2和驱动电路结构220。那么第一子连接线4051和第二子连接线4052中的一者可以与第四连接线404沿厚度方向层叠设置，另一者可以与第一连接线401沿厚度方向 层叠设置。
可选的，当第二区NA不用于显示，且第一岛组件100a包括两个第二电路岛122和第一电路岛121，两个第二电路岛122分设于第一电路岛121的两侧时，第二区NA的信号线400可以包括第一时钟信号线CLK1、第二时钟信号线CLK2、第一扫描线Sn和第二扫描线Sn+1，第一时钟信号线CLK1和第二时钟信号线CLK2可以连接于其中一个第二电路岛122并延伸至第二电路岛122和第一电路岛121之间以连接移位寄存单元221，第一扫描线Sn和第二扫描线Sn+1可以连接于另一第二电路岛122并延伸至第二电路岛122和第一电路岛121之间以连接移位寄存单元221，因此相邻的两个电路岛120之间设置有两条并排设置的连接线，即其中一个第二电路岛122和第一电路岛121之间并排设置有部分的第一时钟信号线CLK1、第二时钟信号线CLK2，另外一个第二电路岛122和第一电路岛121之间并排设置有部分的第一扫描线Sn、第二扫描线Sn+1。
当第二区NA用于显示，且第一岛组件100a包括两个第二电路岛122和第一电路岛121，两个第二电路岛122分设于第一电路岛121的两侧时，第一电路岛121和两个第二电路岛122上设置有第二发光单元，第二发光单元包括第一电极240和第二电极250，且同一第二像素电路结构230驱动同一第一岛组件100a内的三个第二发光单元。这就需要连接线连接相邻两个电路岛120的第一电极240和第二电极250，因此在相邻的两个电路岛120之间增设了第一连接线401和第四连接线404。第一连接线401用于连接相邻电路岛120的第一电极240，第四连接线404用于连接相邻两个电路岛120的第二电极250。由于增设了第一连接线401和第四连接线404，因此第一连接线401可以与原有相邻两个电路岛120之间两个连接线中的一者(例如第一扫描线Sn或第一时钟信号线CLK1)相互层叠设置，第四连接线404可以与原有相邻两个电路岛120之间两个连接线中的另一者(例如第二扫描线Sn+1或第二时钟信号线CLK2)相互层叠设置。
在一些可选的实施例中，信号线400还包括位于第一区AA的冗余走线407、用于连接相邻第一像素电路结构210的信号走线408，至少部分冗余走线407和信号走线408沿厚度方向层叠设置。
在这些实施例中，在第一区AA设置有冗余走线407，令冗余走线407和信号走线408沿厚度方向层叠设置，使得第一区AA和第二区NA的信号线400布置方式趋于相同，能够改善第一区AA和第二区NA之间的拉伸率差异。
可选的，相邻两个像素岛110之间的冗余走线407和信号走线408的数量之和与相邻两个电路岛120之间的第一信号线410的数量相同。进一步改善第一区AA和第二区NA之间的拉伸率差异。
可选的，相邻两个像素岛110之间的冗余走线407和第一连接线401、第二连接线402、第三连接线403和第四连接线404中的至少一者同层同材料设置。例如，当第一连接线401和第一扫描线Sn层叠设置时，冗余走线407可以与第一连接线401、第一扫描线Sn中的一者同层同材料设置，信号走线408和另一者同层同材料设置，以简化显示面板的制备工艺。
在一些可选的实施例中，第一信号线410包括第一子线411，第一子线411由第一电路岛121在第二方向Y的两侧伸出；第二信号线420包括第二子线421，第二子线421由第二电路岛122在第二方向Y的两侧伸出，其中，各第一电路岛121对应的第一子线411的数量和各第二电路岛122对应的第二子线421的数量相同。第一电路岛121对应的第一子线411是指由该第一电路岛121在第二方向Y的两侧伸出的第一子线411。第二电路岛122对应的第二子线421是指由该第二电路岛122在第二方向Y两侧伸出的第二子线421。
在这些可选的实施例中，由第一电路岛121和第二电路岛122同侧伸出的第一子线 411和第二子线421的数量相同，使得第一电路岛121和第二电路岛122在第二方向Y上的拉伸率趋于一致，能够很好地改善显示面板第二区NA在第二方向Y上的拉伸性能。
可选的，第一电路岛121在第二方向Y的两侧均伸出有第一子线411，且沿第二方向Y对应设置的第一子线411可以用于传输相同的信号，第一子线411例如包括高电平电源线(VGH)、低电平电源线(VGL)中的至少一者。
可选的，第二电路岛122在第二方向Y的两侧均伸出有第二子线421，且沿第二方向Y对应设置的第二子线421用于传输相同的信号，第二子线421例如包括第一时钟信号线(CLK1)、第二时钟信号线(CLK2)、第一电源信号线(VSS)、扫描线(Sn)、数据线(data)和第六连接线(Vin)中的至少一者。第二子线421作为扫描线可以连接相邻两行的移位寄存单元221，或者第二子线421作为扫描线可以用于连接相邻两行沿第二方向Y延伸的扫描线，以使得第i行的像素驱动单元被驱动时，第i+1行的像素驱动单元可以被复位。
可选的，当第二区NA用于显示时，第二子线421可以包括第一时钟信号线、第二时钟信号线、扫描线、数据线和第六连接线中的至少一者。当第二区NA不用于显示时，第二子线421可以包括第一时钟信号线(CLK1)、第二时钟信号线(CLK2)、第一电源信号线(VSS)、扫描线(Sn)中的至少一者。
可选的，驱动信号线430包括第三子线431，第三子线431由像素岛110在第二方向Y的两侧伸出，各像素岛110对应的第三子线431的数量和各第一电路岛121内第一子线411的数量相同。各像素岛110对应的第三子线431为由该像素岛110伸出的第三子线431。
在这些可选的实施例中，单个像素岛110的第三子线431的数量和单个第一电路岛121的第一子线411的数量相同，使得第一区AA和第二区NA在第二方向Y上的拉伸率趋于一致，能够很好地改善显示面板整体在第二方向Y上的拉伸性能。
可选的，第三子线431可以包括数据线、第一电源信号线、第二电源信号线等。
在一些可选的实施例中，第一信号线410包括第四子线412，第四子线412由第一电路岛121在第一方向X的两侧伸出；第二信号线420包括第五子线422，第五子线422由第二电路岛122在第一方向X的两侧伸出，其中，各第一电路岛121对应的第四子线412的数量和各第二电路岛122对应的第五子线422的数量相同。
在这些可选的实施例中，单个第一电路岛121上伸出的第四子线412的数量和单个第二电路岛122上伸出的第五子线422的数量相同，使得第一电路岛121和第二电路岛122在第一方向X上的拉伸率趋于一致，能够很好地改善显示面板第二区NA在第一方向X上的拉伸性能。
可选的，第四子线412可以包括上述的第一连接线401、第二连接线402、第三连接线403、第四连接线404和第五连接线405中的至少一者，例如，用于连接第一电路岛121的第一连接线401、第二连接线402、第三连接线403、第四连接线404和第五连接线405中的至少一者可以为第四子线412。
第五子线422可以包括上述的第一连接线401、第二连接线402、第三连接线403、第四连接线404和第五连接线405中的至少一者。
可选的，至少部分第四子线412和至少部分第五子线422相互连接，使得第一电路岛121的移位寄存单元221可以通过第四子线412、第五子线422连接连接部222，使得第二信号线420可以连接于移位寄存单元221。
在一些可选的实施例中，驱动信号线430包括第六子线432，第六子线432由像素岛110在第一方向X的两侧伸出，各像素岛110对应的第六子线432的数量和各第一电路岛121对应的第四子线412的数量相同。
在这些可选的实施例中，单个像素岛110上伸出的第六子线432的数量和单个第一电路岛121伸出的第四子线412的数量一致，使得第一区AA和第二区NA在第一方向X上的延伸率趋于一直，能够提高显示面板整体的拉伸性能。
可选的，第六子线432可以包括上述的信号走线408和冗余走线407。
可选的，至少部分第四子线412和至少部分第六子线432相互连接，使得移位寄存单元221能够通过第四子线412、第六子线432连接第一像素电路结构210，从而向第一像素电路结构210传输驱动信号。
可选的，至少部分第五子线422和至少部分第六子线432相互连接，使得第一像素电路结构210能够通过第六子线432、第五子线422连接第二电路岛122的连接部222。
可选的，第一子线411、第二子线421、第三子线431、第四子线412、第五子线422和第六子线432的不同之处在于其布置位置不同，其中的至少两者可以用于传输相同的信号，至少两者可以位于同一导电层并一体成型，或者至少两者的延伸方向可以相同或不同。
在一些可选的实施例中，同一第一电路岛121对应的第一子线411的数量和第三子线431的数量相同。使得移位寄存单元221在不同方向的受力更加平衡。
在一些可选的实施例中，同一第二电路岛122对应的第二子线421的数量和第五子线422的数量相同。使得连接部222在不同方向的受力更加平衡。
在一些可选的实施例中，同一像素岛110对应的第三子线431的数量和第六子线432的数量相同。使得第一像素电路结构210在不同方向的受力更加平衡。在一些实施例中，第二子线421包括第一时钟信号线、第二时钟信号线、第一扫描线和第一负电压信号线(即第一电源信号线)，第五子线422可以用于连接第一时钟信号线和移位寄存单元，或者第五子线422可以用于连接第二时钟信号线和移位寄存单元221，或者，第五子线422用于连接移位寄存单元221和第一扫描线。
在一些实施例中，驱动信号线430包括数据线、第二扫描线、第二负电压信号线、第一正电压信号线(即第二电源线)。第六子线432也可以通过第四子线412连接移位寄存单元221和第一像素电路结构210。第六子线432可以连接第一扫描线和第二扫描线，或者第六子线432也可以连接第一负电压信号线和第二负电压信号线。
在一些可选的实施例中，如图1和图2所示，第二区NA包括沿第一方向X延伸的第一子区NA1和沿第二方向Y延伸的第二子区NA2，第一岛组件100a位于第二子区NA2，显示面板还包括绑定引脚500，绑定引脚500位于第一子区NA1。
在这些可选的实施例中，第二区NA分为第一子区NA1和第二子区NA2，第一岛组件100a位于第二子区NA2，绑定引脚500位于第一子区NA1，使得第一岛组件100a和绑定引脚500的布置互不影响。在第一子区NA1内可以为绑定引脚500设置连续的金属层或其他材料层。
可选的，拉伸部300位于第二子区NA2，且拉伸部300沿第一方向X贯穿第二子区NA2，电路岛120设置于相邻的拉伸部300之间。
可选的，两个第二子区NA2分设于第一区AA在第一方向X的两侧，各第二子区NA2内均设置有第一岛组件100a，即各第二子区NA2内均设置有移位寄存单元221，以便于从第一区AA在第一方向X的两侧同时驱动第一区AA内的发光单元，能够改善驱动迟滞性，提高显示面板的显示效果。
可选的，绑定引脚500可以用于绑定连接扫描驱动器、显示驱动器等。可选的，多个绑定引脚500在第一子区NA1内沿第二方向Y间隔分布，以便于通过绑定引脚500连接多个驱动器等部件。
可选的，两个第一子区NA1分设于第一区AA在第二方向Y的两侧，各第一子区NA1内均设置有绑定引脚500，以便于在第一子区NA1内布置更多的绑定引脚500。
可选的，第一子区NA1在第一方向X上的延伸尺寸小于第二子区NA2在第二方向Y上的延伸尺寸。即第一方向X可以为显示面板的宽度方向，第二方向Y为显示面板的长度方向。第一岛组件100a在第二子区NA2内沿长度方向分布，能够提高显示面板在其长度方向上的拉伸性能。
请参阅图11，在其他实施例中，绑定引脚500也可以设置于第二子区NA2，第一岛组件100a设置于第一子区NA1。此时，拉伸部300可以位于第一子区NA1，以提高第一子区NA1的拉伸性能。
在一些可选的实施例中，如图1至图10所示，信号线400还包括驱动信号线430，驱动信号线430连接于第一像素电路结构210，且驱动信号线430沿弯折路径延伸成型。
在这些可选的实施例中，驱动信号线430沿弯折路径延伸成型，能够提高驱动信号线430的拉伸性能，改善驱动信号线430在拉伸显示面板过程中易损坏的问题。
可选的，驱动信号线430可以为数据线(Data)、扫描线(Scan)、第二电源线(VSS)等。第二电源线可以连接于第一区AA发光单元的阳极。
在一些可选的实施例中，像素岛110、第一电路岛121和第二电路岛122中的至少两者的尺寸相同。使得显示面板不同位置的拉伸率趋于一致，能够很好地改善显示面板的拉伸性能。
例如，第一电路岛121和第二电路岛122的尺寸相同，使得沿第二方向Y相邻的两个第一电路岛121之间的间隙与沿第二方向Y相邻的两个第二电路岛122之间的间隙相同，进而使得第二区NA内第一电路岛121所在位置和第二电路岛122所在位置的拉伸率趋于一致，改善第二区NA的拉伸性能。
或者，像素岛110、第一电路岛121和第二电路岛122三者的尺寸均相同，使得第二区NA的拉伸率与第一区A的拉伸率趋于一致，能够改善显示面板整体的拉伸性能。
如图3所示，第二电路岛122可以为一个，第二电路岛122用于设置连接部222，第一电路岛121用于设置移位寄存单元221，本申请通过将第二区NA内的连接部222和移位寄存单元221分设在不同的电路岛120，能够增加移位寄存单元221与连接部222之间的距离，保证移位寄存单元221与连接部222之间的绝缘性能。
在另一些可选的实施例中，如图5所示，第二电路岛122的个数为两个以上。例如，第二电路岛122的个数为两个，其中一个第二电路岛122的第二信号线420包括时钟信号线，例如，其中一个第二电路岛122的第二信号线420包括第一时钟信号线CLK1和第二时钟信号线(CLK2)，另一个第二电路岛122的第二信号线420包括扫描线和第一电源信号线(VDD)。如图2所示，两个第二电路岛122可以分设于第一电路岛121在第一方向X的两侧，或者两个第二电路岛122可以位于第一电路岛121在第一方向X的同侧。
可选的，在图5所示的显示面板中，两个第二电路岛122分设于第一电路岛121在第一方向X的两侧。远离第一区AA的第二电路岛122上设置有第一时钟信号线CLK1和第二时钟信号线CLK2，第一时钟信号线CLK1和第二时钟信号线CLK2延伸至第二电路岛122和第一电路岛121之间以连接第一电路岛121的移位寄存单元221。靠近第一区AA的第二电路岛122上设置有扫描线和第一电源信号线VDD，扫描线包括第一扫描线Sn和第二扫描线Sn+1，第一扫描线Sn作为输入延伸至第二电路岛122和第一电路岛121之间以连接移位寄存单元221，第二扫描线Sn+1作为输出延伸至第二电路岛122和第一电路岛121之间以连接移位寄存单元221。可选的，第一电路岛121上还可以连接有高电平电源线VGH和低电平电源线VGL，高电平电源线VGH和低电平电源线VGL由第一电路岛121在第二方向Y上的两侧伸出。可选的，上述的第一信号线410包括上述与移位寄存单元221连接的信号线400，上述的第二信号线420包括连接于第二电路岛122的信号线400，本申请以设置位置和连接对象将信号线400分为第一 信号线410和第二信号线420，部分第一信号线410和第二信号线420可以用于传输相同的信号。
或者，如图12所示，第二电路岛122的个数为三个以上，例如第二电路岛122的个数为三个，第二信号线420包括时钟信号线、虚拟信号线(dum)、扫描线和第一电源信号线，时钟信号线、虚拟信号线、扫描线和第一电源信号线设置于三个第二电路岛122上。时钟信号线可以包括第一时钟信号线(CLK1)和第二时钟信号线(CLK2)，虚拟信号线也可以包括第一虚拟信号线和第二虚拟信号线，例如，第一时钟信号线和第一虚拟信号线设置于同一第二电路岛122，第二虚拟信号线和第二时钟信号线设置于另一第二电路岛122，扫描线和第一电源信号线设置于还以第二电路岛122。
请继续参阅图12，可选的，第二电路岛122的个数为三个，第一电路岛121的个数为一个，两个第二电路岛122位于第一电路岛121远离第一区AA的一侧，一个第二电路岛122位于第一电路岛121靠近第一区AA的一侧。在第一电路岛121远离第一区AA的两个第二电路岛122中，其各自分别连接有一个时钟信号线和一个虚拟信号线，例如左起第一个第二电路岛122连接有第一时钟信号线CLK1和一虚拟信号线dum，左起第二个第二电路岛122连接有第二时钟信号线CLK2和一虚拟信号线dum，第一时钟信号线CLK1和第二时钟信号线CLK2延伸至两个第二电路岛122、及第二电路岛122和第一电路岛121以连接移位寄存单元221。靠近第一区AA的第二电路岛122上设置有扫描线和第一电源信号线VDD，扫描线和第一电源信号线VDD的设置方式如图3所示，在此不再赘述。第一电路岛121上还可以连接有高电平电源线VGH和低电平电源线VGL，其设置方式如图3，在此不再赘述。
或者，如图13所示，第二电路岛122的个数还可以为四个，各第二电路岛122分别包括两条第二信号线，虚拟信号线的数量为四个，各虚拟信号线分别设置于各第二电路岛122，第一时钟信号线、第二时钟信号线、扫描线和第一电源信号线分别设置于各第二电路岛122。
如图13所示，第二电路岛122的个数为四个，四个第二电路岛122平均分设于第一电路岛121的两侧，即第一电路岛121的一侧设置有两个第二电路岛122。位于第一电路岛121远离第一区AA一侧的两个第二电路岛122及其上连接的信号线400的设置方式如图12所示，在此不再赘述。在靠近第一区AA的两个第二电路岛122中，其中一者连接有扫描线和虚拟信号线dum，另一者连接有第一电源信号线VDD和虚拟信号线dum，扫描线和延伸至两个第二电路岛122、及第二电路岛122和第一电路岛121之间以连接移位寄存单元221。第一电路岛121上还可以连接有高电平电源线VGH和低电平电源线VGL，其设置方式如图3，在此不再赘述。
可选的，在上述任一实施例中，如图13所示，信号线400上还可以设置有辅助线409，辅助线409和信号线400交叉并位于电路岛120上，辅助线409用于增加信号线400和电路岛120的接触面积，提高信号线400位置的稳定性。
在上述实施例中，通过增设虚拟信号线125，一方面可以通过合理布置虚拟信号线的位置，使得虚拟信号线靠近第二区NA背离第一区AA的一侧布置，可以使得至少部分第二信号线420(例如第一电源信号线)远离第二区NA的边缘设置，从而能够改善切割产生的静电对第二信号线420的影响；另外通过合理设置虚拟信号线的数量，还能够使得第二电路岛122的第二子线421、第五子线422与第一电路岛121的第一子线411、第四子线412的数量趋于一致，改善显示面板的拉伸性能。
可选的，信号线400的延伸路径设置方式有多种，例如信号线400不为直线。例如，至少部分信号线400呈弧形。例如信号线400包括圆弧分段，信号线400包括半圆弧分段。可选的，同一功能岛100的同侧伸出有两条信号线400。可选的，连接于同一功能岛100、且由功能岛100同侧伸出的两条信号线400的半圆弧分段对称设置。可选 的，当信号线400包括第一信号线410，第一电路岛121的一侧设置有并排分布的两条第一信号线410时，两条第一信号线410的弧形开口相对设置。弧形开口为半圆形第一信号线410弯折形成的开口。
可选的，第一区AA的两侧均设置有第二区NA，且各第二区NA内均设置有驱动电路结构220，实现显示面板的双侧驱动，能够改善压降的问题，提升显示面板的显示效果。
本申请第一方面的实施例还提供另一显示面板，具有第一区AA和环绕至少部分第一区AA设置的第二区NA，第一区AA和第二区NA均包括岛区和拉伸区，多个岛区在第一区AA和第二区NA阵列分布，拉伸区位于相邻两行和/或相邻两列岛区之间，显示面板包括功能岛100、拉伸部300和信号线400，各功能岛100位于各岛区且功能岛上设置有功能件200，多个功能岛100包括位于第一区AA的多个像素岛110和位于第二区NA的多个电路岛120，功能件200包括设置于像素岛110的第一像素电路结构210和设置于电路岛120的驱动电路结构220；拉伸部300设置于拉伸区并连接于相邻的两个功能岛100之间，且在第二区NA，至少部分拉伸区沿第一区AA至第二区NA的方向贯穿第二区NA设置；信号线400设置于拉伸部300并用于连接相邻的两个功能岛100的功能件200。多个电路岛120包括第一岛组件100a，第一岛组件100a包括第一电路岛121和第二电路岛122，驱动电路结构220包括设置于第一电路岛121的移位寄存单元221，第二电路岛122和第一电路岛121并排设置，移位寄存单元221通过信号线400与第一像素电路结构210连接，以向第一像素电路结构210提供扫描信号。同一第一岛组件100a内的第一电路岛121和第二电路岛122沿第一方向X间隔设置，多个第一岛组件100a在第二区NA内沿第二方向Y间隔设置。功能件200还包括设置于第一电路岛121和第二电路岛122至少一者上的第二像素电路结构230和第二发光单元，第二像素电路结构230用于驱动第二发光单元发光。第一岛组件100a的第一电路岛121和第二电路岛122中靠近第一区AA的电路岛120上设置有第二像素电路结构230和第二发光单元，令部分靠近第一区AA的第二区NA能够显示，进而扩大显示面板的显示区域面积，实现窄边框的目的。
可选的，该显示面板的设置方式如上述任一实施例的显示面板所述，在此不再赘述。
本申请第二方面的实施例还提供一种显示装置，包括上述任一第一方面实施例的显示面板。由于本申请第二方面实施例提供的显示装置包括上述第一方面任一实施例的显示面板，因此本申请第二方面实施例提供的显示装置具有上述第一方面任一实施例的显示面板具有的有益效果，在此不再赘述。
本申请实施例中的显示装置包括但不限于手机、个人数字助理(Personal Digital Assistant，简称：PDA)、平板电脑、电子书、电视机、门禁、智能固定电话、控制台等具有显示功能的设备。
虽然已经参考优选实施例对本申请进行了描述，但在不脱离本申请的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本申请并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (36)

  1. 一种显示面板，其中，所述显示面板具有第一区和位于所述第一区周边的第二区，所述第一区和所述第二区均包括岛区和拉伸区，多个所述岛区在所述第一区和所述第二区阵列分布，所述拉伸区位于相邻两行和/或相邻两列所述岛区之间，所述显示面板包括：
    多个功能岛，各所述功能岛位于各所述岛区且所述功能岛上设置有功能件，多个所述功能岛包括位于所述第一区的多个像素岛和位于所述第二区的多个电路岛，所述功能件包括设置于所述像素岛的第一像素电路结构、第一发光单元和设置于所述电路岛的驱动电路结构，所述第一像素电路结构用于驱动所述第一发光单元发光；
    拉伸部，设置于所述拉伸区并连接于相邻的两个所述功能岛之间，且在所述第二区，至少部分所述拉伸区沿所述第一区至所述第二区的方向贯穿所述第二区设置；
    信号线，设置于所述拉伸部并用于连接相邻的两个所述功能岛的所述功能件。
  2. 根据权利要求1所述的显示面板，其中，多个所述电路岛包括第一岛组件，所述第一岛组件包括：
    第一电路岛，所述驱动电路结构包括设置于所述第一电路岛的移位寄存单元；
    第二电路岛，和所述第一电路岛并排设置，所述驱动电路结构包括设置于所述第二电路岛的连接部；
    所述信号线包括连接所述移位寄存单元的第一信号线、连接所述连接部的第二信号线，多个所述移位寄存单元通过至少部分所述第二信号线、所述连接部和所述第一信号线与所述第一像素电路结构连接，以向所述第一像素电路结构提供扫描信号。
  3. 根据权利要求2所述的显示面板，其中，多个所述电路岛和多个所述像素岛沿第一方向和第二方向成行成列排布，同一行的所述电路岛和所述像素岛中，所述电路岛上的所述移位寄存单元用于驱动与其同行的所述像素岛的所述第一像素电路结构。
  4. 根据权利要求2所述的显示面板，其中，所述第一岛组件的所述第一电路岛和所述第二电路岛沿所述第一方向并排设置，且多个所述第一岛组件沿所述第二方向间隔设置。
  5. 根据权利要求4所述的显示面板，其中，沿所述第二方向间隔设置的多个所述第一岛组件的所述第一电路岛沿所述第二方向对齐设置；
    和/或，沿所述第二方向间隔设置的多个所述第一岛组件的所述第二电路岛沿所述第二方向对齐设置。
  6. 根据权利要求4所述的显示面板，其中，所述功能件还包括设置于所述第一电路岛和所述第二电路岛至少一者上的第二像素电路结构和与第二像素电路结构电连接的第二发光单元，所述第二像素电路结构用于驱动所述第二发光单元发光。
  7. 根据权利要求6所述的显示面板，其中，所述第一岛组件的所述第一电路岛和所述第二电路岛中靠近所述第一区的所述电路岛上设有所述第二像素电路结构和所述第二发光单元。
  8. 根据权利要求6所述的显示面板，其中，所述第一岛组件包括一个所述第一电路岛和两个所述第二电路岛，两个所述第二电路岛分设于所述第一电路岛的两侧，所述第二像素电路结构设置于位于所述第一电路岛靠近所述第一区的所述第二电路岛上。
  9. 根据权利要求6所述的显示面板，其中，同一所述第一岛组件中的所述第一电路岛和所述第二电路岛上均设置有所述第二发光单元，且同一所述第一岛组件中的所述第一电路岛和所述第二电路岛中的一者上设置有所述第二像素电路结构，所述第二像素电路结构用于驱动同一所述第一岛组件中的多个所述第二发光单元发光。
  10. 根据权利要求8所述的显示面板，其中，至少一个所述第二电路岛上设置有虚拟像素电路，其中，两个所述第二电路岛上均设置有所述虚拟像素电路，且其中一个所述第二电路岛上的所述第二像素电路结构和所述虚拟像素电路的数量之和与另一所述第二电路岛上的所述虚拟像素电路数量之和相等。
  11. 根据权利要求9所述的显示面板，其中，所述第一发光单元包括第一电极，所述信号线包括：
    第一连接线，用于连接同一所述第一岛组件内相邻的两个所述第一电极；
    第二连接线，为扫描线并用于连接所述驱动电路结构和所述第二像素电路结构，或者，用于连接相邻的第一像素电路结构和第二像素电路结构；
    第三连接线，为电源信号线并用于连接所述第一像素电路结构和所述第二像素电路结构；
    其中，连接于相邻两个所述电路岛之间的第二连接线与第一连接线沿所述显示面板的厚度方向层叠设置；和/或，连接于相邻两个所述电路岛之间的第二连接线与第三连接线沿所述显示面板的厚度方向层叠设置。
  12. 根据权利要求11所述的显示面板，其中，所述第二发光单元包括第二电极，所述信号线还包括第四连接线，所述第四连接线用于连接相邻两个所述电路岛上的所述第二电极，所述第四连接线与所述第二连接线沿所述厚度方向层叠设置。
  13. 根据权利要求12所述的显示面板，其中，所述第四连接线和所述第一电极同层并间隔绝缘设置，所述第四连接线和所述第二电极过孔连接。
  14. 根据权利要求12所述的显示面板，其中，所述第二连接线包括第一扫描线和第二扫描线，所述第一扫描线和所述第二扫描线沿所述第二方向间隔设置，所述第一扫描线和所述第四连接线沿所述厚度方向层叠设置，所述第二扫描线和所述第一连接线沿所述厚度方向层叠设置，或者，所述第二扫描线和所述第三连接线沿所述厚度方向层叠设置。
  15. 根据权利要求14所述的显示面板，其中，所述信号线包括连接所述像素岛并沿所述第二方向延伸的第七连接线，至少一条所述第四连接线连接所述第二电路岛和所述像素岛，且在所述像素岛连接所述第七连接线，
    和/或，所述信号线包括连接设置有所述第二像素电路结构的第二电路岛的数据线和第六连接线，所述数据线和所述第六连接线沿所述第一方向并排设置，且所述第六连接线和所述第一扫描线相互电连接。
  16. 根据权利要求12所述的显示面板，其中，所述信号线包括：
    时钟信号线，所述时钟信号线连接于位于所述第一电路结构背离所述第一区的所述第二电路岛上；
    第五连接线，所述第五连接线连接所述时钟信号线和所述驱动电路结构，连接于相邻两个所述电路岛之间的第五连接线与第一连接线沿所述厚度方向层叠设置；和/或，连接于相邻两个所述电路岛之间的第五连接线与第四连接线沿所述厚度方向层叠设置。
  17. 根据权利要求16所述的显示面板，其中，所述时钟信号线包括第一时钟信号线和第二时钟信号线，所述第五连接线包括连接所述第一时钟信号线的第一子连接线和连接所述第二时钟信号线的第二子连接线，所述第一子连接线和所述第二子连接线沿所述第二方向间隔设置，所述第一子连接线和所述第四连接线沿所述厚度方向层叠设置，所述第二子连接线和所述第一连接线沿所述厚度方向层叠设置。
  18. 根据权利要求12所述的显示面板，其中，所述信号线还包括位于所述第一区的冗余走线、用于连接相邻所述第一像素电路结构的信号走线，至少部分所述冗余走线和所述信号走线沿所述厚度方向层叠设置。
  19. 根据权利要求18所述的显示面板，其中，相邻两个所述像素岛之间的所述冗余 走线和所述信号走线的数量之和与相邻两个所述电路岛之间的所述信号线的数量相同；
    和/或，相邻两个所述像素岛之间的所述冗余走线和所述第一连接线、所述第二连接线、所述第三连接线和所述第四连接线中的至少一者同层同材料设置。
  20. 根据权利要求3所述的显示面板，其中，
    所述第一信号线包括第一子线，所述第一子线由所述第一电路岛在所述第二方向的两侧伸出；
    所述第二信号线包括第二子线，所述第二子线由所述第二电路岛在所述第二方向的两侧伸出，
    其中，各所述第一电路岛对应的所述第一子线的数量和各所述第二电路岛对应的所述第二子线的数量相同。
  21. 根据权利要求20所述的显示面板，其中，所述信号线还包括连接所述第一像素电路结构的驱动信号线，所述驱动信号线包括第三子线，所述第三子线由所述像素岛在所述第二方向的两侧伸出，各所述像素岛对应的所述第三子线的数量和各所述第一电路岛对应的所述第一子线的数量相同。
  22. 根据权利要求21所述的显示面板，其中，所述第一信号线包括第四子线，所述第四子线由所述第一电路岛在所述第一方向的两侧伸出；
    所述第二信号线包括第五子线，所述第五子线由所述第二电路岛在所述第一方向的两侧伸出，
    其中，各所述第一电路岛对应的所述第四子线的数量和各所述第二电路岛对应的所述第五子线的数量相同。
  23. 根据权利要求22所述的显示面板，其中，所述驱动信号线包括第六子线，所述第六子线由所述像素岛在所述第一方向的两侧伸出，各所述像素岛对应的所述第六子线的数量和各所述第一电路岛对应的所述第四子线的数量相同。
  24. 根据权利要求23所述的显示面板，其中，至少部分所述第三子线和至少部分所述第六子线相互连接，以使所述第一像素电路结构能够通过所述第六子线、所述第三子线和所述移位寄存单元相互电连接；
    和/或，至少部分所述第四子线和至少或部分所述第六子线相互连接，以使所述第一像素电路结构能够通过所述第六子线、所述第四子线和所述连接部相互电连接。
  25. 根据权利要求4所述的显示面板，其中，所述第二电路岛的个数为一个，所述第二电路岛设置于所述第一电路岛朝向或背离所述第一区的一侧；
    所述第二信号线包括时钟信号线、扫描线和第一电源信号线中的至少一者。
  26. 根据权利要求2所述的显示面板，其中，所述第二区包括沿第一方向延伸的第一子区和沿第二方向延伸的第二子区，所述第一岛组件位于所述第二子区，所述显示面板还包括绑定引脚，所述绑定引脚位于所述第一子区。
  27. 根据权利要求26所述的显示面板，其中，至少部分所述拉伸部沿所述第一方向贯穿所述第二子区设置；
    和/或，两个所述第二子区分设于所述第一区在所述第一方向的两侧，各所述第二子区内均设置有所述第一岛组件。
  28. 根据权利要求26所述的显示面板，其中，多个所述绑定引脚在所述第一子区沿第二方向间隔分布；两个所述第一子区分设于所述第一区在所述第二方向的两侧，各所述第一子区内均设置有所述绑定引脚。
  29. 根据权利要求26所述的显示面板，其中，所述第一子区在第一方向上的延伸尺寸小于第二子区在所述第二方向上的延伸尺寸。
  30. 根据权利要求2所述的显示面板，其中，所述像素岛、所述第一电路岛和所述第二电路岛中的至少两者的尺寸相同。
  31. 根据权利要求2所述的显示面板，其中，所述第二电路岛的个数为多个，多个所述第二电路岛分设于所述第一电路岛的两侧，或者多个所述第二电路岛设置于所述第一电路岛朝向或背离所述第一区的一侧。
  32. 根据权利要求31所述的显示面板，其中，所述第二电路岛的个数为两个，其中一个所述第二电路岛对应的所述第二信号线包括第一时钟信号线和第二时钟信号线，另一个所述第二电路岛对应的所述第二信号线包括扫描线和第一电源信号线，所述第一信号线包括高电平电源线和低电平电源线；
    或者，所述第二电路岛的个数为三个以上，至少一个所述第二电路岛对应的所述第二信号线包括虚拟信号线。
  33. 根据权利要求32所述的显示面板，其中，所述第二信号线包括虚拟信号线，且所述虚拟信号线的数量和与其连接于同一所述第二电路岛的所述信号线对称设置。
  34. 根据权利要求1所述的显示面板，其中，所述信号线包括圆弧分段，
    连接于同一所述功能岛、且由所述功能岛同侧伸出的两条所述信号线的圆弧分段对称设置。
  35. 一种显示面板，其中，所述显示面板具有第一区和位于所述第一区周边的第二区，所述第一区和所述第二区均包括岛区和拉伸区，多个所述岛区在所述第一区和所述第二区阵列分布，所述拉伸区位于相邻两行和/或相邻两列所述岛区之间，所述显示面板包括：
    多个功能岛，各所述功能岛位于各所述岛区且所述功能岛上设置有功能件，多个所述功能岛包括位于所述第一区的多个像素岛和位于所述第二区的多个电路岛，所述功能件包括设置于所述像素岛的第一像素电路结构、第一发光单元和设置于所述电路岛的驱动电路结构，所述第一像素电路结构用于驱动所述第一发光单元发光；
    拉伸部，设置于所述拉伸区并连接于相邻的两个所述功能岛之间，且在所述第二区，至少部分所述拉伸区沿所述第一区至所述第二区的方向贯穿所述第二区设置；
    信号线，设置于所述拉伸部并用于连接相邻的两个所述功能岛的所述功能件；
    多个所述电路岛包括第一岛组件，所述第一岛组件包括：
    第一电路岛，所述驱动电路结构包括设置于所述第一电路岛的移位寄存单元；
    第二电路岛，和所述第一电路岛并排设置，所述驱动电路结构包括设置于所述第二电路岛的连接部，
    所述移位寄存单元通过所述信号线与所述第一像素电路结构连接，以向所述第一像素电路结构提供扫描信号，
    所述第一岛组件的所述第一电路岛和所述第二电路岛沿第一方向并排设置，且多个所述第一岛组件沿第二方向间隔设置，所述功能件还包括设置于所述第一电路岛和所述第二电路岛至少一者上的第二像素电路结构和与第二像素电路结构电连接的第二发光单元，所述第二像素电路结构用于驱动所述第二发光单元发光，所述第一岛组件的所述第一电路岛和所述第二电路岛中靠近所述第一区的所述电路岛上设有所述第二像素电路结构和所述第二发光单元。
  36. 一种显示装置，其中，包括权利要求1-35任一项所述的显示面板。
PCT/CN2024/072250 2023-03-29 2024-01-15 显示面板及显示装置 Ceased WO2024198643A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202310319700.6A CN116322145A (zh) 2023-03-29 2023-03-29 显示面板及显示装置
CN202310319700.6 2023-03-29
CN202311857627.4A CN117715458A (zh) 2023-03-29 2023-12-29 显示面板及显示装置
CN202311857627.4 2023-12-29

Publications (1)

Publication Number Publication Date
WO2024198643A1 true WO2024198643A1 (zh) 2024-10-03

Family

ID=86799543

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/072250 Ceased WO2024198643A1 (zh) 2023-03-29 2024-01-15 显示面板及显示装置

Country Status (2)

Country Link
CN (2) CN116322145A (zh)
WO (1) WO2024198643A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116322145A (zh) * 2023-03-29 2023-06-23 昆山国显光电有限公司 显示面板及显示装置
CN116844445B (zh) * 2023-06-30 2026-02-24 云谷（固安）科技有限公司 显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341813A (zh) * 2020-03-11 2020-06-26 上海天马微电子有限公司 显示面板及显示装置
CN112258994A (zh) * 2020-11-20 2021-01-22 上海天马微电子有限公司 一种可拉伸显示面板和可拉伸显示装置
CN115035805A (zh) * 2022-07-21 2022-09-09 京东方科技集团股份有限公司 可拉伸显示面板及可拉伸显示装置
CN116322145A (zh) * 2023-03-29 2023-06-23 昆山国显光电有限公司 显示面板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341813A (zh) * 2020-03-11 2020-06-26 上海天马微电子有限公司 显示面板及显示装置
CN112258994A (zh) * 2020-11-20 2021-01-22 上海天马微电子有限公司 一种可拉伸显示面板和可拉伸显示装置
CN115035805A (zh) * 2022-07-21 2022-09-09 京东方科技集团股份有限公司 可拉伸显示面板及可拉伸显示装置
CN116322145A (zh) * 2023-03-29 2023-06-23 昆山国显光电有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN116322145A (zh) 2023-06-23
CN117715458A (zh) 2024-03-15

Similar Documents

Publication Publication Date Title
US12412517B2 (en) Light-emitting diode display panel and light-emitting diode display device
US10983404B2 (en) Display device
CN115311981B (zh) 显示面板和显示装置
WO2024198643A1 (zh) 显示面板及显示装置
CN112002697A (zh) 源极侧的扇出结构、阵列基板和显示装置
CN116056519B (zh) 显示面板及可穿戴的电子设备
CN101740582B (zh) 晶体管阵列下板
CN116665595A (zh) 阵列基板、显示面板及显示装置
CN112908237B (zh) 一种显示装置及其驱动方法
CN120417670A (zh) 一种显示基板、显示面板及显示装置
WO2025179537A1 (zh) 显示面板和显示装置
CN115148151A (zh) 显示面板以及显示装置
CN119600895A (zh) 一种显示面板及显示装置
CN120636264A (zh) 显示面板、显示模组以及电子设备
TW202015019A (zh) 顯示裝置及其修補方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24777438

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 24777438

Country of ref document: EP

Kind code of ref document: A1