WO2024141879A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024141879A1
WO2024141879A1 PCT/IB2023/063057 IB2023063057W WO2024141879A1 WO 2024141879 A1 WO2024141879 A1 WO 2024141879A1 IB 2023063057 W IB2023063057 W IB 2023063057W WO 2024141879 A1 WO2024141879 A1 WO 2024141879A1
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Prior art keywords
insulating layer
layer
transistor
conductive layer
semiconductor
Prior art date
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Ceased
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PCT/IB2023/063057
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English (en)
French (fr)
Japanese (ja)
Inventor
神長正美
島行徳
中田昌孝
肥塚純一
岡崎健一
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202380087400.8A priority Critical patent/CN120391099A/zh
Priority to JP2024566910A priority patent/JPWO2024141879A1/ja
Priority to KR1020257023969A priority patent/KR20250129700A/ko
Publication of WO2024141879A1 publication Critical patent/WO2024141879A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the contour shape of the opening is any one of a circle, an ellipse, a rectangle with rounded corners, a regular polygon, a polygon other than a regular polygon, a concave polygon, a polygon with rounded corners, or a closed curve that combines straight lines and curves.
  • Another aspect of the present invention includes a first insulating layer, a second insulating layer, a first transistor, and a second transistor, the first transistor having a first semiconductor layer, a first gate insulating layer, a first gate electrode, a first source electrode, and a first drain electrode, one of the first source electrode and the first drain electrode being provided on the first insulating layer, the other of the first source electrode and the first drain electrode being provided on a second insulating layer, and the second insulating layer has a first opening that reaches the first insulating layer and overlaps with a part of one of the first source electrode and the first drain electrode, the first semiconductor layer is provided in contact with a side surface of the first opening of the second insulating layer, an upper surface of the first insulating layer in the first opening, an upper surface of one of the first source electrode and the first drain electrode, and a side surface of the other of the first source electrode and the first drain electrode, and the first gate insulating layer is provided in contact with the first semiconductor layer, the first source electrode
  • FIG 10A is a top view illustrating an example of a semiconductor device
  • FIG 10B is a cross-sectional view illustrating the example of the semiconductor device
  • 11A is a top view illustrating an example of a semiconductor device
  • FIG.11B is a cross-sectional view illustrating an example of the semiconductor device
  • 12A to 12C are cross-sectional views showing an example of a semiconductor device
  • 13A is a top view illustrating an example of a semiconductor device
  • FIG 13B is a cross-sectional view illustrating the example of the semiconductor device
  • 14A is a top view illustrating an example of a semiconductor device
  • FIG 14B is a cross-sectional view illustrating the example of the semiconductor device.
  • 37A to 37D are diagrams for explaining a configuration example of a display device.
  • 38A to 38C are diagrams illustrating a configuration example of a display device.
  • 39A to 39F are diagrams showing an example of an electronic device.
  • 40A to 40G are diagrams showing an example of an electronic device.
  • Fig. 41A is a diagram for explaining a sub-display section, and
  • Fig. 41B1 to Fig. 41B7 are diagrams for explaining examples of pixel configurations.
  • 42A to 42G are diagrams for explaining examples of pixel configurations.
  • 43A to 43D are diagrams illustrating configuration examples of a light-emitting device.
  • an identification number such as “_1”, “[n]”, “[m,n]” may be added to the reference number. Also, when an identification number such as “_1”, “[n]”, “[m,n]” is added to the reference number in the drawings, etc., when it is not necessary to distinguish between them in this specification, the identification number may not be added.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., process order or stacking order). Furthermore, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification and the like, the terms “source” and “drain” may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.
  • Gate and backgate can be used interchangeably. For this reason, in this specification and the like, the terms “gate” and “backgate” can be used interchangeably. Note that the names of the gate and backgate of a transistor can be appropriately changed depending on the situation, such as gate electrode and backgate electrode.
  • the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that “top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting device, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • FIG 1A A perspective schematic view of the transistor 20 is shown in FIG 1A.
  • FIG 1B A cross-sectional schematic view of a cut surface along dashed line A-B shown in FIG 1A is shown in FIG 1B.
  • FIG 8A A top schematic view (also referred to as a plan schematic view) of the transistor 20 is shown in FIG 8A. Note that some components (such as the gate electrode 23 and the gate insulating layer 22) are omitted in FIG 1A and FIG 8A. Also, in FIG 1A, the source electrode 24a is shown through the insulating layer 32.
  • the transistor 20 is provided on an insulating layer 31 and has a semiconductor layer 21, a gate insulating layer 22, a gate electrode 23, a source electrode 24a, and a drain electrode 24b.
  • the source electrode 24a is provided on the insulating layer 31. Furthermore, an insulating layer 32 is provided on the insulating layer 31, and a drain electrode 24b is provided on the insulating layer 32.
  • the insulating layer 32 has an opening 30 that reaches the insulating layer 31, and the opening 30 is provided so as to overlap a part of the source electrode 24a. In other words, a part of the source electrode 24a is provided so as to protrude from the side wall of the opening 30 (which may refer to the side surface of the opening 30, or the side surface of the insulating layer 32 at the opening 30).
  • the side surface of the drain electrode 24b on the opening 30 side is provided so as to be flush with the side surface of the insulating layer 32 at the opening 30.
  • the semiconductor layer 21 is provided in contact with the side surface of the insulating layer 32 at the opening 30.
  • the gate insulating layer 22 is provided so as to cover the semiconductor layer 21, the insulating layer 31, the source electrode 24a, the drain electrode 24b, etc.
  • the gate electrode 23 overlaps the opening 30 and is located on the gate insulating layer 22.
  • the semiconductor layer 21 is provided in contact with each of the source electrode 24a and the drain electrode 24b.
  • the semiconductor layer 21 is provided in a sidewall shape along the side of the opening 30.
  • the semiconductor layer 21 can be formed in a sidewall shape by forming it using an anisotropic etching method.
  • the semiconductor layer 21 contacts a part of the upper surface of the source electrode 24a.
  • the semiconductor layer 21 also contacts at least the side of the drain electrode 24b.
  • a structure can be formed in which the semiconductor layer 21 covers the vicinity of the side of the drain electrode 24b and contacts the side and upper surface of the drain electrode 24b. This makes it possible to increase the contact area between the semiconductor layer 21 and the drain electrode 24b.
  • the semiconductor layer 21 can be formed in a sidewall shape near the drain electrode 24b, so that the semiconductor layer 21 contacts the side surface of the drain electrode 24b but does not contact the top surface of the drain electrode 24b.
  • the lower surface of the semiconductor layer 21 that is not in contact with the source electrode 24a is in contact with the upper surface of the insulating layer 31.
  • the upper surface of the semiconductor layer 21, the upper surface of the drain electrode 24b, and the upper surface of the insulating layer 32 may be in contact with the gate insulating layer 22. Since there is an area at the bottom of the opening 30 where the semiconductor layer 21 is not provided, the gate insulating layer 22 is in contact with the insulating layer 31 at the bottom of the opening 30.
  • the contour shape of the opening 30 is a rectangle with rounded corners, but it is not limited to this and can be a variety of shapes.
  • it can be a circle, an ellipse, a rectangle with rounded corners, etc.
  • It can also be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon.
  • the channel length L can be increased by using a concave polygon, such as a star-shaped polygon, which is a polygon with at least one interior angle exceeding 180 degrees.
  • it can be a polygon with rounded corners, a closed curve that combines straight lines and curves, etc.
  • the ratio of channel width W to channel length L may be used as an index of transistor characteristics.
  • the minimum values of channel length and channel width depend on the exposure limit of an exposure device, so that in order to reduce the W/L ratio, it is necessary to increase L, resulting in a problem of an increase in the area occupied by the transistor.
  • the channel width W can be made smaller than the exposure limit of an exposure device, so that a transistor with an extremely small W/L ratio can be realized without increasing the area occupied by the transistor.
  • FIG. 4A shows an example in which part of the contour of the opening 30 is wavy. This allows the channel length L to be increased without increasing the area occupied by the opening 30.
  • FIG. 4C shows a schematic diagram of an expanded region of the semiconductor layer 21 corresponding to the channel length L1.
  • the source electrode 24a is formed at the lower end of the semiconductor layer 21, and the drain electrode 24b is formed at the upper end of the semiconductor layer 21.
  • the channel length L1 may be formed parallel to the diagonal line connecting the source electrode 24a and the drain electrode 24b, rather than parallel to the periphery of the opening 30.
  • the transistor according to this embodiment can have a longer channel length L1 than when the source electrode 24a and the drain electrode 24b are formed on the same plane.
  • the semiconductor layer 21 contacts the source electrode 24a at the extension 26a and contacts the drain electrode 24b at the extension 26c.
  • the semiconductor layer 21 may also be configured to contact the source electrode 24a or the drain electrode 24b at the bent portion.
  • the semiconductor layer 21 may be configured to contact the source electrode 24a at the bent portion 28a and contact the drain electrode 24b at the bent portion 28b.
  • the opening 30 may have multiple extensions and at least one bend.
  • the number of bends is one less than the number of extensions.
  • the opening 30 may have two extensions and one bend.
  • the opening 30 may have four or more extensions and three or more bends.
  • the contour shape of the opening 30 may be a roll shape, as shown in FIG. 8E.
  • FIG. 7A and 7B show an example of a configuration in which the source electrode 24a and the drain electrode 24b are provided adjacent to each other, and further, the semiconductor layer 21 is not provided on the sidewall of the opening 30 between the source electrode 24a and the drain electrode 24b.
  • the channel length L of the transistor can be made closer to the perimeter of the opening 30, and the channel length L can be made longer.
  • FIG. 9A A top view (also referred to as a plan view) of the semiconductor device 10 is shown in Fig. 9A.
  • FIG. 9B A cross-sectional view of the cut surface along dashed line A1-A2 shown in Fig. 9A is shown in Fig. 9B. Note that some of the components of the semiconductor device 10 (insulating layers, etc.) are omitted in Fig. 9A. As with Fig. 9A, some of the components are omitted in the top views of the semiconductor device in the following drawings.
  • the semiconductor device 10 has a transistor 100, a transistor 200, and an insulating layer 110.
  • the transistor 100, the transistor 200, and the insulating layer 110 are provided on a substrate 102.
  • an insulating layer serving as a base film may be provided on the upper part of the substrate 102.
  • the transistor 100, the transistor 200, and the insulating layer 110 are formed on the insulating layer serving as a base film. Therefore, hereinafter, the upper surface of the substrate 102 also includes the upper surface of the insulating layer serving as a base film on the upper part of the substrate 102.
  • Transistor 100 and transistor 200 have different structures. Transistor 100 and transistor 200 can be formed by sharing some of the steps.
  • transistor 100 When semiconductor device 10 is applied to a display device, it is preferable to use transistor 100 as a pixel selection transistor and transistor 200 as a driving transistor. More specifically, since it is preferable for the driving transistor to have high saturation, transistor 200 with a long channel length can be preferably used. In this way, the semiconductor device of one embodiment of the present invention has an excellent effect that transistors with different channel lengths can be freely designed on the same substrate by changing the thickness of the insulating layer and pattern formation.
  • the above-mentioned descriptions regarding the gate electrode 23, the source electrode 24a, the drain electrode 24b, the gate insulating layer 22, and the semiconductor layer 21 can be referred to.
  • the insulating layer 110 has an opening 145.
  • a conductive layer 212a is provided under the insulating layer 110, and a conductive layer 212b is provided on the insulating layer 110.
  • the opening 145 is formed so as to overlap with a part of the conductive layer 212a. It can also be said that the vicinity of the side end of the conductive layer 212a protrudes from the side wall of the opening 145 (which may refer to the side surface of the opening 145, or the side surface of the insulating layer 110 at the opening 145).
  • the insulating layer 106 is provided so as to cover the opening 145.
  • the insulating layer 106 is provided on the substrate 102, the semiconductor layer 208, the conductive layer 212a, the conductive layer 212b, and the insulating layer 110.
  • the insulating layer 106 has an area that contacts the upper surface and side surfaces of the semiconductor layer 208, the upper surface and side surfaces near the side ends of the conductive layer 212a, the upper surface and side surfaces of the conductive layer 212b, the side surfaces of the insulating layer 110, and the upper surface of the substrate 102.
  • the conductive layer 204 is provided on the insulating layer 106, overlapping the opening 145, and has a region in contact with the upper surface of the insulating layer 106.
  • the conductive layer 204 has a region facing the semiconductor layer 208 via the insulating layer 106.
  • the side end of the conductive layer 204 near the conductive layer 212b preferably overlaps with the side end of the semiconductor layer 208 on the conductor 212b side, and more preferably overlaps up to the vicinity of the side end of the conductive layer 212b on the opening 145 side. With this configuration, a gate electric field can be applied up to the vicinity of the conductive layer 212b of the semiconductor layer 208.
  • the conductive layer 204 has a shape that follows the shape of the upper surface and side surface of the insulating layer 106.
  • a part of the semiconductor layer 208 may be in contact with the upper surface of the conductive layer 212b.
  • the semiconductor layer 208 is in contact with the upper surface and side surface near the side end of the conductive layer 212b.
  • the transistor 100 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode
  • the conductive layer 112b functions as the other.
  • Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure.
  • a conductive layer 112a is provided on the substrate 102, and an insulating layer 110 is provided on the conductive layer 112a.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the insulating layer 110 has an opening 141 that reaches the conductive layer 112a in a region overlapping with the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141.
  • the conductive layer 112a can be made of the same material as the conductive layer 212a. In addition, the conductive layer 112a can be formed in the same process as the conductive layer 212a.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b functions as the other of the source region and the drain region.
  • a channel formation region is provided between the source region and the drain region.
  • the transistor 100 can have a source electrode, a layer having a channel formation region, and a drain electrode that are stacked, so the area it occupies can be significantly reduced compared to a so-called planar type transistor in which the layer having the channel formation region is arranged in a planar shape.
  • the conductive layer 112a and the conductive layer 112b functioning as the source electrode and the drain electrode of the transistor 100 are provided on different surfaces. Specifically, the conductive layer 112a is provided on the substrate 102, the conductive layer 112b is provided on the insulating layer 110, and the insulating layer 110 is sandwiched between the conductive layer 112a and the conductive layer 112b. Similarly, the conductive layer 212a and the conductive layer 212b functioning as the source electrode and the drain electrode of the transistor 200 are provided on different surfaces. Specifically, the conductive layer 212a is provided on the substrate 102, and the conductive layer 212b is provided on the insulating layer 110.
  • one of the source electrode and the drain electrode of the transistor 100 is provided on the same surface as one of the source electrode and the drain electrode of the transistor 200, and the other is provided on the same surface as the other of the source electrode and the drain electrode of the transistor 200.
  • the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and the region in contact with the channel formation region of the semiconductor layer 208 contain oxygen.
  • One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 and the region in contact with the channel formation region of the semiconductor layer 208.
  • FIGS. 10A and 10B show enlarged views of transistor 200 shown in FIG. 9A and FIG. 9B.
  • FIGS. 11A and 11B show enlarged views of transistor 100.
  • the insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b. Thus, at least the region of the semiconductor layer 208 in contact with the insulating layer 110b and the region of the semiconductor layer 108 in contact with the insulating layer 110b can each function as a channel formation region.
  • a film that releases oxygen when heated for the insulating layer 110b It is more preferable to use a film that releases oxygen when heated for the insulating layer 110b.
  • the insulating layer 110b releases oxygen, so that oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies (V O ) are repaired, and the oxygen vacancies (V O ) can be reduced.
  • defects in which hydrogen has entered the oxygen vacancies (V O ) (hereinafter also referred to as V O H) can be reduced by supplying oxygen. Therefore, a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.
  • the insulating layer 110a and the insulating layer 110c are preferably made of a film that is difficult for oxygen to permeate. This can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, the oxygen contained in the insulating layer 110b can be suppressed from diffusing to the conductive layer 112b through the insulating layer 110c. This can suppress the conductive layer 112a and the conductive layer 112b from being oxidized and their electrical resistance from increasing. In addition, the amount of oxygen supplied from the insulating layer 110b to the channel formation region is increased, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • the thickness T110a of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more, and can be less than 1 ⁇ m, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. As shown in FIG. 11B, the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the lower surface of the insulating layer 110b in a cross-sectional view.
  • the thickness T110a of the insulating layer 110a When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112a can be prevented from increasing.
  • the thickness T110c of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more, and can be 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. As shown in FIG. 11B, the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the lower surface of the conductive layer 112b in a cross-sectional view.
  • the thickness T110c of the insulating layer 110c When the thickness T110c of the insulating layer 110c is large, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110c is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110c within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b can be prevented from increasing.
  • At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c may be a region having a lower electrical resistance than the channel formation region (hereinafter, also referred to as a low-resistance region).
  • the region may be a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region.
  • the low resistance regions can function as buffer regions to reduce the drain electric field. These low resistance regions may also function as source or drain regions.
  • the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110a into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the region of the semiconductor layer 208 in contact with the insulating layer 110a may be a low resistance region compared to the channel formation region.
  • This region can also be said to be a region with a high carrier concentration or a high oxygen defect density compared to the channel formation region.
  • the region in contact with the insulating layer 110a can be a low resistance region.
  • the semiconductor layer 208 can be configured to have a low resistance region between the region in contact with the conductive layer 212a (one of the source region and the drain region) and the channel formation region.
  • the low resistance region can function as a buffer region for relaxing the drain electric field. Note that the low resistance region may function as a source region or a drain region.
  • the top surface shapes of the openings 145, 141, and 143 are not limited, and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • it is preferable that the top surface shapes of the openings 141 and 143 are each circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, and openings of a fine size can be formed.
  • a circle is not limited to a perfect circle.
  • the top surface shape of opening 145 refers to the shape of the top surface end portion of insulating layer 110 on the opening 145 side.
  • the top surface shape of opening 141 refers to the shape of the top surface end portion of insulating layer 110 on the opening 141 side.
  • the top surface shape of opening 143 refers to the shape of the bottom surface end portion of conductive layer 112b on the opening 143 side.
  • the top surface shapes of openings 141 and 143 can be made to match or roughly match each other.
  • the bottom surface end of conductive layer 112b on the opening 143 side match or roughly match the top surface end of insulating layer 110 on the opening 141 side.
  • the bottom surface of conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of insulating layer 110 refers to the surface on the conductive layer 112b side.
  • openings 141 and 143 do not have to be the same. Furthermore, when the top surface shapes of openings 141 and 143 are circular, openings 141 and 143 may or may not be concentric.
  • the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow.
  • the channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle ⁇ 110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely small channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m).
  • a transistor with a channel length of less than 10 nm without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L100 can be 100 nm or more and 1 ⁇ m or less.
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L100 can be controlled by adjusting the thickness T110b and angle ⁇ 110 of the insulating layer 110b. Note that in FIG. 11B, the thickness T110b of the insulating layer 110b is indicated by a double-headed arrow of a dashed line.
  • the thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • Figure 11B and other figures show an example in which the side of the insulating layer 110 on the opening 141 side is vertical, as shown in Figure 12C, the side of the insulating layer 110 on the opening 141 side can also be tapered.
  • the angle ⁇ 110 is 90 degrees or less.
  • the coverage of the layer (e.g., semiconductor layer 108) formed on the insulating layer 110 can be improved.
  • the smaller the angle ⁇ 110 the larger the channel length L100 can be, and the larger the angle ⁇ 110, the smaller the channel length L100 can be.
  • the angle ⁇ 110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and 90 degrees or less, 85 degrees or less, or 80 degrees or less.
  • the angle ⁇ 110 may also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.
  • the conductive layer 112b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 112b does not have a region that is in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 matches the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).
  • the width D141 of opening 141 is indicated by a double-headed arrow with a two-dot chain line.
  • Figure 11A shows an example in which the top surface shape of opening 141 is circular.
  • width D141 corresponds to the diameter of the circle
  • channel width W100 of transistor 100 is the length of the circumference of the circle.
  • channel width W100 is ⁇ x D141. In this way, when the top surface shape of opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.
  • the width D141 of the opening 141 may vary in the depth direction.
  • the average value of the diameter at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters may be used as the width D141 of the opening 141.
  • the diameter of the opening 141 may be any one of the diameters at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these two diameters.
  • the insulating layer 110a and the insulating layer 110c are made of a material that releases less hydrogen.
  • the insulating layer 110a and the insulating layer 110c are made of a material that releases even a small amount of hydrogen, it is preferable that the thicknesses of these layers are thin.
  • the channel length L200 of the transistor 200 is indicated by a solid double-headed arrow.
  • the channel length L200 corresponds to the distance between the conductive layer 212a and the conductive layer 212b along the circumferential direction of the semiconductor layer 208 provided on the sidewall of the opening 145.
  • the channel length L200 of the transistor 200 can be controlled by the top surface shape and size of the opening 145. Therefore, the channel length L200 can be made larger than the channel length L100.
  • the channel width W200 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure device.
  • the channel length L100 is determined by the film thickness of the insulating layer 110b, when multiple transistors 100 are formed on the same surface in the same process, all the transistors 100 have the same channel length.
  • the channel length L200 of the transistor 200 can be controlled by the upper surface shape and size of the opening 145.
  • the transistor 200 can be formed by sharing some of the processes with the transistor 100. Therefore, the transistor 100 with a short channel length and the transistor 200 with a longer channel length can be formed on the same surface with good productivity.
  • the angle between the side of the insulating layer 110b on the opening 145 side and the surface on which the insulating layer 110b is to be formed may also match or approximately match the angle ⁇ 110, as in the case of the transistor 100.
  • FIG. 10B and other figures show an example in which the side of the insulating layer 110 on the opening 145 side is vertical, as shown in FIG. 12B, the side of the insulating layer 110 on the opening 145 side may also be tapered. In this case, as shown in FIG. 12B, the side of the conductive layer 112b on the opening 145 side may also be tapered.
  • the semiconductor layer 108 and the semiconductor layer 208 may each be, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, also written as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Z oxide), or the like.
  • In oxide indium oxide
  • In-Zn oxide indium zinc oxide
  • In-Sn oxide indium tin oxide
  • ITO indium titanium oxide
  • In-Ga oxide indium gallium oxide
  • In-W oxide also written as IWO
  • IWO indium gallium aluminum oxide
  • In-Ga-Sn oxide indium gallium tin oxide
  • the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor and increases its reliability.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of element M.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 108 and the semiconductor layer 208 may each have the same or approximately the same composition.
  • a stacked structure of metal oxide layers with the same composition for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the higher the substrate temperature during formation the more crystalline the metal oxide can be formed.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation.
  • the higher the ratio of the flow rate of oxygen gas to the total film formation gas used in formation (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber the more crystalline the metal oxide can be formed.
  • the crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • VOH When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to reduce VOH in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies ( VOH ).
  • impurities such as water and hydrogen in the metal oxide
  • VOH repair oxygen vacancies
  • supplying oxygen to a metal oxide to repair oxygen vacancies ( VOH ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, conductive layer 212b may each have a single layer structure or a laminated structure of two or more layers.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can each be preferably made of a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum is preferable because of its excellent mass productivity.
  • a metal oxide that has become a conductor can be called an oxide conductor.
  • conductive layer 112a, conductive layer 112b, conductive layer 112a, and conductive layer 112b it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized.
  • the conductive layers 112a, 112b, 212a, and 212b may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • Substrate 102 Although there is no significant limitation on the material of the substrate 102, it is necessary that the material has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102.
  • a semiconductor element may be provided on the substrate 102.
  • the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • FIG 13A is a top view of a semiconductor device 10A according to one embodiment of the present invention
  • FIG 13B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 13A.
  • Insulating layer 149 contacts the side surface and upper surface of the protruding portion of insulating layer 147, and the side surface and lower surface of semiconductor layer 108. As shown in FIG. 13B, in a cross-sectional view, the side surface of insulating layer 149 may be flush with the side end portion of the protruding portion of insulating layer 147.
  • insulating layer 147, insulating layer 149, insulating layer 247, insulating layer 249, semiconductor layer 108, and semiconductor layer 208 shown here can also be applied to other configuration examples.
  • FIG 14A is a top view of a transistor 200B according to one embodiment of the present invention, and FIG 14B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 14A.
  • the opening 145 differs from the transistor 200 shown in FIG. 9A etc. mainly in that it has an extension and a bend.
  • the top surface shape of the opening 145 formed by combining the extension and the bend can be called a serpentine shape, a roundabout shape, a bent shape, or a meandering shape.
  • the opening 145 has an extension 146a, an extension 146b, an extension 146c, a bend 148a, and a bend 148b.
  • the top surface shape of the opening 145 can be considered as a shape in which the extensions 146a and 146b are connected via the bend 148a, and the extensions 146b and 146c are connected via the bend 148b.
  • a semiconductor layer 208 is provided in contact with the side surface of the opening 145. In the opening 145, the semiconductor layer 208 is provided facing the conductive layer 204 with the insulating layer 106 interposed therebetween. Here, the semiconductor layer 208 is in contact with the conductive layer 212a at the extension 146a, and in contact with the conductive layer 212b at the extension 146b.
  • Extending portion 146a, extending portion 146b, and extending portion 146c have a shape that extends in one direction (in FIG. 14A, a direction perpendicular to dashed line A1-A2) when viewed from above.
  • bending portion 148a and bending portion 148b are provided such that one end is bent relative to the other end when viewed from above.
  • a folded structure can be formed in the opening 145.
  • the length of the opening 145 can be significantly longer than the distance between the conductive layers 212a and 212b. This significantly increases the channel length of the transistor 200B, and increases the saturation of the transistor 200B.
  • the present invention is not limited to this.
  • a configuration in which the conductive layer functioning as a source electrode or drain electrode is in contact with the semiconductor layer at the bent portion may also be used.
  • a configuration in which the semiconductor layer 208 is in contact with the conductive layer 212a at the bent portion 148a and in contact with the conductive layer 212b at the bent portion 148b may also be used.
  • the opening 145 has extensions 146a, 146b, 146c, bends 148a, and 148b, but the present invention is not limited to this.
  • the opening 145 only needs to have multiple extensions and at least one bend.
  • it is preferable that the number of bends is one less than the number of extensions.
  • the opening 145 may have two extensions and one bend.
  • the opening 145 may have four or more extensions and three or more bends.
  • the top surface shape of the opening 145 is shown with rounded corners, but the present invention is not limited to this, and the corners of the extension and bent parts may be angular. In this case, the top surface shape of the opening 145 may be called a zigzag shape.
  • the transistor 200B shown in FIG. 15A only the semiconductor layer 208 in the path represented by the dashed line C1-C2 functions as a channel formation region. Therefore, compared to the transistor 200B shown in FIG. 14A, the effective channel width can be considered to be about half. Therefore, the transistor 200B shown in FIG. 15A has a smaller channel width, and therefore can have higher saturation.
  • Transistor 200C differs from transistor 200 mainly in that it has conductive layer 212a and conductive layer 216 on substrate 102 (or on an insulating layer serving as a base film provided on top of substrate 102), and in that insulating layer 110 has a six-layer structure.
  • the conductive layer 216 functions as a back gate electrode (which can also be called a second gate electrode) of the transistor 200C.
  • the conductive layer 216 is preferably located on the insulating layer 110d1.
  • the conductive layer 212a and the conductive layer 216 are electrically insulated from each other by the insulating layers 110a, 110b1, and 110d1.
  • the conductive layer 216 preferably has an opening, and the opening 145 is preferably provided inside the opening.
  • the conductive layer 216 may be electrically connected to the conductive layer 212a.
  • the conductive layer 212a and the conductive layer 216 may be in contact with each other through openings provided in the insulating layers 110a, 110b1, and 110d1.
  • the conductive layer 216 may be electrically connected to the conductive layer 212b.
  • the conductive layer 212b and the conductive layer 216 may be in contact with each other through openings provided in the insulating layers 110c, 110b2, and 110d2.
  • FIG. 16A illustrates an example in which the cross-sectional shape of the conductive layer 216 has a tapered shape
  • the conductive layer 216 may be arranged so that its cross-sectional shape is vertical. With this arrangement, the side surface of the conductive layer 216 and the surface of the semiconductor layer 208 that contacts the insulating layer 110 become parallel. With this arrangement, the potential given to the conductive layer 216 can be efficiently applied to the semiconductor layer 208, which is preferable.
  • the insulating layer 110d2 covers the upper and side surfaces of the conductive layer 216.
  • the insulating layer 110d2 is provided so as to cover a portion of the opening of the conductive layer 216. It is preferable that the insulating layer 110d2 contacts the insulating layer 110d1 through the opening.
  • FIG. 16A shows an example in which the thickness of insulating layer 110d1 is uniform regardless of location, the present invention is not limited to this.
  • insulating layer 110d1 may have different thicknesses in areas that overlap with conductive layer 216 and areas that do not overlap. For example, when processing the film that will become conductive layer 216, parts of insulating layer 110d1 that do not overlap with conductive layer 216 may be removed, resulting in a thinner thickness.
  • the insulating layer 110b2 preferably covers the upper and side surfaces of the conductive layer 216 via the insulating layer 110d2.
  • the insulating layer 110b2 is preferably provided so as to cover a portion of the opening of the conductive layer 216 via the insulating layer 110d2.
  • the semiconductor layer 208 has an area that overlaps with the conductive layer 204 via the insulating layer 106 and with the conductive layer 216 via a part of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2).
  • the transistor 200C has a back gate electrode, the potential of the back channel of the semiconductor layer 208 can be fixed, and a negative shift in the threshold voltage can be suppressed. This makes it possible to realize a transistor with normally-off characteristics (i.e., a threshold voltage of a positive value).
  • Transistor 200C has a region in which conductive layer 216, insulating layer 110, semiconductor layer 208, insulating layer 106, and conductive layer 204 overlap in this order in one direction without any other layers in between. By widening this region, the electric field of the back channel of semiconductor layer 208 can be more reliably controlled.
  • the shortest distance between the conductive layer 216 and the semiconductor layer 208 may differ on the left and right sides of the opening in the insulating layer 110.
  • the conductive layer 116 corresponds to the conductive layer 216 described above, and the description of the conductive layer 216 can be referred to. That is, the conductive layer 116 functions as a backgate electrode of the transistor 100C.
  • the insulating layer 110 has the same structure as the insulating layer 110 shown in FIG. 16A. That is, a part of the insulating layer 110 functions as a backgate insulating layer of the transistor 100C.
  • the transistor 100C there is also a region in the semiconductor layer 108 that overlaps with the conductive layer 104 via the insulating layer 106 and overlaps with the conductive layer 116 via a portion of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2).
  • the semiconductor layer 108 is sandwiched between the side of the conductive layer 104 and the side of the conductive layer 116, a portion of the insulating layer 110 (particularly, the insulating layer 110b2 and the insulating layer 110d2) is provided between at least a portion of the semiconductor layer 108 and the side of the conductive layer 104, and the insulating layer 106 is provided between at least a portion of the semiconductor layer 108 and the side of the conductive layer 116.
  • the transistor 100C has a back gate electrode, the potential of the back gate side (also called the back channel) of the semiconductor layer 108 can be fixed. Therefore, the saturation of the Id-Vd characteristics of the transistor 200C can be further improved.
  • the transistor 100C has a back gate electrode, the potential of the back channel of the semiconductor layer 108 can be fixed, and a negative shift in the threshold voltage can be suppressed. This makes it possible to realize a transistor with normally-off characteristics (i.e., a threshold voltage of a positive value).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), ALD, and molecular beam epitaxy (MBE).
  • CVD methods include PECVD and thermal CVD.
  • thermal CVD method is metal organic chemical vapor deposition (MOCVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films may be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • etching the thin film one or more of the following methods can be used: dry etching, wet etching, and sandblasting.
  • Fig. 17A to Fig. 20B show cross-sectional views taken along dashed line A1-A2 in Fig. 9A.
  • Fig. 21A to Fig. 22B show top views.
  • a film that will become the conductive layer 112a and the conductive layer 212a is formed on the substrate 102, and the film is processed to form the conductive layer 112a and the conductive layer 212a.
  • the film can be preferably formed by a sputtering method.
  • the conductive layer 112a and the conductive layer 212a can be preferably formed by, for example, a wet etching method. Note that an insulating layer that will become a base film may be laminated on the substrate 102 before the film is formed.
  • a conductive film having high conductivity such as copper can be used for the conductive layer 112a and the conductive layer 212a.
  • a laminated film having a copper layer and an ITSO layer on the copper layer can be used for the conductive layer 112a and the conductive layer 212a.
  • the conductive layer 112a and the conductive layer 212a are disposed on a flat portion on the substrate 102, so that the conductive layer 112a and the conductive layer 212a can be relatively easily routed even if a conductive film having high conductivity such as copper is used. Therefore, the conductive layer 112a and the conductive layer 212a can function as wiring with low electrical resistance.
  • insulating film 110af which will become insulating layer 110a
  • insulating film 110bf which will become insulating layer 110b
  • the channel length L100 of transistor 100 and the channel width W200 of transistor 200 depend on the film thickness of insulating film 110bf. Therefore, the film thickness of insulating film 110bf can be set according to the electrical characteristics desired for transistor 100 and transistor 200.
  • the insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to continuously form the insulating film 110bf in a vacuum without exposing the surface of the insulating film 110af to the atmosphere. By continuously forming the insulating films 110af and 110bf, it is possible to prevent impurities derived from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic matter.
  • the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, even more preferably 350°C or higher and 400°C or lower.
  • the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating film itself and to suppress the diffusion of impurities into the semiconductor layer 108. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., water and hydrogen
  • the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.
  • oxygen may be supplied to the insulating film 110bf.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen.
  • an apparatus that converts oxygen gas into plasma by high-frequency power can be suitably used.
  • a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus can be given as an apparatus that converts gas into plasma by high-frequency power.
  • the plasma treatment is preferably performed in an atmosphere containing oxygen.
  • the plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), carbon monoxide, and carbon dioxide.
  • a metal oxide layer 137 on the insulating film 110bf (FIG. 17B). By forming the metal oxide layer 137, oxygen can be supplied to the insulating film 110bf.
  • the conductivity of the metal oxide layer 137 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the metal oxide layer 137.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used as the metal oxide layer 137.
  • the metal oxide layer 137 it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferable to use a metal oxide material that can be applied to the semiconductor layer 108 and the semiconductor layer 208.
  • oxygen can be supplied to the insulating film 110bf during the formation of the metal oxide layer 137, and oxygen can be prevented from being released from the insulating film 110bf.
  • a large amount of oxygen can be trapped in the insulating film 110bf.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • the temperature of the heat treatment is preferably 150°C or more, 200°C or more, 230°C or more, or 250°C or more, and is less than the distortion point of the substrate, 450°C or less, 400°C or less, 350°C or less, or 300°C or less.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen.
  • a noble gas nitrogen, or oxygen.
  • dry air CODA: Clean Dry Air
  • It is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible.
  • As the atmosphere it is preferable to use a high-purity gas with a dew point of -60°C or less, preferably -100°C or less.
  • the metal oxide layer 137 is removed.
  • a wet etching method can be preferably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when removing the metal oxide layer 137. This can suppress the thickness of the insulating film 110bf from becoming thin, and the thickness of the insulating layer 110b can be made uniform.
  • oxygen may be further supplied to the insulating film 110bf.
  • the above description can be referred to for the method of supplying oxygen.
  • a film 139 may be formed on the insulating film 110bf, and oxygen may be supplied to the insulating film 110bf through the film 139.
  • a plasma treatment in an atmosphere containing oxygen can be used.
  • FIG. 17C shows a schematic diagram with arrows showing the state in which oxygen is supplied to the insulating film 110bf.
  • the thickness of film 139 is preferably thin. Specifically, the thickness of film 139 is preferably 1 nm or more, 2 nm or more, or 3 nm or more, and 20 nm or less, 15 nm or less, or 10 nm or less. Typically, the thickness can be about 5 nm.
  • the substrate temperature during the formation of film 139 is preferably 350°C or less, more preferably 340°C or less, even more preferably 330°C or less, and even more preferably 300°C or less. This allows a large amount of oxygen to be supplied to insulating film 110bf.
  • a dry etching apparatus As the processing apparatus for supplying oxygen, a dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used. In particular, it is preferable to use an ashing apparatus.
  • the bias voltage When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage may be set to, for example, 10 V or more and 1 kV or less. Alternatively, the power density of the bias may be set to, for example, 1 W/cm 2 or more and 5 W/cm 2 or less.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110b.
  • the substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C.
  • a substrate temperature of from room temperature to 140°C is preferable because it increases productivity.
  • the crystallinity can be reduced.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. This can reduce oxygen vacancies ( VO ) and VOH in the channel formation region. At this time, it is more preferable to perform the heat treatment before processing the metal oxide film 108f into the semiconductor layer 108 and the semiconductor layer 208.
  • the above description can be referred to for the heat treatment, and detailed description thereof will be omitted. Note that the heat treatment is not limited to this, and oxygen may also be supplied to the channel formation region in a step in which heat is applied after the formation of the metal oxide film 108f (for example, a step of forming the insulating layer 106).
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it may be combined with a heat treatment performed in a later process. Also, a high-temperature process in a later process (e.g., a film formation process) may also serve as the heat treatment.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, the conductive layer 212a, the conductive layer 212b, the insulating layer 110, and the substrate 102 (FIG. 20A).
  • the insulating layer 106 can be formed preferably by, for example, the PECVD method or the ALD method.
  • insulating layer 195 is formed to cover conductive layer 104, conductive layer 204, and insulating layer 106 (FIG. 9B).
  • the insulating layer 195 can be preferably formed by the PECVD method.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of a substrate supporting a display element (also called a display device) and an opposing substrate.
  • FIG. 23A shows a perspective view of a display device 50A.
  • Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • FIG. 23A shows an example in which an IC 173 is provided on a substrate 151 by a COG method or a COF method.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 50A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method or the like.
  • the semiconductor device of one embodiment of the present invention can be used, for example, as one or both of the display portion 162 and the circuit portion 164 of the display device 50A.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in a display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the display unit 162 is an area in the display device 50A that displays an image, and has a number of periodically arranged pixels 210.
  • Figure 23A shows an enlarged view of one pixel 210.
  • pixel arrangements there are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • the pixel 210 shown in FIG. 23A has a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light.
  • a full-color display can be realized by configuring one pixel 210 with pixels 230R, 230G, and 230B.
  • Each of pixels 230R, 230G, and 230B functions as a subpixel.
  • the display device 50A shown in FIG. 23A shows an example in which pixels 230 that function as subpixels are arranged in a stripe array.
  • the number of subpixels that configure one pixel 210 is not limited to three, and may be four or more.
  • the pixel 210 may have four subpixels that emit R, G, B, and white (W) light.
  • the pixel 210 may have four subpixels that emit R, G, B, and Y light.
  • Pixel 230R, pixel 230G, and pixel 230B each have a display element and a circuit that controls the driving of the display element.
  • liquid crystal elements also called liquid crystal devices
  • light-emitting devices Other elements that can be used include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that use microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc.
  • QLEDs Quantum-dot LEDs that use a light source and color conversion technology using quantum dot materials.
  • Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PNLC Polymer Network liquid crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc.
  • either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the display device of one embodiment of the present invention may be a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting device is formed, a bottom-emission type that emits light toward the substrate on which the light-emitting device is formed, or a dual-emission type that emits light on both sides.
  • FIG. 23B is a block diagram illustrating the display device 50A.
  • the display device 50A has a display unit 162 and a circuit unit 164.
  • the display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or more).
  • the circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.
  • the circuit included in the first drive circuit unit 231 functions, for example, as a scanning line drive circuit.
  • the circuit included in the second drive circuit unit 232 functions, for example, as a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 162.
  • the circuit portion 164 may include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit.
  • the circuit portion 164 may include transistors and capacitor elements. The transistors in the circuit portion 164 may be formed in the same process as the transistors included in the pixel 230.
  • Display device 50A has wiring 236 that are arranged approximately in parallel and whose potential is controlled by a circuit included in first drive circuit section 231, and wiring 238 that are arranged approximately in parallel and whose potential is controlled by a circuit included in second drive circuit section 232.
  • FIG. 23B shows an example in which wiring 236 and wiring 238 are connected to pixel 230.
  • wiring 236 and wiring 238 are just an example, and wirings connected to pixel 230 are not limited to wiring 236 and wiring 238.
  • a VFET having a channel length of submicron size and a large on-state current and a VLFET having a long channel length and high saturation can be formed by sharing some of the steps.
  • An oxide semiconductor (OS) can be preferably used for the channel formation region of these transistors, and the transistors can have a small off-state current.
  • the semiconductor device according to one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164.
  • the semiconductor device according to one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this way, it is possible to achieve an effect of keeping the manufacturing cost low.
  • the transistor Tr33 when a high potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After the data is written to the latch circuit LAT, if the potential of the terminal SMP is set to a low potential, the transistor Tr33 is turned off. As a result, the potential of the node N is held, and the data written to the latch circuit LAT is held.
  • writing data to the latch circuit LAT such that the signal input from terminal SP2 is output to terminal LIN may be simply referred to as "writing data to the latch circuit LAT.”
  • writing data with a value of "1" to the latch circuit LAT may be simply referred to as "writing data to the latch circuit LAT.”
  • a semiconductor device can be suitably used in the latch circuit LAT.
  • the transistor 100 or the transistor 200 shown in FIG. 9B or the like can be used as one or more of the transistors Tr31, Tr33, Tr35, and Tr36.
  • the inverter circuit INV has transistors Tr41, Tr43, Tr45, Tr47, and a capacitance element C41.
  • VDD is supplied to one of the source and drain of transistor Tr43 and one of the source and drain of transistor Tr47.
  • VSS is supplied to one of the source and drain of transistor Tr41 and one of the source and drain of transistor Tr45.
  • all the transistors in the latch circuit LAT can be transistors of the same polarity, for example, n-channel transistors. This allows, for example, transistor Tr33 as well as transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 to be OS transistors. Therefore, all the transistors in the latch circuit LAT can be manufactured in the same process.
  • a semiconductor device can be preferably used for the inverter circuit INV.
  • the transistor 100 or the transistor 200 shown in FIG. 9B or the like can be used for one or more of the transistors Tr41, Tr43, Tr45, and Tr47.
  • Transistor 52B has the function of controlling the amount of current flowing through light-emitting device 61.
  • Capacitive element 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by light-emitting device 61 is controlled according to an image signal supplied to the gate of transistor 52B.
  • One of the source and drain of transistor 52C is electrically connected to one of the source and drain of transistor 52B.
  • the other of the source and drain of transistor 52C is electrically connected to wiring V0.
  • a reference potential is supplied to wiring V0.
  • the gate of transistor 52C is electrically connected to wiring GL.
  • the above-mentioned semiconductor device can be suitably used in the pixel circuit 51A.
  • the transistor 52B By using one of the transistors 20, 200, and 200A, which have a long channel length, as the transistor 52B, a highly reliable display device can be obtained.
  • the transistor 100 By using the transistor 100 as the transistors 52A and 52C, the area occupied by the pixel circuit 51A can be reduced, and a high-definition display device can be obtained. Note that the transistor 100 may also be used as the transistor 52B.
  • Transistor 52A and transistor 52B are provided on substrate 102.
  • Figure 25C shows a configuration in which insulating layers 121 and 123 are provided between transistor 52A and transistor 52B and substrate 102.
  • the insulating layer 233 and the insulating layer 235 are preferably organic insulating films.
  • Examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may have a laminated structure of an organic insulating film and an inorganic insulating film. It is preferable that the insulating layer 235 has a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. This allows the inorganic insulating film to function as an etching protection layer when forming the light-emitting device 61.
  • the display device 50B has a configuration in which a pixel circuit, a driver circuit, and the like are provided on a substrate 310.
  • the display device 50B has an element layer 71, an element layer 73, an element layer 75, and a wiring layer 77.
  • the wiring layer 77 is a layer in which wirings are provided.
  • Transistor 300 can be a transistor included in element layer 71.
  • Transistor MTCK can be a transistor included in element layer 73.
  • Light-emitting device 130 can be a light-emitting device included in element layer 75.
  • the transistor 300 has an element isolation layer 312, a conductive layer 316, an insulating layer 315, an insulating layer 317, a semiconductor region 313 formed of a part of the substrate 310, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. Therefore, the transistor 300 is a Si transistor. Note that FIG.
  • FIG. 27 shows a configuration in which one of the source and drain of the transistor 300 is electrically connected to a conductive layer 330, a conductive layer 356, and a conductive layer 514, which will be described later, via a conductive layer 328, which will be described later, but the electrical connection configuration of the display device of one embodiment of the present invention is not limited to this.
  • the display device of one embodiment of the present invention may have a configuration in which, for example, the gate of the transistor 300 is electrically connected to the conductive layer 514 via the conductive layer 328.
  • the transistor 300 can be made into a Fin type by, for example, configuring the upper surface and the side surface in the channel width direction of the semiconductor region 313 to be covered by the conductive layer 316 via the insulating layer 315 that functions as a gate insulating layer.
  • the effective channel width can be increased, and the on characteristics of the transistor 300 can be improved.
  • the contribution of the electric field of the gate electrode can be increased, and therefore the off characteristics of the transistor 300 can be improved.
  • the transistor 300 may be a planar type instead of a Fin type.
  • the transistor 300 may be either a p-channel type or an n-channel type. Alternatively, multiple transistors 300 may be provided, and both p-channel and n-channel types may be used.
  • the work function is determined by the material of the conductor, so the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as a laminated material for the conductor, and in particular, it is preferable to use tungsten in terms of heat resistance.
  • an insulating layer 320 and an insulating layer 322 are stacked in this order from the substrate 310 side.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and connects to the transistor MTCK and the like that are provided above the insulating layer 322.
  • the conductive layer 328 functions as a plug or wiring.
  • the conductive layer 328 can be made of a material that can be used for the conductive layer MPG.
  • a wiring layer 77 is provided on the transistor 300.
  • the wiring layer 77 includes, for example, an insulating layer 324, an insulating layer 326, a conductive layer 330, an insulating layer 350, an insulating layer 352, an insulating layer 354, and a conductive layer 356.
  • Insulating layer 324 and insulating layer 326 are laminated in this order on insulating layer 322 and conductive layer 328.
  • an opening is formed in insulating layer 324 and insulating layer 326 in the area overlapping conductive layer 328.
  • conductive layer 330 is embedded in the opening.
  • Insulating layer 350, insulating layer 352, and insulating layer 354 are laminated in this order on insulating layer 326 and conductive layer 330. In addition, in the region overlapping conductive layer 330, openings are formed in insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 is embedded in the opening.
  • the conductive layer 330 and the conductive layer 356 function as a plug or wiring that connects to the transistor 300. Note that the conductive layer 330 and the conductive layer 356 can be formed using a material similar to that of the conductive layer 328 or the conductive layer 596 described above.
  • the insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting device, it is possible to suppress leakage of light from the light-emitting device to an adjacent light-emitting device through the insulating layer 127 (stray light). This makes it possible to improve the display quality of the display panel. In addition, since the display quality can be improved without using a polarizing plate in the display panel, it is possible to make the display panel lighter and thinner.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • the structure of the insulating layer 127 and other components will be described using the structure of the insulating layer 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same can be said about the insulating layer 127 between the light-emitting device 130G and the light-emitting device 130B, and the insulating layer 127 between the light-emitting device 130B and the light-emitting device 130R.
  • the following may be described using the end of the insulating layer 127 on the second layer 113b as an example, but the same can be said about the end of the insulating layer 127 on the first layer 113a, and the end of the insulating layer 127 on the third layer 113c.
  • the upper surface of the insulating layer 127 preferably has a convex curved shape.
  • the convex curved shape of the upper surface of the insulating layer 127 is preferably a shape that bulges gently toward the center.
  • the convex curved portion at the center of the upper surface of the insulating layer 127 is preferably a shape that is continuously connected to the tapered portion at the side edge.
  • one end of the insulating layer 127 overlaps with the conductive layer 126a that functions as a pixel electrode, and the other end of the insulating layer 127 overlaps with the conductive layer 126b that functions as a pixel electrode.
  • the end of the insulating layer 127 can be formed on a roughly flat region of the first layer 113a (second layer 113b). Therefore, it is relatively easy to process the tapered shape of the insulating layer 127 as described above.
  • the display device of this embodiment can narrow the distance between light-emitting devices.
  • the distance between light-emitting devices, between EL layers, or between pixel electrodes can be less than 10 ⁇ m, 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.
  • a protective layer 131 is provided on the light-emitting device 130.
  • the protective layer 131 is a film that functions as a passivation film that protects the light-emitting device 130.
  • impurities such as water and oxygen
  • aluminum oxide, silicon nitride, or silicon oxynitride can be used for the protective layer 131.
  • FIG. 28B is a block diagram of the electronic device 150 of FIG. 28A.
  • the electronic device 150 has a display device 90_L, a display device 90_R, a motion detection unit 101, a gaze detection unit 84, a calculation unit 103, and a communication unit 85, and transmits and receives various signals between them via bus wiring BW.
  • the display device 90_L and the display device 90_R each have a plurality of pixels 230, a drive circuit 65, and a function circuit 40.
  • One pixel 230 includes one light-emitting device 61 and one pixel circuit 51.
  • the display device 90_L and the display device 90_R each include a plurality of light-emitting devices 61 and a plurality of pixel circuits 51.
  • the gaze detection unit 84 has a function of acquiring information about the user's gaze. Specifically, it has a function of detecting the user's gaze.
  • the user's gaze may be acquired, for example, by an eye tracking method such as the Pupil Center Corneal Reflection method or the Bright/Dark Pupil Effect method. Alternatively, it may be acquired by an eye tracking method using a laser or ultrasound.
  • the calculation unit 103 has a function of using the second information to determine the size and shape of multiple areas to be set on the display unit of each of the display devices 90_L and 90_R. Specifically, the calculation unit 103 calculates a gaze point on the display unit according to the second information, and sets a first area S1 to a third area S3, etc. (described later) on the display unit based on the gaze point.
  • the calculation unit 103 performs various data processing and program control by interpreting and executing commands from various programs using the processor.
  • the programs that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a separately provided storage unit.
  • the storage unit for example, a storage device using non-volatile storage elements such as flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), and FeRAM (Ferroelectric RAM), or a storage device using volatile storage elements such as DRAM (Dynamic RAM) and SRAM (Static RAM) may be used.
  • the communication unit 85 has the function of communicating with external devices wirelessly or via wired connections to obtain various data such as image data.
  • the communication unit 85 may be provided with, for example, a high-frequency circuit (RF circuit) for transmitting and receiving RF signals.
  • the high-frequency circuit is a circuit that converts between electromagnetic signals and electrical signals in a frequency band determined by the legislation of each country, and uses the electromagnetic signals to communicate wirelessly with other communication devices.
  • the information on the multiple areas in the display unit of the display device determined by the calculation unit 103 is used for driving the display unit to have different resolutions for each area.
  • the functional circuit 40 has a function of controlling the drive circuit 65 to perform a high-resolution display in an area close to the gaze point, and to control the drive circuit 65 to perform a low-resolution display in an area far from the gaze point.
  • the sensor 97 may be used to measure the surrounding temperature, humidity, illuminance, odor, etc.
  • the sensor 97 may also be used to obtain information for personal authentication using, for example, a fingerprint, palm print, iris, retina, pulse shape (including vein shape and artery shape), or face.
  • the sensor 97 may also be used to measure the number of times the user blinks, eyelid behavior, pupil size, body temperature, pulse rate, or oxygen saturation in the blood, and detect the user's fatigue level and health condition, etc.
  • the electronic device 150 may detect the user's fatigue level and health condition, etc., and display a warning, etc. on the display device 90.
  • the operation of electronic device 150 may be controlled by detecting the movement of the user's eyes and eyelids. Since the user does not need to touch electronic device 150 to operate it, input operations can be performed without holding anything in both hands (both hands are free).
  • the housing 105 preferably has a mechanism that allows the left-right positions of the lens 88 and the display devices 90_L and 90_R to be adjusted so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the housing 105 has a mechanism that allows the focus to be adjusted by changing the distance between the lens 88 and the display devices 90_L and 90_R.
  • the electronic device of one embodiment of the present invention may further include an earphone 99A.
  • the earphone 99A has a communication unit (not shown) and has a wireless communication function.
  • the earphone 99A can output audio data using the wireless communication function.
  • the earphone 99A may also have a vibration mechanism that functions as a bone conduction earphone.
  • the earphone 99A can be configured to be connected directly to the mounting portion 86 or connected via a wire, like the earphone 99B shown in FIG. 29B.
  • the earphone 99B and the mounting portion 86 may also have a magnet. This allows the earphone 99B to be fixed to the mounting portion 86 by magnetic force, which is preferable as it makes storage easier.
  • Example of the configuration of the display device The configuration of a display device 90A that can be applied to the display device 90_L and the display device 90_R shown in FIGS. 28A and 28B will be described with reference to FIGS. 30A, 30B, and 31.
  • FIG. 30A, 30B, and 31 The configuration of a display device 90A that can be applied to the display device 90_L and the display device 90_R shown in FIGS. 28A and 28B will be described with reference to FIGS. 30A, 30B, and 31.
  • FIG. 30A is a perspective view of a display device 90A that can be used with the display devices 90_L and 90_R shown in FIGS. 28A and 28B.
  • a display unit 93 capable of displaying at a resolution of so-called full high vision (also called “2K resolution”, “2K1K”, or “2K”).
  • a display unit 93 capable of displaying at a resolution of so-called ultra high vision (also called “4K resolution”, “4K2K”, or “4K”).
  • a display unit 93 capable of displaying at a resolution of so-called super high vision (also called “8K resolution”, “8K4K”, or “8K”).
  • the pixel density (resolution) of the display unit 93 is preferably 1000 ppi or more and 10000 ppi or less. For example, it may be 2000 ppi or more and 6000 ppi or less, or 3000 ppi or more and 5000 ppi or less.
  • the display unit 93 can support various screen ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.
  • a display element may sometimes be replaced with “device.”
  • a display element, a light-emitting device, and a liquid crystal element may be replaced with, for example, a display device, a light-emitting device, and a liquid crystal device.
  • Display device 90A receives various signals and power supply potentials from the outside via terminal section 94, and can display images using display elements provided in display section 93.
  • Various elements can be used as the display elements.
  • Representative examples include light-emitting devices that have the function of emitting light, such as organic EL elements and LED elements, liquid crystal elements, and MEMS elements.
  • a number of layers are provided between substrate 91 and substrate 92, and each layer is provided with transistors for performing circuit operations or display elements for emitting light.
  • pixel circuits having the function of controlling the operation of the display elements
  • drive circuits having the function of controlling the pixel circuits
  • functional circuits having the function of controlling the drive circuits, etc. are provided.
  • Figure 30B shows a perspective view that illustrates the configuration of each layer provided between substrate 91 and substrate 92.
  • the transistor 63 can be, for example, a transistor having single crystal silicon in the channel formation region (also called a "c-Si transistor").
  • a transistor having single crystal silicon in the channel formation region is used as the transistor provided in the layer 62, the on-state current of the transistor can be increased. This is preferable because the circuit in the layer 62 can be driven at high speed.
  • a Si transistor can be formed by microfabrication so that the channel length is 3 nm or more and 10 nm or less, it can be used as the display device 90A in which an accelerator such as a CPU or GPU, an application processor, etc. are provided integrally with the display unit.
  • the width of the non-display area (also called the frame) present on the periphery of the display unit 93 of the display device 90A can be made extremely narrow compared to the case where these circuits and the display unit 93 are arranged side by side, and the display device 90A can be made smaller.
  • a layer 83 is provided on the layer 62.
  • the layer 83 has a pixel circuit group 55 including a plurality of pixel circuits 51.
  • the layer 83 may include an OS transistor.
  • the pixel circuit 51 may include an OS transistor.
  • the layer 83 may be stacked on the layer 62.
  • Si transistors may be provided in layer 83.
  • pixel circuit 51 may be configured to include transistors having single crystal silicon or polycrystalline silicon in the channel formation region.
  • LTPS may be used as the polycrystalline silicon.
  • layer 83 may be formed on a separate substrate and bonded to layer 62.
  • the pixel circuit 51 may be composed of multiple types of transistors using different semiconductor materials.
  • the transistors may be provided in different layers for each type of transistor.
  • the Si transistors and the OS transistors may be provided in a stacked state. By providing the transistors in a stacked state, the area occupied by the pixel circuit 51 is reduced. This makes it possible to improve the resolution of the display device 90A.
  • LTPO a configuration in which LTPS transistors and OS transistors are combined may be referred to as LTPO.
  • the diagonal size of the display unit 93 can be 0.1 inches or more and 5.0 inches or less, preferably 0.5 inches or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less.
  • the diagonal size of the display unit 93 may be 1.5 inches or close to 1.5 inches.
  • the display device 90A can be applied to devices other than wearable electronic devices.
  • the diagonal size of the display unit 93 may exceed 2.0 inches.
  • the configuration of the transistors used in the pixel circuit 51 may be appropriately selected according to the diagonal size of the display unit 93.
  • the diagonal size of the display unit 93 is preferably 0.1 inches or more and 3 inches or less.
  • the diagonal size of the display unit 93 is preferably 0.1 inches or more and 30 inches or less, and more preferably 1 inch or more and 30 inches or less.
  • the diagonal size of the display unit 93 is preferably 0.1 inches or more and 50 inches or less, and more preferably 1 inch or more and 50 inches or less.
  • the diagonal size of the display section 93 is preferably 0.1 inches or more and 200 inches or less, and more preferably 50 inches or more and 100 inches or less.
  • LTPS transistors are not restricted by the use of a laser crystallization device in the manufacturing process, and can be manufactured at a relatively low process temperature (typically 450°C or lower), so they can accommodate display devices with a relatively large area (typically 50 inches or more and 100 inches or less in diagonal size).
  • LTPO can be applied to the diagonal size of the display area in the area between when LTPS transistors are used and when OS transistors are used (typically 1 inch or more and 50 inches or less).
  • the digital-to-analog conversion circuit 67 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., described below, into analog data.
  • the image data converted into analog data is amplified by an amplifier circuit 35, such as an operational amplifier, and transmitted to the pixel circuit 51 via the source driver circuit 66. Note that the image data may be transmitted in the order of the source driver circuit 66, the digital-to-analog conversion circuit 67, and the pixel circuit 51.
  • the digital-to-analog conversion circuit 67 and the amplifier circuit 35 may also be included in the source driver circuit 66.
  • the functional circuit 40 may include a plurality of circuits capable of improving the display quality of the display device 90A.
  • such circuits may include a correction circuit (color adjustment, dimming) that detects color unevenness in the displayed image and corrects the color unevenness to create an optimal image.
  • the functional circuit 40 may include an EL correction circuit that corrects image data according to the characteristics of the light-emitting device.
  • the functional circuit 40 includes an EL correction circuit 43.
  • the sensor controller 46 has, as an example, a function for controlling the sensor. Also, in FIG. 31, wiring SNCL is illustrated as wiring for electrically connecting to the sensor.
  • the wiring electrically connecting the pixel circuit 51 and the drive circuit 65 can be shortened, and the wiring resistance of the wiring can be reduced. Therefore, data can be written at high speed, and the display device 90A can be driven at high speed. As a result, even if the display device 90A has a large number of pixel circuits 51, a sufficient frame period can be secured, and the pixel density of the display device 90A can be increased. In addition, by increasing the pixel density of the display device 90A, the resolution of the image displayed by the display device 90A can be increased. For example, the pixel density of the display device 90A can be 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 90A can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs in which the display unit is close to the user.
  • FIG. 33A and FIG. 33B show an example of pixel circuit 51 having a total of three transistors, one embodiment of the present invention is not limited to this. Below, an example of the configuration of a pixel circuit that can be applied to pixel circuit 51 and an example of a driving method will be described.
  • the pixel circuit 51B shown in FIG. 34B has a configuration in which a transistor 52C is added to the pixel circuit 51A. In addition, the pixel circuit 51B is electrically connected to the wiring V0.
  • Pixel circuit 51C shown in FIG. 34C is an example in which transistors having a pair of gates electrically connected are used as transistors 52A and 52B of pixel circuit 51A.
  • Pixel circuit 51D shown in FIG. 34D is an example in which the same transistor is used in pixel circuit 51B. This can increase the current that the transistor can pass. Note that, although transistors having a pair of gates electrically connected are used for all transistors here, this is not limited to this. Also, transistors having a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to the source.
  • the pixel circuit 51F shown in FIG. 35B is an example in which a capacitive element 53A is added to the pixel circuit 51E.
  • the capacitive element 53A functions as a storage capacitor.
  • Pixel circuit 51G shown in FIG. 35C and pixel circuit 51H shown in FIG. 35D are examples in which a transistor having a pair of gates is applied to pixel circuit 51E or pixel circuit 51F, respectively.
  • Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, and transistor 52B is a transistor in which one gate is electrically connected to its source.
  • the display device 90B has a pixel circuit group 55 including a plurality of pixel circuits 51 and a drive circuit 65 stacked on top of each other.
  • the pixel circuit group 55 is divided into a plurality of sections 59
  • the drive circuit 65 is divided into a plurality of sections 39.
  • Each of the plurality of sections 39 has a source driver circuit 66 and a gate driver circuit 33.
  • the display device 90B can arbitrarily set the drive frequency for image display for each sub-display unit 95 by using the timing controller 44 of the functional circuit 40.
  • the functional circuit 40 has a function of controlling the operation of each of the multiple sections 39 and the multiple sections 59. In other words, the functional circuit 40 has a function of controlling the drive frequency and operation timing of each of the multiple sub-display units 95 arranged in a matrix.
  • the functional circuit 40 also has a function of adjusting synchronization between the sub-display units.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • 41A shows p lines GL arranged approximately in parallel and whose potentials are controlled by the gate driver circuit 33, and q lines SL arranged approximately in parallel and whose potentials are controlled by the source driver circuit 66.
  • the pixel 230 arranged in the rth row (r is an arbitrary number, and in this embodiment, etc., is an integer between 1 and p) is electrically connected to the gate driver circuit 33 via the line GL in the rth row.
  • the pixel 230 arranged in the sth column (s is an arbitrary number, and in this embodiment, etc., is an integer between 1 and q) is electrically connected to the source driver circuit 66 via the line SL in the sth column.
  • the pixel 230 in the rth row and sth column is shown as pixel 230[r,s].
  • a display unit 93 capable of full-color display at so-called 2K resolution can be realized.
  • a display unit 93 capable of full-color display at so-called 4K resolution can be realized.
  • a display unit 93 capable of full-color display at so-called 8K resolution can be realized.
  • pixel 230 that emits infrared light can be applied to pixel 230X. That is, pixel 230X has a light-emitting device 61 that emits infrared light (IR).
  • pixel 237 preferably has a light-receiving element that detects infrared light. For example, while an image is displayed by pixel 230 that emits visible light, reflected infrared light emitted by sub-pixel X can be detected by pixel 237.
  • the luminescent color of the EL layer 175a and the EL layer 175b may be the same.
  • the luminescent color of the EL layer 175a and the EL layer 175b may both be green.
  • the EL layer 175a and the EL layer 175b of the R sub-pixel each have a material capable of emitting red light
  • the EL layer 175a and the EL layer 175b of the G sub-pixel each have a material capable of emitting green light
  • the EL layer 175a and the EL layer 175b of the B sub-pixel each have a material capable of emitting blue light.
  • the material of the light-emitting layer 4411 and the light-emitting layer 4412 may be the same.
  • the light emission color of the light emitting device can be red, green, blue, cyan, magenta, yellow, or white, depending on the material that constitutes the EL layer 175.
  • the color purity can be further improved by providing the light emitting device with a microcavity structure.
  • the light-emitting layer preferably contains two or more types of luminescent materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc.
  • the light-emitting layer contains two or more types of luminescent materials, and the light emitted by each luminescent material contains spectral components of two or more colors of R, G, and B.
  • a material that emits near-infrared light can also be used as the luminescent material.
  • Light-emitting substances include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). Not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used as light-emitting substances.

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PCT/IB2023/063057 2022-12-28 2023-12-21 半導体装置 Ceased WO2024141879A1 (ja)

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