WO2024100489A1 - 半導体装置、半導体装置の作製方法、及び電子機器 - Google Patents

半導体装置、半導体装置の作製方法、及び電子機器 Download PDF

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Publication number
WO2024100489A1
WO2024100489A1 PCT/IB2023/060887 IB2023060887W WO2024100489A1 WO 2024100489 A1 WO2024100489 A1 WO 2024100489A1 IB 2023060887 W IB2023060887 W IB 2023060887W WO 2024100489 A1 WO2024100489 A1 WO 2024100489A1
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Prior art keywords
layer
conductive layer
insulating layer
semiconductor
conductive
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
松嵜隆徳
井坂史人
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Another aspect of the present invention relates to a memory device and a method for manufacturing the memory device. Another aspect of the present invention relates to a transistor and a method for manufacturing the transistor. Another aspect of the present invention relates to an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (such as a transistor, a diode, or a photodiode), and a device having the same circuit. It also refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a diode, or a photodiode
  • an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices.
  • a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.
  • LSIs large scale integrated circuits
  • CPUs central processing units
  • memories are used in semiconductor devices.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.
  • IC chips Semiconductor circuits such as CPUs and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in various electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor and a second transistor using an oxide semiconductor to provide multiple stacked memory cells.
  • Patent Document 4 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulating layer.
  • the threshold voltage of a transistor affects the operation of the transistor. For example, in the case of an n-channel transistor, a low threshold voltage tends to result in a normally-on characteristic.
  • One embodiment of the present invention has an object to provide a semiconductor device or storage device capable of controlling the threshold voltage of a transistor. Another embodiment of the present invention has an object to provide a semiconductor device or storage device with favorable electrical characteristics. Another embodiment of the present invention has an object to provide a highly reliable semiconductor device or storage device. Another embodiment of the present invention has an object to provide a semiconductor device or storage device that operates at high speed. Another embodiment of the present invention has an object to provide a semiconductor device or storage device that can be miniaturized or highly integrated. Another embodiment of the present invention has an object to provide a small semiconductor device or storage device. Another embodiment of the present invention has an object to provide a large-capacity storage device. Another embodiment of the present invention has an object to provide a semiconductor device or storage device with low power consumption.
  • Another embodiment of the present invention has an object to provide a low-cost semiconductor device or storage device. Another embodiment of the present invention has an object to provide a transistor with high on-current. Another embodiment of the present invention has an object to provide a transistor with low off-current. Alternatively, one of the objectives of one embodiment of the present invention is to provide a transistor with good electrical characteristics. Alternatively, one of the objectives of one embodiment of the present invention is to provide a new semiconductor device, memory device, or transistor.
  • One embodiment of the present invention has an object to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device in which the threshold voltage of a transistor can be controlled. Or, another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device with good electrical characteristics. Or, another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device with high reliability. Or, another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device that operates at high speed.
  • another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device that can be miniaturized or highly integrated.
  • another object of one embodiment of the present invention is to provide a method for manufacturing a small semiconductor device or a method for manufacturing a memory device.
  • another object of one embodiment of the present invention is to provide a method for manufacturing a large-capacity memory device.
  • another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a method for manufacturing a memory device with low power consumption.
  • one object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device with high yield.
  • one object of one embodiment of the present invention is to provide a method for manufacturing a transistor with high on-state current.
  • one object of one embodiment of the present invention is to provide a method for manufacturing a transistor with low off-state current.
  • one object of one embodiment of the present invention is to provide a method for manufacturing a transistor with good electrical characteristics.
  • one object of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device, a memory device, or a transistor.
  • One aspect of the present invention is a transistor having a first insulating layer and a second insulating layer, the transistor having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a third insulating layer and a fourth insulating layer, the first insulating layer being provided on the first conductive layer, the second conductive layer and the third insulating layer being provided on the first insulating layer, the second insulating layer being provided on the second conductive layer and the third insulating layer, the third conductive layer being provided on the second insulating layer, the first insulating layer, the second insulating layer, the third insulating layer, and
  • the third conductive layer has an opening that reaches the first conductive layer, the semiconductor layer is provided so as to have a region located inside the opening, the semiconductor layer has a region in contact with the first conductive layer and a region in contact with the third conductive layer, the third insulating layer is provided between the semiconductor layer and the second
  • the second conductive layer and the fourth conductive layer may have a region that sandwiches the channel formation region of the semiconductor layer inside the opening.
  • the second conductive layer may be provided with an oxide region having an area in contact with the third insulating layer.
  • the oxide region may include an oxide of a material included in the second conductive layer.
  • the first conductive layer may have a first layer and a second layer, the second layer being provided on the first layer, and the semiconductor layer may have a region in contact with the top surface of the first layer and a region in contact with the side surface of the second layer.
  • the first insulating layer has a first layer, a second layer, and a third layer
  • the second insulating layer has a fourth layer, a fifth layer, and a sixth layer
  • the second layer is provided on the first layer
  • the third layer is provided on the second layer
  • the fifth layer is provided on the fourth layer
  • the sixth layer is provided on the fifth layer
  • the first layer, the third layer, the fourth layer, and the sixth layer may contain nitrogen.
  • the second layer and the fifth layer may contain oxygen.
  • An electronic device having a semiconductor device according to one embodiment of the present invention and a camera is also one embodiment of the present invention.
  • one aspect of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a second insulating layer on the second conductive layer, forming a third conductive layer on the second insulating layer, forming an opening in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer that reaches the first conductive layer, and performing a first processing on the second conductive layer to recess a side surface of the second conductive layer at the opening, and forming a region in contact with a side surface of the second conductive layer on the first conductive layer, the first insulating layer, the second insulating layer, and the third conductive layer.
  • the first processing may be performed by isotropic etching
  • the second processing may be performed by anisotropic etching
  • an oxidation treatment may be performed on the side surface of the second conductive layer at the opening, thereby forming an oxide region in the second conductive layer.
  • the oxidation treatment may be performed by microwave treatment in an oxygen-containing atmosphere.
  • a first layer and a second layer on the first layer may be formed as the first conductive layer, and after the formation of the third conductive layer, an opening reaching the second layer may be formed in the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, and after the oxidation treatment and before the formation of the semiconductor layer, the area of the second layer overlapping with the opening may be removed.
  • a first layer, a second layer on the first layer, and a third layer on the second layer are formed as the first insulating layer, and a fourth layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer are formed as the second insulating layer, the insulating film is formed to have a region in contact with the upper surface of the sixth layer, the insulating film contains oxygen, and the sixth layer may contain nitrogen.
  • the first layer, the third layer, and the fourth layer may contain nitrogen.
  • the second layer and the fifth layer may contain oxygen.
  • the semiconductor layer may have a metal oxide.
  • the metal oxide may have one or more selected from indium, zinc, and element M, and element M may be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • a semiconductor device or storage device capable of controlling the threshold voltage of a transistor can be provided.
  • a semiconductor device or storage device having good electrical characteristics can be provided.
  • a highly reliable semiconductor device or storage device can be provided.
  • a semiconductor device or storage device that operates at high speed can be provided.
  • a semiconductor device or storage device that can be miniaturized or highly integrated can be provided.
  • a small-sized semiconductor device or storage device can be provided.
  • a large-capacity storage device can be provided.
  • a semiconductor device or storage device with low power consumption can be provided.
  • a low-cost semiconductor device or storage device can be provided.
  • a transistor with high on-current can be provided.
  • a transistor with low off-current can be provided.
  • a transistor with good electrical characteristics can be provided.
  • a novel semiconductor device, storage device, or transistor can be provided.
  • a method for manufacturing a semiconductor device or a method for manufacturing a memory device capable of controlling the threshold voltage of a transistor can be provided.
  • a method for manufacturing a semiconductor device or a memory device having good electrical characteristics can be provided.
  • a method for manufacturing a semiconductor device or a memory device having high reliability can be provided.
  • a method for manufacturing a semiconductor device or a memory device that operates at high speed can be provided.
  • a method for manufacturing a semiconductor device or a memory device that can be miniaturized or highly integrated can be provided.
  • a method for manufacturing a small semiconductor device or a memory device can be provided.
  • a method for manufacturing a large-capacity memory device can be provided.
  • a method for manufacturing a semiconductor device or a memory device with low power consumption can be provided.
  • a method for manufacturing a semiconductor device or a memory device with high yield can be provided.
  • a method for manufacturing a transistor with high on-current can be provided.
  • one embodiment of the present invention can provide a method for manufacturing a transistor with low off-state current.
  • one embodiment of the present invention can provide a method for manufacturing a transistor with good electrical characteristics.
  • one embodiment of the present invention can provide a novel method for manufacturing a semiconductor device, a novel method for manufacturing a memory device, or a novel method for manufacturing a transistor.
  • FIG. 1 is a perspective view showing a configuration example of a semiconductor device.
  • 2A1 and 2A2 are plan views showing an example of the configuration of a semiconductor device, and Fig. 2B, Fig. 2C, and Fig. 2D are cross-sectional views showing an example of the configuration of a semiconductor device.
  • 3A and 3B are cross-sectional views showing a configuration example of a semiconductor device.
  • 4A and 4B are cross-sectional and plan views illustrating an example of the configuration of a semiconductor device.
  • 5A1 and 5A2 are plan views showing a configuration example of a semiconductor device, and Fig. 5B and Fig. 5C are cross-sectional views showing a configuration example of a semiconductor device.
  • FIG. 6A to 6C are cross-sectional views showing configuration examples of a semiconductor device.
  • 7A to 7D are cross-sectional views showing configuration examples of a semiconductor device.
  • 8A to 8D are cross-sectional views showing configuration examples of a semiconductor device.
  • Fig. 9A is a plan view showing a configuration example of a semiconductor device
  • Fig. 9B and Fig. 9C are cross-sectional views showing the configuration example of a semiconductor device.
  • 10A to 10C are cross-sectional views showing configuration examples of a semiconductor device.
  • 11A and 11B are plan views showing a configuration example of a semiconductor device.
  • Fig. 12A is a plan view showing a configuration example of a semiconductor device
  • FIGS. 14B and 14C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • 16A1 and 16A2 are plan views illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 17B and 17C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • 18A1 and 18A2 are plan views illustrating a configuration example of a semiconductor device
  • Fig. 18B and Fig. 18C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device.
  • 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS.
  • 19B and 19C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • 20A1 and 20A2 are plan views illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 21A to 21F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • Fig. 22A1 and Fig. 22A2 are plan views showing a configuration example of a memory device
  • Fig. 22B and Fig. 22C are cross-sectional views showing a configuration example of a memory device
  • Fig. 22D1 and Fig. 22D2 are circuit diagrams showing a configuration example of a memory device.
  • Fig. 23A is a plan view showing a configuration example of a storage device
  • Fig. 23B and Fig. 23C are cross-sectional views showing the configuration example of the storage device.
  • 24A is a plan view showing a configuration example of a storage device
  • FIG 24B is a cross-sectional view showing the configuration example of a storage device.
  • 25A is a plan view showing a configuration example of a storage device
  • FIG 25B is a cross-sectional view showing the configuration example of a storage device.
  • 26A is a plan view showing a configuration example of a storage device
  • FIG 26B is a cross-sectional view showing the configuration example of a storage device.
  • FIG. 27 is a cross-sectional view showing a configuration example of a storage device.
  • FIG. 28A to 28C are plan views showing configuration examples of a storage device.
  • 29A to 29C are plan views showing configuration examples of a storage device.
  • FIG. 30 is a block diagram showing an example of the configuration of a storage device.
  • 31A is a schematic diagram showing a configuration example of a memory device
  • FIG 31B is a circuit diagram showing a configuration example of a memory device.
  • 32A and 32B are schematic diagrams showing configuration examples of a storage device.
  • FIG. 33 is a circuit diagram showing a configuration example of a memory device.
  • 34A and 34B are diagrams showing an example of a chip on which a memory device is mounted.
  • 35A and 35B are diagrams illustrating an example of an electronic component.
  • 36A to 36E are schematic diagrams showing an example of a storage device.
  • 37A to 37H are diagrams showing an example of an electronic component.
  • FIG. 38 is a diagram showing an example of space equipment.
  • the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc.
  • the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.
  • a layer or resist mask may be unintentionally reduced by a process such as etching, but this may not be reflected in the drawings for ease of understanding.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • ordinal numbers attached to components in one place in this specification may not match the ordinal numbers attached to the same components in other places in this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the density of defect states in the semiconductor may increase or the crystallinity may decrease.
  • examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as Vo
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • the terms “film” and “layer” can be interchanged depending on the situation.
  • the term “conductive layer” can be changed to the term “conductive film”, and the term “conductive film” can be changed to the term “conductive layer”.
  • the term “insulating film” can be changed to the term “insulating layer”, and the term “insulating layer” can be changed to the term “insulating film”.
  • the term “semiconductor film” can be changed to the term “semiconductor layer", and the term “semiconductor layer” can be changed to the term “semiconductor film”.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Voltage refers to the potential difference from a reference potential, and if the reference potential is the ground potential, for example, “voltage” can be interchanged with “potential.” Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, for example, the potential supplied to wiring, the potential applied to a circuit, and the potential output from a circuit also change.
  • electrically connected includes a connection via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitance, and other elements with various functions.
  • the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • the top surface shape of a certain component refers to the contour shape of the component in a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a fine curvature, or approximately planar with fine irregularities.
  • A covers B
  • at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.
  • metal oxide is an oxide of a metal in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
  • oxide semiconductors also referred to as oxide semiconductors or simply OS.
  • the metal oxide when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor.
  • OS transistor when a transistor is referred to as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.
  • the transistor can be a transistor in which a semiconductor layer is provided inside an opening formed in a first interlayer insulating layer on a substrate and a second interlayer insulating layer on the first interlayer insulating layer.
  • the channel length direction of the transistor can be set along the side surfaces of the first and second interlayer insulating layers in the opening. Therefore, the channel length is no longer affected by the performance of an exposure device used to manufacture the transistor, and the channel length can be made smaller than the limit resolution of the exposure device. Therefore, the on-current of the transistor can be increased, and the semiconductor device can be operated at high speed.
  • a first conductive layer provided under the opening is used as one of the source electrode or drain electrode of the transistor.
  • first and second interlayer insulating layers are provided on the first conductive layer, and openings are provided in the first and second interlayer insulating layers so as to reach the first conductive layer.
  • a second conductive layer provided on the second interlayer insulating layer and having an opening overlapping the above opening is used as the other of the source electrode or drain electrode of the transistor.
  • a semiconductor layer is provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer.
  • a first gate insulating layer is provided on the semiconductor layer, and a first gate electrode is provided on the first gate insulating layer.
  • the threshold voltage of the transistor when the channel length of the transistor is reduced, the threshold voltage of the transistor is reduced and, for example, the transistor may have normally-on characteristics. Therefore, a second gate electrode and a second gate insulating layer are provided in the transistor included in the semiconductor device of one embodiment of the present invention. This makes it possible to control, for example, the threshold voltage of the transistor. Therefore, for example, the threshold voltage of the transistor can be made higher than when the transistor does not have the second gate electrode and the second gate insulating layer. This makes it possible to prevent the transistor from having normally-on characteristics. In other words, the transistor can have normally-off characteristics. As described above, a semiconductor device with good electrical characteristics can be provided.
  • a transistor having normally-on characteristics means that a channel exists in the semiconductor layer and a current flows between the source and drain of the transistor even when a potential is not supplied to the gate of the transistor.
  • a transistor having normally-off characteristics means that no current flows between the source and drain of the transistor when a potential is not supplied to the gate of the transistor.
  • a transistor having normally-on characteristics means that a current flows between the source and drain of the transistor even when a potential is not supplied to the first gate electrode, which has a function of controlling the magnitude of the current flowing in the channel formation region of the semiconductor layer.
  • a transistor having normally-off characteristics means that no current flows between the source and drain of the transistor when a potential is not supplied to the first gate electrode.
  • the second gate electrode and the second gate insulating layer are provided between the first interlayer insulating layer and the second interlayer insulating layer.
  • the second gate insulating layer has an opening that overlaps with the openings provided in the first and second interlayer insulating layers, and covers a part of the side surface of the semiconductor layer at the opening.
  • the second gate electrode covers at least a part of the side surface of the second gate insulating layer.
  • the second gate electrode also covers a part of the side surface of the semiconductor layer via the second gate insulating layer.
  • the side surface of the second gate insulating layer has a region that contacts the side surface of the semiconductor layer
  • the side surface of the second gate electrode has a region that contacts the side surface of the second gate insulating layer opposite the semiconductor layer.
  • a transistor included in a semiconductor device first, a first conductive layer on a substrate, a first interlayer insulating layer on the first conductive layer, a second gate electrode on the first interlayer insulating layer, a second interlayer insulating layer on the second gate electrode, and a second conductive layer on the second interlayer insulating layer are formed in this order.
  • an opening reaching the first conductive layer is formed in the first interlayer insulating layer, the second gate electrode, the second interlayer insulating layer, and the second conductive layer.
  • a first processing is performed on the side surface of the second gate electrode in the opening, and the side surface is recessed. As a result, a recess formed by the first interlayer insulating layer, the second gate electrode, and the second interlayer insulating layer is formed.
  • the first processing can be performed, for example, by using isotropic etching.
  • a second gate insulating layer is formed between the first interlayer insulating layer and the second interlayer insulating layer so as to have a region in contact with the side surface of the second gate electrode at the opening.
  • an insulating film is formed on the first conductive layer, the first interlayer insulating layer, the second interlayer insulating layer, and the second conductive layer so as to have a region in contact with the side surface of the second gate electrode at the opening, and the second gate insulating layer is then subjected to a second processing, thereby forming the second gate insulating layer.
  • the second processing can be performed, for example, by using anisotropic etching.
  • a semiconductor layer, a first gate insulating layer, and a first gate electrode are formed in this order so as to have a region located inside the opening.
  • a transistor included in a semiconductor device according to one embodiment of the present invention can be manufactured.
  • FIG 1 is a perspective view showing a configuration example of a semiconductor device according to one embodiment of the present invention, and shows a configuration example of a transistor 100 included in the semiconductor device.
  • FIG 2A1 is a plan view showing the configuration example when FIG 1 is viewed in the Z direction, specifically, for example, from the top in the Z direction. In FIG 2A1, some elements such as an insulating layer are omitted for clarity of the drawing. Some elements are also omitted in the plan views shown later.
  • FIG 2B is a cross-sectional view taken along dashed line A1-A2 in FIG 2A1
  • FIG 2C is a cross-sectional view taken along dashed line A3-A4 in FIG 2A1.
  • the X-direction, the Y-direction, and the Z-direction are shown on the coordinate axes.
  • the direction of the dashed line A1-A2 is the X-direction
  • the direction of the dashed line A3-A4 is the Y-direction
  • the direction perpendicular to the XY plane is the Z-direction.
  • the X-direction, the Y-direction, and the Z-direction can be mutually intersecting directions, specifically, mutually perpendicular directions.
  • the definitions of the X-direction, the Y-direction, and the Z-direction are shown on the coordinate axes, but the definitions may be the same as those in 1, 2A1, 2B, and 2C, or may be different.
  • the X-direction, the Y-direction, and the Z-direction are shown by arrows, but the forward direction and the reverse direction are not distinguished unless otherwise specified. The same applies to the following drawings.
  • one of the X direction, Y direction, and Z direction may be referred to as the "first direction.”
  • the other may be referred to as the “second direction.”
  • the remaining may be referred to as the "third direction.”
  • the semiconductor device of one embodiment of the present invention has an insulating layer 101 on a substrate (not shown) and a transistor 100 on the insulating layer 101.
  • the semiconductor device of one embodiment of the present invention also has an insulating layer 103 on the insulating layer 101, an insulating layer 104 on the insulating layer 103, and an insulating layer 107 on the insulating layer 104 and on the transistor 100.
  • the insulating layer 101, the insulating layer 103, and the insulating layer 104 function as interlayer insulating layers.
  • the layers that function as interlayer insulating layers, including these insulating layers, are preferably planarized. Note that the layers that function as interlayer insulating layers do not have to be planarized.
  • the transistor 100 has a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, a conductive layer 115, an insulating layer 106, and a conductive layer 117.
  • FIG. 2A2 shows a plan view in which the conductive layer 115, the semiconductor layer 113, and the conductive layer 112 are omitted from FIG. 2A1, and the insulating layer 106 is added.
  • FIG. 2A1 shows an example in which the conductive layer 115 is provided to extend in the X direction, and the conductive layer 112 is provided to extend in the Y direction.
  • FIGS. 2A1 and 2A2 show an example in which the conductive layer 117 is provided to extend in the Y direction.
  • the insulating layers 101, 103, 104, 105, 106, and 107 can be made of an insulator described in the section [Insulator] below, in a single layer or a stacked layer.
  • the conductive layers 111, 112, 115, and 117 can be made of a conductor described in the section [Conductor] below, in a single layer or a stacked layer.
  • the semiconductor layer 113 can be made of a metal oxide described in the section [Metal oxide] below, in a single layer or a stacked layer.
  • the semiconductor layer 113 can be made of a material such as silicon described in the section [Other semiconductor materials] below, in a single layer or a stacked layer.
  • a transistor using metal oxide for the channel formation region of a semiconductor layer is called an OS transistor.
  • a transistor using silicon for the channel formation region of a semiconductor layer is called a Si transistor.
  • the transistor 100 can be an OS transistor.
  • the transistor 100 can be a Si transistor.
  • the conductive layer 111 functions as one of the source electrode and drain electrode of the transistor 100.
  • the conductive layer 112 functions as the other of the source electrode and drain electrode of the transistor 100.
  • the insulating layer 105 and the insulating layer 106 function as the gate insulating layer of the transistor 100.
  • the conductive layer 115 and the conductive layer 117 function as the gate electrode of the transistor 100.
  • the conductive layer 111 is provided on the insulating layer 101, the insulating layer 103 is provided on the insulating layer 101 and the conductive layer 111, the insulating layer 106 and the conductive layer 117 are provided on the insulating layer 103, the insulating layer 104 is provided on the insulating layer 103, the insulating layer 106, and the conductive layer 117, and the conductive layer 112 is provided on the insulating layer 104.
  • the conductive layer 111, the insulating layer 106, and the conductive layer 117 can have regions where they overlap with each other through the insulating layer 103, and the insulating layer 106, the conductive layer 117, and the conductive layer 112 can have regions where they overlap with each other through the insulating layer 104. Therefore, the conductive layer 111 and the conductive layer 112 can have regions where they overlap with each other through the insulating layer 103 and the insulating layer 104.
  • the insulating layer 103, the insulating layer 106, the insulating layer 104, and the conductive layer 112 are provided with an opening 121 that reaches the conductive layer 111.
  • the opening 121 can be formed by processing a part of these layers, for example, by an etching method. In particular, processing by a dry etching method is preferable because it is suitable for fine processing.
  • FIGS. 2A1 and 2A2 show an example in which the shape of the opening 121 is circular in a plan view.
  • the processing precision when forming the opening 121 can be improved, and the opening 121 can be formed with a fine size.
  • a circle is not limited to a perfect circle.
  • the shape of the opening 121 in a plan view may be, for example, an ellipse.
  • 1, 2A1, and 2B show an example in which, in the X direction, the side end of conductive layer 111 is located outside the side end of conductive layer 117 that does not face opening 121, and the side end of conductive layer 117 that does not face opening 121 is located outside the side end of conductive layer 112 that does not face opening 121. That is, in the X direction, Fig.
  • 1, 2A1, and 2B show an example in which the side end of conductive layer 112 that does not face opening 121 overlaps conductive layer 117 and conductive layer 111, and the side end of conductive layer 117 that does not face opening 121 overlaps conductive layer 111, but the side end of conductive layer 111 does not overlap conductive layer 112 and conductive layer 117, and the side end of conductive layer 117 that does not face opening 121 does not overlap conductive layer 112.
  • the side end of the conductive layer 111 may be located inside the side end of the conductive layer 117 that does not face the opening 121, or may be located inside the side end of the conductive layer 112 that does not face the opening 121.
  • the side end of the conductive layer 117 may be located inside the side end of the conductive layer 112 that does not face the opening 121.
  • the semiconductor layer 113 is provided to cover the opening 121 and to have a region located inside the opening 121.
  • the semiconductor layer 113 can have a shape that conforms to the shapes of the upper surface of the conductive layer 111, the side surface of the insulating layer 103, the side surface of the insulating layer 106, the side surface of the insulating layer 104, and the side and upper surface of the conductive layer 112. As a result, the semiconductor layer 113 has a recess at a position that overlaps with the opening 121.
  • the semiconductor layer 113 can have a region in contact with the upper surface of the conductive layer 111, a region in contact with the side surface of the insulating layer 103, a region in contact with the side surface of the insulating layer 106, a region in contact with the side surface of the insulating layer 104, a region in contact with the side surface of the conductive layer 112, and a region in contact with the upper surface of the conductive layer 112.
  • the semiconductor layer 113 preferably covers the side end of the conductive layer 112 on the opening 121 side.
  • Figures 1, 2A1, 2B, and 2C show a configuration in which the side end of the semiconductor layer 113 is located on the conductive layer 112. This configuration can also be said to be such that the lower end of the semiconductor layer 113 contacts the upper surface of the conductive layer 112.
  • the side end of the semiconductor layer 113 may be located outside the side end of the conductive layer 112. In this case, the semiconductor layer 113 can cover the side of the conductive layer 112 that does not face the opening 121.
  • the upper end refers to the uppermost part of the side end
  • the lower end refers to the lowermost part of the side end.
  • the upper end and the lower end are each part of the side end.
  • Fig. 1, Fig. 2A1, Fig. 2B, and Fig. 2C show an example in which the semiconductor layer 113 is divided in both the X direction and the Y direction to form islands.
  • “island-like” refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.
  • the insulating layer 105 is provided so as to cover the opening 121 and have a region located inside the opening 121.
  • the insulating layer 105 is provided on the semiconductor layer 113, the conductive layer 112, and the insulating layer 104.
  • the insulating layer 105 can have a shape that follows the shapes of the upper surface and side surface of the semiconductor layer 113, the upper surface and side surface of the conductive layer 112, and the upper surface of the insulating layer 104. Since the insulating layer 105 has a shape that follows the upper surface and side surface of the semiconductor layer 113, the insulating layer 105 has a recess at a position overlapping the opening 121.
  • the insulating layer 105 can have a region in contact with the upper surface of the semiconductor layer 113, a region in contact with the side surface of the semiconductor layer 113, a region in contact with the upper surface of the conductive layer 112, a region in contact with the side surface of the conductive layer 112, and a region in contact with the upper surface of the insulating layer 104.
  • the conductive layer 115 is provided on the insulating layer 105 and can have a region in contact with the upper surface of the insulating layer 105 and the side surface of the recess.
  • the conductive layer 115 has a region located inside the opening 121.
  • the conductive layer 115 and the semiconductor layer 113 have regions that face each other across the insulating layer 105 at positions along the sidewalls and bottom of the opening 121.
  • the semiconductor layer 113 can be configured to cover the side surface and bottom surface of the conductive layer 115 through the insulating layer 105 inside the opening 121.
  • the insulating layer 105 can have a region in contact with the side surface of the semiconductor layer 113, a region in contact with the upper surface of the recess of the semiconductor layer 113, a region in contact with the side surface of the conductive layer 115, and a region in contact with the bottom surface of the conductive layer 115.
  • the transistor 100 shown in FIG. 1, FIG. 2B, and FIG. 2C is a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside an opening formed in an interlayer insulating layer.
  • the channel length direction of the transistor 100 can be set along the side surfaces of the insulating layers 103, 106, and 104 in the opening 121. Therefore, the channel length is not affected by the performance of the exposure device used to manufacture the transistor 100, so that the channel length can be made smaller than the limit resolution of the exposure device. Therefore, the on-current of the transistor 100 can be increased. As a result, a semiconductor device that operates at high speed can be provided. Note that, for example, FIG.
  • 2A1 shows an example in which the entire opening 121 has a region overlapping with the conductive layer 111, the semiconductor layer 113, and the conductive layer 115, but a part of the opening 121 does not have to overlap with at least one of the conductive layer 111, the semiconductor layer 113, and the conductive layer 115.
  • a portion of the conductive layer 115 is located outside the opening 121, i.e., on the conductive layer 112 and the insulating layer 104.
  • the side end of the conductive layer 115 may be located outside the side end of the semiconductor layer 113. In this case, the conductive layer 115 can cover the entire semiconductor layer 113.
  • an insulating layer 106 and a conductive layer 117 are provided between the insulating layer 103 and the insulating layer 104.
  • the insulating layer 106 covers a part of the side surface of the recess of the semiconductor layer 113.
  • the conductive layer 117 is provided outside the insulating layer 106 (the side opposite the opening 121). In other words, the insulating layer 106 is provided between the semiconductor layer 113 and the conductive layer 117.
  • the conductive layer 117 covers at least a portion of the side surface of the insulating layer 106.
  • the conductive layer 117 also covers a portion of the recessed side surface of the semiconductor layer 113 via the insulating layer 106.
  • the side surface of the insulating layer 106 at the opening 121 has an area that contacts the recessed side surface of the semiconductor layer 113
  • the side surface of the conductive layer 117 has an area that contacts the side surface of the insulating layer 106 on the opposite side to the opening 121.
  • the conductive layer 117 functions as a gate electrode
  • the insulating layer 106 functions as a gate insulating layer.
  • the insulating layer 104 can cover the upper surface of the insulating layer 106 and the upper surface and side surface of the conductive layer 117.
  • a recess 132 formed by an insulating layer 103, a conductive layer 117, and an insulating layer 104 is provided, and an insulating layer 106 is provided so as to have a region located inside the recess 132.
  • an opening 123 having a region overlapping with the opening 121 and including the recess 132 is provided in the conductive layer 117.
  • the opening 123 may include, for example, a region overlapping with the opening 121 and the recess 132.
  • the insulating layer 106 is provided in the region of the opening 123 between the insulating layer 103 and the insulating layer 104.
  • the shape of the opening 123 in a plan view can be the same as the shape of the opening 121 in a plan view.
  • FIG. 2A1 and FIG. 2A2 an example in which the shape of the opening 123 is circular in a plan view is shown. Note that the shape of the opening 123 in a plan view may be, for example, elliptical.
  • the transistor 100 is a transistor with a dual gate structure having two gate electrodes, and the conductive layer 115 functioning as the first gate electrode and the conductive layer 117 functioning as the second gate electrode are provided so as to have a region sandwiching the channel formation region of the semiconductor layer 113 inside the opening 121.
  • the magnitude of the current flowing through the channel formation region of the semiconductor layer 113 can be controlled based on the potential of the conductive layer 115, and the threshold voltage of the transistor 100 can be controlled based on the potential of the conductive layer 117.
  • the channel length of the transistor 100 is small, for example, smaller than the limit resolution of an exposure device.
  • the threshold voltage of the transistor 100 is small, and for example, the transistor 100 may have normally-on characteristics. Therefore, the threshold voltage of the transistor 100 is controlled by controlling the potential of the conductive layer 117, specifically, the threshold voltage of the transistor 100 is made larger than that of the transistor 100 without the conductive layer 117, thereby preventing the transistor 100 from having normally-on characteristics. In other words, the transistor 100 can have normally-off characteristics. Note that by controlling the threshold voltage of the transistor 100, the threshold voltage of the transistor 100 can be made smaller to increase the on-current of the transistor 100.
  • the variation in electrical characteristics of each transistor 100 can be reduced.
  • a semiconductor device with good electrical characteristics can be provided.
  • the transistor 100 is an n-channel transistor. Note that even when the transistor 100 is a p-channel transistor, one embodiment of the present invention can be applied by appropriately reversing the magnitude relationships of the various potentials and threshold voltages shown in this specification from the case where the transistor 100 is an n-channel transistor.
  • the first gate electrode can be referred to as a front gate electrode, and the second gate electrode can be referred to as a back gate electrode.
  • the insulating layer 105 can be the first gate insulating layer, and the insulating layer 106 can be the second gate insulating layer.
  • the first gate electrode and the second gate electrode may be interchanged.
  • the conductive layer 115 may be used as the second gate electrode, and the conductive layer 117 may be used as the first gate electrode.
  • the insulating layer 105 can be referred to as the second gate insulating layer, and the insulating layer 106 can be referred to as the first gate insulating layer.
  • the conductive layer 117 can be supplied with, for example, a constant potential. For example, supplying a ground potential or a negative potential to the conductive layer 117 can prevent the transistor 100 from becoming normally on. Note that the same potential as the potential of the conductive layer 115 may be supplied to the conductive layer 117. This can increase, for example, the on-current of the transistor 100.
  • the transistor 100 is an n-channel transistor, for example, the potential supplied to the conductive layer 117 when the transistor 100 is turned on may be higher than the potential supplied to the conductive layer 117 when the transistor 100 is turned off. For example, a positive potential may be supplied to the conductive layer 117 when the transistor 100 is turned on, and a ground potential or a negative potential may be supplied to the conductive layer 117 when the transistor 100 is turned off.
  • the electric field from the conductive layer 117 may not reach the region of the semiconductor layer 113 that is not covered by the conductive layer 117. If the electrical resistivity of the region of the semiconductor layer 113 that is not reached by the electric field from the conductive layer 117 is lower than the electrical resistivity of the region of the semiconductor layer 113 that is reached by the electric field from the conductive layer 117, this is preferable because, for example, the on-current of the transistor 100 can be increased.
  • the electrical resistivity of the region of the semiconductor layer 113 that is in contact with the insulating layer 103 and the region that is in contact with the insulating layer 104 is lower than the electrical resistivity of the region of the semiconductor layer 113 that is in contact with the insulating layer 106.
  • an insulator containing nitrogen when used as the insulating layer 103 and the insulating layer 104, nitrogen can be supplied to the semiconductor layer 113.
  • a metal oxide is used for the semiconductor layer 113, electrons that are carriers are generated in the semiconductor layer 113, and the carrier concentration may increase. Therefore, the electrical resistivity of, for example, the region of the semiconductor layer 113 that contacts the insulating layer 103 and the region that contacts the insulating layer 104 can be made lower than the electrical resistivity of the region of the semiconductor layer 113 that contacts the insulating layer 106.
  • An example of an insulator containing nitrogen is silicon nitride. Also, for example, silicon nitride oxide or aluminum nitride may be used as the insulating layer 103 and the insulating layer 104.
  • an insulator containing oxygen may be used as the insulating layer 103 and the insulating layer 104.
  • the insulating layer 103 and the insulating layer 104 disposed near the channel formation region of the semiconductor layer 113 contain oxygen that is desorbed by heating (hereinafter, sometimes referred to as excess oxygen).
  • excess oxygen oxygen that is desorbed by heating
  • insulators containing oxygen include silicon oxide and silicon oxynitride.
  • an insulator having a function of capturing hydrogen or a function of fixing hydrogen may be used as the insulating layer 103 and the insulating layer 104 disposed near the channel formation region of the semiconductor layer 113.
  • hydrogen in the channel formation region of the semiconductor layer 113 can be captured or fixed (also called gettering), and the hydrogen concentration in the semiconductor layer 113 can be reduced.
  • insulating layers 103 and 104 include magnesium oxide and aluminum oxide.
  • An insulating layer 107 is provided on the conductive layer 115 and on the insulating layer 105.
  • the insulating layer 107 can be provided so as to cover the top and side surfaces of the conductive layer 115.
  • the insulating layer 107 has a function of preventing impurities from entering the transistor 100, for example, preventing impurities from entering the semiconductor layer 113.
  • FIG. 1D shows an example in which the side end of the insulating layer 105 shown in FIG. 2C coincides or roughly coincides with the side end of the conductive layer 115.
  • FIG. 2D shows an example in which the side end of the insulating layer 105 shown in FIG. 2C coincides or roughly coincides with the side end of the conductive layer 115.
  • FIG. 3A is an enlarged view of the insulating layer 106 shown in FIGS. 2B to 2D and its vicinity.
  • FIG. 3A shows the insulating layer 103, the insulating layer 104, the semiconductor layer 113, and a part of the conductive layer 117.
  • the side of the insulating layer 106 can be coincident or approximately coincident with the side of the insulating layer 103 and the side of the insulating layer 104.
  • the side of the insulating layer 106 may not be coincident or approximately coincident with one or both of the side of the insulating layer 103 and the side of the insulating layer 104.
  • the side of the insulating layer 106 may be located closer to the conductive layer 117 than one or both of the side of the insulating layer 103 and the side of the insulating layer 104.
  • FIG. 3B is a diagram showing an example of a configuration in which the insulating layer 106 shown in FIG. 3A has a recess 133.
  • the semiconductor layer 113 can be provided inside the recess 133.
  • the insulating layer 106 can be shaped to follow the wall surface of the recess 132.
  • FIG. 3B is a diagram showing an example of a configuration in which the insulating layer 106 shown in FIG. 3A has a recess 133.
  • the semiconductor layer 113 can be provided inside the recess 133.
  • the insulating layer 106 can be shaped to follow the wall surface of the recess 132.
  • the distance d1 between the side of the conductive layer 117 and the side of the semiconductor layer 113 in the recess 133, the distance d2 between the top surface of the insulating layer 103 and the bottom surface of the semiconductor layer 113 in the recess 133, and the distance d3 between the bottom surface of the insulating layer 104 and the top surface of the semiconductor layer 113 in the recess 133 can all be the film thickness of the insulating layer 106.
  • the distances d1, d2, and d3 can be made to match or approximately match each other. Note that, for example, due to the formation process of the insulating layer 106, the distances d1, d2, and d3 may not match or approximately match each other.
  • FIG. 3B an example is shown in which the side of the insulating layer 106 in the region between the insulating layer 103 and the recess 133 in the opening 121 coincides or roughly coincides with the side of the insulating layer 103, and the side of the insulating layer 106 in the region between the insulating layer 104 and the recess 133 coincides or roughly coincides with the side of the insulating layer 104.
  • the side of the insulating layer 106 in the region between the insulating layer 103 and the recess 133 in the opening 121 may not coincide or roughly coincide with the side of the insulating layer 103, and may be located closer to the conductive layer 117 than the side of the insulating layer 103. Also, in the opening 121, the side of the insulating layer 106 in the region between the insulating layer 104 and the recess 133 may not coincide or roughly coincide with the side of the insulating layer 104, and may be located closer to the conductive layer 117 than the side of the insulating layer 104.
  • FIG. 4A is an enlarged view of the transistor 100 shown in FIG. 2C and its vicinity.
  • FIG. 4B shows a plan view of the XY plane of the transistor 100 shown in FIG. 4A, including the conductive layer 112. Note that FIG. 4B does not show the conductive layer 111 and the conductive layer 117.
  • the semiconductor layer 113 has a region 113i and regions 113na and 113nb arranged to sandwich the region 113i.
  • Region 113na is a region in contact with conductive layer 111 of semiconductor layer 113. At least a portion of region 113na functions as one of the source region and drain region of transistor 100.
  • Region 113nb is a region in contact with conductive layer 112 of semiconductor layer 113. At least a portion of region 113nb functions as the other of the source region and drain region of transistor 100.
  • conductive layer 112 contacts the entire outer periphery of semiconductor layer 113. Therefore, the other of the source region and drain region of transistor 100 can be formed on the entire outer periphery of a portion of semiconductor layer 113 formed in the same layer as conductive layer 112.
  • Region 113i is a region between regions 113na and 113nb of the semiconductor layer 113. At least a part of region 113i functions as a channel formation region of the transistor 100. That is, the channel formation region of the transistor 100 is located in a region of the semiconductor layer 113 between the conductive layer 111 and the conductive layer 112. It is also said that the channel formation region of the transistor 100 is located in a region of the semiconductor layer 113 that is in contact with the insulating layer 103 or in the vicinity thereof, a region that is in contact with the insulating layer 106 or in the vicinity thereof, and a region that is in contact with the insulating layer 104 or in the vicinity thereof.
  • the channel length of a transistor is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 100 is determined by the thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 on the conductive layer 111.
  • the channel length L of the transistor 100 is indicated by a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the end of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a cross-sectional view.
  • the channel length L corresponds to the length of the side of the insulating layer 103, the insulating layer 106, and the insulating layer 104 at the opening 121 in a cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the region where they overlap with the conductive layer 111. Therefore, the channel length of the transistor 100 can be made to be an extremely fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more) that is below the exposure limit of photolithography. This increases the on-current of the transistor 100. Therefore, a semiconductor device that operates at high speed can be provided.
  • OS transistors have higher resistance to short-channel effects than Si transistors.
  • the transistor 100 having the structure shown in FIG. 4A and FIG. 4B can have a shorter channel length than conventional transistors.
  • materials other than metal oxide, such as silicon, may be used for the semiconductor layer 113.
  • the channel formation region, the source region, and the drain region can be formed in the opening 121. This allows the area occupied by the transistor to be reduced compared to conventional transistors in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the semiconductor device to be miniaturized.
  • the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged concentrically. Therefore, the side of the conductive layer 115 arranged in the center faces the side of the semiconductor layer 113 through the insulating layer 105. That is, in a plan view, the entire outer periphery of the semiconductor layer 113 becomes the channel formation region. At this time, for example, the channel width of the transistor 100 is determined by the length of the outer periphery of the semiconductor layer 113.
  • the channel width of the transistor 100 is determined by the size of the maximum width of the opening 121 (maximum diameter when the opening 121 is circular in a plan view).
  • the maximum width D of the opening 121 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 100 is indicated by a double-dot chain line of a one-dot chain line.
  • the maximum width D of the opening 121 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the maximum width D of the opening 121 corresponds to the diameter of the opening 121, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 100 is preferably at least smaller than the channel width W of the transistor 100.
  • the channel length L of the transistor 100 is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 100.
  • the semiconductor layer 113 the insulating layer 105, and the conductive layer 115 in a concentric manner, the distance between the conductive layer 115 and the semiconductor layer 113 becomes approximately uniform. Therefore, a gate electric field can be applied approximately uniformly to the semiconductor layer 113.
  • the sidewalls of the opening 121 are preferably perpendicular to the top surface of the conductive layer 111, for example. With such a configuration, the transistor 100 can be miniaturized. Note that the sidewalls of the opening 121 may be tapered.
  • the semiconductor layer 113 can be made of a metal oxide described in the section [Metal oxide] below, in a single layer or a multilayer structure.
  • the semiconductor layer 113 can be made of a material such as silicon described in the section [Other semiconductor materials] below, in a single layer or a multilayer structure.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • energy dispersive X-ray spectrometry EDX
  • XPS XPS
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the atomic layer deposition (ALD) method can be suitably used to form metal oxides.
  • the metal oxide may be formed by sputtering or chemical vapor deposition (CVD).
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the metal oxide used for the semiconductor layer 113 is preferably crystalline.
  • crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, and single crystal oxide semiconductor. It is preferable to use CAAC-OS or nc-OS as the semiconductor layer 113, and it is particularly preferable to use CAAC-OS.
  • CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the semiconductor layer 113 preferably has layered crystals that are approximately parallel to the sidewall of the opening 121, particularly the side surfaces of the insulating layers 103, 106, and 104. With this configuration, the layered crystals of the semiconductor layer 113 are formed approximately parallel to the channel length direction of the transistor 100, thereby increasing the on-current of the transistor 100.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies, etc.).
  • a temperature e.g. 400° C. or higher and 600° C. or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the semiconductor layer 113 by using a crystalline metal oxide such as CAAC-OS as the semiconductor layer 113, it is possible to suppress the extraction of oxygen from the semiconductor layer 113 by the source electrode or drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the semiconductor layer 113, so that the transistor 100 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline metal oxide such as CAAC-OS
  • the crystallinity of the semiconductor layer 113 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the thickness of the semiconductor layer 113 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the semiconductor layer 113 may have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above metal oxides are appropriately stacked may be used.
  • the semiconductor layer 113 can have a region in contact with the conductive layer 111 and a region in contact with the conductive layer 112.
  • a metal compound or oxygen deficiency may be formed, and the region 113na of the semiconductor layer 113 may have a low resistance.
  • the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.
  • the region 113nb of the semiconductor layer 113 may have a low resistance. Therefore, the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced.
  • silicon oxide or silicon oxynitride can be used as the insulating layer 105 and the insulating layer 106, which function as gate insulating layers. Silicon oxide and silicon oxynitride are preferable because they are stable to heat.
  • the insulating layers 105 and 106 may be made of a material having a high relative dielectric constant, so-called high-k material, as described in the section [Insulator] below.
  • high-k material a material having a high relative dielectric constant
  • hafnium oxide or aluminum oxide may be used.
  • the thickness of the insulating layer 105 and the insulating layer 106 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm.
  • the insulating layer 105 and the insulating layer 106 preferably have a region with the above-mentioned thickness in at least a part.
  • the thickness of the insulating layer 106 indicates the distance between the side of the insulating layer 106 and the side opposite to that side, for example, the distance in the horizontal direction (direction perpendicular to the Z direction).
  • the concentration of impurities such as water and hydrogen in the insulating layer 105 and the insulating layer 106 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.
  • the insulating layer 105 and the insulating layer 106 are shown as single layers in FIG. 1, FIG. 2B, FIG. 2C, and the like, one embodiment of the present invention is not limited to this.
  • the insulating layer 105 and the insulating layer 106 may have a stacked structure.
  • the conductive layer 115 that functions as a gate electrode can be made of a conductive material with high conductivity, such as tungsten, aluminum, or copper.
  • an alloy can be used for the conductive layer 115, such as an alloy of aluminum and titanium (Al-Ti).
  • the conductive layer 115 it is preferable to use a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing the diffusion of oxygen, as the conductive layer 115.
  • the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride), and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 115.
  • a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used as the conductive layer 115.
  • the conductive layer 115 is shown as a single layer in FIG. 1, FIG. 2B, FIG. 2C, and the like, one embodiment of the present invention is not limited to this.
  • the conductive layer 115 may have a stacked structure.
  • the conductive layer 111 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen for example, titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride is in contact with the insulating layer 101, and tantalum nitride is in contact with the semiconductor layer 113. With such a structure, excessive oxidation of the conductive layer 111 by the semiconductor layer 113 can be suppressed.
  • the conductive layer 111 may be made of a structure in which tungsten is stacked on titanium nitride, for example.
  • the conductive layer 111 has a region in contact with the semiconductor layer 113, it is preferable to use a conductive material containing oxygen.
  • a conductive material containing oxygen for the conductive layer 111, the conductive layer 111 can maintain conductivity even if it absorbs oxygen.
  • indium tin oxide also referred to as ITO
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • the like can be used as a single layer or a stacked layer for the conductive layer 111.
  • 1, 2B to 2D, and 4A show a configuration in which the upper surface of the conductive layer 111 is flat, but the present invention is not limited to this.
  • a configuration in which a recess that overlaps with the opening 121 is formed on the upper surface of the conductive layer 111 may be used.
  • the conductive layer 112 can be made of a highly conductive material, such as tungsten, aluminum, or copper.
  • the conductive layer 112 is preferably made of a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • titanium nitride or tantalum nitride can be used. With such a structure, the conductive layer 112 can be prevented from being excessively oxidized by the semiconductor layer 113.
  • the conductive layer 112 may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide.
  • a structure in which tungsten is laminated on titanium nitride may be used.
  • the conductivity of the conductive layer 112 can be improved.
  • the conductive layer 112 has a laminated structure of a first conductive layer and a second conductive layer
  • a conductive material with high conductivity may be used for the first conductive layer
  • a conductive material containing oxygen may be used for the second conductive layer.
  • a conductive material containing oxygen as the second conductive layer, whose area in contact with the insulating layer 105 is larger than that of the first conductive layer, it is possible to suppress the diffusion of oxygen in the insulating layer 105 to the first conductive layer of the conductive layer 112.
  • tungsten may be used as the first conductive layer of the conductive layer 112
  • indium tin oxide with added silicon may be used as the second conductive layer of the conductive layer 112.
  • the insulating layer 101 preferably has a low dielectric constant. This reduces the parasitic capacitance that occurs between wiring lines.
  • a single layer or a multilayer of an insulator containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulating layer 101 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.
  • the insulating layer 107 it is preferable to use an insulator having barrier properties against hydrogen, as described in the [Insulator] section below. This can prevent hydrogen from diffusing from the outside of the transistor 100 to the semiconductor layer 113 through the insulating layer 105.
  • Silicon nitride and silicon nitride oxide each have the characteristics of releasing little impurities such as water and hydrogen from themselves, and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 107.
  • an insulator having a function of capturing hydrogen or a function of fixing hydrogen as described in the section [Insulator] below, as the insulating layer 107.
  • an insulator having a function of capturing hydrogen or a function of fixing hydrogen as described in the section [Insulator] below.
  • Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as the insulating layer 107.
  • a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 107.
  • the configuration in which the insulating layer 107 is formed on the top surface of the transistor 100 is shown, but the present invention is not limited to this.
  • the insulating layer 107 or an insulating layer having the same function and material as the insulating layer 107 may be formed on the side and bottom surfaces of the transistor 100, and the transistor 100 may be surrounded by the insulating layer 107. With this configuration, impurities such as water and hydrogen can be prevented from entering the inside of the transistor 100.
  • 5A1, 5A2, 5B, and 5C are diagrams showing examples of a configuration in which the conductive layer 117 shown in FIGS. 2A1, 2A2, 2B, and 2C has an oxide region 117ox.
  • the oxide region 117ox can be formed by oxidizing the side surface of the conductive layer 117 at the opening 123.
  • the oxide region 117ox covers at least a part of the side surface of the insulating layer 106, and has a region in contact with, for example, the side surface of the insulating layer 106 opposite to the opening 121.
  • the oxide region 117ox is a region having a higher electrical resistivity than the conductive layer 117 and has insulating properties.
  • the oxide region 117ox can be a region having a higher electrical resistivity than the semiconductor layer 113. Note that the oxide region 117ox does not need to be oxidized as long as it has insulating properties.
  • the oxide region 117ox can be referred to as a high-resistance region.
  • the insulating layer 106 not only the insulating layer 106 but also the oxide region 117ox can function as the second gate insulating layer of the transistor 100.
  • the thickness of the second gate insulating layer of the transistor 100 can be ensured. This can prevent a short circuit between the semiconductor layer 113 and the second gate electrode of the transistor 100 (the non-oxidized region of the conductive layer 117).
  • the oxide region 117ox is included in the conductive layer 117, that is, the oxide region 117ox can be part of the conductive layer 117. Note that the oxide region 117ox does not necessarily have to be included in the conductive layer 117.
  • a material that increases electrical resistivity by a chemical reaction such as oxidation and becomes, for example, insulating is used for the conductive layer 117.
  • a metal or a metal nitride can be used for the conductive layer 117.
  • materials that can be used for the conductive layer 117 include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, and tungsten.
  • the oxide region 117ox contains an oxide of the material contained in the conductive layer 117.
  • the oxide region 117ox contains tantalum oxide
  • titanium nitride is used as the conductive layer 117
  • the oxide region 117ox contains titanium oxide.
  • the oxide region 117ox may contain, for example, nitrogen.
  • the oxide region 117ox of the conductive layer 117 can be formed by forming an insulating film that will become the insulating layer 106 on the conductive layer 111 and the conductive layer 112 so as to have a region in contact with the side surface of the conductive layer 117 after the conductive layer 111, the conductive layer 117, and the conductive layer 112 are formed, and then performing an oxidation treatment.
  • the oxidation treatment can be a microwave treatment in an atmosphere containing oxygen.
  • the insulating film can be processed by, for example, anisotropic etching to form the insulating layer 106.
  • microwave processing refers to processing using a device having a power source that generates high-density plasma using microwaves.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • Microwave processing can also be called microwave-excited high-density plasma processing.
  • the oxidation treatment is performed not only on the conductive layer 117 but also on the conductive layer 111 and the conductive layer 112. Therefore, when the oxide region 117ox is formed in the conductive layer 117, a material that is less likely to be oxidized than the conductive layer 117 or a material that has conductivity even when oxidized is used for the conductive layer 111 and the conductive layer 112. For example, a conductive material containing oxygen can be used for the conductive layer 111 and the conductive layer 112.
  • indium tin oxide also referred to as ITO
  • indium tin oxide with silicon added also referred to as ITSO
  • indium zinc oxide also referred to as IZO (registered trademark)
  • ITO indium tin oxide
  • ITSO indium tin oxide with silicon added
  • IZO indium zinc oxide
  • the like can be used as a single layer or a stacked layer for the conductive layer 111 and the conductive layer 112.
  • the above-mentioned oxidation treatment can be performed to make the oxide region 117ox a region containing the components contained in the conductive layer 117 and the components contained in the insulating layer 106.
  • the oxide region 117ox can be said to be an alloyed region.
  • the oxide region 117ox can be a region containing tantalum, silicon, oxygen, and nitrogen.
  • the oxide region 117ox can be a region containing tungsten, silicon, and oxygen.
  • the conductive layer 112 and the insulating film that will become the insulating layer 106 may be alloyed. This may allow the conductive layer 112 to contain silicon, for example. For example, when the conductive layer 112 is formed using ITO, the conductive layer 112 may be allowed to contain ITSO. Similarly, the conductive layer 111 and the insulating film that will become the insulating layer 106 may be alloyed.
  • the shape of the oxide region 117ox in plan view can be the same as the shape of the insulating layer 106 in plan view.
  • FIG. 5A2 shows an example in which the shape of the oxide region 117ox in plan view is the same as the shape of the insulating layer 106 in plan view.
  • an example is shown in which the shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 in plan view is the same as the shape of the outer periphery of the opening 123 in plan view.
  • FIG. 5A2 shows an example in which the shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 in plan view is the same as the shape of the outer periphery of the opening 123 in plan view.
  • 5A2 shows an example in which the shape of the boundary between the oxide region 117ox and the non-oxidized region of the conductive layer 117 in plan view and the shape of the outer periphery of the opening 123 in plan view are both circular.
  • one embodiment of the present invention is not limited to this, and the type of shape of the oxide region 117ox in plan view and the type of shape of the insulating layer 106 in plan view may be different.
  • Figures 6A and 6B are diagrams showing the conductive layer 111 shown in Figures 5B and 5C, respectively, in a two-layer stacked structure of a conductive layer 111a and a conductive layer 111b on the conductive layer 111a.
  • Figure 6C is an enlarged view of the conductive layer 111 shown in Figure 6B and the area nearby.
  • Figure 6C shows a region 113na, at least a part of which functions as one of the source region and drain region of the transistor 100, and a region 113i, at least a part of which functions as a channel formation region of the transistor 100.
  • the opening 121 is also provided in the conductive layer 111b and reaches the conductive layer 111a.
  • the semiconductor layer 113 can have a region inside the opening 121 that contacts the top surface of the conductive layer 111a and a region that contacts the side surface of the conductive layer 111b.
  • the conductive layer 117 is oxidized to form an oxide region 117ox, and then the region of the conductive layer 111b that overlaps with the opening 121 is removed. This allows the opening 121 to reach the conductive layer 111a.
  • a recess having a region that overlaps with the opening 121 may be provided in the conductive layer 111a.
  • the opening 121 may not reach the conductive layer 111a, and a recess having a region that overlaps with the opening 121 may be provided in the conductive layer 111b.
  • the transistor 100 has the structure shown in FIG. 6A to FIG. 6C, a part of the conductive layer 111b is removed after the oxidation treatment. As a result, even if the conductive layer 111b is oxidized by the oxidation treatment, at least a part of the region of the conductive layer 111 oxidized by the oxidation treatment can be removed. Therefore, the electrical resistance at the contact interface between the conductive layer 111 and the semiconductor layer 113 can be reduced. As a result, for example, when the transistor 100 is in an on state, it is possible to suppress the current from flowing between the conductive layer 111 and the conductive layer 112 of the semiconductor layer 113 and the current flowing from being reduced. Therefore, a highly reliable semiconductor device can be provided.
  • the oxide region 117ox is formed in the conductive layer 117, for example, a material having low oxidation resistance but high conductivity can be used for the conductive layer 111. This allows the range of materials to be selected for the conductive layer 111 to be expanded. Note that, as shown in FIG. 5B and FIG. 5C, even when the conductive layer 111 is, for example, a single layer, at least a part of the oxidized region of the conductive layer 111 may be removed after the oxidation treatment. In this case, a recess having an area overlapping with the opening 121 is provided in the conductive layer 111.
  • the conductive layer 111 and the conductive layer 115 have regions that face each other along the sidewall of the opening 121, sandwiching the semiconductor layer 113 and the insulating layer 105 therebetween.
  • the conductive layer 111a and the conductive layer 111b can be made of a conductor described in the section [Conductor] described later.
  • a conductive material having high conductivity such as tungsten, aluminum, or copper, can be used as one or both of the conductive layer 111a and the conductive layer 111b.
  • a conductive material containing oxygen can be used as one or both of the conductive layer 111a and the conductive layer 111b, similar to the conductive layer 111 shown in FIG. 2B and FIG. 2C.
  • tungsten can be used as one of the conductive layer 111a and the conductive layer 111b, and indium tin oxide to which silicon has been added can be used as the other of the conductive layer 111a and the conductive layer 111b.
  • the conductive layer 111 may have a stacked structure of three or more layers.
  • the conductive layer 111 shown in Figures 1, 2B, 2C, 2D, and 4A may have a two-layer structure of conductive layer 111a and conductive layer 111b on conductive layer 111a.
  • the opening 121 may reach conductive layer 111a, or may reach conductive layer 111b but not conductive layer 111a. If the opening 121 reaches conductive layer 111b but not conductive layer 111a, the semiconductor layer 113 may have a region in contact with the upper surface of conductive layer 111b.
  • Figures 7A and 7B show examples in which the sidewalls of the opening 121 shown in Figures 2B and 2C, respectively, are tapered, i.e., the side surfaces of the insulating layer 103, insulating layer 106, insulating layer 104, and conductive layer 112 in the opening 121 are tapered.
  • the angle ⁇ between the side surface of the insulating layer 103 in the opening 121 and the top surface of the conductive layer 111 is preferably 45 degrees or more and less than 90 degrees, more preferably 45 degrees or more and 75 degrees or less, and even more preferably 45 degrees or more and 65 degrees or less.
  • the sidewall of the opening 121 may be perpendicular to the top surface of the conductive layer 111. In other words, the angle ⁇ may be 90 degrees.
  • the shape of the opening 121 shown in Figures 7A and 7B is a truncated cone.
  • the opening 121 is circular in plan view and trapezoidal in cross-sectional view.
  • the area of the upper base surface of the truncated cone e.g., the upper surface of the opening 121 provided in the conductive layer 112 is larger than the area of the lower base surface of the truncated cone (the upper surface of the conductive layer 111 exposed by the opening 121).
  • the maximum diameter of the opening 121 may be calculated based on the upper base surface of the truncated cone.
  • the channel length can be set by the film thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the region overlapping with the conductive layer 111, and the angle ⁇ between the side surface of the insulating layer 103 in the opening 121 and the top surface of the conductive layer 111.
  • the outer periphery of the semiconductor layer 113 in a planar view may be determined, for example, at the position of the region in contact with the conductive layer 112 or at a position half the thickness of the conductive layer 117. If necessary, the periphery at any position (depth) of the opening 121 may be the channel width of the transistor 100.
  • the periphery at the bottom of the opening 121 may be the channel width
  • the periphery at the top of the opening 121 may be the channel width.
  • FIG. 7A and 7B show an example in which the side of the conductive layer 112 in the opening 121, the side of the insulating layer 104 in the opening 121, the side of the insulating layer 106 in the opening 121, and the side of the insulating layer 103 in the opening 121 are provided on the same plane, but one embodiment of the present invention is not limited to this.
  • the side of the conductive layer 112 in the opening 121 and the side of the insulating layer 104 in the opening 121 may be discontinuous.
  • At least one of the inclination of the side of the conductive layer 112 in the opening 121, the inclination of the side of the insulating layer 104 in the opening 121, the inclination of the side of the insulating layer 106 in the opening 121, and the inclination of the side of the insulating layer 103 in the opening 121 may be different from the others.
  • the angle formed by the side of the conductive layer 112 in the opening 121 and the upper surface of the conductive layer 111 is preferably smaller than the angle ⁇ . This configuration improves coverage of the semiconductor layer 113 on the side surface of the conductive layer 112 in the opening 121, reducing defects such as voids.
  • the bottom of the conductive layer 115 located inside the opening 121 has a flat region. Note that depending on the size of the maximum width of the opening 121 (maximum diameter when the opening 121 is circular in plan view), the film thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the area overlapping with the conductive layer 111 (corresponding to the depth of the opening 121), the film thickness of the semiconductor layer 113, and the film thickness of the insulating layer 105, the bottom of the conductive layer 115 located inside the opening 121 may not have a flat region.
  • Figures 7C and 7D show an example in which the bottom shape of the conductive layer 115 located inside the opening 121 shown in Figures 7A and 7B is needle-shaped.
  • needle-like refers to a shape that becomes thinner toward the tip (approaching the bottom of the conductive layer 115 located inside the opening 121).
  • the tip of the needle may be acute-angled or may have a downwardly convex curved shape.
  • a needle-like shape with an acute-angled tip may be called a V-shape.
  • the conductive layer 115 located inside the opening 121 the region facing the semiconductor layer 113 via the insulating layer 105 functions as a gate electrode. Therefore, the conductive layer 115 embedded in the opening 121 and having a needle-shaped bottom may be called a needle-shaped gate. Also, as shown in Figures 7A and 7B, even if the conductive layer 115 has a shape with a flat bottom, it may be called a needle-shaped gate in some cases.
  • the sidewall of the opening 121 may have a reverse tapered shape.
  • the angle ⁇ may be greater than 90 degrees.
  • the inverted taper shape is a shape having a side or top that protrudes in a direction parallel to the substrate from the bottom.
  • the shape of the opening 121 is a truncated cone.
  • the opening 121 is circular in a plan view, and the opening 121 is trapezoidal in a cross-sectional view.
  • the area of the upper bottom surface of the truncated cone shape (for example, the upper surface of the opening 121 provided in the conductive layer 112) is smaller than the area of the lower bottom surface of the truncated cone shape (the upper surface of the conductive layer 111 exposed in the opening 121). With this configuration, the area of contact between the semiconductor layer 113 and the conductive layer 111 can be increased.
  • Figures 8A and 8B are diagrams showing the insulating layer 103 and insulating layer 104 shown in Figures 2B and 2C, respectively, in a three-layer laminate structure.
  • the insulating layer 103 has an insulating layer 103a, an insulating layer 103b on insulating layer 103a, and an insulating layer 103c on insulating layer 103b.
  • the insulating layer 104 has an insulating layer 104a, an insulating layer 104b on insulating layer 104a, and an insulating layer 104c on insulating layer 104b.
  • an insulator containing, for example, nitrogen, such as silicon nitride, silicon nitride oxide, or aluminum nitride can be used.
  • the insulating layers 103b and 104b can be planarized layers. It is preferable that the insulating layer 103b is a layer that is more easily planarized than the insulating layer 103a, and it is preferable that the insulating layer 104b is a layer that is more easily planarized than the insulating layer 104a.
  • an insulator containing, for example, oxygen, such as silicon oxide can be used.
  • the electrical resistivity of the region of the semiconductor layer 113 that contacts the insulating layer 103a, the region that contacts the insulating layer 103c, the region that contacts the insulating layer 104a, and the region that contacts the insulating layer 104c can be lower than the electrical resistivity of the region of the semiconductor layer 113 that contacts the insulating layer 106, and can also be lower than the electrical resistivity of the region of the semiconductor layer 113 that contacts the insulating layer 103b and the region that contacts the insulating layer 104b.
  • the insulating layer 103 and the insulating layer 104 can be planarized, and the electrical resistivity of at least a part of the region of the semiconductor layer 113 that contacts the insulating layer 103 and the region that contacts the insulating layer 104 can be made lower than the electrical resistivity of the region of the semiconductor layer 113 that contacts the insulating layer 106, for example.
  • This makes it possible to provide a semiconductor device that is easy to manufacture and operates faster than when the insulating layer 103 and the insulating layer 104 do not have a layer containing nitrogen, for example.
  • the thicknesses of the insulating layers 103b and 104b are made thin, the height of the region of the semiconductor layer 113 where the electric field from the conductive layer 117 does not reach and does not contain nitrogen, for example, can be reduced, so that the on-current of the transistor 100 can be increased.
  • the thickness of insulating layer 103b the parasitic capacitance formed by conductive layer 111, insulating layer 103, and conductive layer 117 can be reduced
  • the thickness of insulating layer 104b the parasitic capacitance formed by conductive layer 117, insulating layer 104, and conductive layer 112 can be reduced.
  • FIG. 8C and 8D show an example in which the insulating layer 103b and the insulating layer 104b shown in FIG. 8A and FIG. 8B are not in contact with the semiconductor layer 113.
  • the upper surface of the insulating layer 103a and the upper surface of the insulating layer 103b can be made to coincide or approximately coincide with each other, and the upper surface of the insulating layer 104a and the upper surface of the insulating layer 104b can be made to coincide or approximately coincide with each other.
  • the upper surface of the insulating layer 103a can have an area in contact with the insulating layer 103c in addition to an area in contact with the insulating layer 103b
  • the upper surface of the insulating layer 104a can have an area in contact with the insulating layer 104c in addition to an area in contact with the insulating layer 104b.
  • the configuration shown in FIG. 8C and FIG. 8D can be manufactured, for example, by performing the planarization process of the insulating layer 103b and the insulating layer 104b for a longer time than the case of manufacturing the configuration shown in FIG. 8A and FIG. 8B.
  • the channel length of the transistor 100 can be shortened, for example, compared to the example shown in FIG. 8A and FIG. 8B, and therefore the on-current of the transistor 100 can be increased.
  • the parasitic capacitance formed by the conductive layer 111, the insulating layer 103, and the conductive layer 117, and the parasitic capacitance formed by the conductive layer 117, the insulating layer 104, and the conductive layer 112 can be reduced, compared to the example shown in FIG. 8C and FIG. 8D.
  • the insulating layer 103b and the insulating layer 104b contain excess oxygen, thereby reducing the VoH in the channel formation region of the semiconductor layer 113. This stabilizes the electrical characteristics of the transistor 100 and improves its reliability.
  • the insulating layer 103c has a region in contact with the bottom surface of the conductive layer 117, and the insulating layer 104a can have a region in contact with the top surface and side surface of the conductive layer 117.
  • the insulating layer 103c and the insulating layer 104a are insulating layers that do not contain oxygen, even if the insulating layer 103b and the insulating layer 104b contain oxygen, for example, the region of the conductive layer 117 away from the semiconductor layer 113 can be suppressed from being oxidized. Therefore, an increase in the wiring resistance of the conductive layer 117 can be suppressed.
  • the insulating layer 104c is an insulating layer that does not contain oxygen, even if the insulating layer 104b contains oxygen, for example, the conductive layer 112 can be suppressed from being oxidized.
  • the insulating layer 104c may not be provided, and the insulating layer 104 may have a two-layer structure of the insulating layer 104a and the insulating layer 104b.
  • FIGS. 9A, 9B, and 9C are diagrams in which the conductive layer 117 shown in FIGS. 2A1, 2B, and 2C has a planar shape. Note that the conductive layer 117 may also have a strip shape extending in the X direction.
  • Figures 10A and 10B are diagrams showing a stacked structure of the semiconductor layer 113, insulating layer 105, and conductive layer 115 shown in Figures 2B and 2C, respectively.
  • Figure 10C is an enlarged view of the transistor 100 shown in Figure 10B.
  • the semiconductor layer 113 has a two-layer structure of a semiconductor layer 113a and a semiconductor layer 113b on the semiconductor layer 113a.
  • the insulating layer 105 has a three-layer structure of an insulating layer 105a, an insulating layer 105b on the insulating layer 105a, and an insulating layer 105c on the insulating layer 105b.
  • the conductive layer 115 has a two-layer structure of a conductive layer 115a and a conductive layer 115b on the conductive layer 115a.
  • the conductivity of the material used for semiconductor layer 113a is preferably different from the conductivity of the material used for semiconductor layer 113b.
  • the semiconductor layer 113a can be made of a material having a higher conductivity than the semiconductor layer 113b.
  • the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced. This allows the transistor 100 to have a large on-state current.
  • the threshold voltage of the transistor 100 becomes small, and the transistor 100 may become normally-on. Therefore, it is preferable to use a material with lower conductivity than the semiconductor layer 113a for the semiconductor layer 113b. This can increase the threshold voltage of the transistor 100, and can prevent the transistor 100 from becoming normally-on. In other words, the transistor 100 can become normally-off.
  • the transistor 100 can have normally-off characteristics and a large on-current. Therefore, a semiconductor device that consumes low power and operates at high speed can be provided.
  • the carrier concentration of the semiconductor layer 113a is preferably higher than that of the semiconductor layer 113b. Increasing the carrier concentration of the semiconductor layer 113a increases the conductivity, and the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112 can be reduced. This allows the transistor 100 to have a large on-current. In addition, decreasing the carrier concentration of the semiconductor layer 113b decreases the conductivity, and the transistor 100 can have normally-off characteristics.
  • the semiconductor layer 113a is made of a material having a higher conductivity than the semiconductor layer 113b, but one embodiment of the present invention is not limited to this.
  • the semiconductor layer 113a may be made of a material having a lower conductivity than the semiconductor layer 113b.
  • the carrier concentration of the semiconductor layer 113a can be lower than the carrier concentration of the semiconductor layer 113b.
  • the band gap of the first metal oxide used in the semiconductor layer 113a is preferably different from the band gap of the second metal oxide used in the semiconductor layer 113b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the semiconductor layer 113a can be smaller than the band gap of the second metal oxide used in the semiconductor layer 113b. This can reduce the contact resistance between the semiconductor layer 113 and the conductive layer 111 and the contact resistance between the semiconductor layer 113 and the conductive layer 112, and the transistor 100 can have a large on-current. In addition, the threshold voltage of the transistor 100 can be increased, and the transistor 100 can have normally-off characteristics.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide, but one aspect of the present invention is not limited to this.
  • the band gap of the first metal oxide may be equal to or larger than the band gap of the second metal oxide.
  • the band gap of the first metal oxide used in the semiconductor layer 113a can be smaller than the band gap of the second metal oxide used in the semiconductor layer 113b.
  • the composition of the first metal oxide is preferably different from the composition of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxide
  • the first metal oxide may not contain element M.
  • the first metal oxide used in the semiconductor layer 113a may be In-Zn oxide
  • the second metal oxide used in the semiconductor layer 113b may be In-M-Zn oxide.
  • the first metal oxide may be In-Zn oxide
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide may have different compositions, and the contents of elements other than element M may be different.
  • the second metal oxide may be used for the semiconductor layer 113a
  • the first metal oxide may be used for the semiconductor layer 113b.
  • the thickness of the semiconductor layer 113 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer constituting the semiconductor layer 113 may be determined so that the thickness of the semiconductor layer 113 falls within the above-mentioned range.
  • the thickness of the semiconductor layer 113a can be determined so that the contact resistance between the semiconductor layer 113a and the conductive layer 111 and the contact resistance between the semiconductor layer 113a and the conductive layer 112 fall within the desired range.
  • the thickness of the semiconductor layer 113b can be determined so that the threshold voltage of the transistor 100 falls within the desired range. Note that the thickness of the semiconductor layer 113a may be the same as or different from the thickness of the semiconductor layer 113b.
  • 10A to 10C show a configuration in which the semiconductor layer 113 has a two-layer stacked structure of the semiconductor layer 113a and the semiconductor layer 113b, but one embodiment of the present invention is not limited to this.
  • the semiconductor layer 113 may have a stacked structure of three or more layers.
  • the on-current of the transistor 100 can be increased.
  • the variation in the electrical characteristics of the transistor 100 can be reduced, improving the reliability of the semiconductor device.
  • the insulating layer 105a is preferably made of an insulator having a barrier property against oxygen, as described in the section [Insulator] below.
  • the insulating layer 105a has a region in contact with the semiconductor layer 113.
  • the insulating layer 105a has a barrier property against oxygen, it is possible to suppress oxygen from being released from the semiconductor layer 113, for example, during heat treatment. Thus, it is possible to suppress the formation of oxygen vacancies in the semiconductor layer 113. This can improve the electrical characteristics of the transistor 100 and improve the reliability of the semiconductor device of one embodiment of the present invention.
  • aluminum oxide is preferably used as the insulating layer 105a.
  • the insulating layer 105a contains at least oxygen and aluminum.
  • the insulating layer 105b is preferably made of a material with a low dielectric constant, as described in the [Insulator] section below.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulating layer 105b contains at least oxygen and silicon.
  • the insulating layer 105c it is preferable to use an insulator having a barrier property against hydrogen, as described in the [Insulator] section below. This can suppress the diffusion of impurities contained in the conductive layer 115 into the semiconductor layer 113.
  • silicon nitride has a high hydrogen barrier property and is therefore suitable for the insulating layer 105c.
  • the insulating layer 105c contains at least nitrogen and silicon.
  • the insulating layer 105c may further have a barrier property against oxygen.
  • the insulating layer 105c is provided between the insulating layer 105b and the conductive layer 115. This prevents the oxygen contained in the insulating layer 105b from diffusing into the conductive layer 115, and suppresses oxidation of the conductive layer 115.
  • an insulator may be provided between the insulating layer 105b and the insulating layer 105c.
  • the insulator it is preferable to use an insulator having a function of capturing or fixing hydrogen, as described in the section [Insulator] below.
  • the insulator hydrogen contained in the semiconductor layer 113 can be captured or fixed more effectively. Therefore, the hydrogen concentration in the semiconductor layer 113 can be reduced.
  • hafnium oxide is preferably used as the insulator.
  • the insulator contains at least oxygen and hafnium.
  • the insulator may have an amorphous structure.
  • the thicknesses of the insulating layers 105a to 105c are preferably thin and within the above-mentioned range.
  • the thicknesses of the insulating layer 105a, the insulating layer 105b, the insulator having the function of capturing or fixing hydrogen, and the insulating layer 105c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a configuration, the transistor 100 can have good electrical characteristics even when miniaturized.
  • each layer included in the insulating layer 105 may be appropriately selected from the insulating layers 105a to 105c and an insulator that has a function of capturing or fixing hydrogen.
  • the conductive layer 115 has a two-layer structure of conductive layer 115a and conductive layer 115b
  • titanium nitride can be used for conductive layer 115a and tungsten can be used for conductive layer 115b.
  • tungsten can be used for conductive layer 115b.
  • 10A to 10C show a configuration in which the conductive layer 115 has a two-layer stacked structure of a conductive layer 115a and a conductive layer 115b, but one embodiment of the present invention is not limited to this.
  • the conductive layer 115 may have a stacked structure of three or more layers.
  • Figure 11A shows an example in which the shapes of openings 121 and 123 shown in Figure 2A2 are quadrangular in plan view.
  • the shapes of openings 121 and 123 are square in plan view, but the shapes of openings 121 and 123 are not limited to this and may be, for example, rectangular, rhombus, or parallelogram in plan view.
  • the shapes of openings 121 and 123 may be, for example, triangular, or polygonal with pentagons or more sides, or may be star-shaped in plan view.
  • Figure 11B shows an example in which the corners of the opening 121 shown in Figure 11A are rounded. That is, Figure 11B shows an example in which the shape of the opening 121 and the opening 123 is a rectangle with rounded corners in a planar view. Note that in Figure 11B, the shape of the opening 121 and the opening 123 is a square with rounded corners in a planar view, but the shape of the opening 121 and the opening 123 is not limited to this, and may be, for example, a rectangle with rounded corners, a rhombus with rounded corners, a parallelogram with rounded corners, a triangle with rounded corners, a polygon with 5 or more sides with rounded corners, or a star with rounded corners in a planar view.
  • Figures 2A2, 11A, and 11B show an example in which the shape of opening 123 in a plan view is the same as the shape of opening 121 in a plan view
  • the type of shape of opening 121 in a plan view and the type of shape of opening 123 in a plan view may be different.
  • opening 121 may have a circular shape in a plan view
  • opening 123 may have a rectangular shape or a rectangular shape with rounded corners in a plan view.
  • opening 121 may have a rectangular shape in a plan view
  • opening 123 may have a rectangular shape with rounded corners or a circular shape in a plan view.
  • Figures 12A, 12B, and 12C show an example in which the semiconductor layer 113 shown in Figures 2A1, 2B, and 2C, respectively, is provided extending in the Y direction. That is, Figures 12A, 12B, and 12C show an example in which the semiconductor layer 113 extends in a direction parallel to the direction in which the conductive layer 112 extends. Note that in the examples shown in Figures 12A, 12B, and 12C, the semiconductor layer 113 is divided in the X direction, similar to the examples shown in Figures 2A1, 2B, and 2C.
  • FIGS. 13A1, 13A2, 13B, and 13C are modified examples of the configurations shown in FIGS. 2A1, 2A2, 2B, and 2C, respectively, and show an example in which the shape of the opening 121 provided in the insulating layer 103, the insulating layer 106, and the insulating layer 104 in a plan view does not match the shape of the opening 121 provided in the conductive layer 112 in a plan view.
  • the opening 121 provided in the insulating layer 103, the insulating layer 106, and the insulating layer 104 is referred to as opening 121a
  • the opening 121 provided in the conductive layer 112 is referred to as opening 121b.
  • the shape of the opening 121b in a plan view is a circle with a larger radius than the opening 121a.
  • the shape of opening 121a in a plan view and/or the shape of opening 121b in a plan view do not have to be circular.
  • the shape of opening 121a in a plan view and/or the shape of opening 121b in a plan view can be a rectangle, a rectangle with rounded corners, or any other shape that opening 121 can have.
  • conductive layer 112 has an area that protrudes beyond the sidewall of opening 121a.
  • the shape of the openings 121a in plan view may differ from the shape of the openings 121b in plan view.
  • the shape of the openings 121a in plan view may differ from the shape of the openings 121b in plan view.
  • the shape of the openings 121a in plan view may differ from the shape of the openings 121b in plan view.
  • the area of the openings 121b in plan view may be larger than the area of the openings 121a in plan view, even when the openings 121a and 121b are formed in the same process.
  • the substrate on which the transistor 100 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • Examples of the semiconductor substrate include a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Examples of the conductive substrate include a substrate having a metal nitride and a substrate having a metal oxide.
  • Examples of the conductive substrate include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate.
  • these substrates on which elements are provided may also be used.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • the thinner gate insulating layer can cause leakage current problems.
  • a high-k material for the insulator that functions as the gate insulating layer it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer.
  • EOT equivalent oxide thickness
  • a material with a low dielectric constant for the insulator that functions as the interlayer insulating layer it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material according to the function of the insulator. Note that a material with a low dielectric constant also has a high dielectric strength.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • Silicon oxide may be formed using an organic silane such as tetraethoxysilane (TEOS).
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, or metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • an insulator such as a gate insulating layer that is in contact with a semiconductor layer or that is provided near the semiconductor layer is preferably an insulator that has a region containing excess oxygen.
  • an insulator that has a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced.
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide that has vacancies.
  • Insulators having a barrier property against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.
  • Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these oxides have an amorphous structure, but crystalline regions may be formed in some parts.
  • a barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.
  • hydrogen when described as a corresponding substance indicates, for example, at least one of a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance indicate impurities in a channel formation region or a semiconductor layer unless otherwise specified, and indicate, for example, at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, and NO 2 , etc.), and a copper atom.
  • oxygen when described as a corresponding substance indicates, for example, at least one of an oxygen atom, an oxygen molecule, etc.
  • the barrier property against oxygen indicates a property that at least one of an oxygen atom, an oxygen molecule, etc. is difficult to diffuse.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used as the alloy containing the above-mentioned metal elements as a component.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive material containing oxygen may be referred to as an oxide conductor.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a stacked structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode may also be used.
  • a conductive material containing the above-mentioned metal element and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause the generation of lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • the electrical characteristics may easily fluctuate and the reliability may be reduced, particularly if oxygen vacancies (Vo) and impurities are present in the channel formation region in the metal oxide.
  • oxygen vacancies Vo
  • hydrogen near the oxygen vacancies may form VoH and generate electrons that serve as carriers.
  • the channel formation region in the metal oxide contains oxygen vacancies, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide.
  • the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures.
  • the a-like structure has a structure between the nc structure and the amorphous structure.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for the transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor.
  • the crystal it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, it is preferable for the crystal to have a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS.
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the above three-layered crystal structure has the following structure.
  • the first layer has an atomic coordination structure of an octahedron of oxygen with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure of a trigonal bipyramid or tetrahedron of oxygen with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure of a trigonal bipyramid or tetrahedron of oxygen with the metal of the third layer at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements are sometimes collectively referred to as “metal elements", and the "metal element” described in this specification and the like may include metalloid elements.
  • metal oxides examples include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZO), indium gallium
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more kinds of metal elements having a higher period number in the periodic table instead of indium.
  • the metal oxide may have one or more kinds of metal elements having a higher period number in the periodic table in addition to indium.
  • Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • a metal oxide having the above-mentioned layered crystal structure it is preferable to deposit atoms one layer at a time. By using the ALD method, it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • Examples of the ALD method include the Thermal ALD method, in which the reaction between the precursor and reactant is carried out using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, in which a plasma-excited reactant is used.
  • Thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy
  • PEALD Plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, which has the advantages of enabling extremely thin films to be formed, films to be formed on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films to be formed at low temperatures.
  • the PEALD method can be preferable in some cases because it uses plasma to enable films to be formed at lower temperatures.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the amount of these elements can be quantified using XPS or SIMS.
  • the amount of carbon and chlorine contained in the film can be reduced by adopting conditions in which the substrate temperature is high during film formation and/or by performing an impurity removal process, compared to when the ALD method is used without applying these methods.
  • an impurity removal treatment intermittently in an oxygen-containing atmosphere during the formation of the metal oxide film.
  • an impurity removal treatment in an oxygen-containing atmosphere after the formation of the metal oxide film.
  • impurity removal treatments include microwave treatment and heat treatment.
  • the substrate temperature is at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and at most 500°C, or at most 450°C. It is also preferable that the heat treatment temperature is at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and at most 500°C, or at most 450°C.
  • the temperature during the impurity removal process is preferably set to a temperature equal to or lower than the maximum temperature in the manufacturing process of a transistor or semiconductor device, in particular, so that the content of impurities in the metal oxide can be reduced without reducing productivity.
  • the productivity of the semiconductor device can be increased.
  • the microwave processing it is preferable to use a microwave processing device having a power source that generates high-density plasma using microwaves.
  • the frequency of the microwave processing device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz.
  • the power of the power source that applies the microwaves of the microwave processing device is preferably 1000 W to 10000 W, preferably 2000 W to 5000 W.
  • the microwave processing device may have a power source that applies RF (Radio Frequency) to the substrate side.
  • RF Radio Frequency
  • the microwave treatment is preferably carried out under reduced pressure, with the pressure being preferably from 10 Pa to 1000 Pa, and more preferably from 300 Pa to 700 Pa.
  • the treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300°C to 500°C, and even more preferably from 400°C to 450°C.
  • a heat treatment may be performed continuously without exposure to the outside air.
  • the temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.
  • the microwave treatment can be performed using, for example, oxygen gas and argon gas.
  • the oxygen flow ratio ( O2 /( O2 +Ar)) is greater than 0% and less than 100%.
  • the oxygen flow ratio ( O2 /( O2 +Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio ( O2 /( O2 +Ar)) is greater than 10% and less than 40%. Even more preferably, the oxygen flow ratio ( O2 /( O2 +Ar)) is greater than 10% and less than 30%.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been desorbed.
  • the heat treatment may be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).
  • impurities such as hydrogen or carbon contained in the metal oxide can be removed.
  • carbon in the metal oxide can be released as CO2 and CO
  • hydrogen in the metal oxide can be released as H2O .
  • rearrangement of metal atoms and oxygen atoms can be carried out, improving crystallinity. Therefore, a metal oxide having a highly crystalline layered crystal structure, particularly the above-mentioned metal oxide having the CAAC structure, can be formed.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio, for example.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • a method can be used in which a first metal oxide is formed by using a sputtering method, and a second metal oxide is formed on the first metal oxide by using an ALD method.
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the resulting film by the amount of raw material gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time).
  • the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, it is preferable to lower the impurity concentration in the oxide semiconductor film and to lower the density of defect states.
  • a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ / n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source region and drain region are n + type regions.
  • the OS transistor can have good electrical characteristics even when miniaturized. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor layer 113 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • the semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as the semiconductor.
  • a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material.
  • layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of semiconductors that can be used as semiconductor materials include silicon and germanium.
  • Examples of silicon that can be used as semiconductor layers include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).By applying the above-mentioned transition metal chalcogen
  • Example 1 of manufacturing method of semiconductor device As a method for manufacturing a semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 2A1, 2B, and 2C will be described below.
  • the insulating material for forming the insulating layer, the conductive material for forming the conductive layer, or the semiconductor material for forming the semiconductor layer can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.
  • CVD methods can be classified into plasma CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo CVD (Photo CVD), which uses light.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • CVD methods can also be classified into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • the plasma CVD method can obtain high-quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma.
  • wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device.
  • thermal CVD method which does not use plasma, such plasma damage does not occur, and therefore the yield of semiconductor devices can be increased.
  • plasma damage does not occur during film formation, so films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases.
  • the CVD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.
  • a and A1 in each figure are plan views. Also, B in each figure is a cross-sectional view taken along dashed line A1-A2 of A or A1 in each figure, and C in each figure is a cross-sectional view taken along dashed line A3-A4 of A or A1 in each figure.
  • a substrate (not shown) is prepared, and an insulating layer 101 is formed on the substrate (FIGS. 14A, 14B, and 14C).
  • the insulating material described above can be used as appropriate for the insulating layer 101.
  • the insulating layer 101 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a conductive layer 111 is formed on the insulating layer 101 (FIGS. 14A, 14B, and 14C).
  • a conductive film that will become the conductive layer 111 is formed and then processed to form the conductive layer 111.
  • the conductive film that will become the conductive layer 111 can be formed using any of the conductive materials that can be used for the conductive layer 111 described above.
  • the conductive film that becomes the conductive layer 111 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a pattern is formed by, for example, a lithography method, and the conductive film is processed by a dry etching method or a wet etching method based on the pattern, thereby forming the conductive layer 111.
  • the resist is first exposed to light through a mask. Next, the exposed areas are removed or left to form a resist mask using a developer. This forms a pattern.
  • a resist mask is formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV light, or the like.
  • a liquid immersion technique may be used in which exposure is performed by filling a liquid such as water between the substrate and the projection lens.
  • an electron beam or ion beam may be used instead of the light described above. Note that when an electron beam or ion beam is used, a mask is not required.
  • the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.
  • an etching process is performed through the resist mask. This allows the conductive film, semiconductor film, insulating film, etc. to be processed into the desired shape.
  • an etching gas containing halogen can be used as the etching gas, specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used.
  • an etching gas containing one or more of fluorine, chlorine, and bromine can be used as the etching gas.
  • C4F6 gas, C5F6 gas , C4F8 gas, CF4 gas , SF6 gas, NF3 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, CCl4 gas, and BBr3 gas can be used alone or in a mixture of two or more gases.
  • oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas.
  • the etching conditions can be appropriately set according to the object to be etched.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Or, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Or, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Or, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high density plasma source.
  • the insulating layer 103 is formed on the insulating layer 101 and the conductive layer 111 (FIGS. 14A, 14B, and 14C).
  • the insulating layer 103 can be formed using any of the insulating materials described above.
  • the insulating layer 103 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating layer 103 is preferably planarized by performing a chemical mechanical polishing (CMP) process after the film formation.
  • CMP chemical mechanical polishing
  • a planarization process may be performed until the insulating layer 103 is reached.
  • the planarization process By performing the planarization process, the surface of the insulating layer 103 can be planarized and smoothed. By placing this aluminum oxide on the insulating layer 103 and performing the planarization process, it becomes easier to detect the end point of the planarization process.
  • the planarization process does not need to be performed.
  • the upper surface of the insulating layer 103 has a convex curved shape.
  • a conductive layer 117 is formed on the insulating layer 103 (FIGS. 14A, 14B, and 14C).
  • the conductive layer 117 can be formed by a method similar to that used to form the conductive layer 111.
  • the conductive film that becomes the conductive layer 117 can be made of any of the conductive materials that can be used for the conductive layer 117 described above. Note that, when the conductive layer 117 has a planar shape as shown in FIGS. 9A, 9B, and 9C, it may not be necessary to form a pattern by lithography and to process the conductive film based on the pattern.
  • the insulating layer 104 is formed on the insulating layer 103 and the conductive layer 117 (FIGS. 14A, 14B, and 14C).
  • the insulating layer 104 can be formed by a method similar to that used for forming the insulating layer 103.
  • the insulating material described above can be appropriately used for the insulating layer 104.
  • the film thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 in the regions where they overlap with the conductive layer 111 correspond to the channel length of the transistor 100. Therefore, the film thicknesses of the insulating layer 103, the conductive layer 117, and the insulating layer 104 can be appropriately set according to the design value of the channel length of the transistor 100.
  • a conductive layer 112 is formed on the insulating layer 104 (FIGS. 14A, 14B, and 14C).
  • the conductive layer 112 can be formed by a method similar to that used for forming the conductive layer 111.
  • the above-mentioned conductive material that can be used for the conductive layer 112 can be appropriately used.
  • a part of the conductive layer 112, a part of the insulating layer 104, a part of the conductive layer 117, and a part of the insulating layer 103 are processed to form an opening 121 that reaches the conductive layer 111 ( Figures 15A, 15B, and 15C).
  • the opening 121 can be formed by using, for example, a lithography method and an etching method.
  • the sidewalls of the opening 121 are preferably perpendicular to the top surface of the conductive layer 111. With such a configuration, the transistor 100 can be miniaturized.
  • the sidewalls of the opening 121 may also be tapered. By tapering the sidewalls of the opening 121, the coverage of the metal oxide film that becomes the semiconductor layer 113 described below can be improved, and defects such as voids can be reduced.
  • the opening 121 has a large aspect ratio, it is preferable to process a part of the conductive layer 112, a part of the insulating layer 104, a part of the conductive layer 117, and a part of the insulating layer 103 using anisotropic etching.
  • processing by a dry etching method is preferable because it is suitable for fine processing.
  • the processing may be performed under different conditions.
  • the part of the insulating layer 104, the part of the conductive layer 117, and the part of the insulating layer 103 at least one of the inclination of the side surface of the conductive layer 112 in the opening 121, the inclination of the side surface of the insulating layer 104 in the opening 121, the inclination of the side surface of the conductive layer 117 in the opening 121, and the inclination of the side surface of the insulating layer 103 in the opening 121 may be different from the others.
  • a heat treatment may be performed.
  • the heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed, for example, in a nitrogen gas or inert gas atmosphere.
  • the heat treatment may also be performed under reduced pressure.
  • the gas used in the heat treatment is highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the side of the conductive layer 117 at the opening 121 is processed to set back the side (FIGS. 16A1, 16A2, 16B, and 16C).
  • the insulating layer 103, the conductive layer 117, and the insulating layer 104 form a recess 132.
  • the conductive layer 112 shown in FIG. 16A1 is shown by a dashed line without a hatched pattern.
  • the above-mentioned side surface can be processed by, for example, isotropic etching.
  • the conductive layer 117 is preferably processed under conditions where the etching selectivity with respect to the insulating layer 103, the insulating layer 104, the conductive layer 111, and the conductive layer 112 is high, that is, under conditions where the conductive layer 117 is easily etched and the insulating layer 103, the insulating layer 104, the conductive layer 111, and the conductive layer 112 are not easily etched.
  • the conductive layer 117 can be processed by, for example, wet etching or dry etching.
  • the steps shown in Figures 16A1, 16A2, 16B, and 16C can be said to be steps of processing the conductive layer 117 in the horizontal direction and receding the side surface of the opening 121 of the conductive layer 117. In this specification and the like, this processing may be referred to as the first processing.
  • the opening 121 provided in the conductive layer 117 after the step of recessing the side surface at the opening 121 in the conductive layer 117 is referred to as the opening 123.
  • the opening 123 may include, for example, a region overlapping with the opening 121 and a recess 132.
  • the inclination of the side surface at the opening 123 in the conductive layer 117 may differ from at least one of the inclination of the side surface of the conductive layer 112 at the opening 121, the inclination of the side surface of the insulating layer 104 at the opening 121, and the inclination of the side surface of the insulating layer 103 at the opening 121.
  • the inclination of the conductive layer 117 in the opening 121 is different from at least one of the inclination of the side of the conductive layer 112 in the opening 121, the inclination of the side of the insulating layer 104 in the opening 121, and the inclination of the side of the insulating layer 103 in the opening 121, the inclination of the side of the conductive layer 117 in the opening 123 may be different from at least one of the inclination of the side of the conductive layer 112 in the opening 121, the inclination of the side of the insulating layer 104 in the opening 121, and the inclination of the side of the insulating layer 103 in the opening 121.
  • an insulating film 106A which will later become the insulating layer 106, is formed so as to cover the openings 121 and 123 and have a region located inside the openings 121 and a region located inside the openings 123 ( Figures 17A, 17B, and 17C). Note that the insulating film 106A is shown by a solid line in Figure 17(A). In the subsequent plan views, the insulating film 106A is also shown by a solid line.
  • the insulating film 106A can have a shape that follows the top surface of the conductive layer 111, the side surface of the insulating layer 103, the inner wall of the recess 132, the side surface and top surface of the insulating layer 104, and the side surface and top surface of the conductive layer 112. As a result, recesses are formed in the insulating film 106A at positions where it overlaps with the opening 121 and at positions where it overlaps with the recess 132.
  • a recess may not be formed at a position where it overlaps with the recess 132.
  • the insulating film 106A can be formed on the conductive layer 111, the insulating layer 103, the insulating layer 104, and the conductive layer 112 so as to have an area in contact with the side of the conductive layer 117 at the opening 123.
  • the insulating film 106A can be formed so as to have an area in contact with the top surface of the conductive layer 111, an area in contact with the side of the insulating layer 103, an area in contact with the top surface of the insulating layer 103 in the recess 132, an area in contact with the side of the conductive layer 117 in the recess 132, an area in contact with the bottom surface of the insulating layer 104 in the recess 132, an area in contact with the side of the insulating layer 104, an area in contact with the side of the conductive layer 112, an area in contact with the top surface of the conductive layer 112, and an area in contact with the top surface of the insulating layer 104.
  • the insulating film 106A can be formed using an insulating material that can be used for the insulating layer 106 described above.
  • the insulating film 106A can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film 106A is preferably formed in contact with the side surface of the recess 132 of the conductive layer 117. Therefore, the insulating film 106A is preferably formed using a film formation method that has good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • silicon oxide is formed as the insulating film 106A using the ALD method.
  • FIG. 18A1 is a plan view of FIG. 18A1 with conductive layer 112 omitted and insulating layer 106 added.
  • the insulating film 106A remains in the recess 132, and the insulating layer 106 can be formed.
  • the processing of the insulating film 106A is preferably performed by a method suitable for fine processing, and can be performed by using, for example, a dry etching method. In this specification and the like, the processing of the insulating film 106A may be referred to as the second processing.
  • the first processing which is the processing for retracting the side surface of the conductive layer 117 at the opening 121
  • the second processing can be performed by using anisotropic etching. Therefore, it can be said that the second processing is a processing method with higher anisotropy than the first processing.
  • the insulating film 106A it is preferable to process the insulating film 106A under conditions where the etching selectivity between the insulating layer 104 and the insulating film 106A is high, that is, under conditions where the insulating film 106A is easily etched and the insulating layer 104 is not easily etched. This makes it possible to prevent the insulating layer 104, specifically, for example, the top surface of the insulating layer 104, from being processed when the insulating film 106A is processed.
  • the insulating layer 104 has a laminated structure of insulating layer 104a, insulating layer 104b on insulating layer 104a, and insulating layer 104c on insulating layer 104b as shown in FIG. 8A to FIG. 8D, it is preferable to use a material different from that used for insulating layer 104c.
  • a material different from that used for insulating layer 104c For example, when an insulator containing oxygen such as silicon oxide is used for insulating layer 106A, an insulator containing nitrogen such as silicon nitride can be used for insulating layer 104c. This allows the insulating layer 106A to be processed under conditions where the etching selectivity between insulating layer 104 and insulating layer 106A is high.
  • the side of the insulating layer 106 opposite the conductive layer 117 can coincide or approximately coincide with the side of the opening 121 of the insulating layer 103 and the side of the opening 121 of the insulating layer 104, as shown in FIG. 3A, for example. Therefore, it can be said that an opening 121 is provided in the insulating layer 106. Note that the side of the insulating layer 106 opposite the conductive layer 117 may not coincide or approximately coincide with one or both of the side of the opening 121 of the insulating layer 103 and the side of the opening 121 of the insulating layer 104. Even in this case, it can be said that an opening 121 is provided in the insulating layer 106.
  • a recess 133 as shown in FIG. 3B may be formed in the insulating layer 106.
  • the recess 133 may be formed in the insulating layer 106.
  • it is preferable to form the semiconductor film that becomes the semiconductor layer 113 by a method that has particularly high coverage for example, it is preferable to form the semiconductor film by the ALD method.
  • a semiconductor film that becomes the semiconductor layer 113 is formed in contact with the bottom and sidewalls of the opening 121 and at least a part of the top surface of the conductive layer 112.
  • the semiconductor film can be formed by appropriately using a semiconductor that can be applied to the semiconductor layer 113 described above, for example, a metal oxide film.
  • the semiconductor film can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the semiconductor film is preferably formed in contact with the bottom and sidewalls of the opening 121 that has a large aspect ratio.
  • the semiconductor film is preferably formed by using a film formation method that has good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • the semiconductor film that becomes the semiconductor layer 113 can be, for example, an In-Ga-Zn oxide formed by the ALD method.
  • the deposition method of each layer included in the semiconductor layer 113 may be the same or different.
  • the semiconductor film that becomes the semiconductor layer 113a may be deposited by a sputtering method
  • the semiconductor film that becomes the semiconductor layer 113b may be deposited by an ALD method.
  • Metal oxide films formed by sputtering tend to have crystallinity. Therefore, by using a metal oxide film having crystallinity as the semiconductor film to be the semiconductor layer 113a, the crystallinity of the metal oxide film can be improved when the metal oxide film is used as the semiconductor film to be the semiconductor layer 113b. Even if pinholes or discontinuities are formed in the metal oxide film to be the semiconductor layer 113a formed by sputtering, they can be blocked by the metal oxide film to be the semiconductor layer 113b formed by the ALD method, which has good coverage. Note that both the semiconductor layer 113a and the semiconductor layer 113b may be formed by the ALD method. This can improve the coverage of not only the semiconductor layer 113b but also the semiconductor layer 113a.
  • the semiconductor film that becomes the semiconductor layer 113 is preferably formed in contact with the top surface of the conductive layer 111 in the opening 121, the side surfaces of the insulating layer 103, the insulating layer 106, the insulating layer 104, and the conductive layer 112 in the opening 121, and the top surface of the conductive layer 112.
  • the conductive layer 111 functions as one of the source electrode or drain electrode of the transistor 100.
  • the conductive layer 112 functions as the other of the source electrode or drain electrode of the transistor 100.
  • the metal oxide film When a metal oxide film is used as the semiconductor film that becomes the semiconductor layer 113, it is preferable to perform the above-mentioned impurity removal treatment, specifically, for example, microwave treatment, after the metal oxide film is formed.
  • microwave treatment For details of the microwave treatment, refer to the above description.
  • heat treatment it is preferable to perform heat treatment.
  • the heat treatment may be performed in a temperature range in which the metal oxide film does not become polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C.
  • the metal oxide film can be made into, for example, CAAC-OS, and a method for manufacturing a highly reliable semiconductor device can be provided.
  • a heat treatment is performed after the semiconductor film is formed, but this is not a limitation of one embodiment of the present invention. A heat treatment may be performed in a later step.
  • the semiconductor film that will become the semiconductor layer 113 is patterned, for example, by lithography, and then processed by etching based on the pattern. This forms the semiconductor layer 113 (FIGS. 19A, 19B, and 19C). A part of the semiconductor layer 113 is formed inside the opening 121. The semiconductor layer 113 also contacts part of the side and upper surface of the conductive layer 112. As a result, the semiconductor layer 113 is formed so as to have a region in contact with the upper surface of the conductive layer 111, a region in contact with the side of the insulating layer 106, a region in contact with the side of the conductive layer 112, and a region in contact with the upper surface of the conductive layer 112, and a region located inside the opening 121. Note that the semiconductor layer 113 can be formed so as to have a region in contact with the side of the insulating layer 103 and a region in contact with the side of the insulating layer 104 in the opening 121.
  • the insulating layer 105 is formed on the semiconductor layer 113, the conductive layer 112, and the insulating layer 104 (FIGS. 19A, 19B, and 19C).
  • the insulating layer 105 can be formed using any of the above-mentioned insulating materials.
  • the insulating layer 105 can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating layer 105 is preferably formed in contact with the semiconductor layer 113 provided in the opening 121 having a large aspect ratio.
  • the insulating layer 105 is preferably formed using a film formation method with good coverage, and more preferably using a CVD method, an ALD method, or the like.
  • silicon oxide is formed as the insulating layer 105 using the ALD method.
  • the method for forming the insulating layer 105 is not limited to the CVD method or the ALD method.
  • the insulating layer 105 may be formed by a sputtering method.
  • a conductive layer 115 is formed so as to have an area sandwiched between the insulating layer 105 and the semiconductor layer 113 and facing each other ( Figures 19A, 19B, and 19C).
  • the conductive layer 115 can be formed by forming a conductive film that will become the conductive layer 115 on the insulating layer 105 and processing the conductive film.
  • the conductive film that will become the conductive layer 115 can be made of any of the conductive materials that can be used for the conductive layer 115 described above.
  • the conductive film that becomes the conductive layer 115 can be formed by appropriately using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the conductive film is preferably formed in contact with the insulating layer 105 provided in the opening 121 with a large aspect ratio. Therefore, the conductive film that becomes the conductive layer 115 is preferably formed by a film formation method that has good coverage or embedding properties, and more preferably by a CVD method, an ALD method, or the like.
  • the conductive film may be planarized by using, for example, a CMP method.
  • a silicon oxide film or a silicon oxynitride film may be formed on the conductive film that will become the conductive layer 115, and the planarization process may be performed until the silicon oxide film or the silicon oxynitride film is removed.
  • a pattern is formed, for example, by lithography, and the conductive film is processed based on the pattern by dry etching, wet etching, or the like, to form the conductive layer 115.
  • dry etching fine processing can be performed, which is preferable.
  • the side edge of the conductive layer 115 is located inside the side edge of the semiconductor layer 113. This makes it possible to reduce the parasitic capacitance formed by, for example, the conductive layer 112, the insulating layer 105, and the conductive layer 115, as described above.
  • the transistor 100 having the conductive layer 111, the conductive layer 112, the semiconductor layer 113, the insulating layer 105, the conductive layer 115, the insulating layer 106, and the conductive layer 117 can be formed.
  • the conductive layer 111 functions as one of the source electrode and the drain electrode of the transistor 100
  • the conductive layer 112 functions as the other of the source electrode and the drain electrode of the transistor 100.
  • the conductive layer 115 functions as the first gate electrode of the transistor 100
  • the insulating layer 105 functions as the first gate insulating layer of the transistor 100.
  • the conductive layer 117 functions as the second gate electrode of the transistor 100
  • the insulating layer 106 functions as the second gate insulating layer of the transistor 100.
  • the insulating layer 107 is formed to cover the transistor 100. Specifically, the insulating layer 107 is formed to cover the conductive layer 115 and the insulating layer 105 (FIG. 2A1, FIG. 2B, and FIG. 2C).
  • the insulating layer 107 can be formed using any of the insulating materials described above as appropriate.
  • the insulating layer 107 can be formed by a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method as appropriate.
  • a semiconductor device having a transistor 100 as shown in Figures 2A1, 2B, and 2C can be manufactured.
  • Example 2 of manufacturing method of semiconductor device As a method for manufacturing a semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the semiconductor device illustrated in FIGS. 5A1, 5A2, 5B, and 5C will be described below.
  • Figure 20A2 is a plan view in which the insulating film 106A and the conductive layer 112 are omitted from Figure 20A1.
  • the oxidation treatment can be performed by microwave treatment in an atmosphere containing oxygen.
  • the dashed-dotted arrows in Figures 20B and 20C indicate microwaves or high-frequency waves such as RF, oxygen plasma, oxygen radicals, etc. In subsequent figures showing examples of a method for manufacturing a semiconductor device, the dashed-dotted arrows also indicate microwaves or high-frequency waves such as RF, oxygen plasma, oxygen radicals, etc.
  • the conditions of the microwave treatment can be referenced to those shown in the above-mentioned ⁇ Constituent materials of the semiconductor device>.
  • the method of the oxidation treatment is not limited to microwave treatment, and for example, oxygen plasma treatment or thermal oxidation treatment may be used.
  • the oxide region 117ox can be a region containing the components contained in the conductive layer 117 and the components contained in the insulating film 106A. This allows the conductive layer 117 and the insulating film 106A to be alloyed. In this case, the oxide region 117ox can be said to be an alloyed region.
  • the oxide region 117ox can be a region containing tantalum, silicon, oxygen, and nitrogen.
  • the oxide region 117ox can be a region containing tungsten, silicon, and oxygen.
  • the oxidation treatment is performed not only on the conductive layer 117, but also on the conductive layer 111 and the conductive layer 112, which have a region in contact with the insulating film 106A. Therefore, as described above, for the conductive layer 111 and the conductive layer 112, a material that is less likely to oxidize than the conductive layer 117 or a material that is conductive even when oxidized, for example, a conductive material containing oxygen, can be used.
  • the above-mentioned oxidation treatment may enable the conductive layer 112 and the insulating film 106A to be alloyed.
  • This may enable the conductive layer 112 to contain silicon, for example.
  • the conductive layer 112 may be allowed to contain ITSO.
  • the conductive layer 111 and the insulating film 106A may be allowed to be alloyed.
  • the steps shown in Figures 18A1 to 19C and subsequent steps are performed.
  • a semiconductor device having a transistor 100 as shown in Figures 5A1, 5B, and 5C can be manufactured.
  • the above oxidation treatment may be performed after the insulating layer 106 is formed.
  • the above oxidation treatment may also be performed before the insulating film 106A is formed.
  • the above oxidation treatment may also be performed after the insulating layer 106 and the semiconductor layer 113 are formed.
  • the formation of the oxide region 117ox and the removal of impurities from the semiconductor layer 113 may be performed in parallel.
  • the oxide region 117ox can have insulating properties and can function as the second gate insulating layer of the transistor 100 together with the insulating layer 106.
  • the insulating layer 106 becomes thin due to, for example, processing the insulating film 106A, a part of the insulating film 106A in the recess 132 being processed, the thickness of the second gate insulating layer of the transistor 100 can be ensured. Therefore, a short circuit between the semiconductor layer 113 and the second gate electrode can be prevented.
  • a short circuit between the semiconductor layer 113 and the second gate electrode can be prevented.
  • a method for manufacturing a semiconductor device with a high yield can be provided.
  • a low-cost semiconductor device can be provided.
  • Example 3 of manufacturing method of semiconductor device An example of a method for manufacturing a semiconductor device illustrated in FIGS. 6A to 6C will be described below as a method for manufacturing a semiconductor device of one embodiment of the present invention.
  • the conductive layer 111 can be formed by forming a conductive film that will become the conductive layer 111a and a conductive film that will become the conductive layer 111b on the conductive film, and processing these conductive films.
  • the conductive film that will become the conductive layer 111a can be appropriately made from the conductive material applicable to the conductive layer 111a described above, and the conductive film that will become the conductive layer 111b can be appropriately made from the conductive material applicable to the conductive layer 111b described above.
  • the opening 121 is formed so as to reach the conductive layer 111b.
  • FIG. 17A to 17C the side surface of the conductive layer 117 in the opening 121 is oxidized to form an oxide region 117ox in the conductive layer 117 (FIGS. 21A and 21B).
  • FIG. 20A1 and FIG. 20A2 can be referred to for plan views.
  • FIG. 21A corresponds to the cross section taken along dashed line A1-A2 in FIG. 20A1
  • FIG. 21B corresponds to the cross section taken along dashed line A3-A4 in FIG. 20A1.
  • the oxidation treatment can be performed in the same manner as the method shown in FIG. 20A1, FIG. 20A2, FIG. 20B, and FIG. 20C.
  • the oxidation treatment may oxidize the upper surface of the conductive layer 111b in the region overlapping with the opening 121.
  • FIG. 21C corresponds to the cross section taken along dashed line A1-A2 in FIG. 18A1
  • FIG. 21D corresponds to the cross section taken along dashed line A3-A4 in FIG. 18A1.
  • the insulating film 106A can be processed in the same manner as the methods shown in FIGS. 18A1, 18A2, 18B, and 18C.
  • FIG. 18A1 can be referred to for a plan view.
  • FIG. 21E corresponds to the cross section taken along dashed line A1-A2 in FIG. 18A1
  • FIG. 21F corresponds to the cross section taken along dashed line A3-A4 in FIG. 18A1. Note that there are cases where the opening 121 does not reach the conductive layer 111a, and a recess having an area that overlaps with the opening 121 is formed in the conductive layer 111b.
  • the conductive layer 111b can be partially removed by processing the conductive layer 111b using, for example, a dry etching method or a wet etching method.
  • a recess having an area overlapping with the opening 121 may be formed in the conductive layer 111a.
  • the conductive layer 111b it is preferable to process the conductive layer 111b under conditions where the etching selectivity ratio between the conductive layer 111b and the conductive layer 112 is high, that is, under conditions where the conductive layer 111b is easily etched and the conductive layer 112 is not easily etched, and in this case, pattern formation is not required.
  • a material having low oxidation resistance but high conductivity can be used for the conductive layer 111, and the range of material selection for the conductive layer 111 can be expanded.
  • a conductive material having high conductivity can be used for one of the conductive layer 111a or the conductive layer 111b, and a conductive material containing oxygen can be used for the other of the conductive layer 111a or the conductive layer 111b.
  • at least a part of the oxidized region of the conductive layer 111 may be removed by, for example, dry etching or wet etching after the oxidation treatment. In this case, a recess having a region overlapping with the opening 121 is formed in the conductive layer 111.
  • a semiconductor layer, a first gate insulating layer, and a first gate electrode are provided inside an opening formed in a first interlayer insulating layer and a second interlayer insulating layer on the first insulating layer, and a transistor is formed so that one of a source electrode or a drain electrode is provided under the opening and the other of a source electrode or a drain electrode is provided on the second interlayer insulating layer.
  • a second gate electrode having the above opening is formed between the first interlayer insulating layer and the second interlayer insulating layer, and a side surface of the second gate electrode in the above opening is recessed to form a recess composed of the first interlayer insulating layer, the second gate electrode, and the second interlayer insulating layer, and then a second gate insulating layer is formed in the recess.
  • a transistor having a short channel length and a controllable threshold voltage can be manufactured. Therefore, according to one embodiment of the present invention, for example, a method for manufacturing a semiconductor device that operates at high speed and has good electrical characteristics can be provided.
  • FIG. 22A1 is a plan view illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • the memory device according to one embodiment of the present invention includes a memory cell 150 including a transistor 100 and a capacitor 200.
  • FIG. 22A2 is a plan view in which the components of the transistor 100 are omitted from FIG. 22A1, and illustrates a configuration example of the capacitor 200.
  • FIG. 22B is a cross-sectional view taken along dashed line A1-A2 in FIG. 22A1
  • FIG. 22C is a cross-sectional view taken along dashed line A3-A4 in FIG. 22A1.
  • the memory device shown in Figures 22A1, 22B, and 22C has a conductive layer 211 between the insulating layer 101, the insulating layer 103, and the conductive layer 111, and a capacitor 200 on the conductive layer 211.
  • the memory device also has an insulating layer 203 on the conductive layer 211, and an insulating layer 209 on the insulating layer 203.
  • the conductive layer 211 can be provided in a planar shape.
  • the insulating layer 203 and the insulating layer 209 function as interlayer insulating layers.
  • the insulating layer 203 has an opening 221 that reaches the conductive layer 211.
  • Figures 22A1 and 22A2 show an example in which the shape of the opening 221 is circular in a plan view. By making the shape of the opening 221 circular in a plan view, the processing accuracy when forming the opening 221 can be improved, and the opening 221 can be formed with a fine size. Note that the shape of the opening 221 in a plan view is not limited to a circle, and can be the same shape as the opening 121.
  • Capacitor 200 has conductive layer 214, insulating layer 205, and conductive layer 215. Conductive layer 214 and conductive layer 215 function as a pair of electrodes of capacitor 200, and insulating layer 205 functions as a dielectric layer of capacitor 200. Capacitor 200 can be configured as a MIM (Metal-Insulator-Metal) capacitor.
  • MIM Metal-Insulator-Metal
  • the conductive layer 214 is provided to cover the opening 221 and to have a region located inside the opening 221.
  • the conductive layer 214 can have a shape that conforms to the upper surface of the conductive layer 211 and the side and upper surface of the insulating layer 203. This allows the conductive layer 214 to have a recess at a position that overlaps with the opening 221.
  • the conductive layer 214 can have a region that contacts the upper surface of the conductive layer 211, a region that contacts the side surface of the insulating layer 203, and a region that contacts the upper surface of the insulating layer 203.
  • the insulating layer 205 is provided to cover the opening 221 and to have a region located inside the opening 221.
  • the insulating layer 205 is provided on the conductive layer 214 and on the insulating layer 203.
  • the insulating layer 205 can have a shape that follows the shapes of the upper and side surfaces of the conductive layer 214 and the upper surface of the insulating layer 203. Since the insulating layer 205 has a shape that follows the upper and side surfaces of the conductive layer 214, the insulating layer 205 has a recess at a position that overlaps with the opening 221.
  • the insulating layer 205 can have a region that contacts the upper surface of the conductive layer 214, a region that contacts the side surface of the conductive layer 214, and a region that contacts the upper surface of the insulating layer 203.
  • the conductive layer 215 is provided on the insulating layer 205 and can have a region in contact with the upper surface and the side surface of the recess of the insulating layer 205.
  • the conductive layer 215 has a region located inside the opening 221.
  • the conductive layer 215 and the conductive layer 214 face each other across the insulating layer 205 not only at the bottom of the opening 221 but also at a position along the side wall. Therefore, the deeper the opening 221, the larger the capacitance value per unit area of the capacitor 200 can be. This allows the read operation of the memory device to be performed stably, and a highly reliable memory device can be provided.
  • the capacitance value can be secured even if the area occupied by the capacitor 200 is small, a miniaturized memory device and a highly integrated memory device can be provided. As a result, a small memory device and a large-capacity memory device can be provided.
  • the conductive layer 214 can be configured to cover the side and bottom surfaces of the conductive layer 215 through the insulating layer 205 inside the opening 221.
  • the insulating layer 205 can have a region in contact with the side of the conductive layer 214, a region in contact with the upper surface of the recess of the conductive layer 214, a region in contact with the side of the conductive layer 215, and a region in contact with the bottom surface of the conductive layer 215.
  • 22A1, 22A2, 22B, and 22C show an example in which the side end of the conductive layer 215 is located inside the side end of the conductive layer 214 in both the X direction and the Y direction. Note that the side end of the conductive layer 215 may be located outside the side end of the conductive layer 214 in either or both of the X direction and the Y direction.
  • Capacitor 200 is a capacitor in which conductive layer 214 and insulating layer 205 are laminated along the side of insulating layer 203 and the top surface of conductive layer 211, and conductive layer 215 is provided on insulating layer 205 so as to fill opening 221.
  • a capacitor having such a configuration can be called a trench type capacitor or trench capacitance.
  • the sidewall of the opening 221 is preferably perpendicular to the upper surface of the conductive layer 211.
  • the opening 221 has, for example, a cylindrical shape.
  • the sidewall of the opening 221 may have a tapered shape, for example, like the sidewall of the opening 121 shown in Figures 7A to 7D.
  • the insulating layer 209 covers the side of the conductive layer 215 outside the opening 221. Outside the opening 221, the insulating layer 209 has an area that contacts, for example, the side of the conductive layer 215.
  • the insulating layer 209 and the conductive layer 215 are planarized, and the upper surface of the insulating layer 209 and the upper surface of the conductive layer 215 can be configured to coincide or approximately coincide. Note that, although an example in which the insulating layer 205 is provided in a planar shape is shown in FIG. 22B and FIG. 22C, the side end of the insulating layer 205 and the side end of the conductive layer 215 may coincide or approximately coincide. For example, by processing the insulating layer 205 with the same pattern as the conductive layer 215, the side end of the insulating layer 205 and the side end of the conductive layer 215 can be configured to coincide or approximately coincide.
  • the conductive layer 214 and the insulating layer 205 are formed, and then a conductive film that will become the conductive layer 215 is formed on the insulating layer 205.
  • a pattern is formed by, for example, lithography, and the conductive film is processed based on the pattern by dry etching, wet etching, or the like to form the conductive layer 215.
  • an insulating layer 209 is formed on the conductive layer 215 and the insulating layer 205, and the insulating layer 209 is planarized by, for example, CMP, to expose the upper surface of the conductive layer 215.
  • the above is an example of a method for manufacturing the capacitor 200.
  • the conductive layer 211 can be a single layer or a stack of conductive materials described in the above [Conductor] section.
  • a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 211.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen can be used in a single layer or a stacked layer.
  • titanium nitride or indium tin oxide with added silicon may be used.
  • a structure in which titanium nitride is stacked on tungsten may be used.
  • a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used.
  • insulating layer 203 and insulating layer 209 function as interlayer insulating layers, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant as an interlayer insulating layer, the parasitic capacitance that occurs between wirings can be reduced.
  • insulating layer 203 and insulating layer 209 a single layer or a stack of insulators containing a material with a low dielectric constant as described above in the [Insulator] section can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the conductive layer 214 and the conductive layer 215 can be formed of the conductors described in the above [Conductor] section, in a single layer or a stacked layer.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is stacked on titanium nitride may be used.
  • the insulating layer 205 when an oxide insulator is used for the insulating layer 205, the insulating layer 205 can suppress the oxidation of the conductive layer 214 and the conductive layer 215. Furthermore, when an oxide insulator is used for the insulating layer 203, the insulating layer 203 can suppress the oxidation of the conductive layer 214. Furthermore, when an oxide insulator is used for the insulating layer 209, the insulating layer 209 can suppress the oxidation of the conductive layer 215.
  • the insulating layer 205 it is preferable to use a material with a high relative dielectric constant, so-called high-k material, as described above in the [Insulator] section.
  • high-k material a material with a high relative dielectric constant
  • the insulating layer 205 can be made thick enough to suppress leakage current, and the capacitance value of the capacitor 200 can be sufficiently ensured.
  • the insulating layer 205 is preferably made of a high-k material and is preferably a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material.
  • high-k high dielectric constant
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used as the insulating layer 205.
  • an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulator with a relatively high dielectric strength, such as aluminum oxide, and using it as the insulating layer 205 the dielectric strength of the insulating layer 205 is improved and electrostatic breakdown of the capacitor 200 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulating layer 205.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include materials in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 may be set to 1:1 or close thereto.
  • materials that can have ferroelectricity include materials in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1: 1 or close to that.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may be used.
  • Figure 22D1 is a circuit diagram showing the connection relationship of the transistor 100 and the capacitor 200 in the memory cell 150 shown in Figures 22A1, 22B, and 22C.
  • One of the source and drain of the transistor 100 is electrically connected to one electrode of the capacitor 200.
  • the other of the source and drain of the transistor 100 is electrically connected to the wiring BL.
  • the first gate of the transistor 100 is electrically connected to the wiring WL.
  • the second gate of the transistor 100 is electrically connected to the wiring BG.
  • the other electrode of the capacitor 200 is electrically connected to the wiring PL.
  • Wiring BL corresponds to conductive layer 112
  • wiring WL corresponds to conductive layer 115
  • wiring BG corresponds to conductive layer 117
  • wiring PL corresponds to conductive layer 211.
  • conductive layer 112 has a region that functions as wiring BL
  • conductive layer 115 has a region that functions as wiring WL
  • conductive layer 117 has a region that functions as wiring BG
  • conductive layer 211 has a region that functions as wiring PL.
  • conductive layer 214 may have a region that functions as wiring PL.
  • the transistor 100 functions as a switch and has a function of controlling writing of data to the memory cell 150 and reading of data from the memory cell 150. By turning on the transistor 100, data is written to the memory cell 150 or data is read from the memory cell 150. By turning off the transistor 100, the data written to the memory cell 150 is retained.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on/off (conducting or non-conducting) of the transistor 100, which functions as a switch.
  • the wiring PL functions as a constant potential line connected to the capacitor 200.
  • the potential of the wiring BG becomes the potential of the second gate of the transistor 100.
  • Figure 22D2 is a circuit diagram showing an example configuration of memory cell 150A, which is configured by adding transistor 151 to memory cell 150 shown in Figure 22D1.
  • memory cell 150A one of the source or drain of transistor 100 and one electrode of capacitor 200 are electrically connected to the gate of transistor 151.
  • the other of the source or drain of transistor 100 is electrically connected to wiring WBL.
  • One of the source or drain of transistor 151 is electrically connected to wiring RBL.
  • the other of the source or drain of transistor 151 is electrically connected to wiring SL.
  • the second gate electrode is not provided in the transistor 151, but the transistor 151 may be provided with not only the first gate electrode but also a second gate electrode.
  • the second gate electrode of the transistor 151 may be supplied with, for example, a constant potential or the same potential as the potential of the first gate electrode of the transistor 151.
  • the potential of the second gate potential of the transistor 151 may be made different between when data is read from the memory cell 150A and when it is not.
  • the wiring WBL functions as a bit line for writing data and is also called a write bit line.
  • the wiring RBL functions as a bit line for reading data and is also called a read bit line.
  • the wiring SL functions as a constant potential line.
  • a pulse signal (a signal whose potential changes during a period when a specific operation is performed) is supplied to wiring PL.
  • a pulse signal may be supplied to wiring SL. In this case, a constant potential can be supplied to wiring PL.
  • the current flowing between the source and drain in an off state is extremely small. Therefore, by using an OS transistor as the transistor 100, the charge corresponding to the data stored in the memory cell can be stored in the capacitor 200 for a long time. This allows the memory cell to store data for a long time. This eliminates the need for a refresh operation or reduces the frequency of the refresh operation to an extremely low level, thereby sufficiently reducing the power consumption of the storage device.
  • the OS transistor has high frequency characteristics, data can be written to and read from a memory cell at high speed.
  • Transistor 151 can be a transistor with a larger on-state current than an OS transistor, for example, a Si transistor. This allows data to be read from memory cell 150A at high speed. Note that an OS transistor may be used for transistor 151. In this case, all of the transistors included in memory cell 150A can be the same type of transistor. This allows, for example, all of the transistors included in memory cell 150A to be formed in the same process.
  • Figures 23A, 23B, and 23C show an example in which the conductive layer 111 and insulating layer 209 shown in Figures 22A1, 22B, and 22C, respectively, are not provided.
  • Figures 23B and 23C show an example in which the opening 121 reaches the conductive layer 215, and the bottom surface of the semiconductor layer 113 is in contact with the conductive layer 215.
  • Figures 23B and 23C show an example in which the insulating layer 103 covers the side surface and part of the top surface of the conductive layer 215.
  • the conductive layer 215 functions as one of the source electrode and the drain electrode of the transistor 100.
  • the conductive layer 215 is preferably made of a material similar to that which can be used for the conductive layer 111.
  • the conductive layer 215 is preferably made of a material which is less likely to be oxidized than the conductive layer 117 or which has conductivity even when oxidized.
  • Figure 24A is a plan view showing an example of a memory device in which two memory cells 150 (hereinafter referred to as memory cell 150a and memory cell 150b) are connected to a common wiring.
  • Figure 24B is a cross-sectional view of the dashed line A3-A4 shown in Figure 24A.
  • each of the memory cells 150a and 150b shown in FIG. 24A and FIG. 24B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitance 200a and a transistor 100a
  • the memory cell 150b has a capacitance 200b and a transistor 100b. Therefore, in the memory device shown in FIG. 24A and FIG. 24B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory device shown in FIG. 22A1, FIG. 22B, and FIG. 22C.
  • a conductive layer 115 functioning as a wiring WL is provided in each of the memory cells 150a and 150b.
  • a conductive layer 112 functioning as part of the wiring BL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 112 has a region in contact with the semiconductor layer 113 of the memory cell 150a and a region in contact with the semiconductor layer 113 of the memory cell 150b.
  • An insulating layer 109 functioning as an interlayer insulating layer is provided on the insulating layer 107.
  • the 24A and 24B have conductive layers 141 and 142 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes).
  • the conductive layer 141 is disposed in an opening formed in insulating layers 101, 203, 205, 209, 103, and 104, and is in contact with the bottom surface of the conductive layer 112.
  • the conductive layer 142 is disposed in an opening formed in insulating layers 109, 107, and 105, and is in contact with the top surface of the conductive layer 112. Note that the conductive layers 141 and 142 can be made of a conductive material that can be used for the conductive layer 112.
  • the insulating layer 109 preferably has a low dielectric constant because it functions as an interlayer insulating layer. By using a material with a low dielectric constant as the interlayer insulating layer, the parasitic capacitance that occurs between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant, as described above in the [Insulator] section, can be used in a single layer or a multilayer configuration.
  • the concentration of impurities such as water and hydrogen in the insulating layer 109 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.
  • the conductive layer 141 and the conductive layer 142 function as plugs or wirings for electrically connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to the memory cells 150a and 150b.
  • the conductive layer 141 can be electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 24B
  • the conductive layer 142 can be electrically connected to a similar memory device (not shown) provided above the memory device shown in FIG. 24B.
  • the conductive layer 141 and the conductive layer 142 function as part of the wiring BL. In this way, by providing a memory device or the like above or below the memory device shown in FIG. 24B, the memory capacity per unit area can be increased.
  • the memory cells 150a and 150b are configured to be linearly symmetrical with respect to the perpendicular bisector of the dashed dotted line A3-A4. Therefore, the transistors 100a and 100b are also arranged symmetrically with the conductive layers 141 and 142 in between.
  • the conductive layer 112 functions as the other of the source electrode or drain electrode of the transistor 100a and as the other of the source electrode or drain electrode of the transistor 100b.
  • the transistors 100a and 100b share the conductive layers 141 and 142 that function as plugs. In this way, by configuring the connection between the two transistors and the plugs as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • the conductive layer 211 functioning as the wiring PL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b.
  • the conductive layer 117 functioning as the wiring BG may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b.
  • the conductive layer 211 is provided away from the conductive layer 141 so that the conductive layer 211 and the conductive layer 141 are not short-circuited.
  • the conductive layer 117 is provided away from the conductive layer 141 so that the conductive layer 117 and the conductive layer 141 are not short-circuited.
  • a memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.
  • Figs. 25A and 25B show an example of a memory device in which 2 x 4 x 4 memory cells 150 are arranged in the X, Y, and Z directions.
  • Fig. 25A is a plan view showing an example of the configuration of the memory device.
  • Fig. 25B is a cross-sectional view of dashed line A3-A4 in Fig. 25A.
  • each of the memory cells 150a to 150d shown in FIG. 25A and FIG. 25B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitance 200a and a transistor 100a
  • the memory cell 150b has a capacitance 200b and a transistor 100b
  • the memory cell 150c has a capacitance 200c and a transistor 100c
  • the memory cell 150d has a capacitance 200d and a transistor 100d. Therefore, in the memory device shown in FIG. 25A and FIG. 25B, the same reference numerals are attached to structures having the same functions as the structures constituting the memory devices shown in FIG. 22A1, FIG. 22A2, FIG. 22B, and FIG. 22C.
  • FIG. 25A and FIG. 25B includes a memory unit 160 having memory cells 150a, 150b, 150c, and 150d.
  • Memory units 160[1,1] to 160[4,2] are shown in FIG. 25A and FIG. 25B.
  • Memory units 160[1,1] to 160[4,1] are stacked in this order.
  • Memory units 160[1,2] to 160[4,2] are stacked in this order.
  • Memory units 160[1,2] to 160[4,2] are adjacent to memory units 160[1,1] to 160[4,1] in the X direction, respectively.
  • memory cell 150c is arranged outside memory cell 150a, and memory cell 150d is arranged outside memory cell 150b, with conductive layer 141 at the center.
  • the memory device shown in FIG. 25A and FIG. 25B can be said to be a memory device in which memory cell 150c is provided adjacent to memory cell 150a and memory cell 150d is provided adjacent to memory cell 150b in the memory device shown in FIG. 24A and FIG. 24B.
  • the conductive layer 115 functioning as the wiring WL is shared between memory cells 150 adjacent in the X direction.
  • the conductive layer 112 functioning as part of the wiring BL is shared within the same memory unit. In other words, the conductive layer 112 has a region in contact with each of the semiconductor layers 113 of the memory cells 150a to 150d.
  • a conductive layer 141 is provided between the conductive layers 112 of memory units adjacent in the Z direction.
  • the conductive layer 141 is provided in contact with the upper surface of the conductive layer 112 of memory unit 160[1,1] and the bottom surface of the conductive layer 112 of memory unit 160[2,1].
  • the conductive layer 112 and the conductive layer 141 provided in each memory unit 160 form a wiring BL.
  • the conductive layer 141 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIG. 25B. In this manner, by stacking multiple memory units in the memory device shown in FIG. 25B, the memory capacity per unit area can be increased.
  • the memory cells 150a and 150c and the memory cells 150b and 150d are configured to be linearly symmetrical with respect to the perpendicular bisector of the dashed dotted line A3-A4. Therefore, the transistors 100a and 100c and the transistors 100b and 100d are also arranged symmetrically with the conductive layer 141 in between.
  • the conductive layer 112 functions as the other of the source electrode or drain electrode of each of the transistors 100a to 100d.
  • the transistors 100a to 100d share the conductive layer 141 that functions as a plug. In this way, by configuring the connections between the four transistors and the plug as described above, a memory device that can be miniaturized or highly integrated can be provided.
  • FIG. 25B by stacking multiple memory cells 150, cells can be integrated and arranged without increasing the area occupied by the memory cell array. That is, a 3D memory cell array can be configured. Note that although a configuration in which four layers each having two memory units 160 are stacked is shown in FIG. 25A and FIG. 25B, one embodiment of the present invention is not limited to this.
  • the memory device may have one layer each having at least one memory cell 150, or two or more layers may be stacked.
  • 25A and 25B show a configuration in which the conductive layer 141 functioning as a plug is disposed between the memory cells 150.
  • the conductive layer 141 functioning as a plug is disposed inside the memory unit 160. Note that one embodiment of the present invention is not limited to this.
  • the conductive layer 141 may be disposed outside the memory unit.
  • FIGS. 26A and 26B show an example of a memory device in which 3 ⁇ 3 ⁇ 4 memory cells 150 are arranged in the X, Y, and Z directions.
  • FIG. 26A is a plan view showing an example of the configuration of the memory device.
  • FIG. 26B is a cross-sectional view of dashed line A3-A4 in FIG. 26A.
  • FIG. 26B shows an example in which the layer in which the memory cells 150 are provided is layer 170, and layers 170[1] to 170[4] are stacked in this order.
  • 26A and 26B show an example in which the conductive layer 141 is provided outside the region in which the memory cell 150 is provided.
  • the conductive layer 141 can be electrically connected to the conductive layer 212 provided in the layer above the layer including the conductive layer 141.
  • the conductive layer 141 provided in the layer 170[1] is electrically connected to the conductive layer 212 provided in the layer 170[2].
  • the conductive layer 212 provided in the layer 170[2] is provided in the same layer as the conductive layer 211 included in the layer 170[2]. That is, the conductive layer 212 can be formed in the same process as the conductive layer 211.
  • 26A and 26B show a structure in which the conductive layer 141 is electrically connected to the conductive layer 212 provided in an upper layer of the layer including the conductive layer 141; however, one embodiment of the present invention is not limited to this.
  • the conductive layer 141 may be electrically connected to the conductive layer 212 provided in the layer including the conductive layer 141.
  • the conductive layer 141 provided in the layer 170[1] may be electrically connected to the conductive layer 212 provided in the layer 170[1].
  • FIG. 27 is a diagram showing a configuration example of a transistor 300 below the memory units 160[1,1] to 160[4,1] shown in FIG. 25B.
  • FIG. 27 shows an example in which a gate electrode of the transistor 300 is electrically connected to a conductive layer 141 that functions as part of the wiring BL.
  • the transistor 300 can be a transistor provided in a driver circuit, which is a circuit having a function of controlling the driving of a semiconductor device of one embodiment of the present invention.
  • the transistor 300 shown in FIG. 27 can be a transistor included in a bit line driver circuit that controls writing and reading of data to and from the memory cell 150.
  • the transistor 300 can be a transistor included in a sense amplifier included in the bit line driver circuit, for example.
  • the transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate electrode, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, a low-resistance region 314a that functions as one of the source region and the drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region.
  • the transistor 300 may be an n-channel transistor or a p-channel transistor.
  • the transistor 300 is provided so as to overlap with the memory unit 160.
  • This allows the wiring BL that functions as a bit line to be short, and therefore the parasitic capacitance (also referred to as bit line capacitance) formed by the wiring BL can be reduced. Therefore, even if the storage capacitance of the memory cell 150 is reduced, the difference between the potential of the wiring BL when data having a value of "1" is read from the memory cell 150 and the potential of the wiring BL when data having a value of "0" is read from the memory cell 150 can be maintained. Therefore, even if the storage capacitance of the memory cell 150 is reduced, the semiconductor device of one embodiment of the present invention can correctly read the data stored in the memory cell 150.
  • the storage capacitance of the memory cell 150 can be reduced, for example, the capacitance value of the capacitor 200 can be reduced, and therefore the area occupied by the capacitor 200 can be reduced. Therefore, the area occupied by the memory cell 150 can be reduced.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 27 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer insulating layer, wiring, plugs, etc. may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Furthermore, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order on the transistor 300 as an interlayer insulating layer.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the layer that functions as the interlayer insulating layer may be planarized.
  • the upper surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.
  • a wiring layer may be provided on the insulating layer 326 and on the conductive layer 330.
  • insulating layer 350, insulating layer 352, and insulating layer 354 are laminated in this order.
  • conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.
  • An insulating layer 101 is provided on the insulating layer 354 and the conductive layer 356.
  • a conductive layer 141 is provided on the conductive layer 356.
  • the conductive layer 141 has a region in contact with the top surface of the conductive layer 356, the conductive layer 356 has a region in contact with the top surface of the conductive layer 330, and the conductive layer 330 has a region in contact with the conductive layer 316.
  • the conductive layer 141 functioning as part of the wiring BL is electrically connected to the conductive layer 316 functioning as the gate electrode of the transistor 300.
  • the insulating layer 352 and the insulating layer 354, which function as interlayer insulating layers, can be made of materials similar to those that can be used for the insulating layer 101, for example.
  • the conductive layers described in the above section [Conductor] can be used as the conductive layers that function as plugs or wiring, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • Figure 28A is a plan view showing an example of the configuration of a memory device of one embodiment of the present invention, and shows a region including 16 memory cells 150 shown in Figure 22A1, four in each of the X direction and Y direction.
  • Figure 28A shows a conductive layer 115 that functions as a wiring WL, a conductive layer 112 that functions as a wiring BL, and an opening 121.
  • the memory cell 150 is provided in a region where the conductive layer 115, the conductive layer 112, and the opening 121 overlap.
  • the opening 121 is provided in a region of the conductive layer 112 where the conductive layer 112 and the conductive layer 115 intersect.
  • FIG. 28A shows a configuration in which memory cells 150 are arranged in a matrix. Also, a configuration in which openings 121 are arranged in a matrix is shown. Also, a configuration in which conductive layer 115 is provided extending in the X direction, and conductive layer 112 is provided extending in the Y direction is shown. In other words, a configuration in which conductive layer 115 and conductive layer 112 are orthogonal to each other is shown. Also, a configuration in which conductive layer 115 has a uniform width in a direction perpendicular to the direction in which conductive layer 115 extends (Y direction), and conductive layer 112 has a uniform width in a direction perpendicular to the direction in which conductive layer 112 extends (X direction) is shown. Note that one aspect of the present invention is not limited to this.
  • Figure 28B is another example of a planar layout of a memory device.
  • the planar layout of Figure 28B shows conductive layer 115, conductive layer 112, and opening 121, similar to Figure 28A.
  • the memory device shown in Figure 28B differs from the memory device shown in Figure 28A mainly in the arrangement of memory cells 150 (opening 121), the shape of conductive layer 112, and the direction in which conductive layer 115 extends.
  • the memory cells 150 may be arranged in a zigzag pattern in the X direction.
  • the memory cell adjacent to the first memory cell in the Y direction is the second memory cell
  • the memory cell adjacent to the first and second memory cells in the X direction is the third memory cell.
  • the center of the third memory cell may be located on a straight line that passes through the middle between the first and second memory cells and is parallel to the X direction.
  • the third memory cell can be said to be located at a position that is halfway offset in the Y direction from the first and second memory cells.
  • the conductive layer 112 has a first region and a second region.
  • the first region is the opening 121 and the region in the vicinity thereof, and the width in the X direction of the first region is the first width.
  • the first region can be said to have a shape with rounded corners of a rectangle.
  • the second region is a region between adjacent openings 121 in one conductive layer 112, and the width in the X direction of the second region is the second width. In this case, it is preferable that the second width is smaller than the first width.
  • the extension direction of the conductive layer 115 is inclined with respect to the X direction.
  • the extension direction of the conductive layer 115 may not be perpendicular to the extension direction of the conductive layer 112. In other words, it is preferable that the conductive layer 115 intersects with the conductive layer 112.
  • Figure 28C is another example of a planar layout of a memory device.
  • the planar layout of Figure 28C shows conductive layer 115, conductive layer 112, and opening 121, similar to Figure 28B.
  • the memory device shown in Figure 28C differs from the memory device shown in Figure 28B mainly in the shape of the first region of conductive layer 112.
  • the first region of the conductive layer 112 shown in FIG. 28B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X direction or Y direction.
  • the first region of the conductive layer 112 shown in FIG. 28C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X direction or Y direction.
  • Figures 28B and 28C show an example in which the first region of the conductive layer 112 has a rectangular shape with rounded corners in a plan view, but one aspect of the present invention is not limited to this.
  • Figure 29A is another example of a planar layout of a memory device.
  • the planar layout of Figure 29A shows conductive layer 115, conductive layer 112, and opening 121, similar to Figures 28B and 28C.
  • the memory device shown in Figure 29A differs from the memory device shown in Figures 28B and 28C mainly in the shape of the first region of conductive layer 112. Note that in Figure 29A, the hatching pattern of conductive layer 115 has been omitted for clarity.
  • the first region of the conductive layer 112 shown in FIG. 29A is circular in plan view.
  • the first width is greater than the second width.
  • the first region of the conductive layer 112 in plan view is not limited to the above-mentioned shape.
  • the first region of the conductive layer 112 in plan view may be an approximately circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners.
  • FIG. 29A shows a configuration in which the width of the conductive layer 115 in the direction perpendicular to the direction in which the conductive layer 115 extends is uniform, but this is not a limitation of one aspect of the present invention.
  • Figure 29B is another example of a planar layout of a memory device.
  • the planar layout of Figure 29B shows conductive layer 115, conductive layer 112, and opening 121, similar to Figure 29A.
  • the memory device shown in Figure 29B differs from the memory device shown in Figure 29A mainly in the shape of conductive layer 115.
  • the conductive layer 115 shown in FIG. 29B has a first region and a second region, similar to the conductive layer 112.
  • the first region is the opening 121 and the region in its vicinity, and is circular in plan view.
  • the second region is the region between adjacent openings 121 in one conductive layer 115. Note that the first region of the conductive layer 115 overlaps with the first region of the conductive layer 112.
  • Figure 29C is another example of a planar layout of a memory device.
  • the planar layout of Figure 29C shows conductive layer 115, conductive layer 112, and opening 121, similar to Figure 29A.
  • the memory device shown in Figure 29C differs from the memory device shown in Figure 29A mainly in the shape and extension direction of conductive layer 115.
  • the conductive layer 115 shown in FIG. 29C has a meandering shape like a triangular wave in plan view, and is provided extending in the X direction. With this configuration, when the memory cells 150 (openings 121) are arranged in a zigzag pattern in the X direction, the physical distance between the conductive layers 112 can be reduced. This allows the memory device to be miniaturized and highly integrated. Note that the conductive layer 115 in plan view is not limited to the above, and may be, for example, meandering.
  • one or both of the physical distance between the conductive layers 115 and the physical distance between the conductive layers 112 can be reduced, enabling miniaturization and high integration of the memory device.
  • a memory device having a 3D memory cell array will be described in detail in a later embodiment.
  • ⁇ Configuration example of storage device> 30 is a block diagram illustrating a configuration example of a memory device 400 which is a memory device of one embodiment of the present invention.
  • the memory device 400 illustrated in FIG 30 includes a driver circuit 21 and a memory array 20.
  • the memory array 20 includes a functional layer 50 including a plurality of memory cells 10 and a plurality of functional circuits 51.
  • Figure 30 shows an example in which the memory array 20 has multiple memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • a functional circuit 51 is provided for each wiring BL that functions as a bit line.
  • Figure 30 shows an example in which multiple functional circuits 51 are provided corresponding to n wirings BL.
  • the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n].
  • an arbitrary row may be indicated as row i.
  • An arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j].
  • i+ ⁇ ⁇ is a positive or negative integer
  • the memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the first wiring WL (first row) is indicated as wiring WL[1]
  • the mth wiring WL (mth row) is indicated as wiring WL[m].
  • the first wiring PL (first row) is indicated as wiring PL[1]
  • the mth wiring PL (mth row) is indicated as wiring PL[m].
  • the first wiring BL (first column) is indicated as wiring BL[1]
  • the nth wiring BL (nth column) is indicated as wiring BL[n].
  • the memory cells 10 in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row.
  • the memory cells 10 in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the memory array 20 can be DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).
  • DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and refers to a memory in which the access transistor is an OS transistor.
  • the current that flows between the source and drain, that is, the leakage current is extremely small.
  • DOSRAM can hold a charge corresponding to the data held in the capacitor for a long time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM composed of Si transistors. As a result, it is possible to achieve low power consumption.
  • the memory cells 10 can be stacked by arranging OS transistors in a stacked manner as described in embodiment 1.
  • the memory array 20 shown in FIG. 30 multiple memory arrays 20[1] to 20[m] can be stacked.
  • the memory arrays 20[1] to 20[m] of the memory array 20 can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, thereby improving the memory density of the memory cells 10.
  • the memory array 20 can be manufactured by repeatedly using the same process in the vertical direction.
  • the memory device 400 can reduce the manufacturing cost of the memory array 20. As a result, the memory device 400 can be a low-cost memory device.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on or off state of an access transistor that functions as a switch.
  • the wiring PL functions as a constant potential line connected to a capacitance.
  • the memory cells 10 in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL.
  • the wiring BL can be arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened.
  • the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via the wiring GBL (not shown) described later. With this configuration, it is possible to amplify a slight potential difference of the wiring BL when reading data.
  • the wiring GBL can be arranged in the vertical direction of the substrate surface on which the driver circuit 21 is provided, just like the wiring BL. By arranging the wiring BL and wiring GBL extending from the memory cell 10 of the memory arrays 20[1] to 20[m] in the vertical direction of the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between the two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby reducing power consumption and signal delay.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a conductive layer that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.
  • the memory array 20 can be stacked on the drive circuit 21. By stacking the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby reducing power consumption and signal delay. In addition, the storage device 400 can be made smaller.
  • the functional circuit 51 is made of OS transistors, similar to the transistors in the memory cells 10 of the DOSRAM, and can be freely arranged on circuits using Si transistors, similar to the memory arrays 20[1] to 20[m], making integration easy. By configuring the functional circuit 51 to amplify signals, the circuits in the subsequent stages, such as the sense amplifier 46, can be made smaller, and the memory device 400 can be made smaller.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 400. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 400. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 400.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the memory cells 10.
  • the peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, and the function of retaining the read data.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is data (Din) to be written to the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 400.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 400 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • the memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on the drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased.
  • the memory array 20 provided in the first layer is shown as memory array 20[1]
  • the memory array 20 provided in the second layer is shown as memory array 20[2]
  • the memory array 20 provided in the fifth layer is shown as memory array 20[5].
  • the wiring WL and wiring PL extending in the X direction, and the wiring BL extending in the Z direction are shown. Note that, in order to make the drawing easier to see, the wiring WL and wiring PL of each memory array 20 are partially omitted.
  • FIG. 31A shows a configuration in which the wiring PL is extended in the X direction, one embodiment of the present invention is not limited to this.
  • the wiring PL may be extended in the Y direction, or the wiring PL may be extended in the X direction and the Y direction, for example, the wiring PL may be provided in a planar shape.
  • Figure 31B is a schematic diagram illustrating an example of the configuration of the functional circuit 51 connected to the wiring BL shown in Figure 31A, and the memory cells 10 in the memory arrays 20[1] to 20[5] connected to the wiring BL.
  • Figure 31B also shows a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also called a "memory string.” Note that in the drawings, the wiring GBL may be shown with a thick line to improve visibility.
  • Figure 31B shows an example of the circuit configuration of a memory cell 10 connected to wiring BL.
  • the memory cell 10 has a transistor 11 and a capacitor 12.
  • the transistor 11, the capacitor 12, and each wiring may also be referred to as wiring BL[1] and wiring WL[1], etc.
  • the memory cell 10 shown in FIG. 31B corresponds to the first embodiment, for example, the memory cell 150 shown in FIG. 22D1 of the first embodiment.
  • the transistor 11 and the capacitor 12 of the memory cell 10 correspond to the transistor 100 and the capacitor 200, respectively.
  • an example is shown in which the second gate electrodes of the four transistors 11 shown in FIG. 31B are electrically connected to a common wiring BG.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitor 12.
  • FIG. 32A shows a schematic diagram of a memory device 400 in which the functional layer 50 and the memory arrays 20[1] to 20[m] are repeated as a unit 70. Note that although FIG. 32A shows one wiring GBL, the wiring GBL may be provided as appropriate according to the number of functional circuits 51 provided in the functional layer 50.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL is provided in contact with a conductive layer that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor in the functional circuit 51.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.
  • the repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked.
  • the memory device 400A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as shown in FIG. 32B.
  • the wiring GBL is connected to the functional layer 50 included in the repeating unit 70.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
  • OS transistors are stacked, and wiring that functions as a bit line is arranged in a vertical direction to the substrate surface on which the driver circuit 21 is provided.
  • the wiring that functions as a bit line extending from the memory array 20 in a vertical direction to the substrate surface By arranging the wiring that functions as a bit line extending from the memory array 20 in a vertical direction to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.
  • the layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting the data potential held in the memory cell 10.
  • a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting the data potential held in the memory cell 10.
  • ⁇ Configuration Example of Memory Array 20 and Functional Circuit 51> 33 a configuration example of the functional circuit 51 described in FIG. 30 to FIG. 32 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 will be described.
  • the driver circuit 21 connected to wirings GBL (GBL_A, GBL_B) connected to functional circuits 51 (51_A, 51_B) connected to memory cells 10 (10_A, 10_B) connected to different wirings BL (BL_A, BL_B) is shown.
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are shown.
  • FIG. 33 an example is shown in which the wiring BG electrically connected to the second gate electrode of the transistor 11 provided in the memory cell 10_A is different from the wiring BG electrically connected to the second gate electrode of the transistor 11 provided in the memory cell 10_B, but these wiring BGs may be common.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown as functional circuits 51_A and 51_B.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown in FIG. 33 are OS transistors, similar to transistor 11 included in memory cell 10.
  • the functional layer 50 including the functional circuit 51 can be stacked in the same manner as memory arrays 20[1] to 20[m].
  • Wirings BL_A and BL_B are connected to the gates of transistors 52_a and 52_b.
  • Wirings GBL_A and GBL_B are connected to one of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b.
  • Wirings GBL_A and GBL_B are provided vertically like wirings BL_A and BL_B, and are connected to transistors in driver circuit 21.
  • Control signals WE, RE, and MUX are provided to the gates of transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, as shown in FIG. 33.
  • the transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 33 are composed of Si transistors.
  • the switches 83_A to 83_D constituting the switch circuit 72_A and switch circuit 72_B can also be composed of Si transistors.
  • One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuit 71_A, precharge circuit 71_B, sense amplifier 46, and switch circuit 72_A.
  • the precharge circuit 71_A has n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL1.
  • the precharge circuit 71_B has n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL2.
  • the sense amplifier 46 has a p-channel transistor 82_1, a p-channel transistor 82_2, an n-channel transistor 82_3, and an n-channel transistor 82_4 connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring that has a function of providing VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors that form an inverter loop.
  • the potentials of the precharged wirings BL_A and BL_B change by selecting the memory cell 10_A and the memory cell 10_B, and the potentials of the wirings GBL_A and GBL_B are set to the high power supply potential VDD or the low power supply potential VSS according to the change.
  • the potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D, and the write/read circuit 73.
  • the wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs.
  • the write/read circuit 73 controls the writing of data signals according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B.
  • the switch circuit 72_A is switched on or off under the control of the switching signal CSEL1.
  • the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is on at a high level and off at a low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46.
  • the switch circuit 72_B is switched on or off under the control of the switching signal CSEL2.
  • the switches 83_C and 83_D may be similar to the switches 83_A and 83_B.
  • the memory device 400 can be configured to connect the memory cell 10, the functional circuit 51, and the sense amplifier 46 via wiring BL and wiring GBL arranged in the vertical direction, which is the shortest distance.
  • the number of functional layers 50 having transistors that constitute the functional circuit 51 increases, the load on the wiring BL is reduced, which shortens the write time and makes it easier to read data.
  • each transistor in the functional circuits 51_A and 51_B is controlled in response to control signals WE, RE, and a selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and the selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers composed of OS transistors. With this configuration, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 46 using Si transistors.
  • Embodiment 3 show an example of a chip 1200 on which a memory device of one embodiment of the present invention is implemented.
  • a plurality of circuits (systems) are implemented on the chip 1200.
  • a technology for integrating a plurality of circuits (systems) on one chip in this manner is sometimes called a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
  • Bumps (not shown) are provided on the chip 1200, which are connected to the first surface of the package substrate 1201, as shown in FIG. 34B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222.
  • a storage device such as a DRAM 1221 or a flash memory 1222.
  • the DOSRAM described in the above embodiment can be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the above-mentioned DOSRAM may be used for the memory.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of one embodiment of the present invention, the image processing and multiply-and-accumulate operations can be performed with low power consumption.
  • the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit.
  • the analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, or a controller. Controllers include a mouse, a keyboard, and a game controller. As such an interface, a USB (Universal Serial Bus) or an HDMI (registered trademark) (High-Definition Multimedia Interface) can be used.
  • a USB Universal Serial Bus
  • HDMI registered trademark
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.
  • LAN Local Area Network
  • circuits can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
  • the package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided, can be referred to as the GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles.
  • a product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • Embodiment 4 This embodiment describes an example of an electronic component and an electronic device in which the memory device described in the above embodiment is built in.
  • the electronic components and electronic devices can have low power consumption and high speed.
  • Figure 35A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in Figure 35A has a memory device 720 inside a mold 711. Part of the electronic component 700 is omitted in Figure 35A to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by a wire 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory device 720 has a drive circuit layer 721 and a memory circuit layer 722.
  • FIG 35B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 720 provided on the interposer 731.
  • the memory device described in the above embodiment as the memory device 720, it is possible to reduce power consumption and increase speed.
  • the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.
  • the package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like.
  • the interposer 731 may be a silicon interposer, a resin interposer, or the like.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, wiring on silicon interposers can be formed using semiconductor processes, making it easy to form fine wiring that is difficult to achieve with resin interposers.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 35B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.
  • Embodiment 5 an application example of a storage device using the storage device described in the previous embodiment will be described.
  • the storage device described in the previous embodiment can be applied to various electronic devices (e.g., information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, and the like).
  • the storage device described in the above embodiment as a storage device for the electronic device, the electronic device can be made to consume less power and operate at a higher speed.
  • the computer here includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • FIGS. 36A to 36E are schematic diagrams illustrating some configuration examples of removable storage devices.
  • the storage device described in the previous embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG 36A is a schematic diagram of a USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the board 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the board 1104.
  • the memory device shown in the previous embodiment can be incorporated into the memory chip 1105.
  • FIG 36B is a schematic diagram of the external appearance of an SD card
  • Figure 36C is a schematic diagram of the internal structure of an SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the board 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the board 1113.
  • the capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the board 1113 as well.
  • a wireless chip with a wireless communication function may also be provided on the board 1113. This makes it possible to read and write data from and to the memory chip 1114 through wireless communication between the host device and the SD card 1110.
  • the memory device shown in the previous embodiment can be incorporated into the memory chip 1114.
  • FIG 36D is a schematic diagram of the appearance of an SSD
  • Figure 36E is a schematic diagram of the internal structure of the SSD.
  • SSD 1150 has a housing 1151, a connector 1152, and a board 1153.
  • Board 1153 is housed in housing 1151.
  • memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153.
  • Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip.
  • the capacity of SSD 1150 can be increased.
  • the memory device shown in the previous embodiment can be incorporated into memory chip 1154.
  • the memory device of one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip.
  • a processor such as a CPU or a GPU, or a chip in an electronic device
  • the electronic device can have low power consumption and high speed.
  • Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip using the memory device are shown in FIG. 37A to FIG. 37H .
  • the GPU or chip of one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, audio playback devices, etc.
  • game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, audio playback devices, etc.
  • the GPU or chip of one embodiment of the present invention in an electronic device, it is possible to mount artificial intelligence on the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc. Examples of electronic devices are shown in Figures 37A to 37H.
  • [Information terminal] 37A illustrates a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5100 includes a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.
  • the information terminal 5100 can achieve low power consumption and high speed.
  • FIG. 37B shows a notebook type information terminal 5200.
  • the notebook type information terminal 5200 has an information terminal main body 5201, a display unit 5202, and a keyboard 5203.
  • the notebook information terminal 5200 can achieve low power consumption and high speed by applying a chip of one embodiment of the present invention.
  • a smartphone and a notebook type information terminal are shown as examples of electronic devices in Figs. 37A and 37B, respectively, but information terminals other than smartphones and notebook type information terminals can also be applied.
  • Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.
  • FIG. 37C illustrates a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be detached from the housing 5301.
  • an image displayed on the display portion 5304 can be output to another video device (not shown).
  • the housing 5302 and the housing 5303 can each function as an operation portion. This allows a plurality of players to play a game at the same time.
  • the chip described in the above embodiment can be incorporated in the chip provided on the substrate of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 37D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.
  • a game machine with low power consumption By applying a GPU or chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400, a game machine with low power consumption can be realized.
  • low power consumption can reduce heat generation from the circuit, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • a portable game machine and a stationary game machine are shown as examples of game machines, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to these.
  • game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.
  • the GPU or chip according to one aspect of the present invention can be applied to a large computer.
  • Figure 37E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • Figure 37F is a diagram showing a rack-mounted calculator 5502 that the supercomputer 5500 has.
  • the supercomputer 5500 has a rack 5501 and multiple rack-mounted computers 5502.
  • the multiple computers 5502 are stored in the rack 5501.
  • the computer 5502 is also provided with multiple boards 5504, and the GPU or chip described in the above embodiment can be mounted on the boards.
  • the supercomputer 5500 is a large computer used mainly for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, so power consumption is high and chips generate a lot of heat. For example, in a data center that has multiple supercomputers 5500, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yota) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized.
  • low power consumption can reduce heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a significant contribution to measures against global warming.
  • a supercomputer is shown as an example of a large computer, but large computers to which a GPU or chip of one embodiment of the present invention is applied are not limited to this. Examples of large computers to which a GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers), large general-purpose computers (mainframes), etc.
  • the GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.
  • Figure 37G is a diagram showing the area around the windshield inside an automobile, which is an example of a moving body.
  • Figure 37G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.
  • the display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, air conditioning settings, and the like.
  • the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, making it possible to improve the design.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 can display an image from an imaging device (not shown) installed in the vehicle to complement the field of view (blind spot) blocked by the pillar. In other words, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be increased. In addition, by displaying an image that complements the invisible parts, safety can be confirmed more naturally and without any sense of discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, and therefore, for example, the chip can be used in an automatic driving system for automobiles.
  • the chip can also be used in a system that provides road guidance, hazard prediction, or the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance or hazard prediction.
  • moving bodies are not limited to automobiles.
  • moving bodies can also include trains, monorails, ships, and aircraft, and a chip according to one aspect of the present invention can be applied to these moving bodies to provide a system that utilizes artificial intelligence.
  • examples of aircraft can include helicopters, unmanned aerial vehicles (drones), airplanes, and rockets.
  • [electric appliances] 37H is a diagram showing an example of an electric appliance, an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • an electric refrigerator-freezer 5800 with artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of those ingredients, as well as a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800.
  • An electric refrigerator-freezer has been described as an example of an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, and audiovisual equipment.
  • the electronic device described in this embodiment its functions, examples of applications of artificial intelligence, and its effects, etc., can be appropriately combined with the descriptions of other electronic devices.
  • a storage device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small change in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in space.
  • FIG. 38 a specific example of application of the storage device of one embodiment of the present invention to space equipment will be described with reference to FIG. 38 .
  • Figure 38 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown in outer space.
  • outer space refers to an altitude of, for example, 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a storage device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the electrical characteristics of an OS transistor change less when exposed to radiation than those of a Si transistor. In other words, the OS transistor is highly reliable even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. In this way, the artificial satellite 6800 can function as, for example, an earth observation satellite.
  • a storage device can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

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PCT/IB2023/060887 2022-11-07 2023-10-30 半導体装置、半導体装置の作製方法、及び電子機器 Ceased WO2024100489A1 (ja)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019008483A1 (ja) * 2017-07-06 2019-01-10 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
US20220149166A1 (en) * 2020-11-11 2022-05-12 Samsung Electronics Co., Ltd. Field-effect transistor, field-effect transistor array structure and method of manufacturing field-effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019008483A1 (ja) * 2017-07-06 2019-01-10 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
US20220149166A1 (en) * 2020-11-11 2022-05-12 Samsung Electronics Co., Ltd. Field-effect transistor, field-effect transistor array structure and method of manufacturing field-effect transistor

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