Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/40—Leadframes
  • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/076—Connecting or disconnecting of strap connectors
  • H10W72/07651—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting
  • H10W72/07653—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting changes in shapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
  • H10W72/631—Shapes of strap connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/886—Die-attach connectors and strap connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
  • H10W90/764—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present invention relates to a semiconductor module.
• Semiconductor modules have substrates on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes) are mounted, and are used in inverter devices, etc.
• IGBTs Insulated Gate Bipolar Transistors
• power MOSFETs Metal Oxide Semiconductor Field Effect Transistors
• FWDs Free Wheeling Diodes
• a semiconductor element is placed on an insulating substrate (which may also be called a laminated substrate), and a metal wiring board (which may also be called a lead frame) for wiring is placed on the upper electrode of the semiconductor element.
• the metal wiring board is formed into a predetermined shape, for example, by pressing a metal plate.
• One end of the metal wiring board is electrically joined to the upper electrode via a bonding material such as solder.
• the inside of the case member is filled with sealing resin, and the internal structure including the metal wiring board is covered with the sealing resin.
• a dovetail-shaped groove whose open part is narrower than the width of the bottom is formed in the metal wiring board, and in Patent Document 5, multiple lattice-shaped grooves are formed in the metal wiring board.
• Patent documents 6-9 describe forming multiple dimples on the surface of a metal wiring board and providing protrusions (turned parts, hooked parts) on the inner walls of the dimples to improve the adhesive strength of the sealing resin.
• One method of forming such dimples is to form a hole in a first press process, and then perform a second press process on the periphery of the hole to deform part of the hole and cause a protrusion to protrude from the inner wall.
• the power semiconductor elements generate heat as they switch.
• a metal wiring board is soldered to the surface of a power semiconductor element as described above, there is a risk that distortion will occur at the joint due to fluctuations in internal stress that occur with temperature changes. As a result, it is expected that the adhesion of the sealing resin to the joint of the metal wiring board will decrease.
• the present invention was made in consideration of these points, and one of its objectives is to provide a semiconductor module that can improve adhesion between the joints of the metal wiring board and the sealing resin.
• a semiconductor module comprises a laminated substrate having a plurality of circuit boards arranged on the upper surface of an insulating plate, a semiconductor element arranged on the upper surface of at least one of the circuit boards, and a metal wiring board arranged on the upper surface of the semiconductor element, the metal wiring board having a plate-shaped joint joined to the upper surface of the semiconductor element via a bonding material, and having a plurality of roughened recesses that roughen the upper surface of the joint, each of which is hexagonal in plan view.
• the present invention makes it possible to improve adhesion between the joints of the metal wiring board and the sealing resin in a semiconductor module.
• FIG. 1 is a schematic diagram showing a semiconductor device according to an embodiment of the present invention as viewed from above; 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line AA. 2 is an enlarged view of a metal wiring board according to the present embodiment.
• FIG. 1 is a plan view showing a specific example of a semiconductor module to which a metal wiring board according to an embodiment of the present invention is applied. 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention; 4 is a plan view of the first joint portion of the metal wiring board shown in FIG. 3 as viewed in the direction of arrow B.
• FIG. 7 is a cross-sectional view taken along line CC in FIG. 6.
• FIG. 7 is an enlarged view of part D in FIG. 6 .
• FIG. 7 is an enlarged view of part D in FIG. 6 .
• 11 is a plan view showing a first modified example of a roughened recess provided in a first bonding portion of a metal wiring board.
• FIG. 13 is a plan view showing a second modified example of a roughened recess provided in a first bonding portion of a metal wiring board.
• Fig. 1 is a schematic diagram of a semiconductor device according to the present embodiment as viewed from above.
• Fig. 2 is a cross-sectional view of the semiconductor device shown in Fig. 1 cut along line A-A.
• Fig. 3 is an enlarged view of the metal wiring board according to the present embodiment.
• Fig. 4 is a plan view showing a specific example of a semiconductor module to which the metal wiring board according to the present embodiment is applied.
• Fig. 5 is an equivalent circuit diagram of the semiconductor device according to the present embodiment.
• the semiconductor element 3 is configured to have an inverse-parallel circuit of an IGBT and an FWD connected in series.
• the longitudinal direction of the semiconductor module is defined as the X direction, the short side direction of the semiconductor module (cooler) as the Y direction, and the height direction (thickness direction of the board) as the Z direction.
• the longitudinal direction of the semiconductor module indicates the direction in which multiple circuit boards are arranged.
• the illustrated X, Y, and Z axes are perpendicular to each other and form a right-handed system.
• the X direction may be called the left-right direction, the Y direction as the front-back direction, and the Z direction as the up-down direction.
• the semiconductor device 100 is applied to a power conversion device such as an inverter for an industrial or automotive motor. As shown in Figs. 1 and 2, the semiconductor device 100 is configured by placing a semiconductor module 1 on the upper surface of a cooler 10. Note that the cooler 10 can be configured arbitrarily with respect to the semiconductor module 1.
• the cooler 10 dissipates heat from the semiconductor module 1 to the outside, and has an overall rectangular parallelepiped shape.
• the cooler 10 is configured by providing multiple fins on the underside of a base plate, and these fins are housed in a water jacket.
• the cooler 10 is not limited to this and can be modified as appropriate.
• the semiconductor module 1 is constructed by arranging a laminated substrate 2, a semiconductor element 3, a metal wiring board 4, etc., inside a case 11.
• the laminated substrate 2 is composed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate.
• the laminated substrate 2 is composed of an insulating plate 20, a heat sink 21, and a plurality of circuit boards 22 stacked together, and is formed into a rectangular shape as a whole when viewed from above.
• the insulating plate 20 is formed of a plate-like body having an upper surface and a lower surface, and has a rectangular shape in a plan view that is long in the X direction.
• the insulating plate 20 may be formed of a ceramic material such as aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and zirconium oxide (ZrO 2 ).
• the insulating plate 20 may be formed, for example, from a thermosetting resin such as an epoxy resin or a polyimide resin, or a composite material in which a thermosetting resin is mixed with glass or a ceramic material as a filler.
• the insulating plate 20 is preferably flexible and may be formed, for example, from a material containing a thermosetting resin.
• the insulating plate 20 may also be called an insulating layer or an insulating film.
• the heat sink 21 has a predetermined thickness in the Z direction and a rectangular shape in plan view that is long in the Y direction.
• the heat sink 21 is formed of a metal plate with good thermal conductivity, such as copper or aluminum.
• the heat sink 21 is disposed on the lower surface of the insulating plate 20.
• the lower surface of the heat sink 21 is the mounting surface for the cooler 10 to which the semiconductor module 1 is attached, and also functions as a heat dissipation surface (heat dissipation area) for dissipating heat from the semiconductor module 1.
• the heat sink 21 is bonded to the upper surface of the cooler 10 via a bonding material S1 such as solder.
• the heat sink 21 may be disposed on the upper surface of the cooler 10 via a thermally conductive material such as thermal grease or thermal compound.
• the multiple circuit boards 22 each have a predetermined thickness and are arranged on the upper surface of the insulating plate 20.
• Each circuit board 22 is formed in the shape of an electrically independent island.
• the circuit boards 22 have a rectangular shape in a plan view and are arranged side by side in the X direction on the insulating plate 20.
• the number of circuit boards 22 is not limited to two as shown in FIG. 1 and can be changed as appropriate.
• three or more circuit boards 22 may be arranged on the insulating plate 20.
• the shape, arrangement, etc. of the circuit boards 22 are also not limited to these and can be changed as appropriate.
• These circuit boards 22 are formed from a metal plate with good thermal conductivity, such as copper or aluminum.
• the circuit boards 22 may be called a circuit layer or a circuit pattern.
• a semiconductor element 3 is disposed on the upper surface of a predetermined circuit board 22 (circuit board 22 on the negative side in the X-direction) via a bonding material S2 such as solder.
• the semiconductor element 3 is formed in a rectangular shape in a plan view from a semiconductor substrate such as silicon (Si) or silicon carbide (SiC).
• the semiconductor element 3 may be a power semiconductor element.
• switching elements such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or diodes such as an FWD (Free Wheeling Diode) are used.
• the semiconductor element 3 is composed of an RC (Reverse Conducting)-IGBT element that combines the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.
• RC Reverse Conducting
• IGBT Insulated Gate Bipolar Transistor
• FWD Free Wheeling Diode
• the semiconductor element 3 is not limited to this, and may be configured by combining the above-mentioned switching elements, diodes, etc.
• an IGBT element and an FWD element may be configured separately.
• an RB (Reverse Blocking)-IGBT or the like that has sufficient voltage resistance against reverse bias may be used as the semiconductor element 3.
• the shape, number, and location of the semiconductor element 3 may be changed as appropriate.
• the semiconductor element 3 has electrodes (not shown) formed on its upper and lower surfaces.
• the electrode on the upper surface is composed of an emitter electrode (source electrode) or a gate electrode
• the electrode on the lower surface is composed of a collector electrode (drain electrode).
• the semiconductor element 3 is a so-called vertical switching element in which the above-mentioned functional elements are formed on a semiconductor substrate, but it is not limited to this and may be a horizontal switching element.
• a metal wiring board 4 is disposed on the upper surface of the semiconductor element 3.
• the metal wiring board 4 is composed of a plate-like body having an upper surface and a lower surface, and is formed from a metal material such as copper material, copper alloy material, aluminum alloy material, iron alloy material, etc.
• the metal wiring board 4 is formed into a predetermined shape, for example, by press working. Note that the shape of the metal wiring board 4 shown below is merely an example, and can be modified as appropriate.
• the metal wiring board may also be called a lead frame.
• the metal wiring board 4 is an elongated body extending in the X direction so as to straddle multiple circuit boards 22 in a plan view, and has a crank shape bent multiple times in a side view.
• the metal wiring board 4 includes a first joint 40 joined to the upper surface (upper electrode) of the semiconductor element 3 via a joint material S3, a second joint 41 joined to the upper surface of the circuit board 22 on the positive side in the X direction via a joint material S4, and a connecting portion 42 connecting the first joint 40 and the second joint 41.
• the width of the metal wiring board 4 in the Y direction is uniform from the first joint 40 to the second joint 41.
• the first joint 40, the second joint 41, and the connecting portion 42 are arranged in a line along the X direction in a plan view.
• the width of the metal wiring board 4 in the Y direction does not need to be uniform from the first joint 40 to the second joint 41, and each may have a different width as shown in FIG. 4.
• the first joint 40, the second joint 41, and the connecting portion 42 do not need to be arranged in a line, and each may be arranged diagonally offset as shown in FIG. 4.
• the first joint 40 is formed in a rectangular shape smaller than the outer shape of the semiconductor element 3 in a plan view, and includes a plate-like portion having an upper surface and a lower surface. At the end of the first joint 40 on the positive side in the X direction (the connecting portion 42 side), a first bent portion 43 is formed, which is bent at a substantially right angle and rises upward. One end (left end) of the connecting portion 42 is connected to the upper end of the first bent portion 43.
• the second joint 41 is formed in a rectangular shape smaller than the outline of the circuit board 22 in a plan view, and includes a plate-like portion having an upper surface and a lower surface.
• a second bent portion 44 is formed at the end of the second joint 41 on the negative side in the X direction (the connecting portion 42 side), which is bent at a substantially right angle and rises upward.
• the other end (right end) of the connecting portion 42 is connected to the upper end of the second bent portion 44.
• the connecting portion 42 extends horizontally, and as described above, one end is connected to the first bent portion 43 and the other end is connected to the second bent portion 44.
• the length of the first bend 43 in the Z direction is shorter than that of the second bend 44 by the thickness of the semiconductor element 3.
• the first joint 40 and the second joint 41 are provided at positions with different heights. More specifically, the first joint 40 is provided at a higher position than the second joint 41.
• metal wiring boards 4 are merely examples, and can be modified as appropriate without being limited to these. As will be described in detail later, as shown in FIG. 4, multiple (e.g., four) metal wiring boards 4 may be placed per semiconductor module. In this embodiment, the semiconductor element 3, metal wiring boards 4, and main terminals described later form an inverter circuit, for example, as shown in FIG. 5.
• the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4 are surrounded by a case 11.
• the case 11 has a cylindrical or frame shape with a rectangular ring shape in a plan view, and is formed, for example, from a synthetic resin.
• the case 11 may be formed, for example, from a thermosetting resin material such as epoxy resin or silicone rubber.
• the lower end of the case 11 is adhered to the upper surface of the cooler 10 via an adhesive (not shown), and the upper end extends to a position sufficiently higher than the upper surface of the metal wiring board 4.
• the case 11 surrounds the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4, and defines a space to accommodate the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4.
• the internal space defined by the case 11 is filled with sealing resin 5.
• the sealing resin 5 may be filled up to the top surface of the case 11, thereby sealing the laminated substrate 2, the semiconductor element 3, and the metal wiring board 4.
• the metal wiring board 4 is entirely covered with the sealing resin 5.
• the sealing resin 5 may be made of, for example, a thermosetting resin. It is preferable that the sealing resin 5 contains at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamideimide. For example, an epoxy resin mixed with a filler is preferable for the sealing resin 5 in terms of insulation, heat resistance, and heat dissipation.
• the case 11 may be provided with multiple main terminals 60 for the main current and multiple control terminals 61 for control.
• the main terminals 60 are formed from long, plate-like bodies and are embedded in the side walls of the case 11.
• two main terminals 60 constituting the N terminal and P terminal are arranged side by side in the X direction on the side wall of the case 11 located on the negative side in the Y direction.
• a main terminal 60 constituting the M terminal is arranged on the side wall of the case 11 located on the positive side in the Y direction.
• an inverter circuit such as that shown in FIG. 5 is formed by the semiconductor element 3, the metal wiring board 4, and the main terminals 60.
• These main terminals 60 correspond to IN(N) (which may be called the low potential input terminal or negative terminal), IN(P) (which may be called the high potential input terminal or positive terminal), and OUT(M) (which may be called the output terminal or intermediate terminal) in FIG. 5, respectively.
• the control terminal 61 is formed of a long plate-like body and is embedded in the side wall of the case 11 located on the positive side in the Y direction.
• the control terminal 61 is electrically connected to a predetermined control electrode of the semiconductor element 3 via a wiring member such as a bonding wire.
• These main terminals 60 and control terminals 61 are formed from metal materials such as copper material, copper alloy material, aluminum alloy material, and iron alloy material, and have a predetermined electrical conductivity and a predetermined mechanical strength.
• the shape, number, location, etc. of the main terminals 60 and control terminals 61 are not limited to these and can be changed as appropriate.
• One method for reducing peeling is, for example, to increase the surface area of the metal wiring board and improve the adhesion (anchor effect) between the metal wiring board and the sealing resin.
• One method for increasing the surface area of the metal wiring board is to roughen the surface of the metal wiring board by forming an uneven shape on it.
• the arrangement density of the multiple roughened recesses is increased and peeling of the sealing resin from the metal wiring board is made less likely to progress, improving the anchor effect compared to conventional structures.
• FIG. 6 is a plan view of the first joint 40 of the metal wiring board 4 shown in FIG. 3, as viewed in the direction of arrow B.
• FIG. 7 is a cross-sectional view taken along line C-C in FIG. 6.
• FIGS. 8 and 9 are enlarged views of part D in FIG. 6.
• the first joint 40 which is rectangular in plan view, has a tip outer edge 40a at the tip side in the X direction (the end opposite the connecting portion 42), and a boundary portion 40b that is the boundary with the first bent portion 43 at the end opposite the tip outer edge 40a in the X direction.
• the tip outer edge 40a and the boundary portion 40b each have a linear shape extending in the Y direction.
• the first joint 40 also has a pair of side outer edges 40c and 40d that extend in the X direction and connect both ends of the tip outer edge 40a and the boundary portion 40b.
• the tip outer edge 40a, the boundary portion 40b, the side outer edge 40c, and the side outer edge 40d form the outer edge of the first joint 40, which is rectangular in plan view.
• the upper surface of the first bonding portion 40 is roughened by providing multiple roughened recesses 45.
• Each roughened recess 45 is hexagonal in plan view. Peeling at the interface between the first bonding portion 40 and the sealing resin 5 tends to occur from the end (outer edge) of the first bonding portion 40.
• the hexagonal roughened recesses 45 are easy to arrange at high density, and by providing the roughened recesses 45 evenly over the upper surface of the first bonding portion 40, it is possible to prevent peeling that occurs at the end of the first bonding portion 40 from progressing toward the inner region of the first bonding portion 40.
• each roughened recess 45 has a bottom surface 45a at one end (lower) in the Z direction, and is a bottomed recess whose other end (upper) in the Z direction opens to the upper surface of the first joint portion 40.
• the bottom surface 45a is a regular hexagon, and has six inner wall surfaces 45b extending in the Z direction from each of the six sides of the bottom surface 45a.
• each roughened recess 45 has a hexagonal prism shape surrounded by the bottom surface 45a and the six inner wall surfaces 45b. All of the multiple roughened recesses 45 have the same shape, size, and depth.
• a coating film F may be interposed at the interface between the upper surface of the first bonding portion 40 and the sealing resin 5.
• the upper surface of the first joint 40 is roughened to increase the surface area, improving the adhesion (anchor effect) between the upper surface of the first joint 40 and the sealing resin 5.
• the sealing resin 5 penetrates into the roughened recesses 45. This is expected to provide a further anchor effect. Therefore, it is possible to suppress the progression of peeling of the sealing resin 5 on the upper surface of the metal wiring board 4 above the semiconductor element 3 due to thermal stress.
• the multiple roughened recesses 45 are arranged with their centers located on lattice points Q of a hexagonal lattice (equilateral triangular lattice) in a planar view, and are arranged in the same orientation. Therefore, two adjacent roughened recesses 45 are arranged so that their nearest inner wall surfaces 45b are parallel to each other. There is a predetermined distance K between two adjacent roughened recesses 45 (between the nearest inner wall surfaces 45b). The multiple roughened recesses 45 are arranged at equal intervals over the entire upper surface of the first joint 40 so that the distance K is uniform.
• the roughened recesses 45 can be arranged at high density on the upper surface of the first joint 40.
• the spacing K between the roughened recesses 45 can be narrowed, making it possible to form a large number of roughened recesses 45 on the upper surface of the first joint 40 with good space efficiency. Therefore, compared to using roughened recesses that are rectangular in plan view, etc., an improved anchor effect due to the roughening can be achieved.
• this embodiment is also excellent in preventing the progression of peeling of the sealing resin 5 from the metal wiring board 4 for reasons explained below.
• the upper surface of the first joint 40 has a plurality of roughened recess rows each consisting of a plurality of roughened recesses 45 spaced apart in a first direction.
• the first direction is the direction in which any straight line parallel to the upper surface of the first joint 40 extends.
• the positions of the roughened recesses 45 of two adjacent roughened recess rows are shifted in the first direction, and have an area (overlapping area) where portions of the roughened recesses 45 overlap each other in a second direction perpendicular to the first direction.
• the X direction is the first direction
• the Y direction is the second direction.
• a plurality of roughened recesses 45 arranged at intervals (interval K) in the X direction are referred to as a roughened recess row 45X.
• a series of roughened recesses 45 included in each roughened recess row 45X is represented by being surrounded by a double-dashed line frame.
• the pitch RX the distance between the centers of the roughened recesses 45 arranged in the X direction.
• two adjacent roughened recess rows 45X in the Y direction are arranged with the positions of the roughened recesses 45 shifted in the X direction. More specifically, two adjacent roughened recess rows 45X in the Y direction are arranged with the positions of the roughened recesses 45 shifted in the X direction by a distance of half the pitch RX (half pitch). This makes it possible to bring the two adjacent roughened recess rows 45X closer to each other in the Y direction.
• the two adjacent roughened recess rows 45X are arranged closer to each other in the Y direction so that one roughened recess 45 of one roughened recess row 45X fits between two roughened recesses 45 of the other roughened recess row 45X.
• the two adjacent roughened recess rows 45X in the Y direction have an overlap region Va in the middle region in the Y direction where parts of the roughened recesses 45 of each other are alternately present.
• the overlap region Va is an elongated region that has a predetermined width in the Y direction and extends in the X direction.
• each roughened recess row 45X multiple roughened recesses 45 are arranged in the X direction, so that peeling of the sealing resin 5 from the metal wiring board 4 can be prevented from progressing in the X direction.
• the roughened recesses 45 are always arranged on an arbitrarily set straight line extending in the X direction, and there is no area where the entire X direction is a non-roughened region (an area where the roughened recesses 45 are not formed).
• a plurality of roughened recesses 45 spaced apart in the Y direction is referred to as a roughened recess row 45Y.
• a series of roughened recesses 45 included in each roughened recess row 45Y is represented by being surrounded by a double-dashed line frame.
• the pitch RY the distance between the centers of the roughened recesses 45 lined up in the Y direction.
• Two adjacent roughened recess rows 45Y in the X direction are arranged with the positions of the roughened recesses 45 shifted in the Y direction, and are arranged alternately with the positions shifted in the Y direction by half the pitch RY (half pitch). This makes it possible to bring the two adjacent roughened recess rows 45Y closer together in the X direction.
• the two adjacent roughened recess rows 45Y are arranged closer together in the X direction so that one roughened recess 45 of one roughened recess row 45Y fits between two roughened recesses 45 of the other roughened recess row 45Y.
• the two adjacent roughened recess rows 45Y in the X direction have an overlap region Vb in the middle region in the X direction where parts of the roughened recesses 45 of each row are alternately present.
• the overlap region Vb is a long and narrow region that has a predetermined width in the X direction and extends in the Y direction.
• each roughened recess row 45Y multiple roughened recesses 45 are arranged in the Y direction, so that peeling of the sealing resin 5 from the metal wiring board 4 can be prevented from progressing in the Y direction.
• the roughened recesses 45 are always arranged on an arbitrarily set straight line extending in the Y direction, and there is no area where the entire Y direction is a non-roughened region (an area where the roughened recesses 45 are not formed).
• the roughened recesses 45 are arranged not only on any straight line extending in the X direction and any straight line extending in the Y direction, but also on any straight line extending in a direction intersecting the X direction and the Y direction (diagonal direction), and there are no locations where the entire diagonal direction is a non-roughened region (a region where the roughened recesses 45 are not formed).
• the diagonal direction T1 is shown in FIG. 9.
• the direction perpendicular to the diagonal direction T1 is defined as the orthogonal direction T2.
• the diagonal direction T1 is inclined at 60° (120°) with respect to the X direction and at 30° (150°) with respect to the Y direction.
• a case will be described in which the diagonal direction T1 is defined as the first direction and the orthogonal direction T2 is defined as the second direction.
• a plurality of roughened recesses 45 arranged at intervals in the diagonal direction T1 is defined as a roughened recess row 45T.
• a series of roughened recesses 45 included in each roughened recess row 45T is represented by being surrounded by a double-dashed line frame.
• the distance between the centers of the roughened recesses 45 arranged in the diagonal direction T1 is defined as the pitch RT.
• Two adjacent roughened recess rows 45T in the orthogonal direction T2 are arranged with the positions of the roughened recesses 45 shifted in the diagonal direction T1, and are arranged alternately with the positions shifted by half the pitch RT (half pitch) in the diagonal direction T1. This makes it possible to bring the two adjacent roughened recess rows 45T closer to each other in the orthogonal direction T2.
• the two adjacent roughened recess rows 45T are arranged close to each other in the orthogonal direction T2 so that one roughened recess 45 of one roughened recess row 45T fits between the two roughened recesses 45 of the other roughened recess row 45T.
• the two adjacent roughened recess rows 45T in the orthogonal direction T2 have an overlap region Vc in the middle region of the orthogonal direction T2 where parts of the roughened recesses 45 of each other are alternately present.
• the overlap region Vc is an elongated region that has a predetermined width in the orthogonal direction T2 and extends in the diagonal direction T1.
• each roughened recess row 45T multiple roughened recesses 45 are arranged in the diagonal direction T1, so that peeling of the sealing resin 5 from the metal wiring board 4 can be prevented from progressing in the diagonal direction T1.
• the roughened recesses 45 are always arranged on a straight line extending in the arbitrarily set diagonal direction T1, and there is no place where the entire diagonal direction T1 is a non-roughened region (a region where the roughened recesses 45 are not formed).
• the X direction, Y direction, and diagonal direction T1 are shown as examples of directions (first directions) in which the non-roughened region is not continuous on the top surface of the first joint 40, but in the arrangement structure of the roughened recesses 45 in this embodiment, there are no locations where the non-roughened region is continuous in a straight line in all directions within the roughened range of the top surface of the first joint 40.
• the orthogonal direction T2 in FIG. 9 is the first direction and the diagonal direction T1 is the second direction, the same condition (overlap of two adjacent rows of roughened recesses) as above is satisfied, and the same effect as above can be obtained.
• the roughened recesses 45 will always be located on a straight line extending in the arbitrarily set orthogonal direction T2, and there will be no area where the entire orthogonal direction T2 is a non-roughened area (an area where the roughened recesses 45 are not formed).
• each roughened recess 45 which is hexagonal in plan view, is arranged so that two of the six inner wall surfaces 45b are parallel to the Y direction.
• Figures 10 and 11 show modified examples in which the roughened recesses 45 are arranged in a different direction.
• each roughened recess 45 is hexagonal in plan view and is arranged such that two of the six inner wall surfaces 45b are parallel to the X direction. In other words, the orientation of each roughened recess 45 is rotated 90° (270°) from the orientation of the roughened recess 45 shown in FIG. 6.
• the second modified example shown in FIG. 11 is an arrangement in which each roughened recess 45, which is hexagonal in plan view, is arranged so that all six inner wall surfaces 45b are non-parallel to the X and Y directions. Specifically, the orientation of each roughened recess 45 is rotated 45° (135°) from the orientation of the roughened recess 45 shown in FIG. 6.
• Both the first and second modified examples are common to the above embodiment in that multiple roughened recesses 45 can be arranged at high density on the top surface of the first joint 40, and that there are no linearly continuous non-roughened areas in the area roughened by the multiple roughened recesses 45 (roughened recesses 45 are always present on any straight line along the top surface of the first joint 40). Therefore, the same effects as the above embodiment can be obtained.
• none of the six inner wall surfaces 45b of the roughened recess 45 are parallel to the tip outer edge 40a, boundary 40b, side outer edge 40c, and side outer edge 40d of the first joint 40, so there is a slight bias in the arrangement density of the roughened recess 45 on the outer edge side of the first joint 40.
• two of the six inner wall surfaces 45b of the roughened recess 45 are parallel to the tip outer edge 40a and boundary 40b of the first joint 40, and the roughened recess 45 is evenly arranged at a position along the side outer edge 40c and side outer edge 40d.
• two of the six inner wall surfaces 45b of the roughened recess 45 are parallel to the side outer edge 40c and side outer edge 40d of the first joint 40, and the roughened recess 45 is evenly arranged at a position along the tip outer edge 40a and boundary 40b.
• each of the multiple roughened recesses 45 it is preferable to arrange each of the multiple roughened recesses 45 so that two of the six inner wall surfaces 45b are oriented parallel to the end (outer edge) of the first joint 40.
• the configurations of this embodiment and the modified examples are highly effective in preventing peeling of the sealing resin 5 on the upper surface of the first joint 40 of the metal wiring board 4, and can improve adhesion between the metal wiring board 4 and the sealing resin 5.
• Each of the multiple roughened recesses 45 that roughen the upper surface of the first joint 40 has a simple hexagonal shape in a plan view, which has the advantage that they can be easily formed on the metal wiring board 4 at low cost.
• the roughened recesses 45 can be formed by pressing the metal wiring board 4.
• the semiconductor element 3 which is a heat source, is located directly below the first joint 40, the first joint 40 is greatly affected by the anchor effect due to the roughening. Therefore, it is desirable to provide multiple roughened recesses 45 on at least the top surface of the first joint 40 of the metal wiring board 4.
• the portions of the metal wiring board 4 other than the first joint 40 i.e., the connecting portion 42, the first bent portion 43, and the second bent portion 44, have less effect on peeling of the sealing resin 5 compared to the first joint 40, so the presence or absence of the roughened recesses 45 can be appropriately selected.
• the processing cost of the metal wiring board 4 can be reduced.
• the surfaces of the second joint 41, the connecting portion 42, the first bent portion 43, and the second bent portion 44 are flat, and the surface roughness thereof may be equivalent to the surface roughness of the underside of the first joint 40.
• a plurality of roughened recesses 45 are arranged at equal intervals over substantially the entire upper surface of the first joint 40 of the metal wiring board 4, but a portion of the upper surface of the first joint 40 may be a non-roughened area that does not have a roughened recess 45.
• the location where the wire is connected may be a non-roughened area.
• a protrusion protruding upward from the metal wiring board 4 or a through hole penetrating the upper and lower surfaces of the metal wiring board 4 may be used as a non-roughened area.
• the roughened recesses 45 can be provided at high density around the non-roughened area, so that the above-mentioned effect of the roughened recesses 45 can be obtained.
• the multiple roughened recesses 45 provided on the upper surface of the first joint 40 have the same depth in the Z direction.
• the roughening process becomes easier and it becomes easier to control the shape precision of the first joint 40.
• there is no limit to the depth of the multiple roughened recesses and it is also possible to adopt a configuration in which roughened recesses of different depths are mixed.
• the multiple roughened recesses 45 provided on the upper surface of the first joint 40 are all the same size in a plan view, but it is also possible to make some of the roughened recesses different sizes.
• roughened recesses having a smaller area in a plan view than the roughened recesses 45 may be arranged in the areas near the outer edges along the tip outer edge 40a, boundary portion 40b, side outer edge 40c, and side outer edge 40d of the first joint 40. This allows the first joint 40 to be efficiently roughened up to the vicinity of the outer edge while obtaining the above-mentioned effects of the roughened recesses 45.
• the number and placement of the semiconductor elements are not limited to the above configuration and can be changed as appropriate.
• the number and layout of the circuit boards are not limited to the above configuration and can be changed as appropriate.
• the laminated substrate and the semiconductor element are configured to be rectangular or square in plan view, but are not limited to this configuration. These configurations may be formed into polygonal shapes other than those described above.
• the present embodiment is not limited to the above-mentioned embodiment and modifications, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may be included within the scope of the technical idea.
• the semiconductor module of the above embodiment comprises a laminated substrate having a plurality of circuit boards arranged on an upper surface of an insulating plate, a semiconductor element arranged on the upper surface of at least one of the circuit boards, and a metal wiring plate arranged on the upper surface of the semiconductor element, the metal wiring plate having a plate-shaped joint joined to the upper surface of the semiconductor element via a bonding material and a plurality of roughened recesses for roughening the upper surface of the joint, each of which is hexagonal in a planar view.
• the roughened recesses are arranged such that their centers are located on lattice points of a hexagonal lattice in a plan view of the joint, and are oriented in the same direction.
• the upper surface of the joint has a plurality of roughened recess rows each consisting of a plurality of the roughened recesses arranged at intervals in a first direction, and two adjacent roughened recess rows are arranged such that the positions of the roughened recesses are shifted from each other in the first direction, and have an area where portions of the roughened recesses overlap each other in a second direction perpendicular to the first direction.
• the joint is rectangular in plan view, and the first direction and the second direction include a direction parallel to the outer edge of the joint and a direction intersecting the outer edge of the joint.
• each of the roughened recesses has six inner wall surfaces that form a hexagon in plan view, two of which are arranged parallel to the outer edge of the joint.
• the present invention has the effect of improving the adhesion between the joints of the metal wiring board and the sealing resin, and is particularly useful for semiconductor modules for industrial or electrical equipment use.

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• Engineering & Computer Science (AREA)
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• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Structure Of Printed Boards (AREA)

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• 2023
  • 2023-10-10 WO PCT/JP2023/036711 patent/WO2024095714A1/ja not_active Ceased
  • 2023-10-10 JP JP2024554352A patent/JP7848886B2/ja active Active
  • 2023-10-10 CN CN202380037107.0A patent/CN119110985A/zh active Pending
• 2024
  • 2024-10-31 US US18/934,226 patent/US20250062272A1/en active Pending

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