WO2024088532A1 - Procédé de polarisation de récepteur optique pour amplificateur optique à semi-conducteur intégré de manière monolithique et photodiode - Google Patents

Procédé de polarisation de récepteur optique pour amplificateur optique à semi-conducteur intégré de manière monolithique et photodiode Download PDF

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Publication number
WO2024088532A1
WO2024088532A1 PCT/EP2022/079967 EP2022079967W WO2024088532A1 WO 2024088532 A1 WO2024088532 A1 WO 2024088532A1 EP 2022079967 W EP2022079967 W EP 2022079967W WO 2024088532 A1 WO2024088532 A1 WO 2024088532A1
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WO
WIPO (PCT)
Prior art keywords
photodiode
cathode terminal
voltage
soa
optical
Prior art date
Application number
PCT/EP2022/079967
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English (en)
Inventor
Ahmer IQBAL
Giuseppe Talli
Ricardo ROSALES
Kebede Tesema ATRA
Youxi Lin
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/EP2022/079967 priority Critical patent/WO2024088532A1/fr
Publication of WO2024088532A1 publication Critical patent/WO2024088532A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H04B10/697—Arrangements for reducing noise and distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H04B10/691—Arrangements for optimizing the photodetector in the receiver
    • H04B10/6911—Photodiode bias control, e.g. for compensating temperature variations

Definitions

  • the present disclosure relates to optical receivers, for example, to optoelectronic receivers deployed in Passive Optical Networks (PONs), where the optoelectronic receivers comprise photodiodes and semiconductor optical amplifier (SOA) devices to facilitate higher data rates.
  • PONs Passive Optical Networks
  • SOA semiconductor optical amplifier
  • the photodiode and the SOA of an optoelectronic receiver may be monolithically integrated onto a shared semiconductor substrate.
  • the SOA cathode terminal may be connected to the cathode terminal of the photodiode via the substrate resistance of the shared semiconductor substrate. Consequently, if the substrate resistance is finite, despite it being large, a small current may flow between the SOA cathode terminal and the cathode terminal of the photodiode via the substrate, especially when the cathode terminal voltages of the SOA and the photodiode differ from each other. This current may appear as a dark current component of the current flowing out of the photodiode, which may increase the receiver noise and therefore may reduce sensitivity.
  • this disclosure aims to provide an improved optical receiver and a biasing method.
  • An objective is to reduce dark current components, even if the photodiode and the SOA of the optical receiver are integrated on a common substrate.
  • Another objective is to adapt the voltages and currents of the SOA and the photodiode to address the above-mentioned limitations.
  • an optical receiver comprises a semiconductor optical amplifier (SOA) comprising an anode terminal and a cathode terminal, the SOA being configured to receive an optical input signal and to generate an optical output signal based on the optical input signal, a photodiode comprising an anode terminal and a cathode terminal, the photodiode being configured to receive the optical output signal from the SOA, and a circuitry configured to copy a voltage at the cathode terminal of the photodiode to the cathode terminal of the SOA.
  • the SOA and the photodiode are monolithically integrated on a common substrate.
  • this disclosure presents a solution to synchronize terminal voltages of the SOA and the photodiode, especially at the respective cathode terminals of the SOA and the photodiode.
  • the circuitry comprises a first voltage regulator configured to regulate the voltage at the cathode terminal of the photodiode with respect to a reference voltage.
  • the first voltage regulator may comprise or be a conventional low-dropout (LDO) voltage regulator, which may regulate the biasing voltage of the photodiode, especially at the cathode terminal, with respect to the reference voltage.
  • LDO low-dropout
  • the first voltage regulator comprises a first transistor coupled between a source voltage and the cathode terminal of the photodiode, and a first differential amplifier configured to drive the first transistor based on the reference voltage and the voltage at the cathode terminal of the photodiode.
  • This may facilitate a closed feedback-loop operation in order to regulate the biasing voltage of the photodiode with respect to the reference voltage.
  • the voltage at the cathode terminal of the photodiode is greater than a voltage at the anode terminal of the photodiode. This may allow to maintain a reverse operating region bias voltage across the photodiode.
  • the circuitry comprises a second voltage regulator coupled between the first voltage regulator and the cathode terminal of the SOA, the second voltage regulator being configured to regulate the voltage at the cathode terminal of the SOA with respect to the voltage at the cathode terminal of the photodiode, thereby copying the voltage at the cathode terminal of the photodiode to the cathode terminal of the SOA.
  • the second voltage regulator may act as a LDO voltage regulator, which may regulate the biasing voltage of the SOA, especially at the cathode terminal of the SOA, with respect to the biasing voltage of the photodiode.
  • the second voltage regulator comprises a second transistor coupled between the cathode terminal of the SOA and a ground potential, and a second differential amplifier configured to drive the second transistor based on the voltage at the cathode terminal of the photodiode and the voltage at the cathode terminal of the SOA.
  • This may facilitate a closed feedback-loop operation in order to regulate the biasing voltage of the SOA with respect to the biasing voltage of the photodiode.
  • the voltage at the cathode terminal of the SOA is lower than a voltage at the anode terminal of the SOA.
  • the second voltage regulator is configured to sink a current from the cathode terminal of the SOA to ground through the second transistor.
  • the first transistor and the second transistor are power field-effect transistors or complementary metal-oxide semiconductor field-effect transistors or bipolar junction transistors or heterojunction bipolar transistors.
  • the common substrate is a photonic integrated circuit (PIC) substrate.
  • the photodiode is a PIN photodiode.
  • the optical receiver is configured to operate at a data rate greater than or equal to 1 Gb/s. Additionally, the optical receiver may be configured to operate at very high data rates, for example, a data rate greater than or equal to 50 Gb/s.
  • a method for biasing an optical receiver comprising a semiconductor optical amplifier (SOA) and a photodiode monolithically integrated on a common substrate, the semiconductor optical amplifier comprises an anode terminal and a cathode terminal and the photodiode comprises an anode terminal and a cathode terminal.
  • the method comprises the steps of connecting the SOA and the photodiode by a circuitry, and copying a voltage at the cathode terminal of the photodiode to the cathode terminal of the SOA by the circuitry when the optical receiver is operated.
  • the method according to the second aspect corresponds to the optical receiver according to the first aspect and its implementation forms. Accordingly, the method of the second aspect may have corresponding implementation forms. Further, the method of the second aspect achieves the same advantages and effects as the optical receiver of the first aspect and its respective implementation forms.
  • Fig. 1 shows an exemplary diagram of the optical receiver according to this disclosure
  • Fig. 2A shows a first exemplary scenario of substrate current flow between the cathode terminals of the SOA and the photodiode
  • Fig. 2B shows a second exemplary scenario of substrate current flow between the cathode terminals of the SOA and the photodiode
  • Fig. 3 shows the circuitry of the optical receiver in detail
  • Fig. 4 shows an exemplary flow diagram of the method according to this disclosure.
  • the optical receiver 100 may comprise a SOA 101 comprising an anode terminal 102 and a cathode terminal 103.
  • the SOA 101 may receive an optical input signal 104, for example, from an optical network terminal or node via optical fiber cables.
  • the SOA 101 may generate an optical output signal 105 based on the received optical input signal 104.
  • the SOA 101 may comprise a semiconductor, for example, a group III-V compound semiconductor such as GaAs/AlGaAs, InP/InGaAs, InP/InGaAsP and InP/InAlGaAs, or a group II- VI direct bandgap semiconductor, to provide the gain medium.
  • a group III-V compound semiconductor such as GaAs/AlGaAs, InP/InGaAs, InP/InGaAsP and InP/InAlGaAs, or a group II- VI direct bandgap semiconductor
  • the optical receiver 100 may further comprise a photodiode 106 comprising an anode terminal 107 and a cathode terminal 108.
  • the photodiode 106 may receive the optical output signal 105 from the SOA 101.
  • the photodiode 106 may be a PIN photodiode, e.g., having a wide, undoped intrinsic semiconductor region between a p-type semiconductor region and an n-type semiconductor region.
  • the photodiode 106 may generate an electrical signal 111 (e.g., current) based on the received optical output signal 105 along the anode terminal 107 of the photodiode 106.
  • the SOA 101 and the photodiode 106 may be monolithically integrated on a common semiconductor substrate 110, for instance, to form a photonic integrated circuit chip.
  • the substrate 110 may comprise or be of silicon, silica, silicon nitride, InP or a nonlinear crystal material such as lithium niobate.
  • the substrate 110 may further comprise an optical bandpass filter (not shown), e.g., a Fabry-Perot type bandpass filter, especially between the SOA 101 and the photodiode 106, to pass one or more predefined wavelength bands corresponding to the optical input signal 104 from the SOA 101 to the photodiode 106 while blocking others.
  • the optical receiver 100 may further comprise a circuitry 109 operably coupled to the cathode terminal 103 and optionally to the anode terminal 102 of the SOA 101, and further to the cathode terminal 108 of the photodiode 106.
  • the circuitry 109 may copy a voltage at the cathode terminal 108 of the photodiode 106 to the cathode terminal 103 of the SOA 101 while further providing biasing for the SOA 101 and the photodiode 106.
  • the circuitry 109 may further provide the bias sink current for the SOA 101.
  • the structure and operation of the circuitry 109 will be described later in detail.
  • the optical receiver 100 may further comprise an amplifier, for example, a trans-impedance amplifier (TIA) 112, operably coupled to the anode terminal 107 of the photodiode 106.
  • the TIA 112 may receive the electrical signal 111 generated from the photodiode 106, especially generated based on the received optical output signal 105.
  • the TIA 112 may operate as a current to voltage converter while amplifying the current output of the photodiode 106, i.e., the electrical signal 111, to a usable electrical signal 113, e.g. a voltage.
  • the optical receiver 100 may further comprise a processing block or processor 114 operably coupled to the TIA 112.
  • the processing block 114 may receive the usable electrical signal 113, e.g. a voltage, from the TIA 112, and may perform post-processing and/or synthesis of the usable electrical signal 113.
  • the processing block 114 may comprise or be interfaced to a Media Access Controller device (not shown).
  • FIGs. 2A-2B two exemplary scenarios of substrate current flow between the cathode terminals of the SOA 101 and the photodiode 106 are illustrated.
  • Fig. 2 A shows a first exemplary scenario of substrate current flow between the cathode terminals of the SOA 101 and the photodiode 106, especially when the SOA 101 and the photodiode 106 are monolithically integrated on the semiconductor substrate 110.
  • Vbias may denote the voltage at the anode terminal 102 of the SOA 101
  • Vsoa may denote the voltage at the cathode terminal 103 of the SOA 101
  • Isoax may denote the SOA bias current along the anode terminal 102 of the SOA 101
  • Isoa may denote the SOA bias sink current along the cathode terminal 103 of the SOA 101.
  • Vpd may denote the voltage at the cathode terminal 108 of the photodiode 106
  • Vano may denote the voltage at the anode terminal 107 of the photodiode 106
  • Ipdx may denote the photodiode bias current along the cathode terminal 108 of the photodiode
  • Ipd may denote the photodiode current along the anode terminal 107 of the photodiode 106.
  • the cathode terminal 103 of the SOA 101 may be connected to the cathode terminal 108 of the photodiode 106 via the resistive substrate, which is exemplarily illustrated herein as a substrate resistance 200.
  • the substrate resistance 200 may have a finite but very large resistive value, however, due to the finite value of the substrate resistance 200, a small current Isub may flow through the substrate resistance 200 when a mismatch occurs between the voltages Vsoa and Vpd, which may be later translated as the dark current, i.e., the flow of current in the absence of an incoming light signal.
  • the voltage Vsoa is greater than the voltage Vpd, i.e., a mismatch between the voltages Vsoa and Vpd occurs, which may result in the current Isub flowing from the cathode terminal 103 of the SOA 101 to the cathode terminal 108 of the photodiode 106 through the semiconductor substrate 110.
  • Fig. 2B shows a second exemplary scenario of substrate current flow between the cathode terminals of the SOA 101 and the photodiode 106, especially when the SOA 101 and the photodiode 106 are monolithically integrated on the semiconductor substrate 110.
  • the voltage Vsoa is smaller than the voltage Vpd, i.e., a mismatch between the voltages Vsoa and Vpd occurs, which may result in the current Isub flowing from the cathode terminal 108 of the photodiode 106 to the cathode terminal 103 of the SOA 101 through the semiconductor substrate 110.
  • a mismatch between the voltages Vsoa and Vpd may result in the magnitude of the current Isub greater than zero, which may flow between the SO A 101 and the photodiode 106 through the semiconductor substrate 110 even in the absence of an optical transmission between the SOA 101 and the photodiode 106.
  • the circuitry 109 of the optical receiver 100 especially the components of the circuitry 109 and their connections to the SOA 101 and the photodiode 106, are illustrated by way of an example.
  • the circuitry 109 may comprise a first voltage regulator 310 that may regulate the voltage Vpd at the cathode terminal 108 of the photodiode 106 with respect to a reference voltage Vref.
  • the first voltage regulator 310 may comprise a first differential amplifier 311 and a first transistor, for example, a PFET 314.
  • the inverting terminal 312 of the first differential amplifier 311 may input the reference voltage Vref and the non-inverting terminal 313 of the first differential amplifier 311 may be coupled to a common node 316, which may be further coupled to the cathode terminal 108 of the photodiode 106, especially to regulate the voltage Vpd at the cathode terminal 108 of the photodiode 106.
  • the output of the first differential amplifier 311 may be coupled to the PFET 314, especially to the gate terminal of the PFET 314.
  • the PFET 314 may be coupled between a source voltage 315 and the common node 316, thereby effectively coupled between the source voltage 315 at the source terminal of the PFET 314 and the cathode terminal 108 of the photodiode 106 at the drain terminal of the PFET 314.
  • the PFET 314 in combination with the first differential amplifier 311, may act as the photodiode current source to provide the photodiode bias current Ipdx along the cathode terminal 108 of the photodiode 106.
  • the first voltage regulator 310 may regulate the voltage Vpd at the cathode terminal 108 of the photodiode 106 such that the voltage Vpd at the cathode terminal remains larger compared to the voltage Vano at the anode terminal 107 of the photodiode 106 in order to maintain a reverse-bias condition of the photodiode 106.
  • the anode terminal 107 of the photodiode 106 may be further coupled to the TIA 112 (not shown) to feed the photodiode current Ipd generated by the photodiode 106.
  • the circuitry 109 may further comprise a second voltage regulator 320 coupled between the first voltage regulator 310 and the cathode terminal 103 of the SO A 101.
  • the second voltage regulator 320 may regulate the voltage Vsoa at the cathode terminal 103 of the SOA 101 with respect to the voltage Vpd at the cathode terminal 108 of the photodiode 106.
  • the second voltage regulator 320 may comprise a second differential amplifier 321 and a second transistor, for example, an NFET 324.
  • the inverting terminal 322 of the second differential amplifier 321 may be coupled to the common node 316, thereby effectively coupled to the cathode terminal 108 of the photodiode 106, and the non-inverting terminal 323 of the second differential amplifier 321 may be coupled to the cathode terminal 103 of the SOA 101, especially to regulate the voltage Vsoa at the cathode terminal 103 of the SOA 101 with respect to the voltage Vpd at the cathode terminal 108 of the photodiode 106.
  • the output of the second differential amplifier 321 may be coupled to the NFET 324, especially to the gate terminal of the NFET 324.
  • the NFET 324 may be coupled between the cathode terminal 103 of the SOA 101 and a ground potential 326, thereby effectively coupled between the cathode terminal 103 of the SOA 101 at the drain terminal of the NFET 324 and the ground potential 326 at the source terminal of the NFET 324.
  • the NFET 324 in combination with the second differential amplifier 321, may act as the SOA current sink to provide the SOA bias sink current Isoa along the cathode terminal 103 of the SOA 101.
  • the circuitry 109 may optionally comprise a current source 330 coupled to the anode terminal 102 of the SOA 101.
  • the current source 330 may provide the SOA bias current Isoax along the anode terminal 102 of the SOA 101, thereby forcing the SOA bias voltage Vbias at the anode terminal 102 of the SOA 101.
  • the current source 330 may force the SOA bias voltage Vbias at the anode terminal 102 of the SOA 101 such that the SOA bias voltage Vbias remains larger compared to the voltage Vsoa at the cathode terminal 103 of the SOA 101 in order to maintain a forward-bias condition of the SOA 101.
  • the current source 330 may be implemented as an integrated component or as an external component of the circuitry 109.
  • the current source 330 may be a constant current source, for example, a field-effect transistor-based current source or a bipolar junction transistor-based current source or a combination thereof.
  • the second differential amplifier 321 may form a closed feedback loop around the NFET 324 to copy the voltage Vpd at the cathode terminal 108 of the photodiode 106 through the common node 316 onto the cathode terminal 103 of the SOA 101.
  • the second voltage regulator 320 may force the voltage Vsoa at the cathode terminal 103 of the SOA 101 according to the voltage Vpd at the cathode terminal 108 of the photodiode 106 whilst simultaneously acting as a current sink with the magnitude of Isoa.
  • a SOA and a photodiode monolithically integrated on a common substrate are connected by a circuitry.
  • a voltage at the cathode terminal of the photodiode is copied to the cathode terminal of the SOA by the circuitry when the optical receiver is operated.
  • the embodiments of this disclosure provide the advantageous effect of enabling high performance, low cost and/or low area and/or low loss PICs containing a SOA and a PIN photodiode combination to be utilized in very high data rate (>50 Gb/s), very high sensitivity optoelectronic receivers, especially within PONs.
  • the embodiments of this disclosure enable synchronization of the SOA cathode terminal voltage to the cathode terminal voltage of the photodiode, thereby reducing the dark current flowing between the SOA and photodiode cathode terminals within the PIC substrate, hence minimizing degradation of receiver noise.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)

Abstract

La présente divulgation concerne des récepteurs optiques, par exemple, des récepteurs optoélectroniques déployés dans des réseaux optiques passifs (PON), les récepteurs optoélectroniques comprenant des photodiodes et des dispositifs d'amplificateur optique à semi-conducteur (SOA). Un récepteur optique de la présente divulgation comprend un SOA comprenant une borne d'anode et une borne de cathode, le SOA étant configuré pour recevoir un signal d'entrée optique et pour générer un signal de sortie optique sur la base du signal d'entrée optique. Le récepteur optique comprend en outre une photodiode comprenant une borne d'anode et une borne de cathode, la photodiode étant configurée pour recevoir le signal de sortie optique provenant de l'amplificateur optique à semi-conducteur. Le récepteur optique comprend également des circuits configurés pour copier une tension au niveau de la borne de cathode de la photodiode vers la borne de cathode de l'amplificateur optique à semi-conducteur et pour fournir simultanément un courant absorbé de polarisation pour le SOA. À cet égard, l'amplificateur optique à semi-conducteur et la photodiode sont intégrés de manière monolithique sur un substrat commun.
PCT/EP2022/079967 2022-10-26 2022-10-26 Procédé de polarisation de récepteur optique pour amplificateur optique à semi-conducteur intégré de manière monolithique et photodiode WO2024088532A1 (fr)

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PCT/EP2022/079967 WO2024088532A1 (fr) 2022-10-26 2022-10-26 Procédé de polarisation de récepteur optique pour amplificateur optique à semi-conducteur intégré de manière monolithique et photodiode

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PCT/EP2022/079967 WO2024088532A1 (fr) 2022-10-26 2022-10-26 Procédé de polarisation de récepteur optique pour amplificateur optique à semi-conducteur intégré de manière monolithique et photodiode

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120049934A1 (en) * 2010-08-30 2012-03-01 Analog Devices, Inc. Low-leakage diodes and methods of forming the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120049934A1 (en) * 2010-08-30 2012-03-01 Analog Devices, Inc. Low-leakage diodes and methods of forming the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SOBHANAN ANEESH ET AL: "Semiconductor optical amplifiers: recent advances and applications", UNIVERSITY OF ROCHESTER, vol. 14, no. 3, 20 September 2022 (2022-09-20), pages 571, XP093052189, Retrieved from the Internet <URL:https://opg.optica.org/viewmedia.cfm?URI=aop-14-3-571&am=y> [retrieved on 20230606], DOI: 10.1364/AOP.451872 *

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