WO2024088231A1 - 信号处理方法、装置、设备、介质及芯片 - Google Patents

信号处理方法、装置、设备、介质及芯片 Download PDF

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Publication number
WO2024088231A1
WO2024088231A1 PCT/CN2023/126090 CN2023126090W WO2024088231A1 WO 2024088231 A1 WO2024088231 A1 WO 2024088231A1 CN 2023126090 W CN2023126090 W CN 2023126090W WO 2024088231 A1 WO2024088231 A1 WO 2024088231A1
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data
signal
module
heap
sorting
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English (en)
French (fr)
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梁华文
肖世海
袁伟
田腾
金西
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Huawei Technologies Co Ltd
University of Science and Technology of China USTC
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Huawei Technologies Co Ltd
University of Science and Technology of China USTC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Definitions

  • the present disclosure relates to the field of computers, and more specifically, to a signal processing method, device, equipment, medium and chip.
  • the Top-K algorithm is usually used to find the first K largest elements or smallest elements in an unordered sequence of multiple data, which can be implemented using a heap structure.
  • a heap is a set of data built based on a complete binary tree data structure.
  • Common heaps include a maximum heap and a minimum heap.
  • the properties of a maximum heap include that its nodes satisfy the key value or index of the child node is always greater than its parent node, and the root node at the top of the heap is the maximum value of all elements in the heap;
  • the properties of a minimum heap include that its nodes satisfy the key value or index of the child node is always less than its parent node, and the root node at the top of the heap is the minimum value of all elements in the heap.
  • Heaps are widely used in priority queues, as well as finding the first K largest elements or smallest elements in an unordered sequence of multiple data, namely the Top-K algorithm.
  • the Top-K algorithm is often used in scenarios such as similarity retrieval, recommendation systems, and databases.
  • the embodiments of the present application provide a signal processing method and related electronic devices for optimizing and realizing the rapid finding of the top largest elements or the smallest elements in large-scale disordered data.
  • a signal processing method comprising: inputting multiple signals into a multi-sorting module, the multi-sorting module comprising N sorting modules connected in series in a ring, each of the N sorting modules comprising a Top-K module having K elements, the multi-sorting module comprising a first sorting module and a second sorting module, the first sorting module comprising a first Top-K module, the signal output by the first sorting module that is discarded by the first Top-K module or the top element of the replaced first Top-K module is used as the input signal of the second sorting module.
  • the elements in the multiple Top-K modules in the multi-sorting module are updated. And the M data with the highest order in the multiple signals are obtained, wherein the value of M is the product of N and K, and N, K, and M are positive integers.
  • the implementation of the method of this aspect can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the first sorting module includes a first buffer and a first Top-K module
  • the second sorting module includes a second buffer and a second Top-K module
  • the output of the first buffer of the first sorting module is used as the input of the first Top-K module of the first sorting module
  • the output of the first Top-K module of the first sorting module is used as the input of the second buffer of the second sorting module
  • the output of the second buffer of the second sorting module is used as the input of the second Top-K module of the second sorting module.
  • the buffers and Top-K modules between the sorting modules are alternately connected, and the structure of multiple sorting modules connected in series in a ring can improve processing efficiency.
  • the plurality of signals include a first external signal and a second external signal
  • the first external signal is an input of the first sorting module
  • the second external signal is an input of the second sorting module
  • the method further includes: the first sorting module receives the first external signal, the first sorting module obtains a first write-back signal based on the first external signal, and the first sorting module sends the first write-back signal to the second sorting module.
  • the second sorting module receives the second external signal, the second sorting module receives the first write-back signal, the second sorting module obtains a second write-back signal based on the second external signal and/or the first write-back signal, and the second sorting module sends the second write-back signal to the third sorting module.
  • the first sorting module and the second sorting module are connected in series to improve processing efficiency, and data not needed by the first sorting module can be continued to be processed by the second sorting module to avoid repeated input and processing.
  • the first buffer includes a first first-in-first-out queue (FIFO), a first control logic module, and a first multiplexer, the first multiplexer is used to receive a first external signal, the first first-in-first-out queue is used to receive and cache multiple write-back signals multiple times, and the first first-in-first-out queue is also used to output the first cache signal after being filled with multiple write-back signals, and the second buffer includes a second first-in-first-out queue, a second control logic module, and a second multiplexer, the second multiplexer is used to receive a second external signal, the second first-in-first-out queue is used to receive and cache multiple write-back signals output by the first Top-K module of the first sorting module multiple times, the multiple write-back signals include the first write-back signal, and the second first-in-first-out queue is also used to output the second cache signal after being filled with multiple write-back signals.
  • FIFO first-in-first-out queue
  • the first multiplexer is used
  • the control logic and the multiplexer are used to select the input signal entering the heap based on the cache signal output by the first-in-first-out queue, the input external signal, and the global heap top value.
  • the first-in-first-out queue is used to cache the write-back data output by the previous sorting module.
  • the purpose of setting the first-in-first-out queue to cache the write-back data is because the global The top value of the stack output by the maximum value module will be delayed by several cycles relative to the input signal. Therefore, after the write-back signal is input into the first-in-first-out queue in the buffer, it will not be read until the first-in-first-out queue is full. At this time, the cached signal is the input from multiple cycles ago and will be delayed relative to the global top value of the stack. This is beneficial for the control logic to exert better screening performance and avoid the write-back signal being transmitted in multiple stacks without being screened out.
  • the second sorting module obtains the second write-back signal based on the second external signal and/or the first write-back signal, including: the second control logic module determines the second input signal based on the second external signal and/or the second cache signal, the second multiplexer outputs the second input signal to the second Top-K module, the second Top-K module receives the second input signal from the second multiplexer, and the second Top-K module obtains the second write-back signal based on the second input signal.
  • the second sorting module sends the second write-back signal to the third sorting module, including: the second Top-K module sends the second write-back signal to the third buffer of the third sorting module.
  • the Top-K module is alternately connected to the buffer, which can improve the signal processing efficiency.
  • the second control logic module determines the second input signal based on the second external signal and/or the second cache signal, including: determining whether the second first-in-first-out queue outputs the second cache signal. If the second first-in-first-out queue outputs the second cache signal, then determining whether the second cache signal is valid. If the second cache signal is valid, then comparing the data of the second cache signal with the global top value. If the data of the second cache signal does not exceed the global top value, the second control logic module determines the second cache signal as the second input signal, and if the data of the second cache signal exceeds or equals the global top value, the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module determines the second external signal as the second input signal. And if the second external signal is invalid, the second control logic module reads the third cache signal cached in the non-empty second first-in-first-out queue as the second input signal. That is, the cache signal overflowing in the first-in-first-out queue is processed before the external signal. When there is no overflowing cache signal in the first-in-first-out queue, the valid external signal is used as the input signal of the stack.
  • the write-back signal of the cache that has not overflowed in the non-empty first-in-first-out queue can be read as the input signal of the stack.
  • the first write-back signal includes data of the first write-back signal and a first write-back enable signal, and the first write-back enable signal indicates whether the first write-back signal is valid.
  • the second external signal includes data of the second external signal and a second external enable signal, and the second external enable signal indicates whether the second external signal is valid.
  • the second cache signal includes data of the second cache signal and a second cache enable signal, and the second cache enable signal indicates whether the second cache signal is valid.
  • the Top-K module is a maximum heap
  • the global top value is the maximum value among the data of the top elements of multiple maximum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is less than the maximum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is greater than or equal to the maximum value.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the Top-K module is a minimum heap
  • the global top value is the minimum value among the data of the top elements of multiple minimum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is greater than the minimum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is less than or equal to the minimum value.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second Top-K module obtains a second write-back signal based on a second input signal, including: determining whether the second input signal is valid, and if the second input signal is valid, comparing the data of the second input signal with the data of the current top element of the second Top-K module. If the data of the second input signal does not exceed the data of the current top element of the second Top-K module, the data of the second input signal replaces the data of the current top element of the second Top-K module to become a new element in the second Top-K module, and the data of the current top element of the replaced second Top-K module is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data not needed by the current Top-K module is passed to the next sorting module for processing or discarded in time, which can reduce the number of comparisons required during sorting and save processing resources and storage resources.
  • the method further includes: if the second input signal is invalid, using the data of the second input signal as the data of the second write-back signal, and enabling the second write-back signal to be invalid.
  • the data determined to be useless can be sent to the FIFO of the next sorting module.
  • the control logic of the next sorting module decides to discard the data.
  • the method further includes: the second Top-K module updates the new top element of the second Top-K module, and the second Top-K module sends the top element of the second Top-K module to the global maximum value module.
  • the global maximum value module is used to obtain the top elements of multiple Top-K modules, the global maximum value module is also used to select the maximum value among the data of the top elements of multiple Top-K modules, and the global maximum value module is also used to send the maximum value to the control logic modules in multiple buffers. Since the element replaced into the Top-K module is not necessarily the maximum value in the Top-K module, the Top-K module needs to update the new top element before the next input signal enters the stack to ensure the accuracy of the next processing.
  • the second Top-K module is a maximum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is less than the data of the current top element of the maximum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than or equal to the data of the current top element of the maximum heap.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the second Top-K module is a minimum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than the data of the current top element of the minimum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is less than or equal to the data of the current top element of the minimum heap.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second buffer determines a second input signal based on a second external signal and/or a second cache signal, and within a second time period, the second Top-K module obtains a second write-back signal based on the second input signal.
  • a sorting module can completely complete a processing job, and an iteration cycle can be divided into two time periods, such as a first time period and a second time period. In some embodiments, the first time period is equal to the second time period.
  • the processing cycle in which the buffer determines and selects the data entering the heap is executed alternately with the processing cycle in which the heap processes the input data and outputs the write-back data.
  • Each sorting module can process data in parallel, which can improve processing efficiency, reduce waiting time and processing time, and make full use of processing resources.
  • the multi-sorting module is a multi-heap structure
  • the Top-K module is a heap
  • the multi-heap structure includes multiple heaps
  • each of the multiple heaps includes K elements
  • the multi-heap structure outputs M data
  • the M data is a collection of all elements in the multiple heaps of the multi-heap structure.
  • the working parallelism of the multi-heap structure can be increased to N, achieving a higher data throughput, improving signal processing efficiency, and the size of each heap in the multi-heap structure is reduced to M/N, improving the performance of a single heap, saving storage resources, computing resources and processing resources, and reducing data storage, data transmission, data processing and processing time.
  • the M data are the first M data with the smallest sorted data in multiple signals, and the top element of the maximum heap is the element with the largest data in the maximum heap; if the heap is a minimum heap, the M data are the first M data with the largest sorted data in multiple signals, and the top element of the minimum heap is the element with the smallest data in the minimum heap.
  • the maximum heap helps to screen the minimum value, and the minimum heap helps to screen the maximum value.
  • a signal processing device comprising: an input module, configured to input multiple signals to a multi-sorting module, the multi-sorting module comprising N sorting modules connected in series in a ring, each of the N sorting modules comprising a Top-K module having K elements, the multi-sorting module comprising a first sorting module and a second sorting module, the first sorting module comprising a first Top-K module, the signal discarded by the first Top-K module or the top element of the replaced first Top-K module output by the first sorting module as the input signal of the second sorting module.
  • a processing module configured to update the elements in multiple Top-K modules in the multi-sorting module based on multiple signals.
  • an output module configured to obtain M data with the highest order in the multiple signals, wherein the value of M is the product of N and K, and N, K, and M are positive integers.
  • the signal processing device implemented in this aspect can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the first sorting module includes a first buffer and a first Top-K module
  • the second sorting module includes a second buffer and a second Top-K module
  • the output of the first buffer of the first sorting module is used as the input of the first Top-K module of the first sorting module
  • the output of the first Top-K module of the first sorting module is used as the input of the second buffer of the second sorting module
  • the output of the second buffer of the second sorting module is used as the input of the second Top-K module of the second sorting module.
  • the buffers and Top-K modules between the sorting modules are alternately connected, and the structure of multiple sorting modules connected in series in a ring can improve processing efficiency.
  • the plurality of signals include a first external signal and a second external signal
  • the first external signal is an input of the first sorting module
  • the second external signal is an input of the second sorting module
  • the first sorting module is used to receive the first external signal
  • the first sorting module is also used to obtain a first write-back signal based on the first external signal
  • the first sorting module is also used to send the first write-back signal to the second sorting module.
  • the second sorting module is used to receive the second external signal, the second sorting module is also used to receive the first write-back signal, and the second sorting module is also used to The second sorting module is further used to obtain the second write-back signal based on the second external signal and/or the first write-back signal, and the second sorting module is further used to send the second write-back signal to the third sorting module.
  • the first sorting module and the second sorting module are connected in series to improve processing efficiency, and data not needed by the first sorting module can be processed by the second sorting module to avoid repeated input and processing.
  • the first buffer includes a first first-in-first-out queue, a first control logic module, and a first multiplexer, the first multiplexer is used to receive a first external signal, the first first-in-first-out queue is used to receive and cache multiple write-back signals multiple times, and the first first-in-first-out queue is also used to output the first cache signal after being filled with multiple write-back signals, and the second buffer includes a second first-in-first-out queue, a second control logic module, and a second multiplexer, the second multiplexer is used to receive a second external signal, the second first-in-first-out queue is used to receive and cache multiple write-back signals output by the first Top-K module of the first sorting module multiple times, the multiple write-back signals include the first write-back signal, and the second first-in-first-out queue is also used to output the second cache signal after being filled with multiple write-back signals.
  • the control logic and the multiplexer are used to select the input signal entering the heap based on the cache signal output by the first-in-first-out queue, the input external signal, and the global heap top value.
  • the first-in-first-out queue is used to cache the write-back data output by the previous sorting module.
  • the purpose of setting the first-in-first-out queue to cache write-back data is that the top value of the stack output by the global maximum value module will be delayed by several cycles relative to the input signal. Therefore, after the write-back signal is input to the first-in-first-out queue in the buffer, it will not be read until the first-in-first-out queue is full. At this time, the cached signal is the input from multiple cycles ago and will be delayed relative to the global top value of the stack, which is beneficial for the control logic to exert better screening performance and avoid the write-back signal being transmitted in multiple stacks without being screened out.
  • the second control logic module is further used to determine the second input signal based on the second external signal and/or the second cache signal
  • the second multiplexer is further used to output the second input signal to the second Top-K module
  • the second Top-K module is used to receive the second input signal from the second multiplexer
  • the second Top-K module is further used to obtain a second write-back signal based on the second input signal.
  • the second Top-K module is also used to send the second write-back signal to the third buffer of the third sorting module.
  • the Top-K module is alternately connected to the buffer, which can improve the signal processing efficiency.
  • the second control logic module is used to execute the following judgment logic: determine whether the second first-in-first-out queue outputs the second cache signal. If the second first-in-first-out queue outputs the second cache signal, then determine whether the second cache signal is valid. If the second cache signal is valid, compare the data of the second cache signal with the global top value. If the data of the second cache signal does not exceed the global top value, the second control logic module determines the second cache signal as the second input signal, and if the data of the second cache signal exceeds or equals the global top value, the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module is also used to execute the following judgment logic: if the second first-in-first-out queue does not output the second cache signal, then determine whether the second external signal is valid. If the second external signal is valid, the second control logic module determines the second external signal as the second input signal. And if the second external signal is invalid, the second control logic module reads the third cache signal cached in the non-empty second first-in-first-out queue as the second input signal. That is, the cache signal overflowing in the first-in-first-out queue is processed before the external signal. When there is no overflowing cache signal in the first-in-first-out queue, the valid external signal is used as the input signal of the stack.
  • the write-back signal of the cache that has not overflowed in the non-empty first-in-first-out queue can be read as the input signal of the stack.
  • the first write-back signal includes data of the first write-back signal and a first write-back enable signal, and the first write-back enable signal indicates whether the first write-back signal is valid.
  • the second external signal includes data of the second external signal and a second external enable signal, and the second external enable signal indicates whether the second external signal is valid.
  • the second cache signal includes data of the second cache signal and a second cache enable signal, and the second cache enable signal indicates whether the second cache signal is valid.
  • the Top-K module is a maximum heap
  • the global top value is the maximum value among the data of the top elements of multiple maximum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is less than the maximum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is greater than or equal to the maximum value.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the Top-K module is a minimum heap
  • the global top value is the minimum value among the data of the top elements of multiple minimum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is greater than the minimum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is less than or equal to the minimum value.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second Top-K module is used to execute the following judgment logic: the second Top-K module obtains a second write-back signal based on a second input signal, including: judging whether the second input signal is valid, and if the second input signal is valid, comparing the data of the second input signal with the data of the current top element of the second Top-K module.
  • the data of the second input signal replaces the data of the current top element of the second Top-K module to become a new element in the second Top-K module, and the data of the current top element of the replaced second Top-K module is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data not needed by the current Top-K module is passed to the next sorting module for processing or discarded in time, which can reduce the number of comparisons required during sorting and save processing resources and storage resources.
  • the second Top-K module is further used to execute the following judgment logic: if the second input signal is invalid, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled to be invalid.
  • the data determined to be useless can be sent to the FIFO of the next sorting module, and the control logic of the next sorting module decides to discard the data.
  • the second Top-K module is also used to update the new top element of the second Top-K module, and the second Top-K module is also used to send the top element of the second Top-K module to the global maximum value module.
  • the global maximum value module is used to obtain the top elements of multiple Top-K modules, the global maximum value module is also used to select the maximum value among the data of the top elements of multiple Top-K modules, and the global maximum value module is also used to send the maximum value to the control logic modules in multiple buffers. Since the element replaced into the Top-K module is not necessarily the maximum value in the Top-K module, the Top-K module needs to update the new top element before the next input signal enters the stack to ensure the accuracy of the next processing.
  • the second Top-K module is a maximum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is less than the data of the current top element of the maximum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than or equal to the data of the current top element of the maximum heap.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the second Top-K module is a minimum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than the data of the current top element of the minimum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is less than or equal to the data of the current top element of the minimum heap.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second buffer determines a second input signal based on a second external signal and/or a second cache signal, and within a second time period, the second Top-K module obtains a second write-back signal based on the second input signal.
  • a sorting module can completely complete a processing job, and an iteration cycle can be divided into two time periods, such as a first time period and a second time period. In some embodiments, the first time period is equal to the second time period.
  • the processing cycle in which the buffer determines and selects the data entering the heap is executed alternately with the processing cycle in which the heap processes the input data and outputs the write-back data.
  • Each sorting module can process data in parallel, which can improve processing efficiency, reduce waiting time and processing time, and make full use of processing resources.
  • the multi-sorting module is a multi-heap structure
  • the Top-K module is a heap
  • the multi-heap structure includes multiple heaps
  • each of the multiple heaps includes K elements
  • the multi-heap structure outputs M data
  • the M data is a collection of all elements in the multiple heaps of the multi-heap structure.
  • the working parallelism of the multi-heap structure can be increased to N, achieving a higher data throughput, improving signal processing efficiency, and the size of each heap in the multi-heap structure is reduced to M/N, improving the performance of a single heap, saving storage resources, computing resources, and processing resources, and reducing data storage, data transmission, data processing, and processing time.
  • the M data are the first M data with the smallest sorted data in multiple signals, and the top element of the maximum heap is the element with the largest data in the maximum heap; if the heap is a minimum heap, the M data are the first M data with the largest sorted data in multiple signals, and the top element of the minimum heap is the element with the smallest data in the minimum heap.
  • the maximum heap helps to screen the minimum value, and the minimum heap helps to screen the maximum value.
  • an electronic device comprising a memory and a processor coupled to the memory, wherein the memory stores executable instructions, and the processor is used to call the executable instructions so that the electronic device performs the following operations according to the method in the first aspect or any one of its embodiments.
  • a computer-readable storage medium which stores computer-executable instructions.
  • the operations of the method according to the first aspect or any one of its embodiments are implemented.
  • a computer program product which includes computer executable instructions.
  • the computer executable instructions When the computer executable instructions are executed, the operations of the method according to the first aspect or any one of its embodiments are implemented.
  • a chip or a chip system which includes a processing circuit configured to implement the operation of the method according to the above-mentioned first aspect or any one of its embodiments.
  • Implementing one or more of the above aspects of the present application can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • FIG1 shows a schematic diagram of a stack structure according to some embodiments of the present disclosure
  • FIG2 is a schematic diagram showing a signal processing method flow according to some embodiments of the present disclosure.
  • FIG3 is a schematic diagram showing functional modules of a data processing system according to some embodiments of the present disclosure.
  • FIG4 shows a schematic diagram of a multi-stack structure according to some embodiments of the present disclosure
  • FIG5 shows a schematic diagram of a sorting module of a multi-pile structure according to some embodiments of the present disclosure
  • FIG6 is a schematic diagram showing a control logic flow of a sorting module of a multi-stack structure according to some embodiments of the present disclosure
  • FIG7 shows a schematic diagram of a stack module according to some embodiments of the present disclosure
  • FIG8 is a schematic diagram showing a stack control logic flow of a stack module according to some embodiments of the present disclosure.
  • FIG9 shows a schematic diagram of a dual stack structure according to some embodiments of the present disclosure.
  • FIG10 shows a schematic diagram of a sorting module of a dual-heap structure according to some embodiments of the present disclosure
  • FIG11 is a schematic diagram showing a control logic flow of a sorting module of a dual-heap structure according to some embodiments of the present disclosure
  • FIG12 is a schematic diagram showing a stack control logic flow of a stack module according to some embodiments of the present disclosure.
  • FIG. 13 shows a schematic diagram of a structure of an electronic device according to some embodiments of the present disclosure.
  • the term “including” and similar terms should be understood as open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be understood as “at least one embodiment”. It should be understood that the expressions “first”, “second”, “third” and the like are only intended to indicate that multiple objects may be different, but at the same time do not exclude that two objects are the same.
  • the expressions “first”, “second”, “third” and the like should not be interpreted as any limitation on the embodiments.
  • the terms “first” and “second” are used only for descriptive purposes and should not be understood as implying or suggesting relative importance or implicitly indicating the number of technical features indicated.
  • first and second may explicitly or implicitly include one or more of the features.
  • the meaning of “multiple” is two or more.
  • Other explicit and implicit definitions may also be included below.
  • Exemplary application scenarios can be, for example, finding the 100 videos with the highest click-through rates in a continuously updated mass of videos for recommendation; another example, assigning tasks to the 10 devices with the lowest CPU utilization in a distributed system; another example, generating a list of the top 100 game players with the highest game scores based on a massive and continuously updated data of game players.
  • a heap structure of a maximum heap or a minimum heap can be used to find the top K smallest or largest data tuples that are dynamically updated in large-scale data.
  • the update operation of the heap usually starts from the root node, which limits the parallelism of the heap.
  • N is a positive integer
  • O logN
  • the heap structure 100 divides all the data to be processed into two parts, namely, database 101 and database 102, which are respectively input into heap 103 and heap 104 of size K (K is a positive integer) to complete Top-K sorting, namely, database 101 inputs heap 103 for Top-K sorting, and database 102 inputs heap 104 for Top-K sorting, and then the results in heap 103 and heap 104 are finally reduced to a Top-K result, namely, heap 105.
  • heap 103 and heap 104 work simultaneously, and the degree of parallelism is 2.
  • the first Top-K sort can be completed by using more heaps of size K, and then the results of multiple first Top-K sorts can be gradually reduced to the final Top-K results.
  • this solution still has the subsequent step of refining K elements, which will cause a waste of storage space, computing resources, and processing resources.
  • the size of the heap in this solution is K.
  • K When K is large, it will bring greater challenges to the on-chip cache and will not improve the performance of a single heap. Therefore, the hardware resource overhead is often large and the parallelism is poor.
  • the signal processing method may include: inputting multiple signals into a multi-sorting module, the multi-sorting module includes multiple sorting modules connected in series in a ring, each of the multiple sorting modules includes a Top-K module, the multiple sorting modules include a first sorting module and a second sorting module, and the output of the first sorting module serves as the input of the second sorting module. Based on the multiple signals, the elements in the multiple Top-K modules are updated, and the elements in the multiple Top-K modules in the multiple sorting modules are output.
  • Implementing the signal processing method and electronic device in one or more embodiments of the present disclosure can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • FIG. 2 shows a schematic diagram of a signal processing method flow 200 of an embodiment of the present application.
  • the electronic device implementing the signal processing method may be a smart phone, a tablet computer, a personal computer, a desktop computer, a laptop computer, a handheld computer, a game console, a smart screen (smart TV), a drone, an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, a car machine (on-board device), an Internet of Things (IOT) device or other types of electronic devices, etc.
  • the embodiment of the present application does not limit the specific type of the electronic device.
  • the multi-sorting module includes multiple sorting modules connected in series in a ring, such as N sorting modules, each of the multiple sorting modules includes a Top-K module with K elements, and the multi-sorting module includes a first sorting module and a second sorting module, and the output of the first sorting module is used as the input of the second sorting module.
  • the first sorting module includes a first Top-K module, and the signal output by the first sorting module that is discarded by the first Top-K module or the top element of the first Top-K module that is replaced is used as the input signal of the second sorting module.
  • the multiple signals are external signals outside the multi-sorting module, and the external signals can be, for example, network data signals, such as the video click-through rate data signal mentioned in the above application scenario, or CPU utilization signal, or game score data signal, etc.
  • the external signal can include data tuples and enable signals.
  • the multi-sorting module can be implemented as a multi-heap structure 400 shown in Figure 4, or a dual-heap structure 900 shown in Figure 9.
  • the Top-K module can be implemented as a heap, such as a maximum heap or a minimum heap.
  • elements in multiple Top-K modules in the multi-sorting module are updated based on multiple signals.
  • the external signal input into the multi-sorting module is filtered out and replaced with the original elements in the Top-K module as one of the required Top-K elements after being processed by the multi-sorting module.
  • the multi-sorting module is a structure composed of multiple heap rings connected in series. The output signal of a Top-K module will be input to the next Top-K module, thereby transmitting the external signal in sequence until it enters a Top-K module or is discarded.
  • the set of multiple elements in the multiple Top-K modules that have been sorted in the multi-sorting module is the required Top-K elements.
  • Implementing the signal processing method in the above embodiment can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the multi-sorting module is a multi-heap structure
  • the Top-K module is a heap
  • the multi-heap structure includes multiple heaps
  • each of the multiple heaps includes K elements
  • the multi-heap structure outputs M data
  • the M data is a collection of all elements in the multiple heaps of the multi-heap structure.
  • the working parallelism of the multi-heap structure can be increased to N, achieving higher data throughput, improving signal processing efficiency, and the size of each heap in the multi-heap structure is reduced to M/N, improving the performance of a single heap, saving storage resources, computing resources and processing resources, and reducing data storage, data transmission, data processing and processing time.
  • the M data are the first and the last data with the smallest sorting data among the multiple signals.
  • the top element of the max heap is the largest element in the max heap; if the heap is a min heap, then the M data are the first M data with the largest sorted data in multiple signals, and the top element of the min heap is the smallest element in the min heap.
  • the max heap helps to filter the minimum value, and the min heap helps to filter the maximum value.
  • the first sorting module includes a first buffer and a first Top-K module
  • the second sorting module includes a second buffer and a second Top-K module
  • the output of the first buffer of the first sorting module is used as the input of the first Top-K module of the first sorting module
  • the output of the first Top-K module of the first sorting module is used as the input of the second buffer of the second sorting module
  • the output of the second buffer of the second sorting module is used as the input of the second Top-K module of the second sorting module.
  • the buffers and Top-K modules between the sorting modules are alternately connected, and the structure of multiple sorting modules connected in series in a ring can improve processing efficiency.
  • the plurality of signals include a first external signal and a second external signal
  • the first external signal is an input of the first sorting module
  • the second external signal is an input of the second sorting module
  • the method further includes: the first sorting module receives the first external signal, the first sorting module obtains a first write-back signal based on the first external signal, and the first sorting module sends the first write-back signal to the second sorting module.
  • the second sorting module receives the second external signal, the second sorting module receives the first write-back signal, the second sorting module obtains a second write-back signal based on the second external signal and/or the first write-back signal, and the second sorting module sends the second write-back signal to the third sorting module.
  • the first sorting module and the second sorting module are connected in series to improve processing efficiency, and data not needed by the first sorting module can be processed by the second sorting module to avoid repeated input and processing.
  • the multi-heap structure 400 includes a plurality of sorting modules connected in series in a ring, such as a sorting module 500 (which can be a first sorting module or a second sorting module), each sorting module has a corresponding data source input Ik (i.e., one of the plurality of signals, or referred to as an external signal, such as a second external signal), a heap (such as a first Top-K module/first heap or a second Top-K module/second heap), an output Tk of the data value at the top of the heap (i.e., a signal of the top element/top element of the heap), an input WBk -1 of the current sorting module (such as a first write-back signal), an input WBk of the next single sorting module (such as a second write-back signal), and a global heap
  • Ik i.e., one of the plurality of signals, or referred to as an external signal, such as a second external signal
  • a heap such as a
  • N single heap structures are alternately connected through N buffers, so that the outputs and inputs of the N sorting modules are connected end to end in a ring.
  • the scalable high-parallel multi-heap structure shown in FIG4 can have N separate signal inputs, and N-way signal inputs can be completed simultaneously to find the common TOP-M data values in a large number of data inputs of these N-way signals.
  • the multi-stack structure may also be a dual-stack structure 900 as shown in the embodiment of FIG. 9 .
  • FIG. 9 For details, please refer to the embodiment described in the subsequent FIG. 9 , which will not be described in detail here.
  • the first buffer includes a first first-in-first-out queue, a first control logic module and a first multiplexer, the first multiplexer is used to receive a first external signal, the first first-in-first-out queue is used to multiple times receive and cache multiple write-back signals, and the first first-in-first-out queue is also used to output a first cache signal after being filled with multiple write-back signals.
  • the second sorting module (such as the sorting module 500 shown in FIG. 5 or the buffer 1000 shown in FIG. 10 ) includes a second buffer (refer to the buffer 510 shown in FIG. 5 or the buffer 1010 shown in FIG. 10 ), and the second buffer (such as the buffer 510 shown in FIG. 5 or the buffer 1010 shown in FIG.
  • a second first-in-first-out queue such as the FIFO 550 shown in FIG. 5 or the FIFO 1050 shown in FIG. 10
  • a second control logic module such as the control logic 520 shown in FIG. 5 or the control logic 1020 shown in FIG. 10
  • a second multiplexer such as the multiplexer 530 shown in FIG. 5 or the multiplexer 1030 shown in FIG.
  • the second multiplexer (such as MUX k ) is used to receive a second external signal (such as I k ), the second first-in-first-out queue (such as FIFO k ) is used to multiple times receive and cache multiple write-back signals (such as WB k-1 ) output by the first Top-K module of the first sorting module, the multiple write-back signals include the first write-back signal, and the second first-in-first-out queue is also used to output a second cache signal (such as WB′) after being filled with the multiple write-back signals. k-1 ).
  • a second external signal such as I k
  • the second first-in-first-out queue (such as FIFO k ) is used to multiple times receive and cache multiple write-back signals (such as WB k-1 ) output by the first Top-K module of the first sorting module
  • the multiple write-back signals include the first write-back signal
  • the second first-in-first-out queue is also used to output a second
  • the control logic (such as C k ) and the multiplexer (such as MUX k ) are used to select the input signal entering the heap (such as heap k ) based on the cache signal (or cache write-back signal, such as WB′ k-1 ) output by the first-in-first-out queue (such as FIFO k), the input external signal (such as I k ) and the global top value of the heap (such as T g ).
  • the first-in-first-out queue is used to cache the write-back data output by the previous sorting module.
  • the purpose of setting the first-in-first-out queue to cache the write-back data is that the top value of the heap output by the global top value module will be delayed by several cycles relative to the input signal.
  • the cache signal is input multiple cycles ago and will be delayed relative to the global top value of the heap, which is conducive to the control logic to play a better screening performance and avoid the write-back signal from being transmitted in multiple heaps without being screened out.
  • the second control logic module determines the second input signal (such as DI k ) based on the second external signal (such as I k ) and/or the second cache signal (such as WB′ k-1 ).
  • the second multiplexer (such as MUX k ) outputs the second input signal (such as DI k) to the second Top-K module (such as heap k ).
  • the second Top-K module (such as heap k ) receives the second input signal (such as DI k ) from the second multiplexer (such as MUX k ).
  • the second Top-K module (such as heap k ) obtains the second write-back signal (such as WB k) based on the second input signal (such as DI k ) .
  • the second Top-K module (such as heap k ) sends the second write-back signal (such as WB k ) to the third buffer of the third sorting module.
  • the Top-K module is alternately connected to the buffer, which can improve the signal processing efficiency.
  • the second control logic executes the following judgment logic: judging whether the second FIFO queue outputs the second cache signal. If the second FIFO queue outputs the second cache signal, then judging whether the second cache signal is valid. If the second cache signal is valid, The data of the second cache signal is compared with the global top value. If the data of the second cache signal does not exceed the global top value, the second control logic module determines the second cache signal as the second input signal. If the data of the second cache signal exceeds or is equal to the global top value, the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the global maximum value maximum value or minimum value
  • the number of comparisons required during sorting can be reduced, saving the consumption of processing resources.
  • on-chip storage resources such as cache memory can be better utilized, and the utilization efficiency of different on-chip resources can be improved.
  • the top maximum value output Tk of the single heap module represents the top of the current heap structure in this sorting module.
  • Signal Tg represents the maximum value obtained from the N top inputs, that is, the global maximum value (also called the global top maximum value).
  • the second control logic also executes the following judgment logic: if the second first-in-first-out queue does not output the second cache signal, then determine whether the second external signal is valid. If the second external signal is valid, the second control logic module determines the second external signal as the second input signal. And if the second external signal is invalid, the second control logic module reads the third cache signal cached in the non-empty second first-in-first-out queue as the second input signal. That is, the cache signal overflowing in the first-in-first-out queue is processed before the external signal. When there is no overflowing cache signal in the first-in-first-out queue, the valid external signal is used as the input signal of the heap.
  • the write-back signal (such as the third cache signal) of the cache that is not overflowed in the non-empty first-in-first-out queue can be read as the input signal of the heap.
  • the judgment logic executed by the second control logic can be understood in conjunction with the working process 600 of the control logic shown in reference FIG. 6 or the embodiment of the working process 1100 of the control logic shown in FIG. 11, which will not be repeated here.
  • the first write-back signal includes data of the first write-back signal and a first write-back enable signal, and the first write-back enable signal indicates whether the first write-back signal is valid.
  • the second external signal includes data of the second external signal and a second external enable signal, and the second external enable signal indicates whether the second external signal is valid.
  • the second cache signal includes data of the second cache signal and a second cache enable signal, and the second cache enable signal indicates whether the second cache signal is valid.
  • the data source I k represents the data to be sorted of the external output.
  • the data source I k (such as the second external signal) further specifically includes a data signal I_data k (such as the data of the second external signal) and an enable signal I_en k (such as the second external enable signal).
  • the enable signal I_en k indicates whether the data signal I_data k is valid.
  • the input signal WB k-1 from the previous sorting module of the ring structure to the current FIFO k specifically includes the data signal WB_data k-1 (such as the data of the first write-back signal) and the enable signal WB_en k-1 (such as the first write-back enable signal), and the enable signal WB_en k-1 indicates whether the data signal WB_data k-1 is valid.
  • the cache write-back signal WB′ k-1 (such as the second cache signal) output by the FIFO k in the current sorting module specifically includes the data signal WB_data′ k-1 (such as the data of the second cache signal) and the enable signal WB_en′ k-1 (such as the second cache enable signal), and the enable signal WB_en′ k-1 indicates whether the data signal WB_data′ k-1 is valid.
  • the current single sorting module outputs WB k as the input of the next single sorting module.
  • WB k is specifically divided into the data signal WB_data k and the enable signal WB_en k , and the enable signal WB_en k indicates whether the data signal WB_data k is valid. In some embodiments, whether the external signal is valid depends on the cycle of the alternating input.
  • the Top-K module is a maximum heap
  • the global top value is the maximum value among the data of the top elements of multiple maximum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is less than the maximum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is greater than or equal to the maximum value.
  • the structure of the maximum heap can help find a predetermined number of minimum values among multiple input data.
  • the Top-K module is a minimum heap
  • the global top value is the minimum value among the data of the top elements of multiple minimum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is greater than the minimum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is less than or equal to the minimum value.
  • the structure of the minimum heap can help find a predetermined number of maximum values among multiple input data.
  • the second Top-K module may execute the following judgment logic: judge whether the second input signal is valid, and if the second input signal is valid, compare the data of the second input signal with the data of the current top element of the second Top-K module. If the data of the second input signal does not exceed the data of the current top element of the second Top-K module, replace the data of the current top element of the second Top-K module with the data of the second input signal to become a new element in the second Top-K module, and use the data of the current top element of the replaced second Top-K module as the data of the second write-back signal, and enable the second write-back signal to be valid.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, use the data of the second input signal as the data of the second write-back signal, and enable the second write-back signal to be valid.
  • the data not needed by the current Top-K module is passed to the next sorting module for processing or discarded in time, which can reduce the number of comparisons required during sorting and save processing resources and storage resources.
  • the second Top-K module further executes the following judgment logic: if the second input signal is invalid, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled to be invalid.
  • the data determined to be useless can be sent to the FIFO of the next sorting module, and the control logic of the next sorting module decides to discard the data.
  • the second Top-K module updates the new top element of the second Top-K module.
  • the heap structure performs a heapization operation to update the new top element of the heap structure, wherein the heapization operation refers to sorting and updating the elements in the heap.
  • the second Top-K module sends the top element of the second Top-K module to the global maximum value module.
  • the global maximum value module is used to obtain the top elements of multiple Top-K modules, and the global maximum value module is also used to select the maximum value among the data of the top elements of multiple Top-K modules.
  • the global maximum value module is also used to send the maximum value to the control logic module in multiple buffers. Since the element replaced into the Top-K module is not necessarily the maximum value in the Top-K module, the Top-K module needs to update the new top element before the next input signal enters the heap to ensure the accuracy of the next processing.
  • the heap data is generally a hierarchical structure with a heap top. If it is a maximum heap, the heap top is the maximum value of the heap, and if it is a minimum heap, the heap top is the minimum value of the heap. Taking the maximum heap as an example, the common K maximum values of the data in the N data input channels can be obtained.
  • the heap module 700 has an input signal DI k (such as a second input signal) as an input of the heap module (heap k ) (such as a second Top-K module).
  • the specific input signal DI k is further divided into a data signal DI_data k and an enable signal DI_en k , and the enable signal DI_en k indicates whether the data signal DI_data k is valid.
  • the output of the heap module 700 is a data signal WB_data k and an enable signal WB_en k , and the enable signal WB_en k indicates whether the data signal WB_data k is valid.
  • the structure of the second heap and the judgment logic executed can be understood in conjunction with the heap module 700 shown in FIG7-FIG8 and the workflow 800 of the heap control logic or the embodiment of the workflow 1200 of the control logic shown in FIG12, and will not be repeated here.
  • the second Top-K module is a maximum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is less than the data of the current top element of the maximum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than or equal to the data of the current top element of the maximum heap.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the second Top-K module is a minimum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than the data of the current top element of the minimum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is less than or equal to the data of the current top element of the minimum heap.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second buffer determines a second input signal based on a second external signal and/or a second cache signal, and within a second time period, the second Top-K module obtains a second write-back signal based on the second input signal.
  • a sorting module can completely complete a processing job, and an iteration cycle can be divided into two time periods, such as a first time period and a second time period. In some embodiments, the first time period is equal to the second time period.
  • the processing cycle in which the buffer determines and selects the data entering the heap is executed alternately with the processing cycle in which the heap processes the input data and outputs the write-back data.
  • Each sorting module can process data in parallel, which can improve processing efficiency, reduce waiting time and processing time, and make full use of processing resources.
  • some embodiments of the present disclosure can realize a scalable and highly parallel multi-heap structure for large-scale data sorting, and its parallelism can be increased to N, achieving higher data throughput, and for the multi-heap structure for obtaining M Top data, the size of each heap is reduced to M/N, which improves the performance of a single heap, can save storage resources, computing resources and processing resources, and reduce processing time, so as to obtain the required multiple top-ranked data more quickly.
  • the scalable ring-shaped multi-input multi-heap structure can include N sorting modules connected in series head to tail and a global maximum value (maximum value or minimum value) module, and each sorting module can include at least a single heap structure, a buffer, a data source, etc.
  • the buffer receives the write-back data from the previous sorting module and the data from the external data source, receives the global maximum value (maximum value or minimum value), and outputs the data to the corresponding heap.
  • Each buffer includes at least a first-in-first-out queue, a multiplexer and corresponding control logic.
  • the first-in-first-out queue is used to buffer the write-back data output by the heap of the previous sorting module, and the multiplexer and its control logic are used to select the input signal of the heap input to its own sorting module.
  • the heap of each sorting module receives the output of its own multiplexer, generates write-back data and outputs it to the buffer of the next sorting module, and inputs the top of the heap to the global maximum value module. All the heaps and buffers are alternately connected to form a ring structure.
  • the buffer isolates the output of the adjacent previous heap, all heaps can work synchronously or asynchronously, and the input data is transmitted unidirectionally between heaps through the heap's write-back data and the buffer until it enters a certain heap or is thrown away when compared with the global maximum value.
  • the global maximum value (maximum value or minimum value) can constrain the transmission of data, and the data stored in each heap will not be wasted. Therefore, the multi-heap structure of some embodiments of the present disclosure can utilize the ordered nature of the data arrangement in the heap, and through the series connection between the heaps and the constraint of the global maximum value (maximum value or minimum value), the number of comparisons required for sorting is reduced, so that hardware resources are consumed less and storage resources are saved.
  • the processing resource overhead is reduced and the throughput is improved, and Top sorting of larger data volumes and concurrent operation of multiple multi-heap structures can be achieved, and based on In this multi-heap structure, the data stored in each heap will not be wasted, and on-chip storage resources (such as static random access memory (SRAM)) can be better utilized to improve the utilization efficiency of different on-chip resources.
  • SRAM static random access memory
  • FIG3 shows a schematic diagram of the functional modules of the data processing system 300 provided by some embodiments of the present application.
  • the embodiment of the present application can divide the data processing system 300 into functional modules.
  • each function of the data processing system 300 can be divided into each functional module, or two or more functions of the data processing system 300 can be integrated into one functional module, which is not limited in the present embodiment.
  • the above-mentioned integrated module can be implemented in the form of hardware or software, or in the form of a combination of hardware and software.
  • the data processing system 300 includes a storage module 301 , a control module 302 , a data processing module 303 , and a data consumption module 304 , wherein the data processing module 303 also includes a pre-processing module 305 , a sorting module 306 , and a post-processing module 307 .
  • the data processing system 300 can be a dedicated accelerator system based on a dedicated integrated circuit chip and a hardware system based on a programmable logic device.
  • the data processing module 303 may include an application-specific integrated circuit chip (ASIC).
  • ASIC application-specific integrated circuit chip
  • the data processing module 303 includes a programmable logic device (FPGA).
  • the storage subsystem consists of an on-chip SRAM buffer, a random access memory (DDR or HBM), and a non-volatile memory (SSD or HHD) on an ASIC or FPGA.
  • the data consumption module 304 can be a local general-purpose computer system or a remote client application.
  • the application scenario of the present disclosure can be for a computer system that requires data sorting, such as a cloud computing platform to accelerate similarity search, a recommendation system, and a Top sort calculation in a database system.
  • the embodiments of the present disclosure may be implemented in software and hardware in a dedicated accelerator system or a programmable hardware system.
  • the control module 302 controls the input and output of data of the storage module 301 and the control of other modules in the data processing module 303.
  • the pre-processing module 305 and the post-processing module 307 may have different implementations according to different application scenarios.
  • the pre-processing module 305 may process the data input from the off-chip storage system to obtain the data required for sorting; the sorting module 306 is used to perform sorting; the post-processing module 307 may further process the sorting result to obtain the result that can be output to the data consumption module 304.
  • the sorting module 306 may execute one or more corresponding embodiments described in the aforementioned method 200, the sorting module 306 includes an on-chip storage unit, the intermediate result of the sorting is stored on-chip during the sorting process, and the sorting result is output to the post-processing module 307.
  • the pre-processing module 305, the sorting module 306 and the post-processing module 307 may all be implemented on-chip, wherein the control module 302 may be implemented using a general-purpose processor or on an accelerator chip.
  • Implementing the functional modules in the data processing system 300 of the embodiment of the present application can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • Each functional module in the data processing system 300 can be implemented by software, hardware or a combination of the two. It is understandable that the specific implementation of each functional unit included in the data processing system 300 can refer to the detailed description in other embodiments of the present application, and will not be repeated here.
  • the data processing system 300 of the embodiment of the present application does not limit the type, quantity and association relationship of each functional module.
  • the data processing system 300 may include more or fewer functional modules.
  • each functional unit in the embodiment may be integrated into one unit, or may exist physically separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or in the form of a software functional unit, or in the form of a combination of hardware and software.
  • the following introduces a scalable, highly parallel, multi-input multi-heap structure and a dual-heap structure proposed by the present disclosure for sorting large-scale data.
  • Some embodiments of the present disclosure provide an expandable highly parallel annular multi-input multi-heap structure, which is specifically described here by taking the maximum heap as an example, and the minimum heap is vice versa.
  • the multi-heap structure can obtain M minimum values from multiple data
  • the number of parallel heaps in the multi-heap structure is N
  • the expandable annular multi-input multi-heap structure can be composed of N heaps, N buffers, N data sources, N control logics, and a global maximum module.
  • the structures of the N heaps can all be maximum heaps, and the maximum heap is used to screen the minimum value.
  • Each heap can include K elements. After completing a series of inputs and sorting, the set of K elements included in the N heaps finally output is the M minimum values obtained, that is, the value of M is the product of K and N, where K, M, and N are positive integers.
  • the i-th heap can process one input data DI i every two cycles, and return one write-back data WB i after one cycle in which the input data DI i is valid.
  • both the input data DI i and the write-back data WB i can include tuples for sorting and enable signals.
  • the input data DI i includes a tuple DI_Data i and an enable signal DI_en i
  • the write-back data WB i includes a tuple WB_Data i and an enable signal WB_en i
  • the tuple can be expressed as (ID, Value), including a numerical value Value for comparison and a number ID or a corresponding key value for the corresponding numerical value.
  • the enable signal DI_en i of the input data DI i is true, indicating that the input data DI i is valid, and the write-back data WB i is output after one cycle of the input data DI i being valid, and the enable signal WB_en i of the write-back data WB i is valid.
  • the write-back data WB i is the input data DI i , and the stack top remains unchanged. Otherwise, the write-back data WB i is Ti , and the stack top is replaced by DI i .
  • FIFO i is used to buffer the write-back data WB i- 1 from the previous heap i-1 .
  • the read data WB′ i-1 can be output.
  • One of the inputs of the multiplexer MUX i Connected to the corresponding data source I i , another input The write-back data WB′ i-1 of FIFO i is connected.
  • the selection signal S i of the multiplexer MUX i is given by the control logic C i .
  • the selection output of the multiplexer MUX i is connected to the input data DI i of the heap i .
  • WB′ i-1 is compared with the global maximum value T g .
  • T g the output data WB′ i-1 of FIFO i is selected as the output of the multiplexer.
  • the buffer can be judged once every two cycles accordingly.
  • the multi-heap structure also includes N data sources, and the i-th data source I i can be implemented using a first-in first-out memory, etc., for buffering input data tuples of external signals and providing corresponding input data enables.
  • the global maximum module is used to receive the top data Ti of all heaps and generate the maximum value of the top data of all heaps, that is, the global maximum value T g , which may be delayed by several cycles compared to the input based on different implementation forms.
  • the enable of input data of all heaps is invalid, and all heaps are not working.
  • N data sources are enabled and can send data to N buffers every two cycles. For example, for the i-th buffer buffer i , since FIFO i in buffer buffer i is not filled to read data, control logic C i directly selects data source I i as the input of corresponding heap i . Repeat this for multiple cycles until FIFO i in buffer buffer i is filled to output data WB′ i-1 to multiplexer MUX i , and the corresponding control logic C i can make a judgment.
  • multiplexer MUX i selects the output data WB′ i-1 of FIFO i as the input data DI i of heap i .
  • the output data WB′ i-1 of FIFO i is invalid, if the data source I i is enabled, the data source I i is selected as the input data DI i of the heap i .
  • the control logic C i can read other data (such as the third cache signal) cached in the non-empty FIFO i as the input data DI i of the heap i until FIFO i is empty.
  • the set of K ⁇ N elements included in the N heaps (each heap includes K elements) output at last is the M minimum values obtained, and the sorting is completed.
  • the implementation of the multi-heap structure can improve system performance, improve signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • FIG4 shows a schematic diagram of an expandable highly parallel multi-input annular multi-heap structure 400 proposed in the present disclosure.
  • This embodiment uses the heap as a maximum heap for example, and the embodiment of the minimum heap can be reversed.
  • the multi-heap structure 400 includes N single sorting modules 500 as shown in the dotted box and a global maximum module. These N sorting modules can be connected in series to form a ring structure, and a single sorting module can include a buffer and a single heap structure.
  • the specific structure of the single sorting module 500 can refer to the embodiment shown in FIG5.
  • N single heap structures are connected through N buffers, and the N single heap structures and N buffers are arranged alternately, connected end to end to form a ring, and the input of a buffer can be the output of the previous heap connected to it, and the output of a buffer can be the input of the next heap connected to it.
  • the global maximum module is used to receive the top data Ti of all heaps and generate the maximum value of the top data of all heaps, that is, the global maximum value Tg . Tg will be delayed by several cycles compared to the input based on different implementation forms.
  • the scalable high-parallel multi-heap structure 400 shown in FIG4 can have N separate data source inputs, can complete N-way data input at the same time, and the structure of each of the N heaps in the multi-heap structure 400 can be a maximum heap, which is used to screen the minimum value, and each heap can include K elements. A lot of data is input into the multi-heap structure 400.
  • the set of K ⁇ N elements included in the N heaps finally output is the M minimum values to be obtained, that is, the TOP-M data among the many data inputted are found.
  • Implementing the multi-heap structure 400 can improve system performance, improve signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the external interface of the k-th sorting module 500 includes a data source I k , an input WB k-1 from the previous sorting module to the current sorting module, an input WB k from the current sorting module to the next sorting module, a top maximum value output T k of the current single heap module, a global maximum value input signal T g , etc., wherein the lowercase k below represents the k-th single sorting module in the structure of FIG4 (different from the uppercase K in the present disclosure which represents the K maximum or minimum data to be obtained in the TOP-K sorting).
  • the data source I k represents the external output to be processed. The data to be sorted.
  • the data source I k is further divided into a data signal I_data k and an enable signal I_en k .
  • the enable signal I_en k indicates whether the data signal I_data k is valid.
  • the input WB k-1 from the previous single sorting module of the ring structure to the current single sorting module is further divided into a data signal WB_data k-1 and an enable signal WB_en k-1 , and the enable signal WB_en k-1 indicates whether the data signal WB_data k-1 is valid.
  • the output WB k from the current single sorting module to the next single sorting module in the multi-heap structure can be used as the input of the next single sorting module.
  • WB k is further divided into a data signal WB_data k and an enable signal WB_en k , and the enable signal WB_en k indicates whether the data signal WB_data k is valid.
  • the maximum value output T k of the top of the single heap module indicates the top of the current heap structure in the current sorting module.
  • the input signal T g indicates the maximum value among the maximum values of the N heaps output from the tops of the N sorting modules, that is, the global maximum value.
  • a single sorting module 500 taking the kth module as an example, includes a kth heap module (heap k ) 520 and a corresponding buffer module (buffer k ) 510.
  • the buffer module 510 includes a control logic module ( Ck ) 540, a multiplexer module (MUX k ) 530, and a first-in first-out module (FIFO k ) 550.
  • the multiplexer 530 receives the data source Ik corresponding to the sorting module and the output WB'k -1 of the FIFO k 550.
  • the FIFO k 550 receives the write-back signal WBk -1 from the previous sorting module to the current sorting module, and outputs the buffered data WB'k -1 .
  • the selection signal Sk of the multiplexer 530 comes from the output of the control logic module 540.
  • the output DI k of the multiplexer 530 is used as the input of the k-th heap module (heap k ) 520.
  • the specific DI k signal is divided into a data signal DI_data k and an enable signal DI_en k .
  • the enable signal DI_en k indicates whether the data signal DI_data k is valid.
  • the output of the k-th heap module (heap k ) 520 is WB k , which includes the data signal WB_data k and the enable signal WB_en k .
  • the input of the control logic module 540 is WB′ k-1 , I k and T g , and the output is the selection signal S k of the multiplexer 530.
  • the workflow 600 of the control logic in FIG. 5 may be shown in FIG. 6 .
  • the control logic module 540 may start a judgment every two cycles. As shown in FIG. 6 , in box 601, it is judged whether FIFO k has data output. If there is data output, it enters box 602. If there is no data output, it enters box 603. The purpose of this judgment is that, because the T g output by the global maximum module will be delayed by several cycles relative to the input, after WB k-1 is input to FIFO k in the buffer, it will not be read until FIFO k is filled.
  • WB′ k-1 is the input of multiple cycles ago, which will be delayed relative to T g , which is conducive to the control logic to play a better screening performance and avoid WB k-1 from being passed through multiple piles without being screened out.
  • block 602 it is determined whether the enable WB_en′ k-1 corresponding to the data WB′ k-1 output by FIFO k is valid, that is, whether it is true. If it is valid (that is, true), it enters block 604, and if it is invalid (that is, false), it enters block 606. In block 604, it is determined whether WB_data′ k-1 is less than Tg . If it is, it enters block 605, otherwise it enters block 606.
  • the selection signal S k is output to make the multiplexer MUX k select WB′ k-1 as the output of the multiplexer MUX k .
  • the DI k signal is divided into a data signal DI_data k and an enable signal DI_en k .
  • the corresponding enable signal DI_en k is true, and DI_data k is the data value of WB_data′ k-1 .
  • the output selection signal S k enables the multiplexer MUX k to select the data source I k as the output of the multiplexer MUX k .
  • the DI k signal is divided into a data signal DI_data k and an enable signal DI_en k .
  • the data signal and the enable signal of the DI k signal are both outputted from the data source I k , and the data of WB′ k-1 is ignored.
  • I_en k is valid, that is, whether it is true. If it is valid, it enters block 606, and if it is invalid, it enters block 607.
  • other data cached in the non-empty FIFO k are read as DI k .
  • the purpose here is to extract the data that has not overflowed in FIFO k when there is no external input data, to ensure that all data in FIFO k enter the sorting, and to avoid the heap module being idle.
  • the judgment process in block 602 and/or block 604 can also be performed on the write-back data, for example, compared with T g , and then decide whether to use the write-back data as DI k .
  • the structure described by taking the heap module (heap k ) 520 in the k-th single sorting module 500 as an example may be a heap module 700 as shown in FIG7.
  • the heap module 700 may include heap data and heap control logic.
  • the heap data is generally a hierarchical structure with a heap top. If it is a maximum heap, the heap top is the maximum value of the heap. If it is a minimum heap, the heap top is the minimum value of the heap.
  • the heap module of this embodiment takes the maximum heap as an example to find the K minimum values in the input data.
  • the heap module 700 has an input signal DI k as an input of the heap module (heap k ) 520. Specifically, the input signal DI k is divided into a data signal DI_data k and an enable signal DI_en k .
  • the enable signal DI_en k indicates whether the data signal DI_data k is valid.
  • the output of the heap module 700 is WB k , including the data signal WB_data k and the enable signal WB_en k .
  • the enable signal WB_en k indicates whether the data signal WB_data k is valid.
  • the heap module 700 also outputs the heap top T k to the global maximum module.
  • the stack control logic flow 800 in the stack module 700 is shown in FIG8 .
  • the stack module 700 can start processing a data input every two cycles.
  • box 801 determine whether the enable signal DI_en k corresponding to the input signal DI k is valid, that is, whether it is true (true). If it is valid (that is, true), enter box 802, and if it is invalid (that is, false), enter box 805.
  • box 802 determine whether DI_data k is less than the current stack top value T k . If so, enter box 803, otherwise enter box 804.
  • the row is replaced, the value of DI_data k becomes the value of the new top data T k , the value assigned to WB_data k is the value of the top data T k just replaced, and the heap logic starts to perform the heapization operation of the heap.
  • the so-called heapization operation of the heap refers to the specific operation of the data in the heap that is performed to maintain the properties of the heap after the top of the heap changes.
  • WB_en k is set to true, the top data T k remains unchanged, the value assigned to WB_data k is the value of the input data DI_data k , and the heap logic starts to perform the heapization operation of the heap.
  • DI_en k is false, the input data DI_data k is invalid, WB_en k is set to false, the data WB_data k is invalid, and the heap continues to complete the heapization operation.
  • the heapization operation only needs to update the new top element of the heap before the next signal is input to the single heap structure, and there is no need to sort each element in the heap in order.
  • the stack module will send WB_en k and WB_data k to the buffer of the next sorting module, and the control logic of the next buffer will decide whether to keep or discard the WB_data k .
  • the Top-K sorting function as described in FIG. 7 and FIG. 8 does not necessarily need to be implemented by a data structure such as a heap.
  • a data structure such as a heap.
  • the Top-K module is not limited to being implemented by a heap structure. Any other structure or module that can implement a similar Top-K sorting function is within the scope of protection of the present disclosure.
  • the current heap top may optionally be the maximum value of multiple data in other candidate data structures, and in box 804, the maximum value of multiple data in other candidate data structures may be replaced.
  • a single stack processes one data every two cycles, such as process 800, and a corresponding single buffer has a control logic judgment process every two cycles, such as process 600. Therefore, for a multi-stack structure 400 including N sorting modules, the N sorting modules can perform sorting activities in parallel in one iteration cycle, and the N buffers and N stacks can process data in parallel.
  • one iteration cycle may include two clock cycles (not limiting, it may also be four clock cycles, which may be set according to actual conditions).
  • the buffer selects and outputs input data DI k to the stack.
  • the stack module processes the input data DI k and outputs WB k to the FIFO of the next sorting module.
  • the input enable signal of all heaps is invalid, and all heaps do not work.
  • data is input to all buffers. Since the FIFO in all buffers is empty at this time, the external input data is directly selected as the input of the heap.
  • the heap k processes it and writes back the data to the buffer output of the next heap heap k+1 .
  • buffer k starts to work according to the control logic flow 600 in Figure 6, screening the write-back data of the heap and selecting the input data to the heap heap k .
  • the external input data can be transmitted unidirectionally between adjacent heaps until it enters a certain heap or is thrown away.
  • the global maximum value Tg generated by the global maximum module can constrain the values in all heaps, ensure that there is a corresponding threshold upper limit between the heaps, so that the data stored in all heaps meet the sorting requirements.
  • the average data throughput is improved and has a nearly linear scalability gain effect.
  • the embodiments of the present disclosure reduce the number of comparisons required for sorting by utilizing the orderliness of the data in the heap and transferring data and global maximum constraints between multiple heaps, thereby consuming less hardware processing resources, and making better use of on-chip storage resources based on the heap structure, thereby improving the utilization efficiency of different on-chip resources.
  • the number of comparisons for sorting in this scheme is relatively small.
  • each heap For example, for a multi-heap structure for Top-K sorting with a parallelism of N and the need to obtain K top values, the size of each heap is The number of layers is That is, each heap will perform Comparisons are performed, and data is transferred between the heaps at the same time. Each cycle compares N times, so the total number of comparisons is
  • the embodiments shown in Figures 4 to 8 are an implementation method provided by the present application, which is only for the purpose of more clearly illustrating the technical solution of the present application and does not limit other embodiments of the present application.
  • the scalable highly parallel multi-heap structure for sorting large-scale data in some of the above embodiments of the present disclosure can increase its parallelism to N, achieving higher data throughput, and for the multi-heap structure for obtaining M top data, the size of each heap is reduced to M/N, which improves the performance of a single heap, can save storage resources, computing resources and processing resources, and reduce processing time, and obtain the top data faster.
  • the overall structure of this scalable ring multi-input multi-heap structure can include N single heaps, N buffers, corresponding FIFOs and a global maximum/minimum value module.
  • the N buffers include FIFOs, multiplexers MUX and corresponding control logic C.
  • Each heap receives the output of its own buffer module, and its own write-back data is connected to the buffer of the next heap, and the top of the heap is also input to the global maximum/minimum value module.
  • the buffer receives the write-back data from the previous heap and the external data source, receives the global maximum/minimum value, and outputs data to the corresponding heap. All the heaps are alternately connected with the buffer to form a ring structure.
  • the buffer isolates the data output of the adjacent previous heap, all heaps can work synchronously or asynchronously.
  • the input data is transmitted unidirectionally between the heaps through the write-back value of the heap and the buffer until it enters a certain heap or is thrown away by the global maximum/minimum value module.
  • the global maximum/minimum value module can constrain the transmission of data so that the data stored in each heap will not be wasted.
  • the multi-heap structure of some embodiments of the present disclosure can utilize the ordered nature of the data arrangement within the heap, and through the series connection between heaps and the constraints of global maximum/minimum values, reduce the number of comparisons required for sorting, save processing resources and storage resources, and improve throughput, so as to achieve the sorting of the top data of a larger amount of data and the concurrent operation of multiple multi-heap structures.
  • the dual-heap structure may include two heap structures, two buffers, and a data source.
  • Each heap structure can process one input data DI i every two cycles, and return one write-back data WB i after one cycle in which the input data is valid.
  • the input data DI i may include a tuple DI_Data i and an enable signal DI_en i
  • the write-back data WB i may include a tuple WB_Data i and an enable signal WB_en i
  • the tuple may be expressed as (ID, Value), including a numerical value Value for comparison and a number ID or a corresponding key value for the corresponding numerical value.
  • the enable signal DI_en i of the input data DI i is true, indicating that the input data DI i is valid, and the write-back data WB i is output after the input data DI i is valid for one cycle, and the enable signal WB_en i of the write-back data WB i is valid.
  • the write-back data WB i is DI i , and the stack top remains unchanged. Otherwise, the write-back data WB i is Ti , and the stack top is replaced by DI i .
  • the dual stack structure also includes two buffers.
  • FIFO i is used to buffer the write-back data WB i-1 from another stack. When FIFO i is filled to a certain extent, the read data WB′ i-1 may be output.
  • One of the inputs of the multiplexer MUX i Connected to the corresponding data source I, another input The write-back data WB′ i-1 of FIFO i is connected.
  • the selection signal S i of the multiplexer MUX i is given by the control logic Ci .
  • the selection output of the multiplexer MUX i is connected to the input data DI i of the heap i .
  • WB′ i-1 is compared with the top of the current heap Ti .
  • the output data WB′ i-1 of FIFO i is selected as the output of the multiplexer.
  • the output data WB′ i-1 of FIFO i is invalid, if the data source I i is valid, the data source I i is selected as the output of the multiplexer. If the data source I i is invalid, another data in the non-empty FIFO i can be selected as the output of the multiplexer.
  • the buffer can be judged once every two cycles accordingly.
  • the dual-heap structure may also include a data source I, which may be implemented using a first-in-first-out memory or the like, and is used to buffer input data tuples of external signals and provide corresponding input data enable.
  • the data source I may provide input data to the dual-heap structure in turn, and the enable signal is alternately valid for the two buffers. When the data source is empty, the input data enable signals of the two heaps are invalid, and the two heaps do not work.
  • the data source I provides input data to buffer 0 and the enable signal is valid, and the control logic C 0 selects the data source I as the input data DI 0 of the heap. After one cycle, heap 0 outputs write-back data WB 0 to buffer 1.
  • control logic C 1 Since FIFO 1 in buffer 1 is not filled to the point where data can be output, the control logic C 1 selects the input data with a valid enable signal provided by the data source I to buffer 1 as the input data DI 1 of the heap. After one cycle, heap 1 writes back data WB 1 to buffer 0 output. Since FIFO 0 in buffer 0 is not filled to output data, control logic C 0 selects valid data source I as the input data DI 0 of the heap. This is repeated until after multiple cycles, a FIFO in a buffer is filled to output data, such as buffer 0. The corresponding control logic C 0 makes a judgment.
  • the multiplexer selects the output WB′ 1 of FIFO 0 as the input data DI 0 of heap 0. If the output data WB′ 1 of FIFO 0 is greater than the top T 0 of heap 0 , it is determined whether the data source I is valid. If the data source I is valid, the data source is selected as the input data DI 0 of heap 0. If the data source I is invalid, other cache data in the non-empty FIFO 0 can be read as the input data DI 0 of heap 0 .
  • Heap 0 outputs write-back data WB 0 in one cycle after data input and sends WB 0 to buffer 1 , and the corresponding control logic C 1 can perform a judgment process similar to the above control logic C 0.
  • the dual-heap structure alternately inputs data and completes the sorting.
  • the control logic can read the data in the FIFO until the FIFO is empty.
  • the set of elements included in the two heaps finally output is the M minimum values obtained, and the sorting is completed.
  • Implementing the dual-heap structure can improve system performance, improve signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the dual-heap structure for dual-cycle single-input alternation in the embodiment may include two heap structures, two buffers, and a data source input.
  • the dual-heap structure 900 shown in reference figure 9 the two heaps heap 0 and heap 1 in the dual-heap structure are connected through buffers buffer 0 and buffer 1 , and also constitute a ring-shaped loop structure, but the whole has only a single input.
  • Each buffer module includes a multiplexer and control logic.
  • the data source I is connected to buffer 0 (buffer 0 ) and buffer 1 (buffer 1 ) respectively, for inputting external data into the heap structure.
  • the data source I can make the input signals to buffer 0 and buffer 1 valid alternately. For example, in the first cycle, the input signal to buffer 0 is enabled and the input signal to buffer 1 is invalid. In the second cycle, the input signal to buffer 1 is enabled and the input signal to buffer 0 is invalid. In the third cycle, the input signal to buffer 0 is enabled and the input signal to buffer 1 is invalid, and the cycle repeats.
  • Buffer 0 can receive the write-back data WB 1 of heap 1 , the top data T 0 of heap 0 and the data source I, and make a judgment according to the control logic C 0 to select and output a data signal as the input data DI 0 of heap 0. Heap 0 receives the input data DI 0 , and after one cycle, heap 0 sends the data to buffer 0. Buffer 1 outputs a write-back signal WB 0 , and outputs the top data T 0 to buffer 0.
  • buffer 1 can receive the write-back data WB 0 of heap 0 , the top data T 1 of heap 1 , and the data source I, and make a judgment according to the control logic C 1 , and select to output a data signal as the input data DI 1 of heap 1.
  • Heap 1 receives the input data DI 1 , and after one cycle, heap 1 outputs a write-back signal WB 1 to buffer 0 , and outputs the top data T 1 to buffer 1.
  • Implementing the dual-heap structure 900 can improve system performance, improve signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume, and processing time.
  • FIG10 The structure of a single sorting module 1000 in the dual-heap structure 900 is shown in FIG10 , and a sorting module composed of heap 0 and buffer 0, i.e., heap 0 1020 and its buffer 0 1010, is used as an example.
  • the write-back data WB 0 of heap 0 1020 is connected to buffer 1 and control logic C 1 , the input data DI 0 of heap 0 1020 is connected to the output of multiplexer (MUX 0 ) 1030 , the write-back signal WB 1 is used as the input of first-in first-out queue (FIFO 0 ) 1050 inside buffer 1010 , and the output WB′ 1 of FIFO 0 1050 is used as an input of multiplexer MUX 0 1030 .
  • Buffer 0 1010 is connected to data source input data I
  • data source I is connected to internal multiplexer 1030 as an input of multiplexer 1030
  • enable signal I_en is connected to control logic C 0 1040 .
  • the control logic (C 0 ) 1040 receives WB′ 1 , I_en, and the top T 0 of heap 0 , and makes a judgment, and selects to output a data signal as the input data DI 0 of heap 0. Heap 0 receives the input data DI 0 , and after one cycle, heap 0 1020 outputs the write-back data WB 0 to buffer 1 , and outputs the top data T 0 to the control logic (C 0 ) 1040.
  • the connection relationship between heap 1 and its buffer 1 is similar to the connection relationship between heap 0 and its buffer 0 shown in the dual heap structure 900.
  • the judgment process 1100 of the control logic C0 of the buffer buffer0 of the heap heap0 may be as shown in FIG11.
  • the control logic C0 may start a judgment every two cycles. As shown in FIG11, in box 1101, it is judged whether FIFO0 has data output. If there is data output, it enters box 1102, and if there is no data output, it enters box 1103. The purpose of this judgment is that, because the output top of the heap T0 will be delayed by several cycles relative to the input, after WB1 is input to the FIFO0 in the buffer, it will not be read until FIFO0 is filled.
  • WB′1 is the input of multiple cycles ago, which will be delayed relative to T0 , which is conducive to the control logic to play a better screening performance and avoid WB1 from being passed in the double heap without being screened out.
  • the enable WB_en′ 1 corresponding to the data WB′ 1 output by FIFO 0 is valid, that is, whether it is true. If it is valid (that is, true), it enters box 1104, and if it is invalid (that is, false), it enters box 1106.
  • WB_data′ 1 is less than T 0. If it is, it enters box 1105, otherwise it enters box 1106.
  • the output selection signal S 0 enables the multiplexer MUX 0 to select WB′ 1 as the output of the multiplexer MUX 0.
  • the DI 0 signal is divided into a data signal DI_data 0 and an enable signal DI_en 0.
  • the corresponding enable signal DI_en 0 is true, and DI_data 0 is the data value of WB_data′ 1.
  • the output selection signal S 0 enables the multiplexer MUX 0 to select the data source I as the output of the multiplexer MUX 0.
  • the DI 0 signal is divided into a data signal DI_data 0 and an enable signal DI_en 0.
  • the data signal and the enable signal of the DI 0 signal are both outputted from the data source I, and the data of WB′ 1 is ignored.
  • I_en is valid, that is, whether it is true. If it is valid, it enters box 1106, and if it is invalid, it enters box 1107.
  • box 1107 the data cached in the non-empty FIFO 0 is read as DI 0. The purpose here is to extract the data that has not overflowed in FIFO 0 when there is no external input data, to ensure that all data in FIFO 0 enters sorting, and to avoid the heap module being idle.
  • the determination process in block 1102 and/or block 1104 may be performed on the write-back data, such as comparing with T 0 , to determine whether to use the write-back data as DI 0 .
  • the structure described by taking the 0th heap module (heap 0 ) 1020 as an example may be a heap module 700 as shown in FIG7 .
  • the heap module may include heap data and heap control logic.
  • the heap data is generally a hierarchical structure, with a heap top. If it is a maximum heap, the heap top is the maximum value of the heap, and if it is a minimum heap, the heap top is the minimum value of the heap.
  • the heap module of this embodiment takes the maximum heap as an example to find the K minimum values in the input data.
  • the heap module heap 0 has an input signal DI 0 as the input of the heap module heap 0.
  • the specific input signal DI 0 is further divided into a data signal DI_data 0 and an enable signal DI_en 0.
  • the enable signal DI_en 0 indicates whether the data signal DI_data 0 is valid.
  • the output of the heap module heap 0 is WB 0 , including a data signal WB_data 0 and an enable signal WB_en 0.
  • the enable signal WB_en 0 indicates whether the data signal WB_data 0 is valid.
  • the heap module heap 0 also outputs a heap top T 0 to the control logic C 0 .
  • the heap control logic flow 1200 in the heap module heap 0 is shown in FIG12.
  • the heap module heap 0 can start processing a data input every two cycles.
  • box 1201 it is determined whether the enable signal DI_en 0 corresponding to the input signal DI 0 is valid, that is, whether it is true (true). If it is valid (that is, true), it enters box 1202, and if it is invalid (that is, false), it enters box 1205.
  • DI_data 0 is less than the current heap top value T 0. If it is, it enters box 1203, otherwise it enters box 1204.
  • WB_en 0 is set to true, DI_data 0 is replaced with the current heap top data T 0 , and the value of DI_data 0 becomes the value of the new heap top data T 0.
  • the value of the data assigned to WB_data 0 is the value of the heap top data T 0 that has just been replaced, and the heap logic starts to perform the heapization operation of the heap.
  • the so-called heapification operation refers to the specific operation of the data in the heap that is performed in order to maintain the properties of the heap after the top of the heap changes.
  • WB_en 0 is set to true, the top data T 0 remains unchanged, the value of WB_data 0 is assigned to the value of the input data DI_data 0 , and the heap logic starts to perform the heapification operation.
  • DI_en 0 is false, the input data DI_data 0 is invalid, WB_en 0 is set to false, WB_data 0 is invalid, and the heap continues to complete the heapification operation.
  • the heapification operation only needs to update the new top element of the heap before the next signal is input to the heap structure, and there is no need to update each element in the heap. It is understandable that the stack module will send WB_en 0 and WB_data 0 to the buffer of the next sorting module, and the control logic of the next buffer will decide whether to keep or discard the WB_data 0 .
  • the functions described in FIG. 12 do not necessarily need to be implemented by a data structure such as a heap, and can be implemented as long as similar functions are implemented.
  • the current heap top may optionally be the maximum value of multiple data in other candidate data structures, and in box 1204, the maximum value of multiple data in other candidate data structures may be replaced.
  • a single stack processes one data every two cycles, such as process 1200, and the corresponding single buffer undergoes a control logic judgment process every two cycles, such as process 1100. Therefore, for a dual-stack structure 900 including two sorting modules, the two sorting modules can perform sorting activities in parallel in one iteration cycle, and the two buffers and two stacks can process data in parallel.
  • one iteration cycle may include two clock cycles (non-restrictive, it may also be four clock cycles, which can be set according to actual conditions).
  • the buffer selects and outputs input data DI to the stack.
  • the stack module processes the input data DI and writes back data WB to the FIFO output of the next sorting module.
  • the input enable signals of the two stacks are invalid and both stacks do not work.
  • the two stacks have input data alternately.
  • data source I inputs data to buffer 0 , and the enable signal of the input signal is valid. Since FIFO 0 is empty at this time, I is directly used as DI 0 of heap 0 ; in the second cycle, heap 0 outputs write-back data WB 0 to buffer 1 , data source I inputs data to buffer 1 , and the enable signal of the input signal is valid.
  • the selection signal S 0 of multiplexer MUX 0 is controlled to select WB′ 1 and input it to heap 0. Otherwise, it is judged whether the enable I_en of I is valid. If it is valid, I is selected to input it to heap 0. Otherwise, other write-back data WB′ 1 cached in non-empty FIFO 0 is read and WB′ 1 is input to heap 0 , or WB′ 1 is input to multiplexer MUX 0. After that, the two buffers repeat the above operation according to the corresponding FIFO output and data source input I to input data into the heap. When all external data of the dual heap structure are input, and all FIFOs are cleared, the sorting is completed.
  • the size of the write-back data of one heap must be larger than the current heap top. If the write-back value is larger than the heap top of another heap, it will not enter the other heap.
  • the data transfer between the two heaps is completed, and a data input is shared. Its interface is the same as that of a single heap structure.
  • the dual-heap structure 900 has a simpler hardware structure, similar throughput, consumes fewer resources, and can also be used as a single-input heap.
  • FIG. 9 to 12 are an implementation method provided by the present application, which is only for the purpose of more clearly illustrating the technical solution of the present application and does not limit other embodiments of the present application.
  • the dual-heap structure with double-cycle single-input alternation is implemented, and the two heaps work alternately and write data back to each other.
  • the two heap structures can alternately obtain data input from one data input and the write-back data of the other heap, maintain the orderly arrangement of the data of the heap, and improve the throughput to a level close to the upper limit of the traditional heap structure with lower processing resource overhead, and have the same functional abstraction and interface as the traditional heap hardware structure, and can be easily replaced in the existing heap structure hardware design.
  • the structure of the electronic device 1300 provided in the embodiment of the present application is introduced below.
  • the electronic device 1300 implementing one or more embodiments of the present disclosure may be a smart phone (mobile phone), a tablet computer (Pad), a personal computer (PC), a desktop computer, a portable computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, a netbook, a game console, an electronic conference whiteboard, a smart screen (smart TV), a drone, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AR) device, or a computer.
  • PDA personal digital assistant
  • AR augmented reality
  • VR virtual reality
  • AR artificial intelligence
  • the electronic device 1300 may be an intelligent, intelligent, and intelligent (AI) device, a wearable device, a car machine (on-board device), an Internet of Things (IoT) device, an industrial control device, a self-driving device, a remote medical device, a smart grid device, a transportation safety device, a smart city device, a smart home device, or other types of electronic devices.
  • AI intelligent, intelligent, and intelligent
  • IoT Internet of Things
  • industrial control device a self-driving device
  • remote medical device a smart grid device
  • transportation safety device a smart city device
  • smart home device or other types of electronic devices.
  • the electronic device 1300 may be equipped with various types of operating systems, which are not limited in this embodiment.
  • FIG. 13 exemplarily shows the structure of an electronic device 1300 provided in an embodiment of the present application.
  • the electronic device 1300 may include: one or more terminal device processors 1310 , a communication interface 1320 , a memory 1330 , etc. These components may be connected via a bus 1340 or other means, with connection via the bus 1340 being taken as an example. Among them:
  • the processor 1310 is the control center of the electronic device 1300, and is connected to various parts of the electronic device 1300 through various interfaces and lines. Used to read and execute computer-readable instructions. Specifically, the processor 1310 can be used to call the program or data stored in the memory 1330, and execute the instructions contained in the program to realize various functions of the electronic device 1300. In some embodiments, the processor 1310 may include one or more processing units. The processor 1310 can also integrate an application processor and a modem processor. Among them, the application processor is mainly used to process operating systems, user interfaces, and application programs; the modem processor is mainly used to process wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 1310. In some embodiments of the present application, the processor can be used to execute the methods and functions provided in any of the above embodiments of the present application.
  • the memory 1330 is coupled to the processor 1310 and is used to store various software programs and/or multiple groups of instructions.
  • the memory 1330 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices or other non-volatile solid-state storage devices.
  • the memory 1330 may store an operating system, such as an embedded operating system.
  • the memory 1330 may also store a network communication program, which may be used to communicate with one or more additional devices, one or more terminal devices, and one or more network devices.
  • the memory 1330 may also store a terminal device interface program, which may display the content of the application program vividly through a graphical operation interface, and receive the control operation of the terminal device on the application program through input controls such as menus, dialog boxes, and buttons.
  • the memory 1330 may be used to store an implementation program of the method provided by one or more embodiments of the present application on the electronic device 1300 side.
  • the electronic device 1300 may also include an input/output module.
  • the input/output module may be used to implement interaction between the electronic device 1300 and other terminal devices/external environments, and may mainly include an audio input/output module, a key input module, and a display, etc.
  • the input/output module may also include: a camera, a touch screen, and a sensor, etc. Among them, the input/output modules all communicate with the processor 1310 through an interface.
  • the electronic device 1300 shown in FIG. 13 is only one implementation of the embodiment of the present application. In actual applications, the electronic device 1300 may also include more or fewer components, may combine two or more components, or combine certain components, or split certain components, or arrange components differently.
  • the components shown in the figure may be implemented in hardware, software, or a combination of software and hardware, which is not limited here.
  • the signal processing device may include: an input module, configured to input multiple signals to a multi-sorting module, the multi-sorting module includes N sorting modules connected in series in a ring, each of the N sorting modules includes a Top-K module with K elements, the multi-sorting module includes a first sorting module and a second sorting module, the first sorting module includes a first Top-K module, and the signal discarded by the first Top-K module or the top element of the replaced first Top-K module output by the first sorting module is used as the input signal of the second sorting module.
  • a processing module is configured to update the elements in multiple Top-K modules in the multi-sorting module based on multiple signals.
  • an output module is configured to obtain M data with the highest order in multiple signals, where the value of M is the product of N and K, and N, K, and M are positive integers.
  • the signal processing device of this embodiment can improve system performance, increase signal processing efficiency, save storage resources and processing resources, and reduce data storage volume, data transmission volume, data processing volume and processing time.
  • the multi-sorting module is a multi-heap structure
  • the Top-K module is a heap
  • the multi-heap structure includes multiple heaps
  • each of the multiple heaps includes K elements
  • the multi-heap structure outputs M data
  • the M data is a collection of all elements in the multiple heaps of the multi-heap structure.
  • the working parallelism of the multi-heap structure can be increased to N, achieving higher data throughput, improving signal processing efficiency, and the size of each heap in the multi-heap structure is reduced to M/N, improving the performance of a single heap, saving storage resources, computing resources and processing resources, and reducing data storage, data transmission, data processing and processing time.
  • the M data are the first M data with the smallest sorted data in multiple signals, and the top element of the maximum heap is the element with the largest data in the maximum heap; if the heap is a minimum heap, the M data are the first M data with the largest sorted data in multiple signals, and the top element of the minimum heap is the element with the smallest data in the minimum heap.
  • the maximum heap helps to screen the minimum value, and the minimum heap helps to screen the maximum value.
  • the first sorting module includes a first buffer and a first Top-K module
  • the second sorting module includes a second buffer and a second Top-K module
  • the output of the first buffer of the first sorting module is used as the input of the first Top-K module of the first sorting module
  • the output of the first Top-K module of the first sorting module is used as the input of the second buffer of the second sorting module
  • the output of the second buffer of the second sorting module is used as the input of the second Top-K module of the second sorting module.
  • the buffers and Top-K modules between the sorting modules are alternately connected, and the structure of multiple sorting modules connected in series in a ring can improve the processing efficiency.
  • the specific structure of the multiple sorting modules can be combined with the example multi-pile structure 400 shown in reference Figure 4 or the double-pile structure 900 shown in Figure 9, and the specific structure of the single sorting module can be combined with the example sorting module 500 shown in reference Figure 5 or the sorting module 1000 shown in Figure 10, which will not be repeated here.
  • the multiple signals include a first external signal and a second external signal
  • the first external signal is an input to the first sorting module
  • the second external signal is an input to the second sorting module
  • the first sorting module is used to receive the first external signal
  • the first sorting module is also used to obtain a first write-back signal based on the first external signal
  • the first sorting module is also used to send the first write-back signal to the second sorting module.
  • the second sorting module is used to receive the second external signal, the second sorting module is also used to receive the first write-back signal, the second sorting module is also used to obtain a second write-back signal based on the second external signal and/or the first write-back signal, and the second sorting module is also used to send the second write-back signal to the third sorting module.
  • the first sorting module and the second sorting module are connected in series to improve processing efficiency, and data not needed by the first sorting module can be continued to be processed by the second sorting module to avoid repeated input and processing.
  • the first buffer includes a first first-in-first-out queue, a first control logic module, and a first multiplexer, the first multiplexer is used to receive a first external signal, the first first-in-first-out queue is used to receive and cache multiple write-back signals multiple times, and the first first-in-first-out queue is also used to output the first cache signal after being filled with multiple write-back signals, and the second buffer includes a second first-in-first-out queue, a second control logic module, and a second multiplexer, the second multiplexer is used to receive a second external signal, the second first-in-first-out queue is used to receive and cache multiple write-back signals output by the first Top-K module of the first sorting module multiple times, the multiple write-back signals include the first write-back signal, and the second first-in-first-out queue is also used to output the second cache signal after being filled with multiple write-back signals.
  • the control logic and the multiplexer are used to select the input signal entering the heap based on the cache signal output by the first-in-first-out queue, the input external signal, and the global heap top value.
  • the first-in-first-out queue is used to cache the write-back data output by the previous sorting module.
  • the purpose of setting the first-in-first-out queue to cache write-back data is that the top value of the stack output by the global maximum value module will be delayed by several cycles relative to the input signal. Therefore, after the write-back signal is input to the first-in-first-out queue in the buffer, it will not be read until the first-in-first-out queue is full. At this time, the cached signal is the input from multiple cycles ago and will be delayed relative to the global top value of the stack, which is beneficial for the control logic to exert better screening performance and avoid the write-back signal being transmitted in multiple stacks without being screened out.
  • the second control logic module is further used to determine the second input signal based on the second external signal and/or the second cache signal
  • the second multiplexer is further used to output the second input signal to the second Top-K module
  • the second Top-K module is used to receive the second input signal from the second multiplexer
  • the second Top-K module is further used to obtain a second write-back signal based on the second input signal.
  • the second Top-K module is further used to send the second write-back signal to the third buffer of the third sorting module.
  • the Top-K module is alternately connected to the buffer, which can improve the signal processing efficiency.
  • the second control logic module is used to execute the following judgment logic: determine whether the second first-in-first-out queue outputs the second cache signal. If the second first-in-first-out queue outputs the second cache signal, then determine whether the second cache signal is valid. If the second cache signal is valid, compare the data of the second cache signal with the global top value. If the data of the second cache signal does not exceed the global top value, the second control logic module determines the second cache signal as the second input signal, and if the data of the second cache signal exceeds or equals the global top value, the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the second control logic module determines the second external signal as the second input signal, and the second cache signal is discarded.
  • the global maximum value maximum value or minimum value
  • the number of comparisons required for sorting can be reduced, saving the consumption of processing resources.
  • on-chip storage resources such as cache memory can be better utilized, and the utilization efficiency of different on-chip resources is improved.
  • the top maximum value output T k of the single heap module represents the top of the current heap structure in this sorting module.
  • Signal Tg represents the maximum value obtained from the N top-of-heap inputs, that is, the global maximum value (also called the global top-of-heap maximum value).
  • the second control logic module is also used to execute the following judgment logic: if the second first-in-first-out queue does not output the second cache signal, then determine whether the second external signal is valid. If the second external signal is valid, the second control logic module determines the second external signal as the second input signal. And if the second external signal is invalid, the second control logic module reads the third cache signal cached in the non-empty second first-in-first-out queue as the second input signal. That is, the cache signal overflowing in the first-in-first-out queue is processed before the external signal. When there is no overflowing cache signal in the first-in-first-out queue, the valid external signal is used as the input signal of the heap.
  • the write-back signal of the cache that is not overflowed in the non-empty first-in-first-out queue can be read as the input signal of the heap.
  • the judgment logic executed by the second control logic module can be understood in conjunction with the working process 600 of the control logic shown in reference Figure 6 or the embodiment of the working process 1100 of the control logic shown in Figure 11, which will not be repeated here.
  • the first write-back signal includes data of the first write-back signal and a first write-back enable signal, the first write-back enable signal indicating whether the first write-back signal is valid.
  • the second external signal includes data of the second external signal and a second external enable signal, the second external enable signal indicating whether the second external signal is valid.
  • the second cache signal includes data of the second cache signal and a second cache enable signal, the second cache enable signal indicating whether the second cache signal is valid.
  • the Top-K module is a maximum heap
  • the global top value is the maximum value among the data of the top elements of multiple maximum heaps
  • the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is less than the maximum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is greater than or equal to the maximum value.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the Top-K module is a minimum heap
  • the global top value is the maximum value of multiple minimum heaps.
  • the minimum value among the data of the top element of the heap, the data of the second cache signal does not exceed the global top value, including: the data of the second cache signal is greater than the minimum value.
  • the data of the second cache signal exceeds or is equal to the global top value, including: the data of the second cache signal is less than or equal to the minimum value.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second Top-K module is used to execute the following judgment logic: the second Top-K module obtains the second write-back signal based on the second input signal, including: judging whether the second input signal is valid, and if the second input signal is valid, comparing the data of the second input signal with the data of the current top element of the second Top-K module. If the data of the second input signal does not exceed the data of the current top element of the second Top-K module, the data of the second input signal replaces the data of the current top element of the second Top-K module to become a new element in the second Top-K module, and the data of the current top element of the replaced second Top-K module is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled.
  • the data not needed by the current Top-K module is passed to the next sorting module for processing or discarded in time, which can reduce the number of comparisons required during sorting and save processing resources and storage resources.
  • the second Top-K module is further used to execute the following judgment logic: if the second input signal is invalid, the data of the second input signal is used as the data of the second write-back signal, and the second write-back signal is enabled to be invalid.
  • the data determined to be useless can be sent to the FIFO of the next sorting module, and the control logic of the next sorting module decides to discard the data.
  • the second Top-K module is also used to update the new top element of the second Top-K module.
  • the second Top-K module can be a heap structure, and the heap structure can perform a heapization operation to update the new top element of the heap structure.
  • the heapization operation refers to sorting and updating the elements in the heap.
  • the second Top-K module is also used to send the top element of the second Top-K module to the global maximum value module.
  • the global maximum value module is used to obtain the top elements of multiple Top-K modules.
  • the global maximum value module is also used to select the maximum value among the data of the top elements of multiple Top-K modules.
  • the global maximum value module is also used to send the maximum value to the control logic modules in multiple buffers.
  • the Top-K module needs to update the new top element before the next input signal is input into the heap to ensure the accuracy of the next processing.
  • the structure of the second Top-K module and the judgment logic executed can be understood in conjunction with the heap module 700 shown in reference Figures 7-8 and the workflow 800 of the heap control logic or the embodiment of the workflow 1200 of the control logic shown in Figure 12, which will not be repeated here.
  • the second Top-K module is a maximum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is less than the data of the current top element of the maximum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than or equal to the data of the current top element of the maximum heap.
  • the structure of the maximum heap can help find the minimum value of a predetermined number of multiple input data.
  • the second Top-K module is a minimum heap
  • the data of the second input signal does not exceed the data of the current top element of the second Top-K module, including: the data of the second input signal is greater than the data of the current top element of the minimum heap.
  • the data of the second input signal exceeds or is equal to the data of the current top element of the second Top-K module, including: the data of the second input signal is less than or equal to the data of the current top element of the minimum heap.
  • the structure of the minimum heap can help find the maximum value of a predetermined number of multiple input data.
  • the second buffer determines a second input signal based on a second external signal and/or a second cache signal, and within a second time period, the second Top-K module obtains a second write-back signal based on the second input signal.
  • a sorting module can completely complete a processing job, and an iteration cycle can be divided into two time periods, such as a first time period and a second time period. In some embodiments, the first time period is equal to the second time period.
  • the processing cycle in which the buffer determines and selects the data entering the heap is executed alternately with the processing cycle in which the heap processes the input data and outputs the write-back data.
  • Each sorting module can process data in parallel, which can improve processing efficiency, reduce waiting time and processing time, and make full use of processing resources.
  • the signal processing device described in the above embodiment is only to more clearly illustrate an implementation method of the technical solution of the present application, and does not constitute a limitation on other embodiments of the present application.
  • the types, quantities and associations of the various functional modules of the signal processing device are not limited.
  • the signal processing device may include more or fewer functional modules, etc.
  • the various functional modules in the signal processing device can be implemented by software, hardware, or a combination of both. It can be understood that the specific implementation of the various functional units included in the signal processing device can refer to the detailed description in other embodiments of the present application, and no further details are given here.
  • each functional unit in the embodiment may be integrated into one unit, or may exist physically separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or in the form of a software functional unit, or in the form of a combination of hardware and software.
  • the embodiment of the present application further provides a chip, which may include an input interface, an output interface and a processing circuit.
  • the input interface and the output interface may complete the interaction of signaling or data
  • the processing circuit may complete the generation and processing of signaling or data information.
  • the embodiments of the present application also provide a chip system, including a processor, for supporting a computing device to implement the functions involved in any of the above embodiments.
  • the chip system may also include a memory for storing necessary program instructions and data, and when the processor runs the program instructions, the device on which the chip system is installed implements the method involved in any of the above embodiments.
  • the chip system may be composed of one or more chips, and may also include chips and other discrete devices.
  • An embodiment of the present application further provides a processor for coupling with a memory, wherein the memory stores instructions.
  • the processor executes the instructions, the processor executes the methods and functions involved in any of the above embodiments.
  • Computer-readable media can be any tangible medium containing or storing programs for or related to instruction execution systems, devices or equipment.
  • Computer-readable media can be computer-readable signal media or computer-readable storage media.
  • Computer-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or devices, or any suitable combination thereof.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrations.
  • Computer-readable storage media include electrical connections with one or more wires, magnetic media (e.g., disks, floppy disks, hard disks, tapes, magnetic storage devices), optical media (e.g., optical storage devices, DVDs), semiconductor media (e.g., solid-state hard drives), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), or any suitable combination thereof, etc.
  • magnetic media e.g., disks, floppy disks, hard disks, tapes, magnetic storage devices
  • optical media e.g., optical storage devices, DVDs
  • semiconductor media e.g., solid-state hard drives
  • RAM random access memory
  • ROM read-only memory
  • EPROM or flash memory erasable programmable read-only memory
  • the embodiment of the present application can be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it can be implemented in whole or in part in the form of a computer program product.
  • the embodiment of the present application also provides at least one computer program product tangibly stored on a non-temporary computer-readable storage medium.
  • the computer program product includes one or more computer executable instructions, such as instructions included in a program module, which are executed in a device on a real or virtual processor of the target to perform the process, method and function involved in any of the above embodiments.
  • a process or function according to an embodiment of the present application is generated in whole or in part.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instruction can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center.
  • wired e.g., coaxial cable, optical fiber, digital subscriber line
  • wireless e.g., infrared, wireless, microwave, etc.
  • the present application also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer performs the process, method and function in the above-mentioned embodiment.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types.
  • the functions of program modules can be combined or divided between program modules as needed.
  • Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.
  • the computer program code for realizing the method of the present disclosure can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by a computer or other programmable data processing device, causes the function/operation specified in the flow chart and/or block diagram to be implemented.
  • the program code can be executed completely on a computer, partly on a computer, as an independent software package, partly on a computer and partly on a remote computer or completely on a remote computer or server.
  • the computer program code or related data can be carried by any appropriate carrier so that equipment, devices or processors can perform various processing and operations described above.
  • the example of carrier includes signal, computer readable medium, etc.
  • the example of signal can include propagation signals of electricity, light, radio, sound or other forms, such as carrier waves, infrared signals, etc.
  • various embodiments of the present application may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be performed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representations, it should be understood that the boxes, devices, systems, techniques, or methods described herein may be implemented as, for example, non-limiting examples, hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof.
  • the term "when" may be interpreted to mean “if" or “after" or “in response to determining" or “in response to detecting", depending on the context.
  • the phrases “upon determining" or “if (the stated condition or event) is detected” may be interpreted to mean “if determining" or “in response to determining" or “upon detecting (the stated condition or event)” or “in response to detecting (the stated condition or event)", depending on the context.

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Abstract

本公开的实施例提供了一种信号处理方法、装置、设备、介质及芯片。该方法包括：向多排序模块输入多个信号，多排序模块包括环形串联的N个排序模块，每个排序模块包括具有K个元素的Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块包括第一Top-K模块，第一排序模块输出的被第一Top-K模块舍弃的信号或被替换出的第一Top-K模块的顶端元素作为第二排序模块的输入信号。基于多个信号，更新多排序模块中多个Top-K模块中的元素，以及获得多个信号中数据排序靠前的M个数据，M的值为N与K的乘积值。实施本公开的实施例，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，以及减少数据存储量、数据传输量、数据处理量和处理时间。

Description

信号处理方法、装置、设备、介质及芯片
本申请要求于2022年10月28日提交中国国家知识产权局，申请号为202211338060.5，发明名称为“信号处理方法、装置、设备、介质及芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及计算机领域，更具体地，涉及一种信号处理方法、装置、设备、介质及芯片。
背景技术
Top-K算法通常用于在多个数据的无序序列中找出前K个最大的元素或者最小的元素，可以用堆结构来实现。堆是基于完全二叉树的数据结构所构建的一组数据，常见的堆包括最大堆和最小堆。最大堆的性质包括其节点满足子节点的键值或者索引总是大于它的父节点，其堆顶的根节点是堆中所有元素中的最大值；最小堆的性质包括其节点满足子节点的键值或者索引总是小于它的父节点，其堆顶的根节点是堆中所有元素中的最小值。堆广泛应用于优先队列，以及在多个数据的无序序列中找出前K个最大的元素或者最小的元素，即Top-K算法。Top-K算法常应用于相似性检索、推荐系统以及数据库等场景中。
发明内容
本申请的实施例提供了一种信号处理方法以及相关电子设备，用于优化实现在无序的大规模数据中快速找出前面一些最大的元素或者最小的元素。
在本申请的第一方面，提供了一种信号处理方法，该方法包括：向多排序模块输入多个信号，多排序模块包括环形串联的N个排序模块，N个排序模块中的每个排序模块包括具有K个元素的Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块包括第一Top-K模块，第一排序模块输出的被第一Top-K模块舍弃的信号或被替换出的第一Top-K模块的顶端元素作为第二排序模块的输入信号。基于多个信号，更新多排序模块中多个Top-K模块中的元素。以及获得多个信号中数据排序靠前的M个数据，其中M的值为N与K的乘积值，N、K、M为正整数。
实施本方面的方法，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
结合第一方面，在一些实施例中，第一排序模块中包括第一缓冲器和第一Top-K模块，第二排序模块中包括第二缓冲器和第二Top-K模块，第一排序模块的第一缓冲器的输出作为第一排序模块的第一Top-K模块的输入，第一排序模块的第一Top-K模块的输出作为第二排序模块的第二缓冲器的输入，第二排序模块的第二缓冲器的输出作为第二排序模块的第二Top-K模块的输入。各个排序模块之间的缓冲器与Top-K模块交替连接以及多个排序模块环形串联的结构可以提高处理效率。
结合第一方面，在一些实施例中，多个信号包括第一外部信号和第二外部信号，第一外部信号为第一排序模块的输入，第二外部信号为第二排序模块的输入，并且该方法还包括：第一排序模块接收第一外部信号，第一排序模块基于第一外部信号获得第一写回信号，第一排序模块向第二排序模块发送第一写回信号。第二排序模块接收第二外部信号，第二排序模块接收第一写回信号，第二排序模块基于第二外部信号和/或第一写回信号获得第二写回信号，第二排序模块向第三排序模块发送第二写回信号。第一排序模块与第二排序模块串联可以提高处理效率，第一排序模块不需要的数据可以由第二排序模块继续处理，避免重复输入和处理。
结合第一方面，在一些实施例中，第一缓冲器中包括第一先入先出队列(first input first output，FIFO)、第一控制逻辑模块和第一多选器，第一多选器用于接收第一外部信号，第一先入先出队列用于多次接收并缓存多个写回信号，第一先入先出队列还用于在被多个写回信号填满后输出第一缓存信号，以及第二缓冲器中包括第二先入先出队列、第二控制逻辑模块和第二多选器，第二多选器用于接收第二外部信号，第二先入先出队列用于多次接收并缓存第一排序模块的第一Top-K模块输出的多个写回信号，多个写回信号包括第一写回信号，第二先入先出队列还用于在被多个写回信号填满后输出第二缓存信号。控制逻辑和多选器用于基于先入先出队列输出的缓存信号、输入的外部信号和全局堆顶最值来选择进入堆的输入信号。先入先出队列用于缓存上个排序模块输出的写回数据。设置该先入先出队列缓存写回数据的目的是由于全局 最值模块输出的堆顶值相对输入信号会存在几个周期的延迟，于是写回信号输入到缓冲器中的先入先出队列后，直到先入先出队列填充满才被读取，这时的缓存信号为多个周期前的输入，相对全局堆顶最值会延后，有利于控制逻辑能够发挥出较好筛选性能，避免写回信号在多个堆中传递而不会被筛选掉。
结合第一方面，在一些实施例中，第二排序模块基于第二外部信号和/或第一写回信号获得第二写回信号包括：第二控制逻辑模块基于第二外部信号和/或第二缓存信号确定第二输入信号，第二多选器向第二Top-K模块输出第二输入信号，第二Top-K模块接收来自于第二多选器的第二输入信号，第二Top-K模块基于第二输入信号获得第二写回信号。以及第二排序模块向第三排序模块发送第二写回信号，包括：第二Top-K模块向第三排序模块的第三缓冲器发送第二写回信号。Top-K模块与缓冲器交替相连，可以提高信号处理效率。
结合第一方面，在一些实施例中，第二控制逻辑模块基于第二外部信号和/或第二缓存信号确定第二输入信号，包括：判断第二先入先出队列是否输出第二缓存信号。如果第二先入先出队列输出了第二缓存信号，那么判断第二缓存信号是否有效。如果第二缓存信号有效，则将第二缓存信号的数据与全局顶端最值进行比较。如果第二缓存信号的数据未超过全局顶端最值，则第二控制逻辑模块确定第二缓存信号作为第二输入信号，如果第二缓存信号的数据超过或等于全局顶端最值，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。以及如果第二缓存信号无效，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。通过多个堆之间传递数据以及全局最值(最大值或最小值)的约束，可以减少排序时所需比较的次数，节省处理资源的消耗。此外，基于该多堆结构可以较好的利用了高速缓存器等片上存储资源，提高了不同片上资源的利用效率。
结合第一方面，在一些实施例中，如果第二先入先出队列没有输出第二缓存信号，那么判断第二外部信号是否有效。如果第二外部信号有效，则第二控制逻辑模块确定第二外部信号作为第二输入信号。以及如果第二外部信号无效，则第二控制逻辑模块读取非空的第二先入先出队列中缓存的第三缓存信号作为第二输入信号。即先入先出队列中溢出的缓存信号优先于外部信号被处理。当先入先出队列中没有溢出的缓存信号时，将有效的外部信号作为堆的输入信号，如果外部信号无效，为了保证FIFO中的所有数据都进入排序，避免堆模块闲置，可以读取非空的先入先出队列中未溢出的缓存的写回信号作为堆的输入信号。
结合第一方面，在一些实施例中，第一写回信号包括第一写回信号的数据和第一写回使能信号，第一写回使能信号指示第一写回信号是否有效。第二外部信号包括第二外部信号的数据和第二外部使能信号，第二外部使能信号指示第二外部信号是否有效。第二缓存信号包括第二缓存信号的数据和第二缓存使能信号，第二缓存使能信号指示第二缓存信号是否有效。使用写回使能信号和外部使能信号可以更方便地控制信号的输入。
结合第一方面，在一些实施例中，Top-K模块为最大堆，全局顶端最值为多个最大堆的堆顶元素的数据之中的最大值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据小于最大值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据大于或等于最大值。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。
结合第一方面，在一些实施例中，Top-K模块为最小堆，全局顶端最值为多个最小堆的堆顶元素的数据之中的最小值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据大于最小值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据小于或等于最小值。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
结合第一方面，在一些实施例中，第二Top-K模块基于第二输入信号获得第二写回信号，包括：判断第二输入信号是否有效，如果第二输入信号有效，则将第二输入信号的数据与第二Top-K模块的当前的顶端元素的数据进行比较。如果第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据替换掉第二Top-K模块的当前顶端元素的数据以成为第二Top-K模块中新的元素，以及将被替换出的第二Top-K模块的当前顶端元素的数据作为第二写回信号的数据，并且使能第二写回信号有效。以及如果第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号有效。通过利用Top-K模块内数据的有序性以及Top-K模块顶端数据的约束，将本Top-K模块不需要的数据传递给下一个排序模块处理或者及时丢弃，可以减少排序时所需比较的次数，节省处理资源和存储资源。
结合第一方面，在一些实施例中，还包括：如果第二输入信号无效，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号无效。被确定无用的数据可以发送给下一个排序模块的FIFO， 由下一个排序模块的控制逻辑来决策丢弃该数据。
结合第一方面，在一些实施例中，该方法还包括：第二Top-K模块更新第二Top-K模块的新的顶端元素，以及第二Top-K模块将第二Top-K模块的顶端元素发送给全局最值模块。全局最值模块用于获取多个Top-K模块的顶端元素，全局最值模块还用于选出多个Top-K模块的顶端元素的数据之中的最值，全局最值模块还用于将最值发送给多个缓冲器中的控制逻辑模块。由于被替换进入Top-K模块的元素不一定是Top-K模块内最值，所以在下一次输入信号输入堆之前，Top-K模块需要更新出新的顶端元素，以保证下次处理的准确性。
结合第一方面，在一些实施例中，第二Top-K模块为最大堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于最大堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于或等于最大堆的当前堆顶元素的数据。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。
结合第一方面，在一些实施例中，第二Top-K模块为最小堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于最小堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于或等于最小堆的当前堆顶元素的数据。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
结合第一方面，在一些实施例中，在第一时间周期内，第二缓冲器基于第二外部信号和/或第二缓存信号确定第二输入信号，以及在第二时间周期内，第二Top-K模块基于第二输入信号获得第二写回信号。在一个迭代周期内，一个排序模块可以完整的完成一次处理工作，一个迭代周期可以分成两个时间周期，例如第一时间周期和第二时间周期。在一些实施例中，第一时间周期与第二时间周期的时间长度相等。缓冲器判断选择进入堆的数据的处理周期与堆处理输入数据并输出写回数据的处理周期交替地执行，每个排序模块可以并行处理数据，这能够提高处理效率，缩减等待时间和处理时间，充分利用处理资源。
结合第一方面，在一些实施例中，多排序模块为多堆结构，Top-K模块为堆，多堆结构包括多个堆，多个堆中的每个堆中包括K个元素，多堆结构输出M个数据，M个数据为多堆结构的多个堆中的所有元素的集合。多堆结构的工作并行度可以增加到N，实现了更高的数据吞吐量，提高信号处理效率，并且多堆结构中的每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少数据存储量、数据传输量、数据处理量和处理时间。
结合第一方面，在一些实施例中，如果堆为最大堆，那么M个数据为多个信号中排序数据最小的前M个数据，最大堆的堆顶元素为最大堆中数据最大的元素；如果堆为最小堆，那么M个数据为多个信号中排序数据最大的前M个数据，最小堆的堆顶元素为最小堆中数据最小的元素。最大堆有助于筛选最小值，最小堆有助于筛选最大值。
在本申请的第二方面，提供了一种信号处理装置，包括：输入模块，被配置为向多排序模块输入多个信号，多排序模块包括环形串联的N个排序模块，N个排序模块中的每个排序模块包括具有K个元素的Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块包括第一Top-K模块，第一排序模块输出的被第一Top-K模块舍弃的信号或被替换出的第一Top-K模块的顶端元素作为第二排序模块的输入信号。处理模块，被配置为基于多个信号，更新多排序模块中多个Top-K模块中的元素。以及输出模块，被配置为获得多个信号中数据排序靠前的M个数据，其中M的值为N与K的乘积值，N、K、M为正整数。
实施本方面的信号处理装置，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
结合第二方面，在一些实施例中，第一排序模块中包括第一缓冲器和第一Top-K模块，第二排序模块中包括第二缓冲器和第二Top-K模块，第一排序模块的第一缓冲器的输出作为第一排序模块的第一Top-K模块的输入，第一排序模块的第一Top-K模块的输出作为第二排序模块的第二缓冲器的输入，第二排序模块的第二缓冲器的输出作为第二排序模块的第二Top-K模块的输入。各个排序模块之间的缓冲器与Top-K模块交替连接以及多个排序模块环形串联的结构可以提高处理效率。
结合第二方面，在一些实施例中，多个信号包括第一外部信号和第二外部信号，第一外部信号为第一排序模块的输入，第二外部信号为第二排序模块的输入，并且第一排序模块用于接收第一外部信号，第一排序模块还用于基于第一外部信号获得第一写回信号，第一排序模块还用于向第二排序模块发送第一写回信号。第二排序模块用于接收第二外部信号，第二排序模块还用于接收第一写回信号，第二排序模块还用 于基于第二外部信号和/或第一写回信号获得第二写回信号，第二排序模块还用于向第三排序模块发送第二写回信号。第一排序模块与第二排序模块串联可以提高处理效率，第一排序模块不需要的数据可以由第二排序模块继续处理，避免重复输入和处理。
结合第二方面，在一些实施例中，第一缓冲器中包括第一先入先出队列、第一控制逻辑模块和第一多选器，第一多选器用于接收第一外部信号，第一先入先出队列用于多次接收并缓存多个写回信号，第一先入先出队列还用于在被多个写回信号填满后输出第一缓存信号，以及第二缓冲器中包括第二先入先出队列、第二控制逻辑模块和第二多选器，第二多选器用于接收第二外部信号，第二先入先出队列用于多次接收并缓存第一排序模块的第一Top-K模块输出的多个写回信号，多个写回信号包括第一写回信号，第二先入先出队列还用于在被多个写回信号填满后输出第二缓存信号。控制逻辑和多选器用于基于先入先出队列输出的缓存信号、输入的外部信号和全局堆顶最值来选择进入堆的输入信号。先入先出队列用于缓存上个排序模块输出的写回数据。设置该先入先出队列缓存写回数据的目的是由于全局最值模块输出的堆顶值相对输入信号会存在几个周期的延迟，于是写回信号输入到缓冲器中的先入先出队列后，直到先入先出队列填充满才被读取，这时的缓存信号为多个周期前的输入，相对全局堆顶最值会延后，有利于控制逻辑能够发挥出较好筛选性能，避免写回信号在多个堆中传递而不会被筛选掉。
结合第二方面，在一些实施例中，第二控制逻辑模块还用于基于第二外部信号和/或第二缓存信号确定第二输入信号，第二多选器还用于向第二Top-K模块输出第二输入信号，第二Top-K模块用于接收来自于第二多选器的第二输入信号，第二Top-K模块还用于基于第二输入信号获得第二写回信号。以及第二Top-K模块还用于向第三排序模块的第三缓冲器发送第二写回信号。Top-K模块与缓冲器交替相连，可以提高信号处理效率。
结合第二方面，在一些实施例中，第二控制逻辑模块用于执行以下判断逻辑：判断第二先入先出队列是否输出第二缓存信号。如果第二先入先出队列输出了第二缓存信号，那么判断第二缓存信号是否有效。如果第二缓存信号有效，则将第二缓存信号的数据与全局顶端最值进行比较。如果第二缓存信号的数据未超过全局顶端最值，则第二控制逻辑模块确定第二缓存信号作为第二输入信号，如果第二缓存信号的数据超过或等于全局顶端最值，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。以及如果第二缓存信号无效，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。通过多个堆之间传递数据以及全局最值(最大值或最小值)的约束，可以减少排序时所需比较的次数，节省处理资源的消耗。此外，基于该多堆结构可以较好的利用了高速缓存器等片上存储资源，提高了不同片上资源的利用效率。
结合第二方面，在一些实施例中，第二控制逻辑模块还用于执行以下判断逻辑：如果第二先入先出队列没有输出第二缓存信号，那么判断第二外部信号是否有效。如果第二外部信号有效，则第二控制逻辑模块确定第二外部信号作为第二输入信号。以及如果第二外部信号无效，则第二控制逻辑模块读取非空的第二先入先出队列中缓存的第三缓存信号作为第二输入信号。即先入先出队列中溢出的缓存信号优先于外部信号被处理。当先入先出队列中没有溢出的缓存信号时，将有效的外部信号作为堆的输入信号，如果外部信号无效，为了保证FIFO中的所有数据都进入排序，避免堆模块闲置，可以读取非空的先入先出队列中未溢出的缓存的写回信号作为堆的输入信号。
结合第二方面，在一些实施例中，第一写回信号包括第一写回信号的数据和第一写回使能信号，第一写回使能信号指示第一写回信号是否有效。第二外部信号包括第二外部信号的数据和第二外部使能信号，第二外部使能信号指示第二外部信号是否有效。第二缓存信号包括第二缓存信号的数据和第二缓存使能信号，第二缓存使能信号指示第二缓存信号是否有效。使用写回使能信号和外部使能信号可以更方便地控制信号的输入。
结合第二方面，在一些实施例中，Top-K模块为最大堆，全局顶端最值为多个最大堆的堆顶元素的数据之中的最大值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据小于最大值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据大于或等于最大值。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。
结合第二方面，在一些实施例中，Top-K模块为最小堆，全局顶端最值为多个最小堆的堆顶元素的数据之中的最小值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据大于最小值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据小于或等于最小值。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
结合第二方面，在一些实施例中，第二Top-K模块用于执行以下判断逻辑：第二Top-K模块基于第二输入信号获得第二写回信号，包括：判断第二输入信号是否有效，如果第二输入信号有效，则将第二输入信号的数据与第二Top-K模块的当前的顶端元素的数据进行比较。如果第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据替换掉第二Top-K模块的当前顶端元素的数据以成为第二Top-K模块中新的元素，以及将被替换出的第二Top-K模块的当前顶端元素的数据作为第二写回信号的数据，并且使能第二写回信号有效。以及如果第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号有效。通过利用Top-K模块内数据的有序性以及Top-K模块顶端数据的约束，将本Top-K模块不需要的数据传递给下一个排序模块处理或者及时丢弃，可以减少排序时所需比较的次数，节省处理资源和存储资源。
结合第二方面，在一些实施例中，第二Top-K模块还用于执行以下判断逻辑：如果第二输入信号无效，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号无效。被确定无用的数据可以发送给下一个排序模块的FIFO，由下一个排序模块的控制逻辑来决策丢弃该数据。
结合第二方面，在一些实施例中，第二Top-K模块还用于更新第二Top-K模块的新的顶端元素，以及第二Top-K模块还用于将第二Top-K模块的顶端元素发送给全局最值模块。全局最值模块用于获取多个Top-K模块的顶端元素，全局最值模块还用于选出多个Top-K模块的顶端元素的数据之中的最值，全局最值模块还用于将最值发送给多个缓冲器中的控制逻辑模块。由于被替换进入Top-K模块的元素不一定是Top-K模块内最值，所以在下一次输入信号输入堆之前，Top-K模块需要更新出新的顶端元素，以保证下次处理的准确性。
结合第二方面，在一些实施例中，第二Top-K模块为最大堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于最大堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于或等于最大堆的当前堆顶元素的数据。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。
结合第二方面，在一些实施例中，第二Top-K模块为最小堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于最小堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于或等于最小堆的当前堆顶元素的数据。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
结合第二方面，在一些实施例中，在第一时间周期内，第二缓冲器基于第二外部信号和/或第二缓存信号确定第二输入信号，以及在第二时间周期内，第二Top-K模块基于第二输入信号获得第二写回信号。在一个迭代周期内，一个排序模块可以完整的完成一次处理工作，一个迭代周期可以分成两个时间周期，例如第一时间周期和第二时间周期。在一些实施例中，第一时间周期与第二时间周期的时间长度相等。缓冲器判断选择进入堆的数据的处理周期与堆处理输入数据并输出写回数据的处理周期交替地执行，每个排序模块可以并行处理数据，这能够提高处理效率，缩减等待时间和处理时间，充分利用处理资源。
结合第二方面，在一些实施例中，多排序模块为多堆结构，Top-K模块为堆，多堆结构包括多个堆，多个堆中的每个堆中包括K个元素，多堆结构输出M个数据，M个数据为多堆结构的多个堆中的所有元素的集合。多堆结构的工作并行度可以增加到N，实现了更高的数据吞吐量，提高信号处理效率，并且多堆结构中的每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少数据存储量、数据传输量、数据处理量和处理时间。
结合第二方面，在一些实施例中，如果堆为最大堆，那么M个数据为多个信号中排序数据最小的前M个数据，最大堆的堆顶元素为最大堆中数据最大的元素；如果堆为最小堆，那么M个数据为多个信号中排序数据最大的前M个数据，最小堆的堆顶元素为最小堆中数据最小的元素。最大堆有助于筛选最小值，最小堆有助于筛选最大值。
在本申请的第三方面，提供了一种电子设备，电子设备包括存储器以及耦合于存储器的处理器，存储器中存储有可执行指令，处理器用于调用可执行指令，使得电子设备执行以下根据上述第一方面或其任一实施例中的方法的操作。
在本申请的第四方面，提供了一种计算机可读存储介质，该计算机可读存储介质存储有计算机可执行指令，计算机可执行指令被处理器执行时实现根据上述第一方面或其任一实施例中的方法的操作。
在本申请的第五方面，提供了一种计算机程序产品，该计算机程序产品上包含计算机可执行指令，计算机可执行指令在被执行时实现根据上述第一方面或其任一实施例中的方法的操作。
在本申请的第六方面，提供了一种芯片或芯片系统，该芯片或芯片系统包括处理电路，其被配置为实现根据上述第一方面或其任一实施例中的方法的操作。
实施本申请以上一个或多个方面，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标注表示相同或相似的元素，其中：
图1示出了根据本公开的一些实施例的一种堆结构的示意图；
图2示出了根据本公开的一些实施例的信号处理方法流程的示意图；
图3示出了根据本公开的一些实施例的数据处理系统的功能模块的示意图；
图4示出了根据本公开的一些实施例的一种多堆结构的示意图；
图5示出了根据本公开的一些实施例的一种多堆结构的排序模块的示意图；
图6示出了根据本公开的一些实施例的一种多堆结构的排序模块的控制逻辑流程的示意图；
图7示出了根据本公开的一些实施例的一种堆模块的示意图；
图8示出了根据本公开的一些实施例的一种堆模块的堆控制逻辑流程的示意图；
图9示出了根据本公开的一些实施例的一种双堆结构的示意图；
图10示出了根据本公开的一些实施例的一种双堆结构的排序模块的示意图；
图11示出了根据本公开的一些实施例的一种双堆结构的排序模块的控制逻辑流程的示意图；
图12示出了根据本公开的一些实施例的一种堆模块的堆控制逻辑流程的示意图；
图13示出了根据本公开的一些实施例的电子设备结构的示意图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
本申请以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“该”、“上述”、“该”和“这一”旨在也包括复数表达形式，除非其上下文中明确地有相反指示。还应当理解，本申请中使用的术语“和/或”是指并包含一个或多个所列出项目的任何或所有可能组合。
在本申请的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。应理解，“第一”，“第二”，“第三”等表述只是为了表示多个对象可能是不同的，但是同时不排除两个对象之间是相同的。“第一”，“第二”，“第三”等表述不应当解释为对实施例的任何限制。术语“第一”、“第二”仅用于描述目的，而不能理解为暗示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征，在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。下文还可能包括其他明确的和隐含的定义。
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本申请所描述的实施例可以与其它实施例相结合。
在大规模无序数据中求取找出前K个最大的元素或者最小的元素是个广泛的应用。示例性应用场景可以是，例如，在持续更新的海量视频中找出视频点击率最高的100个视频进行推荐；再例如，分布式系统中将任务分配给所监控到的中央处理器(CPU)利用率最低的10个设备；又例如，根据海量且不断更新的游戏玩家的数据，生成游戏分数最高的前100名游戏玩家列表。在这种情形下，可以使用最大堆或最小堆的堆结构来在大规模数据中求取动态更新的前K个最小或最大的数据元组。
由于堆满足的父节点与子节点的有序性，堆的更新操作，如进栈(pop)操作、出栈(push)操作，通常从根节点开始，限制了堆的并行性。对于一个大小为N(N为正整数)的堆，完成一次更新操作所需的比较次数为O(logN)。如图1所示的堆结构100，在一种应用Top-K排序的堆并行方案中，将所有待处理数据分为两个部分，即数据库101和数据库102，分别输入到大小为K(K为正整数)的堆103和堆104中完成Top-K排序，即数据库101输入堆103进行Top-K排序，数据库102输入堆104进行Top-K排序，再将堆103和堆104中的结果最终削减为一个Top-K的结果，即堆105。在这里，堆103和堆104同时工作，并行度为2。对于更高并行度的情况，可以通过使用更多的大小为K的堆完成第一次Top-K排序，再将多个第一次Top-K排序的结果逐步削减为最终Top-K的结果。这种方案在多个堆并行完成第一次堆化操作后，还有后续的提炼K个元素的步骤，会造成存储空间、计算资源、处理资源的浪费，并且这种方案中堆的大小为K，当K较大时会给片上缓存带来较大的挑战，对于单个堆的性能也没有带来提升，因此往往硬件资源开销较大，并行度差。
本公开的一个或多个实施例提出了一种信号处理方法以及电子设备，用于优化实现在无序的大规模数据中快速找出前M个最大的元素或者最小的元素。该信号处理方法可以包括：向多排序模块输入多个信号，多排序模块包括环形串联的多个排序模块，多个排序模块中的每个排序模块包括Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块的输出作为第二排序模块的输入。基于多个信号，更新多个Top-K模块中的元素，以及输出多排序模块中多个Top-K模块中的元素。
实施本公开的一个或多个实施例中的信号处理方法以及电子设备，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
参考图2，图2示出了本申请实施例的信号处理方法流程200的示意图。示例性的，实施该信号处理方法的电子设备可以是智能手机、平板电脑、个人计算机、桌面型计算机、膝上型计算机、手持计算机、游戏机、智慧屏(智能电视)、无人机、增强现实(augmented reality，AR)设备、虚拟现实(virtual reality，VR)设备、人工智能(artificial intelligence，AI)设备、可穿戴式设备、车机(车载设备)、物联网(internet of things，IOT)设备或者其他类型的电子设备等等。本申请实施例对该电子设备的具体类型不做限定。
在框201，向多排序模块输入多个信号。其中，多排序模块包括环形串联的多个排序模块，例如N个排序模块，多个排序模块中的每个排序模块包括具有K个元素的Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块的输出作为第二排序模块的输入。例如，第一排序模块包括第一Top-K模块，第一排序模块输出的被第一Top-K模块舍弃的信号或被替换出的第一Top-K模块的顶端元素作为第二排序模块的输入信号。在本申请的实施例中，该多个信号是多排序模块之外的外部信号，该外部信号可以例如为网络数据信号，例如上述应用场景中提到的视频点击率数据信号，或者CPU利用率信号，或者游戏得分数据信号等。该外部信号可以包括数据元组以及使能信号。在一些实施例中，该多排序模块可以实现为图4所示的多堆结构400，或者图9所示的双堆结构900。Top-K模块可以实现为堆，例如最大堆或最小堆。
在框202，基于多个信号，更新多排序模块中多个Top-K模块中的元素。在一些实施例中，输入多排序模块中的外部信号在经过多排序模块的处理后，被筛选留下以及替换原有的Top-K模块中元素作为所需要的Top-K元素之一。
在框203，获得多个信号中数据排序靠前的M个数据。其中M的值为N与K的乘积值，M＝N×K，N、K、M为正整数。在本申请实施例中，该多排序模块是一个由多个堆环形串联起来的结构，一个Top-K模块的输出信号会输入到下一个Top-K模块，由此将外部信号依次传输下去，直到进入某个Top-K模块或者被舍弃。该多排序模块中的经过排序完成的多个Top-K模块中的多个元素的集合即是所需要的Top-K元素。
实施上述实施例中的信号处理方法，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
在一些实施例中，在一些实施例中，多排序模块为多堆结构，Top-K模块为堆，多堆结构包括多个堆，多个堆中的每个堆中包括K个元素，多堆结构输出M个数据，M个数据为多堆结构的多个堆中的所有元素的集合。多堆结构的工作并行度可以增加到N，实现了更高的数据吞吐量，提高信号处理效率，并且多堆结构中的每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少数据存储量、数据传输量、数据处理量和处理时间。
在一些实施例中，在一些实施例中，如果堆为最大堆，那么M个数据为多个信号中排序数据最小的前 M个数据，最大堆的堆顶元素为最大堆中数据最大的元素；如果堆为最小堆，那么M个数据为多个信号中排序数据最大的前M个数据，最小堆的堆顶元素为最小堆中数据最小的元素。最大堆有助于筛选最小值，最小堆有助于筛选最大值。
在一些实施例中，第一排序模块中包括第一缓冲器和第一Top-K模块，第二排序模块中包括第二缓冲器和第二Top-K模块，第一排序模块的第一缓冲器的输出作为第一排序模块的第一Top-K模块的输入，第一排序模块的第一Top-K模块的输出作为第二排序模块的第二缓冲器的输入，第二排序模块的第二缓冲器的输出作为第二排序模块的第二Top-K模块的输入。各个排序模块之间的缓冲器与Top-K模块交替连接以及多个排序模块环形串联的结构可以提高处理效率。
在一些实施例中，多个信号包括第一外部信号和第二外部信号，第一外部信号为第一排序模块的输入，第二外部信号为第二排序模块的输入，并且该方法还包括：第一排序模块接收第一外部信号，第一排序模块基于第一外部信号获得第一写回信号，第一排序模块向第二排序模块发送第一写回信号。第二排序模块接收第二外部信号，第二排序模块接收第一写回信号，第二排序模块基于第二外部信号和/或第一写回信号获得第二写回信号，第二排序模块向第三排序模块发送第二写回信号。第一排序模块与第二排序模块串联可以提高处理效率，第一排序模块不需要的数据可以由第二排序模块继续处理，避免重复输入和处理。
例如，该多排序模块的具体结构可以结合参考图4所示的示例多堆结构400。结合图4和图5所示的实施例，多堆结构400包括环形串联的多个排序模块，例如排序模块500(可以是第一排序模块或第二排序模块)，每个排序模块具有对应的数据源输入Ik(即多个信号中的一个信号，或者称为外部信号，如第二外部信号)，堆(如第一Top-K模块/第一堆或第二Top-K模块/第二堆)，堆顶的数据值的输出Tk(即顶端元素/堆顶元素的信号)，本排序模块输入WBk-1(如第一写回信号)、下一个单排序模块的输入WBk(如第二写回信号)、以及全局堆顶最大值Tg(即全局最值)。N个单堆结构通过N个缓冲器交替相连，使得N个排序模块的输出和输入首尾相接连成环状。图4所示的可扩展高并行的多堆结构中可以具有N个单独的信号输入，可同时完成N路信号输入以找到这N路信号的大量数据输入中共同的TOP-M个数据值。或者，例如，该多堆结构也可以是图9实施例所示的双堆结构900，具体可以参考后续图9描述的实施例，这里暂不赘述。
在一些实施例中，第一缓冲器中包括第一先入先出队列、第一控制逻辑模块和第一多选器，第一多选器用于接收第一外部信号，第一先入先出队列用于多次接收并缓存多个写回信号，第一先入先出队列还用于在被多个写回信号填满后输出第一缓存信号。第二排序模块(如图5中所示的排序模块500或者图10所示的缓冲器1000)中包括第二缓冲器(参考图5所示的缓冲器510或者图10所示的缓冲器1010)，第二缓冲器(如图5的缓冲器510或者图10的缓冲器1010)中包括第二先入先出队列(如图5的FIFO 550或者图10的FIFO 1050)、第二控制逻辑模块(如图5的控制逻辑520或者图10的控制逻辑1020)和第二多选器(如图5的多选器530或者图10的多选器1030)，第二多选器(如MUXk)用于接收第二外部信号(如Ik)，第二先入先出队列(如FIFOk)用于多次接收并缓存第一排序模块的第一Top-K模块输出的多个写回信号(如WBk-1)，多个写回信号包括第一写回信号，第二先入先出队列还用于在被多个写回信号填满后输出第二缓存信号(如WB′k-1)。控制逻辑(如Ck)和多选器(如MUXk)用于基于先入先出队列(如FIFOk)输出的缓存信号(或者称为缓存写回信号，如WB′k-1)、输入的外部信号(如Ik)和全局堆顶最值(如Tg)来选择进入堆(如heapk)的输入信号。先入先出队列用于缓存上个排序模块输出的写回数据。设置该先入先出队列缓存写回数据的目的是由于全局最值模块输出的堆顶值相对输入信号会存在几个周期的延迟，于是写回信号输入到缓冲器中的先入先出队列后，直到先入先出队列填充满才被读取，这时的缓存信号为多个周期前的输入，相对全局堆顶最值会延后，有利于控制逻辑能够发挥出较好筛选性能，避免写回信号在多个堆中传递而不会被筛选掉。
在一些实施例中，在一些实施例中，第二控制逻辑模块(如Ck)基于第二外部信号(如Ik)和/或第二缓存信号(如WB′k-1)确定第二输入信号(如DIk)。第二多选器(如MUXk)向第二Top-K模块(如heapk)输出第二输入信号(如DIk)。第二Top-K模块(如heapk)接收来自于第二多选器(如MUXk)的第二输入信号(如DIk)。第二Top-K模块(如heapk)基于第二输入信号(如DIk)获得第二写回信号(如WBk)。第二Top-K模块(如heapk)向第三排序模块的第三缓冲器发送第二写回信号(如WBk)。Top-K模块与缓冲器交替相连，可以提高信号处理效率。
在一些实施例中，第二控制逻辑执行以下判断逻辑：判断第二先入先出队列是否输出第二缓存信号。如果第二先入先出队列输出了第二缓存信号，那么判断第二缓存信号是否有效。如果第二缓存信号有效， 则将第二缓存信号的数据与全局顶端最值进行比较。如果第二缓存信号的数据未超过全局顶端最值，则第二控制逻辑模块确定第二缓存信号作为第二输入信号，如果第二缓存信号的数据超过或等于全局顶端最值，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。以及如果第二缓存信号无效，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。通过多个堆之间传递数据以及全局最值(最大值或最小值)的约束，可以减少排序时所需比较的次数，节省处理资源的消耗。此外，基于该多堆结构可以较好的利用了高速缓存器等片上存储资源，提高了不同片上资源的利用效率。例如，在图5所示的实施例中，单堆模块的堆顶最大值输出Tk，表示本排序模块中当前堆结构的堆顶。信号Tg表示从N个堆顶输入获取的最值，即全局最值(又可称为全局堆顶最值)。
在一些实施例中，第二控制逻辑还执行以下判断逻辑：如果第二先入先出队列没有输出第二缓存信号，那么判断第二外部信号是否有效。如果第二外部信号有效，则第二控制逻辑模块确定第二外部信号作为第二输入信号。以及如果第二外部信号无效，则第二控制逻辑模块读取非空的第二先入先出队列中缓存的第三缓存信号作为第二输入信号。即先入先出队列中溢出的缓存信号优先于外部信号被处理。当先入先出队列中没有溢出的缓存信号时，将有效的外部信号作为堆的输入信号，如果外部信号无效，为了保证FIFO中的所有数据都进入排序，避免堆模块闲置，可以读取非空的先入先出队列中未溢出的缓存的写回信号(如第三缓存信号)作为堆的输入信号。关于第二控制逻辑执行的判断逻辑可以结合参考图6所示的控制逻辑的工作流程600或者图11所示的控制逻辑的工作流程1100的实施例进行理解，此处不再赘述。
在一些实施例中，第一写回信号包括第一写回信号的数据和第一写回使能信号，第一写回使能信号指示第一写回信号是否有效。第二外部信号包括第二外部信号的数据和第二外部使能信号，第二外部使能信号指示第二外部信号是否有效。第二缓存信号包括第二缓存信号的数据和第二缓存使能信号，第二缓存使能信号指示第二缓存信号是否有效。使用写回使能信号和外部使能信号可以更方便地控制信号的输入。例如，在一些实施例中，数据源Ik表示外部输出的待进行排序的数据。数据源Ik(如第二外部信号)又具体的包括数据信号I_datak(如第二外部信号的数据)和使能信号I_enk(如第二外部使能信号)。使能信号I_enk表示数据信号I_datak是否有效。环状结构的上一个排序模块给本FIFOk的输入信号WBk-1又具体的包括数据信号WB_datak-1(如第一写回信号的数据)和使能信号WB_enk-1(如第一写回使能信号)，使能信号WB_enk-1表示数据信号WB_datak-1是否有效。本排序模块中的FIFOk的输出的缓存写回信号WB′k-1(如第二缓存信号)又具体的包括数据信号WB_data′k-1(如第二缓存信号的数据)和使能信号WB_en′k-1(如第二缓存使能信号)，使能信号WB_en′k-1表示数据信号WB_data′k-1是否有效。多堆结构中本单排序模块输出给下一个单排序模块，作为下一个单排序模块的输入的WBk，类似的WBk又具体的分为数据信号WB_datak和使能信号WB_enk，使能信号WB_enk表示数据信号WB_datak是否有效。在一些实施例中，外部信号是否有效依据交替输入的周期。
在一些实施例中，Top-K模块为最大堆，全局顶端最值为多个最大堆的堆顶元素的数据之中的最大值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据小于最大值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据大于或等于最大值。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。在一些实施例中，Top-K模块为最小堆，全局顶端最值为多个最小堆的堆顶元素的数据之中的最小值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据大于最小值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据小于或等于最小值。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
在一些实施例中，第二Top-K模块可以执行以下判断逻辑：判断第二输入信号是否有效，如果第二输入信号有效，则将第二输入信号的数据与第二Top-K模块的当前的顶端元素的数据进行比较。如果第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据替换掉第二Top-K模块的当前顶端元素的数据以成为第二Top-K模块中新的元素，以及将被替换出的第二Top-K模块的当前顶端元素的数据作为第二写回信号的数据，并且使能第二写回信号有效。以及如果第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号有效。通过利用Top-K模块内数据的有序性以及Top-K模块顶端数据的约束，将本Top-K模块不需要的数据传递给下一个排序模块处理或者及时丢弃，可以减少排序时所需比较的次数，节省处理资源和存储资源。在一些实施例中，第二Top-K模块还执行以下判断逻辑：如果第二输入信号无效，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号无效。被确定无用的数据可以发送给下一个排序模块的FIFO，由下一个排序模块的控制逻辑来决策丢弃该数据。
在一些实施例中，第二Top-K模块更新第二Top-K模块的新的顶端元素。例如堆结构执行堆化操作以更新堆结构的新的堆顶元素，其中，堆化操作指的是对堆中的元素进行排序更新。)。第二Top-K模块将第二Top-K模块的顶端元素发送给全局最值模块。全局最值模块用于获取多个Top-K模块的顶端元素，全局最值模块还用于选出多个Top-K模块的顶端元素的数据之中的最值，全局最值模块还用于将最值发送给多个缓冲器中的控制逻辑模块。由于被替换进入Top-K模块的元素不一定是Top-K模块内最值，所以在下一次输入信号输入堆之前，Top-K模块需要更新出新的顶端元素，以保证下次处理的准确性。
参考图7所示的堆模块700，堆数据一般为层次结构，具有堆顶，如果是最大堆则堆顶为堆的最大值，如果是最小堆则堆顶为堆的最小值，可以以最大堆为例，求N个数据输入通道内数据的共同的K个最大值。堆模块700有输入信号DIk(如第二输入信号)作为堆模块(heapk)(如第二Top-K模块)的输入，具体的输入信号DIk又分为数据信号DI_datak和使能信号DI_enk，使能信号DI_enk表示数据信号DI_datak是否有效。堆模块700的输出为数据信号WB_datak和使能信号WB_enk，使能信号WB_enk表示数据信号WB_datak是否有效。关于第二堆的结构以及执行的判断逻辑可以结合参考图7-图8所示的堆模块700以及堆控制逻辑的工作流程800或者图12所示的控制逻辑的工作流程1200的实施例进行理解，此处不再赘述。
在一些实施例中，第二Top-K模块为最大堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于最大堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于或等于最大堆的当前堆顶元素的数据。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。在一些实施例中，第二Top-K模块为最小堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于最小堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于或等于最小堆的当前堆顶元素的数据。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
在一些实施例中，在第一时间周期内，第二缓冲器基于第二外部信号和/或第二缓存信号确定第二输入信号，以及在第二时间周期内，第二Top-K模块基于第二输入信号获得第二写回信号。在一个迭代周期内，一个排序模块可以完整的完成一次处理工作，一个迭代周期可以分成两个时间周期，例如第一时间周期和第二时间周期。在一些实施例中，第一时间周期与第二时间周期的时间长度相等。缓冲器判断选择进入堆的数据的处理周期与堆处理输入数据并输出写回数据的处理周期交替地执行，每个排序模块可以并行处理数据，这能够提高处理效率，缩减等待时间和处理时间，充分利用处理资源。
以上实施例仅仅是为了更加清楚的说明本申请的技术方案，并不构成对本申请的限定。在其他实施例中还可以包括更多或更少的流程或步骤，或者各实施例进行组合或拆分，得到更多的实现方式，本申请实施例对此不作限制。
结合上述实施例可以看出，本公开的一些实施例可以实现一种针对大规模数据排序的可扩展高并行的多堆结构，其并行度可以增加到N，实现了更高的数据吞吐量，并且对于求取M个Top数据的多堆结构，其中每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少处理时间，更快的实现得到所需的排序靠前的多个数据。
此可扩展的环形多输入的多堆结构，其整体结构可以包含首尾串联的N个排序模块以及一个全局最值(最大值或最小值)模块，每个排序模块可以至少包括一个单堆结构、一个缓冲器、一个数据源等。其中，缓冲器接收来自上一个排序模块的写回数据以及外部数据源的数据，并且接收全局最值(最大值或最小值)，并向相应的堆输出数据。每个缓冲器至少包含一个先入先出队列、一个多选器以及相应的控制逻辑，先入先出队列用于缓冲前一个排序模块的堆输出的写回数据，多选器及其控制逻辑用于选择输入给自身排序模块的堆的输入信号。每个排序模块的堆接收来自身的多选器的输出，并且生成写回数据输出到下一个排序模块的缓冲器，以及将堆顶输入到全局最值模块。所有的堆与缓冲器交替连接构成一个环形结构。由于缓冲器隔离了相邻的前一个堆的输出，所有的堆可以同步工作或者异步工作，输入数据通过堆的写回数据以及缓冲器，在堆间单向传递直至进入某个堆或者被比较全局最值时扔掉，全局最值(最大值或最小值)可以约束数据的传递，每个堆中存储的数据不会被浪费。因此，本公开的一些实施例的多堆结构可以利用堆内数据排布的有序性质，并通过堆之间的串联，以及全局最值(最大值或最小值)的约束，减少了排序所需的比较次数，使得硬件资源的消耗较少以及节省了存储资源。即，相较于图1所示的排序结构，处理资源开销降低，并提高了吞吐量，可以实现更大数据量的Top排序以及多个多堆结构的并发工作，并且基于 该多堆结构，每个堆中存储的数据不会被浪费，可以较好的利用片上存储资源(如，静态随机存取存储器(static random access memory，SRAM)，提高不同片上资源的利用效率。
下面介绍本申请的实施例提供的数据处理系统300的功能模块(或者称为逻辑单元)。参考图3，图3示出了本申请一些实施例提供的数据处理系统300的功能模块的示意图。
本申请实施例可以对数据处理系统300进行功能模块的划分，例如，可以将数据处理系统300的各个功能划分各个功能模块，也可以将数据处理系统300的两个或两个以上的功能集成在一个功能模块中，本实施例不作限制。上述集成的模块既可以采用硬件或软件的形式实现，也可以采用软硬件结合的形式实现。
示例性的，如图3所示，数据处理系统300中包括存储模块301、控制模块302、数据处理模块303、数据消费模块304，其中，数据处理模块303中还包括前处理模块305、排序模块306、后处理模块307。
该数据处理系统300可以是基于专用集成电路芯片的专用加速器系统以及基于可编程逻辑器件的硬件系统。对于专用加速器系统，数据处理模块303可以包括应用专用集成电路芯片(ASIC)。对于可编程硬件系统，数据处理模块303包括可编程逻辑器件(FPGA)。存储子系统由ASIC或FPGA上的片上SRAM缓冲、随机存储器(DDR或HBM)以及非易失性存储器(SSD或HHD)等组成。数据消费模块304可以是本地通用计算机系统也可以是远程客户端应用。本公开的应用场景可以是针对需要数据排序的计算机系统，例如云计算平台加速相似性搜索、推荐系统以及数据库系统中的Top排序计算。
本公开的实施例可以是在专用加速器系统或者可编程硬件系统的软硬件实现。其中控制模块302控制存储模块301的数据的输入输出以及数据处理模块303中其他模块的控制。前处理模块305和后处理模块307根据应用场景的不同可以有不同的实现。前处理模块305可以针对片外存储系统输入的数据进行处理，以得到排序所需的数据；排序模块306用于执行排序；后处理模块307可以根据排序的结果再进一步处理以得到可以输出给数据消费模块304的结果。例如，排序模块306可以执行前述方法200所描述的相应一个或多个实施例，排序模块306中包含片上存储单元，排序的中间结果在排序过程中存储在片上，排序结果输出到后处理模块307。在专用加速器系统或者可编程硬件系统上，前处理模块305、排序模块306以及后处理模块307可以均在片上实现，其中控制模块302可使用通用处理器或者在加速器芯片上进行实现。
实施本申请实施例的数据处理系统300中的功能模块，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
数据处理系统300中的各个功能模块可以通过软件、硬件或者两者结合的方式实现。可以理解的，关于数据处理系统300包括的各个功能单元的具体实现可参考本申请其他各实施例中的详细描述，这里不多赘述。
需要注意的是，本申请实施例的数据处理系统300中不限定各个功能模块的类型、数量和关联关系，在一些实施例中，数据处理系统300中可以包括更多或更少的功能模块等。
需要说明的是，本申请实施例中对模块或单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时也可以有另外的划分方式。另外，在实施例中的各功能单元可以集成在一个单元中，也可以是单独物理存在，也可以两个或两个以上单元集成为一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现，或者软硬件结合的形式实现。
为了更清楚的理解本公开的内容，下面介绍本公开针对大规模数据的排序提出的一种可扩展高并行的多输入的多堆结构，以及一种双堆结构。
本公开的一些实施例提供了一种可扩展高并行的环形多输入的多堆结构，这里具体以最大堆为例进行说明，最小堆的情况反之亦然。假设该多堆结构可以求取多个数据中的M个最小值，该多堆结构中并行的堆数目为N，可扩展的环形多输入多堆结构可以由N个堆、N个缓冲器、N个数据源、N个控制逻辑以及一个全局最大值模块组成。N个堆的结构可以均为最大堆，最大堆用于筛选最小值，每个堆可以包括K个的元素，完成一系列输入和排序之后，最后输出的这N个堆中所包括的K个元素的集合即为所求取的M个最小值，即M的值为K与N的乘积值，其中K、M、N为正整数。
该多堆结构包括N个堆，其中第i个堆heapi包括输入数据DIi与写回数据WBi以及堆顶数据Ti的接口，其中i＝0,1,…,N-1。在一些实施例中，第i个堆可每两个周期处理一个输入数据DIi，并且在输入数据DIi有效的一个周期后返回一个写回数据WBi。其中，输入数据DIi与写回数据WBi均可以包括进行排序的元组以及使能信号。例如，输入数据DIi包括元组DI_Datai以及使能信号DI_eni，写回数据WBi包括元组WB_Datai以及使能信号WB_eni，其中元组可以表示为(ID,Value)，包含用于比较的数值Value以及用于对应数值的编号ID或者相应的键值等。在一些实施例中，输入数据DIi的使能信号DI_eni为真表示输入数据 DIi有效，在输入数据DIi有效一周期后输出写回数据WBi，并伴随着写回数据WBi的使能信号WB_eni有效。在一些实施例中，当输入数据DIi大于等于堆顶Ti时，写回数据WBi为输入数据DIi，堆顶保持不变。否则，写回数据WBi为Ti，堆顶被替换为DIi。
该多堆结构还包括N个缓冲器，第i个缓冲器bufferi可以包括先入先出队列FIFOi和多选器MUXi以及相应的控制逻辑Ci，其中i＝0,1,…,N-1。FIFOi用于缓冲来自前一个堆heapi-1的写回数据WBi-1。当FIFOi被填满到一定程度后，可以输出被读取数据WB′i-1。多选器MUXi其中一个输入连接着对应的数据源Ii，另一个输入连着FIFOi的写回数据WB′i-1。多选器MUXi的选择信号Si由控制逻辑Ci给出。多选器MUXi的选择输出连着堆heapi的输入数据DIi。在一些实施例中，对于多选器控制逻辑Ci，当FIFOi的输出数据WB′i-1有效时，比较WB′i-1和全局最大值Tg，当WB′i-1的值小于Tg时，选择FIFOi的输出数据WB′i-1作为多选器的输出。当FIFOi的输出数据WB′i-1无效时，如果数据源Ii有效则选择数据源Ii作为多选器的输出，如果数据源Ii无效可以选择读取非空的FIFOi中缓存的数据(如第三缓存信号)作为多选器的输出。在一些实施例中，因为堆每两个周期处理一个数据，所以缓冲器可以相应的每两个周期发生一次判断。
该多堆结构还包括N个数据源，第i个数据源Ii可以使用先入先出存储器等实现，用于缓冲外部信号的输入数据元组并提供相应的输入数据使能。全局最大值模块用于接收所有堆的堆顶数据Ti，并产生所有堆的堆顶数据中的最大值，即全局最大值Tg，Tg基于实现形式的不同会相比输入存在几个周期的延迟。
在一些实施例中，在没有数据输入时，所有堆的输入数据的使能无效，所有堆都不工作。初始时，N个数据源使能有效，可以每两个周期分别向N个缓冲器发送数据。例如对于第i个缓冲器bufferi，由于缓冲器bufferi中的FIFOi未被填充到可以读取数据，控制逻辑Ci直接选择数据源Ii作为相应堆heapi的输入。如此重复多个周期，直到存在缓冲器bufferi中的FIFOi被填充到可以向多选器MUXi输出数据WB′i-1，相应的控制逻辑Ci可以进行判断。当FIFOi的输出数据WB′i-1有效时，比较WB′i-1和全局最大值Tg，如果FIFOi输出数据WB′i-1小于全局最大值模块的输出Tg，则多选器MUXi选择FIFOi的输出数据WB′i-1作为堆heapi的输入数据DIi。当FIFOi的输出数据WB′i-1无效时，如果数据源Ii使能有效，则选择数据源Ii作为堆heapi的输入数据DIi，如果数据源Ii使能无效，控制逻辑Ci可以读取非空的FIFOi中缓存的其他数据(如第三缓存信号)作为堆heapi的输入数据DIi，直到FIFOi为空。当所有数据源输入完成，并且所有缓冲器中的FIFO为空时，待堆执行完所有排序操作后，最后输出的这N个堆中(每个堆包括K个的元素)所包括的K×N个元素的集合即为所求取的M个最小值，排序完成。实现该多堆结构，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
下面结合图4所示的多堆结构400、图5所示的排序模块500、排序模块的控制逻辑流程600、堆模块700、堆模块的堆控制逻辑流程800来更具体地说明本公开提供的一些实施例。
图4示出了本公开提出的一种可扩展的高并行的多输入的环形多堆结构400的示意图。本实施例以堆为最大堆来进行示例说明，最小堆的实施例可以反向推之。如图4所示，多堆结构400中包含N个如虚线框所示的单个排序模块500以及一个全局最大值模块，这N个排序模块可以串连成一个环形结构，单个排序模块中可以包括一个缓冲器和一个单堆结构。单个排序模块500的具体结构可以参考图5所示的实施例。其中，N个单堆结构通过N个缓冲器相连接，N个单堆结构与N个缓冲器交替排列，首尾相接连成环状，一个缓冲器的输入可以是与之相连的前一个堆的输出，一个缓冲器的输出可以是与之相连的下一个堆的输入。全局最大值模块用于接收所有堆的堆顶数据Ti，并产生所有堆的堆顶数据中的最大值，即全局最大值Tg，Tg基于实现形式的不同会相比输入存在几个周期的延迟。可以看出，多堆结构400中所包括的N个排序模块中的第k个排序模块可以具有单独的数据源输入Ik，堆顶的数据值的输出Tk，以及全局堆顶最大值输入Tg，其中k＝0,1,…,N-1。图4所示的可扩展的高并行的多堆结构400，可以具有N个单独的数据源输入，可同时完成N路数据输入，以及多堆结构400中的N个堆的每个堆的结构可以均为最大堆，最大堆用于筛选最小值，每个堆可以包括K个的元素。将很多数据输入该多堆结构400，在完成一系列输入和排序之后，最后输出的这N个堆中所包括的K×N个元素的集合即为所求取的M个最小值，即找到该输入的很多数据中的TOP-M个数据。实现该多堆结构400，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
参考图5中所示的单个排序模块500，第k个排序模块500的外部接口包括数据源Ik、上一个排序模块给本排序模块的输入WBk-1、本排序模块给下一个排序模块的输入WBk、本单堆模块的堆顶最大值输出Tk、全局最大值输入信号Tg等，其中以下小写的k表示如图4结构中的第k个单排序模块(区别于在本公开中的大写的K表示TOP-K排序中需要获得的K个最大或者最小数据)。具体地，数据源Ik表示外部输出的待 进行排序的数据。数据源Ik又具体的分为数据信号I_datak和使能信号I_enk。使能信号I_enk表示数据信号I_datak是否有效。环状结构的上一个单排序模块给本单排序模块的输入WBk-1又具体的分为数据信号WB_datak-1和使能信号WB_enk-1，使能信号WB_enk-1表示数据信号WB_datak-1是否有效。多堆结构中本单排序模块给下一个单排序模块的输出WBk可以作为下一个单排序模块的输入，类似的WBk又具体的分为数据信号WB_datak和使能信号WB_enk，使能信号WB_enk表示数据信号WB_datak是否有效。本单堆模块的堆顶最大值输出Tk，表示本排序模块中当前堆结构的堆顶。输入信号Tg表示从N个排序模块的堆顶输出的N个堆的最大值中的最大值，即全局最大值。
如图5所示的单个排序模块500，以第k个模块为例，包含第k堆模块(heapk)520和对应的缓冲器模块(bufferk)510。缓冲器模块510包含控制逻辑模块(Ck)540、多路选择器模块(MUXk)530和先入先出模块(FIFOk)550等。多路选择器530分别接收本排序模块对应的数据源Ik，和FIFOk 550的输出WB′k-1。FIFOk 550接收上一个排序模块给本排序模块的写回信号WBk-1，并输出缓冲过的数据WB′k-1。多路选择器530的选择信号Sk来自控制逻辑模块540的输出。多路选择器530的输出DIk作为第k堆模块(heapk)520的输入，具体的DIk信号又分为数据信号DI_datak和使能信号DI_enk，使能信号DI_enk表示数据信号DI_datak是否有效。第k堆模块(heapk)520的输出为WBk，包含数据信号WB_datak和使能信号WB_enk。控制逻辑模块540的输入是WB′k-1、Ik和Tg，输出为多路选择器530的选择信号Sk。
以第k个堆的缓冲器510中的控制逻辑(Ck)540为例，其图5中的控制逻辑的工作流程600可以如图6所示。在一些实施例中，控制逻辑模块540可以每两个周期开始一次判断。如图6所示，在框601，判断FIFOk是否有数据输出，如果有数据输出，则进入框602，如果没有数据输出，则进入框603。此判断的目的在于，因为全局最大值模块输出的Tg相对输入会存在几个周期的延迟，WBk-1输入到缓冲器中的FIFOk后，直到FIFOk填充满才被读出，这时WB′k-1为多个周期前的输入，相对Tg会延后，有利于控制逻辑能够发挥出较好筛选性能，避免WBk-1在多个堆中传递而不会被筛选掉。在框602，判断FIFOk输出的数据WB′k-1对应的使能WB_en′k-1是否有效，即是否为真(true)，有效(即为真)则进入框604，无效(即为假)则进入框606。在框604，判断WB_data′k-1是否小于Tg，如果是则进入框605，否则进入框606。在框605，输出选择信号Sk使多选器MUXk选择WB′k-1作为多选器MUXk的输出，如上文描述DIk信号又分为数据信号DI_datak和使能信号DI_enk，对应的使能信号DI_enk为真，DI_datak为WB_data′k-1的数据值，此时数据源Ik不被选择，需要保持数据源Ik。在框606，输出选择信号Sk使多选器MUXk选择数据源Ik作为多选器MUXk的输出，如上文描述DIk信号又分为数据信号DI_datak和使能信号DI_enk，DIk信号的数据信号和使能信号都取数据源Ik的数据信号和使能信号输出，WB′k-1的数据则被忽略。在框603，判断I_enk是否有效，即是否为真，有效则进入框606，无效则进入框607。在框607，读取非空的FIFOk中缓存的其他数据作为DIk，此处的目的是为了在没有外部输入数据时，将FIFOk中并未溢出的数据提取出来，保证FIFOk中所有数据都进入排序，避免堆模块闲置。在另一些可选的实施例中，在提取非空的FIFOk中的数据之后，还可以对该写回数据执行如框602和/或框604中的判断过程，例如与Tg进行比较，再决定是否将该写回数据作为DIk。
以上图4、图5和图6所示的多堆结构400、排序模块500及其控制逻辑的工作流程600相关的实施例仅是为了更加清楚的说明本申请的技术方案而示出的一些示例，并不构成对本申请的限定。在其他实施例中还可以包括更多或更少的模块、结构、流程或步骤，或者各实施例进行组合或拆分，得到更多的实现方式，本申请实施例对此不作限制。
以第k个单排序模块500中的堆模块(heapk)520为例描述的结构可以如图7所示的堆模块700。堆模块700可以包括堆数据和堆控制逻辑。堆数据一般为层次结构，具有堆顶，如果是最大堆则堆顶为堆的最大值，如果是最小堆则堆顶为堆的最小值，本实施例的堆模块是以最大堆为例，求输入数据中的K个最小值。
堆模块700具有输入信号DIk作为堆模块(heapk)520的输入，具体的输入信号DIk又分为数据信号DI_datak和使能信号DI_enk，使能信号DI_enk表示数据信号DI_datak是否有效。堆模块700的输出为WBk，包括数据信号WB_datak和使能信号WB_enk，使能信号WB_enk表示数据信号WB_datak是否有效。另外，堆模块700还输出堆顶Tk给全局最大值模块。
堆模块700中的堆控制逻辑流程800如图8所示。在一些实施例中，堆模块700可以每两个周期开始处理一个数据输入。在框801，判断输入信号DIk对应的使能信号DI_enk是否有效，即是否为真(true)，有效(即为真)则进入框802，无效(即为假)则进入框805。在框802，判断DI_datak是否小于当前堆顶值Tk，如果是则进入框803，否则进入框804。在框803，设置WB_enk为真，DI_datak与当前的堆顶数据Tk进 行替换，DI_datak的值变成新的堆顶数据Tk的值，赋予WB_datak数据的值为刚才被替换出去的堆顶数据Tk的值，同时堆逻辑开始执行堆的堆化操作。所谓堆的堆化操作，是指当堆的堆顶发生变化后为了维护堆的性质，而执行的堆内数据特定的操作。在框804，设置WB_enk为真，堆顶数据Tk保持不变，赋予WB_datak数据的值为输入数据DI_datak的值，同时堆逻辑开始执行堆的堆化操作。在框805，DI_enk为假，输入数据DI_datak无效，设置WB_enk为假，WB_datak数据无效，堆继续完成堆化操作。可以理解的是，进行堆化操作只需要在下一次向单堆结构输入信号之前更新出新的堆顶元素即可，无需将堆中每个元素都按顺序排序好。可以理解的是，堆模块会将WB_enk和WB_datak发送给下一个排序模块的缓冲器，由下一个缓冲器的控制逻辑决定保留还是舍弃该WB_datak。
需要说明的是实现如图7和图8中所述的Top-K排序功能并不一定需要由堆这种数据结构实现，上述实施例中以堆作为示例进行了说明，但是Top-K模块并不仅限于堆结构来实现，其他可以实现类似的Top-K排序功能的任何结构或模块都在本公开的保护范围之内。例如，框803中当前堆顶可选地为其他备选数据结构中多个数据的最大值，框804中，可选地为替换出其他备选数据结构中多个数据的最大值。
在一些实施例中，单个堆每两个周期处理一个数据，如流程800，对应的单个缓冲器每两个周期发生一次控制逻辑的判断流程，如流程600。因此对于包括N个排序模块的多堆结构400，N个排序模块可以以一个迭代周期并行执行排序活动，N个缓冲器、N个堆可以分别并行处理数据。在一个示例中，对于单个排序模块，一个迭代周期可以包括两个时钟周期(非限制性的，也可以是四个时钟周期，具体可以根据实际情况设定)，在一个时钟周期内，缓冲器选择并向堆输出输入数据DIk，在下一个周期里，堆模块对输入数据DIk进行数据处理，并向下一个排序模块的FIFO输出WBk。
此外，可以理解的是，在一些实施例中，多堆结构开始工作后，在没有数据输入时，所有堆的输入使能信号无效，所有堆都不工作。当有数据输入时，向所有缓冲器输入数据，由于此时所有缓冲器中FIFO为空，直接选择外部输入数据作为堆的输入。堆heapk接收数据进行处理后向下一个堆heapk+1的缓冲器输出写回数据。在输入外部数据多个周期后，直到缓冲器bufferk中的FIFO被填满，bufferk开始按照图6中的控制逻辑流程600进行工作，筛选堆的写回数据并选择输入数据到堆heapk。根据以上实施例，外部的输入数据可以在相邻的堆之间单向传递，直至进入某个堆中，或者被扔掉。全局最大值模块产生的全局最大值Tg可以约束所有堆中的值，保证堆之间存在着相应的阈值上限，使得所有堆中存放的数据满足排序的要求。当所有数据输入完成后，bufferk继续工作直到相应bufferk中的FIFO被清空，最终完成排序。
根据本公开的上述一个或多个实施例所实现的用于排序的多输入的多堆结构，数据平均吞吐量提高，并且具有接近线性的扩放性的增益效果。本公开的实施例通过利用堆内数据的有序性，并且多个堆之间通过传递数据以及全局最值约束，减少了排序时所需比较的次数，使得硬件处理资源的消耗较少，并且基于堆结构较好的利用了片上存储资源，提高了不同片上资源的利用效率。此外，本方案排序的比较次数较少。例如，对于并行度为N、需要求取K个靠前值的实现Top-K排序的多堆结构，其中每个堆的大小为层数为即每个堆每周期会进行次比较，同时堆与堆之间传递数据，每周期比较N次，因此总的比较次数为
图4至图8示出的实施例是本申请提供的一种实现方式，仅仅是为了更加清楚的说明本申请的技术方案，并不对本申请的其他实施例构成限定。实施本公开的上述一些实施例中的针对大规模数据的用于排序的可扩展高并行的多堆结构，其并行度可以增加到N，实现了更高的数据吞吐量，并且对于求取M个Top数据的多堆结构，其中每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少处理时间，更快的得到靠前的Top数据。
此可扩展的环形多输入的多堆结构，其整体结构可以包含N个单堆、N个缓冲器、相应的FIFO以及一个全局最大/小值模块，N个缓冲器包含FIFO、多路器MUX以及相应的控制逻辑C。每个堆接收来自身的缓冲器模块的输出，并且自身写回数据连接到下一个堆的缓冲器，还将堆顶输入到全局最大/小值模块。缓冲器接收来自上一个堆的写回数据以及外部数据源，并且接收全局最大/小值，并向相应的堆输出数据。所有的堆与缓冲器交替相连构成一个环形结构。由于缓冲器隔离了相邻的前一个堆的数据输出，所有堆可以同步工作或者异步工作。输入数据通过堆的写回值以及缓冲器，在堆间单向传递直至进入某个堆或者被全局最大/小值模块扔掉，全局最大/小值模块可以约束数据的传递，使得每个堆中存储的数据不会被浪费。因此，本公开的一些实施例的多堆结构可以利用堆内数据排布的有序性质，并通过堆之间的串联，以及全局最大/小值的约束，减少了排序所需的比较次数，节省处理资源的消耗以及节省了存储资源，并提高了吞吐量，可以实现更大数据量的求取靠前数据的排序以及多个多堆结构的并发工作。
本公开的一些实施例还提供了一种针对双周期单输入交替的双堆结构，这里具体以最大堆为例进行说明，最小堆的情况反之亦然。该双堆结构可以包括两个堆结构、两个缓冲器以及数据源。其中两个堆为正常的双周期堆结构heapi，包括输入数据DIi与写回数据WBi以及堆顶数据Ti的接口，其中i＝0,1，分别代表两个堆。每个堆结构可每两个周期处理一个输入数据DIi，并且在输入数据有效的一个周期后返回一个写回数据WBi。在一些实施例中，输入数据DIi可以包括元组DI_Datai以及使能信号DI_eni，写回数据WBi可以包括元组WB_Datai以及使能信号WB_eni，其中元组可以表示为(ID,Value)，包含用于比较的数值Value以及用于对应数值的编号ID或者相应的键值等。在一些实施例中，输入数据DIi的使能信号DI_eni为真表示输入数据DIi有效，在输入数据DIi有效一周期后输出写回数据WBi，并伴随着写回数据WBi的使能信号WB_eni有效。在一些实施例中，当输入数据DIi大于等于堆顶Ti时，写回数据WBi为DIi，堆顶保持不变。否则，写回数据WBi为Ti，堆顶被替换为DIi。
该双堆结构还包括两个缓冲器，第i个缓冲器bufferi可以包括先入先出队列FIFOi和多选器MUXi以及相应的控制逻辑Ci，其中i＝0,1。FIFOi用于缓冲来自另外一个堆的写回数据WBi-1。当FIFOi被填满到一定程度后，可以输出被读取数据WB′i-1。多选器MUXi其中一个输入连接着对应的数据源I，另一个输入连着FIFOi的写回数据WB′i-1。多选器MUXi的选择信号Si由控制逻辑Ci给出。多选器MUXi的选择输出连着堆heapi的输入数据DIi。在一些实施例中，对于多选器控制逻辑Ci，当FIFOi的输出数据WB′i-1有效时，比较WB′i-1和当前堆的堆顶Ti，当WB′i-1的值小于Ti时，选择FIFOi的输出数据WB′i-1作为多选器的输出。当FIFOi的输出数据WB′i-1无效时，如果数据源Ii有效则选择数据源Ii作为多选器的输出，如果数据源Ii无效可以选择读取非空的FIFOi中的另一数据作为多选器的输出。在一些实施例中，因为堆每两个周期处理一个数据，所以缓冲器可以相应的每两个周期发生一次判断。
该双堆结构还可以包括数据源I，数据源I可以使用先入先出存储器等实现，用于缓冲外部信号的输入数据元组并提供相应的输入数据使能。在一些实施例中，数据源I可以轮流为双堆结构提供输入数据，使能信号对两个缓冲器交替有效。当数据源为空时，两个堆的输入数据使能信号无效，两个堆不工作。在初始时，数据源I向buffer0提供输入数据并且使能信号有效，控制逻辑C0选择数据源I作为堆的输入数据DI0。在一个周期后堆heap0向buffer1输出写回数据WB0。由于buffer1中的FIFO1未被填充到可以输出数据，控制逻辑C1选择数据源I向buffer1提供的使能信号有效的输入数据作为堆的输入数据DI1。一个周期后，堆heap1向buffer0输出写回数据WB1，由于buffer0中的FIFO0未被填充到可以输出数据，控制逻辑C0选择有效的数据源I作为堆的输入数据DI0。如此重复直到多个周期后，有一个缓冲器中的FIFO被填充到可以输出数据，例如为buffer0，相应的控制逻辑C0进行判断，如果FIFO0输出数据WB′1小于堆heap0的堆顶T0，则多选器选择FIFO0的输出WB′1作为堆heap0的输入数据DI0。如果FIFO0输出数据WB′1大于堆heap0的堆顶T0，则判断数据源I是否有效，如果数据源I有效则选择数据源作为堆heap0的输入数据DI0，如果数据源I无效则可以读取非空的FIFO0中的其他缓存数据作为堆heap0的输入数据DI0。堆heap0在数据输入后的一个周期输出写回数据WB0并将WB0发送给buffer1，相应的控制逻辑C1可以执行与上述控制逻辑C0类似的判断过程。之后，双堆结构交替输入数据并完成排序。当数据源I的使能信号无效时，控制逻辑可以读取FIFO中的数据，直到FIFO为空。当数据源I输入完成且所有缓冲器中的FIFO为空时，待堆执行完所有排序操作后，最后输出的这两个堆中所包括的元素的集合即为所求取的M个最小值，排序完成。实现该双堆结构，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
示例性的，可以结合参考图9至图11示出的本公开提供的针对双周期单输入交替的双堆结构的一些实施例来更好的理解。以最大堆为例，实施例中针对双周期单输入交替的双堆结构可以包括两个堆结构、两个缓冲器以及一个数据源输入。参考图9示出的双堆结构900中，双堆结构中的两个堆heap0和heap1通过缓冲器buffer0和buffer1相连，也构成一个环形的循环结构，但整体只有一个单一的输入。其中每个缓冲器模块包含了多选器以及控制逻辑。可以看出，本质上，双堆结构900是多堆结构400的N＝2时的一个特殊的实例。其中，数据源I分别连接到缓冲器0(buffer0)和缓冲器1(buffer1)，用于将外部数据输入进入堆结构。该数据源I可以使向buffer0和buffer1的输入信号交替有效，例如第一个周期使能向buffer0的输入信号有效，向buffer1的输入信号无效，第二个周期使能向buffer1的输入信号有效，向buffer0的输入信号无效，第三个周期又使能向buffer0的输入信号有效，向buffer1的输入信号无效，如此循环。buffer0可以接收heap1的写回数据WB1、heap0的堆顶数据T0和数据源I，并根据控制逻辑C0进行判断，选择输出一个数据信号作为heap0的输入数据DI0。heap0接收输入数据DI0，在一个周期后，heap0向 buffer1输出写回信号WB0，以及向buffer0输出堆顶数据T0。类似地，buffer1可以接收heap0的写回数据WB0、heap1的堆顶数据T1和数据源I，并根据控制逻辑C1进行判断，选择输出一个数据信号作为heap1的输入数据DI1。heap1接收输入数据DI1，在一个周期后，heap1向buffer0输出写回信号WB1，以及向buffer1输出堆顶数据T1。实现该双堆结构900，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
双堆结构900中的单个排序模块1000结构如图10所示，以堆0及缓冲器0组成的排序模块，即堆heap01020及其buffer0 1010为例示意。堆heap0 1020的写回数据WB0连接buffer1以及控制逻辑C1，堆heap01020的输入数据DI0与多选器(MUX0)1030的输出相连，写回信号WB1作为缓冲器1010内部先入先出队列(FIFO0)1050的输入，FIFO0 1050的输出WB′1作为多选器MUX0 1030的一个输入。buffer0 1010与数据源输入数据I相连，数据源I连接到内部多选器1030，作为多选器1030的一个输入，并且使能信号I_en连接到控制逻辑C0 1040。控制逻辑(C0)1040接收WB′1、I_en以及heap0的堆顶T0，并进行判断，选择输出一个数据信号作为heap0的输入数据DI0。heap0接收输入数据DI0，在一个周期后，堆heap0 1020向buffer1输出写回数据WB0，以及向控制逻辑(C0)1040输出堆顶数据T0。堆heap1及其buffer1的连接关系与双堆结构900所示的堆heap0及其buffer0的连接关系类似。
在一些实施例中，堆heap0的缓冲器buffer0的控制逻辑C0的判断流程1100可以如图11所示。在一些实施例中，控制逻辑C0可以每两个周期开始一次判断。如图11所示，在框1101，判断FIFO0是否有数据输出，如果有数据输出，则进入框1102，如果没有数据输出，则进入框1103。此判断的目的在于，因为输出的堆顶T0相对输入会存在几个周期的延迟，WB1输入到缓冲器中的FIFO0后，直到FIFO0填充满才被读出，这时WB′1为多个周期前的输入，相对T0会延后，有利于控制逻辑能够发挥出较好筛选性能，避免WB1在双堆中传递而不会被筛选掉。在框1102，判断FIFO0输出的数据WB′1对应的使能WB_en′1是否有效，即是否为真(true)，有效(即为真)则进入框1104，无效(即为假)则进入框1106。在框1104，判断WB_data′1是否小于T0，如果是则进入框1105，否则进入框1106。在框1105，输出选择信号S0使多选器MUX0选择WB′1作为多选器MUX0的输出，如上文描述DI0信号又分为数据信号DI_data0和使能信号DI_en0，对应的使能信号DI_en0为真，DI_data0为WB_data′1的数据值，此时数据源I不被选择，需要保持数据源I。在框1106，输出选择信号S0使多选器MUX0选择数据源I作为多选器MUX0的输出，如上文描述DI0信号又分为数据信号DI_data0和使能信号DI_en0，DI0信号的数据信号和使能信号都取数据源I的数据信号和使能信号输出，WB′1的数据则被忽略。在框1103，判断I_en是否有效，即是否为真，有效则进入框1106，无效则进入框1107。在框1107，读取非空的FIFO0中缓存的数据作为DI0，此处的目的是为了在没有外部输入数据时，将FIFO0中并未溢出的数据提取出来，保证FIFO0中所有数据都进入排序，避免堆模块闲置。在另一些可选的实施例中，在提取非空的FIFO0中的数据之后，还可以对该写回数据执行如框1102和/或框1104中的判断过程，例如与T0进行比较，再决定是否将该写回数据作为DI0。
以第0个堆模块(heap0)1020为例描述的结构可以如图7所示的堆模块700。堆模块可以包括堆数据和堆控制逻辑。堆数据一般为层次结构，具有堆顶，如果是最大堆则堆顶为堆的最大值，如果是最小堆则堆顶为堆的最小值，本实施例的堆模块是以最大堆为例，求输入数据中的K个最小值。堆模块heap0具有输入信号DI0作为堆模块heap0的输入，具体的输入信号DI0又分为数据信号DI_data0和使能信号DI_en0，使能信号DI_en0表示数据信号DI_data0是否有效。堆模块heap0的输出为WB0，包括数据信号WB_data0和使能信号WB_en0，使能信号WB_en0表示数据信号WB_data0是否有效。另外，堆模块heap0还输出堆顶T0给控制逻辑C0。
堆模块heap0中的堆控制逻辑流程1200如图12所示。在一些实施例中，堆模块heap0可以每两个周期开始处理一个数据输入。在框1201，判断输入信号DI0对应的使能信号DI_en0是否有效，即是否为真(true)，有效(即为真)则进入框1202，无效(即为假)则进入框1205。在框1202，判断DI_data0是否小于当前堆顶值T0，如果是则进入框1203，否则进入框1204。在框1203，设置WB_en0为真，DI_data0与当前的堆顶数据T0进行替换，DI_data0的值变成新的堆顶数据T0的值，赋予WB_data0数据的值为刚才被替换出去的堆顶数据T0的值，同时堆逻辑开始执行堆的堆化操作。所谓堆的堆化操作，是指当堆的堆顶发生变化后为了维护堆的性质，而执行的堆内数据特定的操作。在框1204，设置WB_en0为真，堆顶数据T0保持不变，赋予WB_data0数据的值为输入数据DI_data0的值，同时堆逻辑开始执行堆的堆化操作。在框1205，DI_en0为假，输入数据DI_data0无效，设置WB_en0为假，WB_data0数据无效，堆继续完成堆化操作。可以理解的是，进行堆化操作只需要在下一次向堆结构输入信号之前更新出新的堆顶元素即可，无需将堆中每个元 素都按顺序排序好。可以理解的是，堆模块会将WB_en0和WB_data0发送给下一个排序模块的缓冲器，由下一个缓冲器的控制逻辑决定保留还是舍弃该WB_data0。
需要说明的是如图12中所述的功能并不一定需要由堆这种数据结构实现，只要实现类似的功能，均能实现。例如，框1203中当前堆顶可选地为其他备选数据结构中多个数据的最大值，框1204中，可选地为替换出其他备选数据结构中多个数据的最大值。
在一些实施例中，单个堆每两个周期处理一个数据，如流程1200，对应的单个缓冲器每两个周期发生一次控制逻辑的判断流程，如流程1100。因此对于包括两个排序模块的双堆结构900，两个排序模块可以以一个迭代周期并行执行排序活动，两个缓冲器、两个堆可以分别并行处理数据。在一个示例中，对于单个排序模块，一个迭代周期可以包括两个时钟周期(非限制性的，也可以是四个时钟周期，具体可以根据实际情况设定)，在一个时钟周期内，缓冲器选择并向堆输出输入数据DI，在下一个周期里，堆模块对输入数据DI进行数据处理，并向下一个排序模块的FIFO输出写回数据WB。
此外，可以理解的是，在一些实施例中，双堆结构开始工作后，在没有数据输入时，两个堆的输入使能信号无效，两个堆都不工作。当有数据输入时，两个堆交替有输入数据。在一些实施例中，第一个周期，数据源I向buffer0输入数据，并且该输入信号的使能信号有效，因为此时FIFO0为空，所以直接将I作为heap0的DI0；第二个周期，heap0向buffer1输出写回数据WB0，数据源I向buffer1输入数据，并且该输入信号的使能信号有效，由于FIFO1为空，直接将I作为heap1的输入DI1；第三个周期，heap1向buffer0输出写回数据WB1，因为此时FIFO0非满，直接将I作为heap0的DI0；第四个周期，heap0向buffer1输出写回数据WB0，由于FIFO1非满，直接将I作为heap1的输入DI1。如此输入数据多个周期，直到buffer0中的FIFO0被填满，控制逻辑C0根据FIFO0的输出WB′1和heap0堆顶T0进行判断，如果WB′1有效且小于T0，则控制多选器MUX0的选择信号S0选择WB′1输入到heap0，否则，判断I的使能I_en是否有效，如果有效选择I输入到heap0，否则读取非空的FIFO0中缓存的其他写回数据WB′1，将该WB′1输入到heap0，或者将该WB′1输入到多选器MUX0。之后两个缓冲器根据相应的FIFO输出和数据源输入I，重复以上操作，向堆中输入数据。当所有双堆结构的外部数据输入完毕，并且所有FIFO被清空，排序完成。
因为对于最大堆来说，一个堆的写回数据，其大小必定大于当前的堆顶，如果写回值大于另外一个堆的堆顶，必然不会进入到另外一个堆中，通过简单的控制逻辑，完成堆两个之间的数据传递，并且共用一个数据输入，其接口与单个堆结构相同。相比于多堆结构400，双堆结构900的硬件结构更简单，吞吐量近似，所消耗的资源更少，并且也可以作为一个单输入的堆来使用。
图9至图12示出的实施例是本申请提供的一种实现方式，仅仅是为了更加清楚的说明本申请的技术方案，并不对本申请的其他实施例构成限定。实施本公开的上述实施例中的针对双周期单输入交替的双堆结构，两个堆交替工作，并且相互写回数据，通过两个缓冲器以及相应的控制逻辑使得两个堆结构能够交替从一个数据输入以及另一个堆的写回数据中得到数据输入，保持堆的数据排布有序的性质，以较低的处理资源开销提高吞吐量到了接近传统堆结构的上限，并且具有与传统的堆硬件结构相同的功能抽象以及接口，能够轻易的替换到已有的堆结构硬件设计中。
下面介绍本申请的实施例提供的电子设备1300的结构。
本申请实施例对电子设备1300的具体类型不做限定。示例性的，实施本公开的一个或多个实施例的电子设备1300可以是智能手机(mobile phone)、平板电脑(Pad)、个人计算机(personal computer，PC)、台式电脑、便携电脑、桌面型计算机、膝上型计算机、手持计算机、笔记本电脑、上网本、游戏机、电子会议白板、智慧屏(智能电视)、无人机、蜂窝电话、个人数字助理(personal digital assistant，PDA)、增强现实(augmented reality，AR)设备、虚拟现实(virtual reality，VR)设备、人工智能(artificial intelligence，AI)设备、可穿戴式设备、车机(车载设备)、物联网(internet of things，IOT)设备、以及工业控制(industrial control)中的设备、无人驾驶(self driving)中的设备、远程医疗(remote medical)中的设备、智能电网(smart grid)中的设备、运输安全(transportation safety)中的设备、智慧城市(smart city)中的设备、智慧家庭(smart home)中的设备或者其他类型的电子设备等等。电子设备1300可以搭载各种类型的操作系统，本实施例对此不作限制。
图13示例性示出了本申请实施例提供的电子设备1300的结构。
如图13所示，电子设备1300可包括：一个或多个终端设备处理器1310、通信接口1320、存储器1330等，这些部件可通过总线1340或者其他方式连接，以通过总线1340连接为例。其中：
处理器1310是电子设备1300的控制中心，通过各种接口和线路连接电子设备1300的各个部分，可 用于读取和执行计算机可读指令。具体的，处理器1310可用于调用存储于存储器1330中的程序或数据，并执行该程序包含的指令，实现电子设备1300的各种功能。在一些实施例中，处理器1310可包括一个或多个处理单元。处理器1310还可以集成应用处理器和调制解调处理器。其中，应用处理器主要用于处理操作系统、用户界面和应用程序等；调制解调处理器主要用于处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器1310中。在本申请的一些实施例中，处理器可用于执行本申请上述任一实施例中提供的方法和功能。
存储器1330与处理器1310耦合，用于存储各种软件程序和/或多组指令。具体地，存储器1330可包括高速随机存取的存储器，并且也可包括非易失性存储器，例如一个或多个磁盘存储设备、闪存设备或其他非易失性固态存储设备。存储器1330可以存储操作系统，例如嵌入式操作系统。存储器1330还可以存储网络通信程序，该网络通信程序可用于与一个或多个附加设备，一个或多个终端设备，一个或多个网络设备进行通信。存储器1330还可以存储终端设备接口程序，该终端设备接口程序可以通过图形化的操作界面将应用程序的内容形象逼真的显示出来，并通过菜单、对话框以及按键等输入控件接收终端设备对应用程序的控制操作。在本申请的一些实施例中，存储器1330可用于存储本申请的一个或多个实施例提供的方法在电子设备1300侧的实现程序。
电子设备1300还可包括输入输出模块。输入输出模块可用于实现电子设备1300和其他终端设备/外部环境之间的交互，可主要包括音频输入输出模块、按键输入模块以及显示器等。具体地，输入输出模块还可包括：摄像头、触摸屏以及传感器等等。其中，输入输出模块均通过接口与处理器1310进行通信。
需要说明的是，图13所示的电子设备1300仅仅是本申请实施例的一种实现方式，实际应用中，电子设备1300还可以包括更多或更少的部件，可以组合两个或多个的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件、软件或软件和硬件的组合实现，在此不作限定。
以上实施例仅仅是为了更加清楚的说明本申请的技术方案，并不构成对本申请的限定。在其他实施例中还可以包括更多或更少的流程或步骤，或者各实施例进行组合或拆分，得到更多的实现方式，本申请实施例对此不作限制。
下面介绍本申请实施例提供的一种信号处理装置。该信号处理装置可包括：输入模块，被配置为为向多排序模块输入多个信号，多排序模块包括环形串联的N个排序模块，N个排序模块中的每个排序模块包括具有K个元素的Top-K模块，多排序模块包括第一排序模块和第二排序模块，第一排序模块包括第一Top-K模块，第一排序模块输出的被第一Top-K模块舍弃的信号或被替换出的第一Top-K模块的顶端元素作为第二排序模块的输入信号。处理模块，被配置为基于多个信号，更新多排序模块中多个Top-K模块中的元素。以及输出模块，被配置为获得多个信号中数据排序靠前的M个数据，其中M的值为N与K的乘积值，N、K、M为正整数。
实施本实施例的信号处理装置，能够改进系统性能，提高信号处理效率，节省存储资源和处理资源，减少数据存储量、数据传输量、数据处理量和处理时间。
在一些实施例中，在一些实施例中，多排序模块为多堆结构，Top-K模块为堆，多堆结构包括多个堆，多个堆中的每个堆中包括K个元素，多堆结构输出M个数据，M个数据为多堆结构的多个堆中的所有元素的集合。多堆结构的工作并行度可以增加到N，实现了更高的数据吞吐量，提高信号处理效率，并且多堆结构中的每个堆的大小减小为M/N，提高了单个堆的性能，可以节省存储资源、计算资源和处理资源，以及减少数据存储量、数据传输量、数据处理量和处理时间。
在一些实施例中，如果堆为最大堆，那么M个数据为多个信号中排序数据最小的前M个数据，最大堆的堆顶元素为最大堆中数据最大的元素；如果堆为最小堆，那么M个数据为多个信号中排序数据最大的前M个数据，最小堆的堆顶元素为最小堆中数据最小的元素。最大堆有助于筛选最小值，最小堆有助于筛选最大值。
在一些实施例中，第一排序模块中包括第一缓冲器和第一Top-K模块，第二排序模块中包括第二缓冲器和第二Top-K模块，第一排序模块的第一缓冲器的输出作为第一排序模块的第一Top-K模块的输入，第一排序模块的第一Top-K模块的输出作为第二排序模块的第二缓冲器的输入，第二排序模块的第二缓冲器的输出作为第二排序模块的第二Top-K模块的输入。各个排序模块之间的缓冲器与Top-K模块交替连接以及多个排序模块环形串联的结构可以提高处理效率。例如，该多排序模块的具体结构可以结合参考图4所示的示例多堆结构400或者图9所示的双堆结构900，单个排序模块的具体结构可以结合参考图5所示的示例排序模块500或者图10所示的排序模块1000，这里不再赘述。
在一些实施例中，多个信号包括第一外部信号和第二外部信号，第一外部信号为第一排序模块的输入，第二外部信号为第二排序模块的输入，并且第一排序模块用于接收第一外部信号，第一排序模块还用于基于第一外部信号获得第一写回信号，第一排序模块还用于向第二排序模块发送第一写回信号。第二排序模块用于接收第二外部信号，第二排序模块还用于接收第一写回信号，第二排序模块还用于基于第二外部信号和/或第一写回信号获得第二写回信号，第二排序模块还用于向第三排序模块发送第二写回信号。第一排序模块与第二排序模块串联可以提高处理效率，第一排序模块不需要的数据可以由第二排序模块继续处理，避免重复输入和处理。
在一些实施例中，第一缓冲器中包括第一先入先出队列、第一控制逻辑模块和第一多选器，第一多选器用于接收第一外部信号，第一先入先出队列用于多次接收并缓存多个写回信号，第一先入先出队列还用于在被多个写回信号填满后输出第一缓存信号，以及第二缓冲器中包括第二先入先出队列、第二控制逻辑模块和第二多选器，第二多选器用于接收第二外部信号，第二先入先出队列用于多次接收并缓存第一排序模块的第一Top-K模块输出的多个写回信号，多个写回信号包括第一写回信号，第二先入先出队列还用于在被多个写回信号填满后输出第二缓存信号。控制逻辑和多选器用于基于先入先出队列输出的缓存信号、输入的外部信号和全局堆顶最值来选择进入堆的输入信号。先入先出队列用于缓存上个排序模块输出的写回数据。设置该先入先出队列缓存写回数据的目的是由于全局最值模块输出的堆顶值相对输入信号会存在几个周期的延迟，于是写回信号输入到缓冲器中的先入先出队列后，直到先入先出队列填充满才被读取，这时的缓存信号为多个周期前的输入，相对全局堆顶最值会延后，有利于控制逻辑能够发挥出较好筛选性能，避免写回信号在多个堆中传递而不会被筛选掉。
在一些实施例中，第二控制逻辑模块还用于基于第二外部信号和/或第二缓存信号确定第二输入信号，第二多选器还用于向第二Top-K模块输出第二输入信号，第二Top-K模块用于接收来自于第二多选器的第二输入信号，第二Top-K模块还用于基于第二输入信号获得第二写回信号。以及第二Top-K模块还用于向第三排序模块的第三缓冲器发送第二写回信号。Top-K模块与缓冲器交替相连，可以提高信号处理效率。
在一些实施例中，第二控制逻辑模块用于执行以下判断逻辑：判断第二先入先出队列是否输出第二缓存信号。如果第二先入先出队列输出了第二缓存信号，那么判断第二缓存信号是否有效。如果第二缓存信号有效，则将第二缓存信号的数据与全局顶端最值进行比较。如果第二缓存信号的数据未超过全局顶端最值，则第二控制逻辑模块确定第二缓存信号作为第二输入信号，如果第二缓存信号的数据超过或等于全局顶端最值，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。以及如果第二缓存信号无效，则第二控制逻辑模块确定第二外部信号作为第二输入信号，并且第二缓存信号被舍弃。通过多个堆之间传递数据以及全局最值(最大值或最小值)的约束，可以减少排序时所需比较的次数，节省处理资源的消耗。此外，基于该多堆结构可以较好的利用了高速缓存器等片上存储资源，提高了不同片上资源的利用效率。例如，在图5中，单堆模块的堆顶最大值输出Tk，表示本排序模块中当前堆结构的堆顶。信号Tg表示从N个堆顶输入获取的最值，即全局最值(又可称为全局堆顶最值)。
在一些实施例中，第二控制逻辑模块还用于执行以下判断逻辑：如果第二先入先出队列没有输出第二缓存信号，那么判断第二外部信号是否有效。如果第二外部信号有效，则第二控制逻辑模块确定第二外部信号作为第二输入信号。以及如果第二外部信号无效，则第二控制逻辑模块读取非空的第二先入先出队列中缓存的第三缓存信号作为第二输入信号。即先入先出队列中溢出的缓存信号优先于外部信号被处理。当先入先出队列中没有溢出的缓存信号时，将有效的外部信号作为堆的输入信号，如果外部信号无效，为了保证FIFO中的所有数据都进入排序，避免堆模块闲置，可以读取非空的先入先出队列中未溢出的缓存的写回信号作为堆的输入信号。关于第二控制逻辑模块执行的判断逻辑可以结合参考图6所示的控制逻辑的工作流程600或者图11所示的控制逻辑的工作流程1100的实施例进行理解，此处不再赘述。
在一些实施例中，第一写回信号包括第一写回信号的数据和第一写回使能信号，第一写回使能信号指示第一写回信号是否有效。第二外部信号包括第二外部信号的数据和第二外部使能信号，第二外部使能信号指示第二外部信号是否有效。第二缓存信号包括第二缓存信号的数据和第二缓存使能信号，第二缓存使能信号指示第二缓存信号是否有效。使用写回使能信号和外部使能信号可以更方便地控制信号的输入。
在一些实施例中，Top-K模块为最大堆，全局顶端最值为多个最大堆的堆顶元素的数据之中的最大值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据小于最大值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据大于或等于最大值。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。在一些实施例中，Top-K模块为最小堆，全局顶端最值为多个最小堆的 堆顶元素的数据之中的最小值，第二缓存信号的数据未超过全局顶端最值，包括：第二缓存信号的数据大于最小值。第二缓存信号的数据超过或等于全局顶端最值，包括：第二缓存信号的数据小于或等于最小值。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
在一些实施例中，第二Top-K模块用于执行以下判断逻辑：第二Top-K模块基于第二输入信号获得第二写回信号，包括：判断第二输入信号是否有效，如果第二输入信号有效，则将第二输入信号的数据与第二Top-K模块的当前的顶端元素的数据进行比较。如果第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据替换掉第二Top-K模块的当前顶端元素的数据以成为第二Top-K模块中新的元素，以及将被替换出的第二Top-K模块的当前顶端元素的数据作为第二写回信号的数据，并且使能第二写回信号有效。以及如果第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号有效。通过利用Top-K模块内数据的有序性以及Top-K模块顶端数据的约束，将本Top-K模块不需要的数据传递给下一个排序模块处理或者及时丢弃，可以减少排序时所需比较的次数，节省处理资源和存储资源。在一些实施例中，第二Top-K模块还用于执行以下判断逻辑：如果第二输入信号无效，则将第二输入信号的数据作为第二写回信号的数据，并且使能第二写回信号无效。被确定无用的数据可以发送给下一个排序模块的FIFO，由下一个排序模块的控制逻辑来决策丢弃该数据。
在一些实施例中，第二Top-K模块还用于更新第二Top-K模块的新的顶端元素，例如第二Top-K模块可以是堆结构，该堆结构可以执行堆化操作以更新堆结构的新的堆顶元素，堆化操作指的是对堆中的元素进行排序更新。第二Top-K模块还用于将第二Top-K模块的顶端元素发送给全局最值模块。全局最值模块用于获取多个Top-K模块的顶端元素，全局最值模块还用于选出多个Top-K模块的顶端元素的数据之中的最值，全局最值模块还用于将最值发送给多个缓冲器中的控制逻辑模块。由于被替换进入Top-K模块的元素不一定是Top-K模块内最值，所以在下一次输入信号输入堆之前，Top-K模块需要更新出新的顶端元素，以保证下次处理的准确性。关于第二Top-K模块的结构以及执行的判断逻辑可以结合参考图7-图8所示的堆模块700以及堆控制逻辑的工作流程800或者图12所示的控制逻辑的工作流程1200的实施例进行理解，此处不再赘述。
在一些实施例中，第二Top-K模块为最大堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于最大堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于或等于最大堆的当前堆顶元素的数据。最大堆的结构能够帮助求出多个输入数据中预定数目的最小值。在一些实施例中，第二Top-K模块为最小堆，第二输入信号的数据未超过第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据大于最小堆的当前堆顶元素的数据。第二输入信号的数据超过或等于第二Top-K模块的当前顶端元素的数据，包括：第二输入信号的数据小于或等于最小堆的当前堆顶元素的数据。最小堆的结构能够帮助求出多个输入数据中预定数目的最大值。
在一些实施例中，在第一时间周期内，第二缓冲器基于第二外部信号和/或第二缓存信号确定第二输入信号，以及在第二时间周期内，第二Top-K模块基于第二输入信号获得第二写回信号。在一个迭代周期内，一个排序模块可以完整的完成一次处理工作，一个迭代周期可以分成两个时间周期，例如第一时间周期和第二时间周期。在一些实施例中，第一时间周期与第二时间周期的时间长度相等。缓冲器判断选择进入堆的数据的处理周期与堆处理输入数据并输出写回数据的处理周期交替地执行，每个排序模块可以并行处理数据，这能够提高处理效率，缩减等待时间和处理时间，充分利用处理资源。
需要说明的是，以上实施例描述的信号处理装置仅仅是为了更加清楚的说明本申请的技术方案的一种实现方式，并不构成对本申请其他实施例的限定，实际应用中，不限定该信号处理装置的各个功能模块的类型、数量和关联关系。在一些实施例中，该信号处理装置中可以包括更多或更少的功能模块等。该信号处理装置中的各个功能模块可以通过软件、硬件或者两者结合的方式实现。可以理解的，关于该信号处理装置包括的各个功能单元的具体实现可参考本申请其他各实施例中的详细描述，这里不多赘述。
需要说明的是，本申请实施例中对模块或单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时也可以有另外的划分方式。另外，在实施例中的各功能单元可以集成在一个单元中，也可以是单独物理存在，也可以两个或两个以上单元集成为一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现，或者软硬件结合的形式实现。
本申请的实施例还提供了一种芯片，该芯片可以包括输入接口、输出接口和处理电路。在本公开的实 施例中，可以由输入接口和输出接口完成信令或数据的交互，由处理电路完成信令或数据信息的生成以及处理。
本申请的实施例还提供了一种芯片系统，包括处理器，用于支持计算设备以实现上述任一实施例中所涉及的功能。在一种可能的设计中，芯片系统还可以包括存储器，用于存储必要的程序指令和数据，当处理器运行该程序指令时，使得安装该芯片系统的设备实现上述任一实施例中所涉及的方法。示例性地，该芯片系统可以由一个或多个芯片构成，也可以包含芯片和其他分立器件。
本申请的实施例还提供了一种处理器，用于与存储器耦合，存储器存储有指令，当处理器运行所述指令时，使得处理器执行上述任一实施例中涉及的方法和功能。
本申请的实施例还提供了一种计算机可读存储介质，其上存储有计算机指令或程序代码，当处理器运行所述指令或所述程序代码时，使得处理器执行上述任一实施例中涉及的方法和功能。计算机可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。计算机可读介质可以是计算机可读信号介质或计算机可读存储介质。计算机可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。该计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。计算机可读存储介质的更详细示例包括带有一根或多根导线的电气连接、磁性介质(例如，磁盘、软盘、硬盘、磁带、磁存储设备)、光介质(例如光存储设备、DVD)、半导体介质(例如固态硬盘)、随机存储存取器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)，或其任意合适的组合等。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。本申请的实施例还提供了有形地存储在非暂时性计算机可读存储介质上的至少一个计算机程序产品。该计算机程序产品包括一个或多个计算机可执行指令，例如包括在程序模块中的指令，其在目标的真实或虚拟处理器上的设备中执行，以执行上述各实施例中任一实施例中涉及的过程、方法和功能。在计算机上加载和执行该计算机程序指令时，全部或部分地产生按照本申请实施例的流程或功能。该计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行上述实施例中的过程、方法和功能。通常，程序模块包括执行特定任务或实现特定抽象数据类型的例程、程序、库、对象、类、组件、数据结构等。在各种实施例中，可以根据需要在程序模块之间组合或分割程序模块的功能。用于程序模块的机器可执行指令可以在本地或分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质中。
用于实现本公开的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。在本公开的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质、等等。信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
通常，本申请的各种实施例可以以硬件或专用电路、软件、逻辑或其任何组合来实现。一些方面可以用硬件实现，而其他方面可以用固件或软件实现，其可以由控制器，微处理器或其他计算设备执行。虽然本公开的实施例的各个方面被示出并描述为框图，流程图或使用一些其他图示表示，但是应当理解，本文描述的框，装置、系统、技术或方法可以实现为，如非限制性示例，硬件、软件、固件、专用电路或逻辑、通用硬件或控制器或其他计算设备，或其某种组合。
以上已经描述了本公开的各实现，上述说明是示例性的，并非穷尽的，并且也不限于所公开的各实现。在不偏离所说明的各实现的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在很好地解释各实现的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其他普通技术人员能理解本文公开的各个实现方式。
以上的具体实施方式，对本申请实施例的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上仅为本申请实施例的具体实施方式而已，并不用于限定本申请实施例的保护范围，凡在本申请实施例的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请实施例的保护范围之内。
应注意的是，尽管上面分别结合附图描述了本申请的实施例，但是上面的实施例并不是彼此独立的，它们也可以结合以得到其他的实施例。本申请的实施例中的方式、情况、类别以及实施例的划分仅是为了描述的方便，不应构成特别的限定，各种方式、类别、情况以及实施例中的特征在符合逻辑的情况下，可以相互结合。本申请的各实施方式可以任意进行组合，以实现不同的技术效果。本申请的实施例不再对各种结合进行罗列。
此外，尽管在附图中以特定顺序描述了本公开的方法的操作，但是这并非要求或者暗示必须按照该特定顺序来执行这些操作，或是必须执行全部所示的操作才能实现期望的结果。相反，流程图中描绘的步骤可以改变执行顺序。附加地或备选地，可以省略某些步骤，将多个步骤组合为一个步骤执行，和/或将一个步骤分解为多个步骤执行。还应当注意，根据本公开的两个或更多装置的特征和功能可以在一个装置中具体化。反之，上文描述的一个装置的特征和功能可以进一步划分为由多个装置来具体化。
上述实施例中所用，根据上下文，术语“当…时”可以被解释为意思是“如果…”或“在…后”或“响应于确定…”或“响应于检测到…”。类似地，根据上下文，短语“在确定…时”或“如果检测到(所陈述的条件或事件)”可以被解释为意思是“如果确定…”或“响应于确定…”或“在检测到(所陈述的条件或事件)时”或“响应于检测到(所陈述的条件或事件)”。

Claims (22)

  1. 一种信号处理方法，其特征在于，所述方法包括：
    向多排序模块输入多个信号，所述多排序模块包括环形串联的N个排序模块，所述N个排序模块中的每个排序模块包括具有K个元素的Top-K模块，所述多排序模块包括第一排序模块和第二排序模块，所述第一排序模块包括第一Top-K模块，所述第一排序模块输出的被所述第一Top-K模块舍弃的信号或被替换出的所述第一Top-K模块的顶端元素作为所述第二排序模块的输入信号；
    基于所述多个信号，更新所述多排序模块中多个所述Top-K模块中的元素；以及
    获得所述多个信号中数据排序靠前的M个数据，其中M的值为N与K的乘积值，N、K、M为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述第一排序模块中包括第一缓冲器和所述第一Top-K模块，所述第二排序模块中包括第二缓冲器和第二Top-K模块，所述第一排序模块的所述第一缓冲器的输出作为所述第一排序模块的所述第一Top-K模块的输入，所述第一排序模块的所述第一Top-K模块的输出作为所述第二排序模块的所述第二缓冲器的输入，所述第二排序模块的所述第二缓冲器的输出作为所述第二排序模块的所述第二Top-K模块的输入。
  3. 根据权利要求2所述的方法，其特征在于，所述多个信号包括第二外部信号，所述第二外部信号为所述第二排序模块的外部输入信号，并且所述方法还包括：
    所述第二排序模块接收第二外部信号；
    所述第二排序模块接收来自于所述第一排序模块的所述第一写回信号；
    所述第二排序模块根据包括所述第二外部信号、所述第一写回信号和全局顶端最值中的至少一项获得第二写回信号，其中所述全局顶端最值为多个所述Top-K模块的顶端元素之中的最值；
    所述第二排序模块向第三排序模块发送所述第二写回信号。
  4. 根据权利要求3所述的方法，其特征在于，以及所述第二缓冲器中包括第二先入先出队列、第二控制逻辑模块和第二多选器，所述第二多选器用于接收所述第二外部信号，所述第二先入先出队列用于多次接收并缓存所述第一排序模块的所述第一Top-K模块输出的多个写回信号，所述多个写回信号包括所述第一写回信号，所述第二先入先出队列还用于在被所述多个写回信号填满后输出第二缓存信号。
  5. 根据权利要求4所述的方法，其特征在于，所述第二排序模块基于所述第二外部信号和/或所述第一写回信号获得第二写回信号包括：
    所述第二控制逻辑模块基于所述第二外部信号和/或所述第二缓存信号确定第二输入信号；
    所述第二多选器向所述第二Top-K模块输出所述第二输入信号；
    所述第二Top-K模块接收来自于所述第二多选器的所述第二输入信号；
    所述第二Top-K模块基于所述第二输入信号获得所述第二写回信号；以及
    所述第二排序模块向第三排序模块发送所述第二写回信号，包括：
    所述第二Top-K模块向所述第三排序模块的第三缓冲器发送所述第二写回信号。
  6. 根据权利要求5所述的方法，其特征在于，所述第二控制逻辑模块基于所述第二外部信号和/或所述第二缓存信号确定第二输入信号，包括：
    判断所述第二先入先出队列是否输出所述第二缓存信号；
    如果所述第二先入先出队列输出了所述第二缓存信号，那么判断所述第二缓存信号是否有效；
    如果所述第二缓存信号有效，则将所述第二缓存信号的数据与所述全局顶端最值进行比较；
    如果所述第二缓存信号的数据未超过所述全局顶端最值，则所述第二控制逻辑模块确定所述第二缓存信号作为所述第二输入信号；
    如果所述第二缓存信号的数据超过或等于所述全局顶端最值，则所述第二控制逻辑模块确定所述第二外部信号作为所述第二输入信号，并且所述第二缓存信号被舍弃；以及
    如果所述第二缓存信号无效，则所述第二控制逻辑模块确定所述第二外部信号作为所述第二输入信号，并且所述第二缓存信号被舍弃。
  7. 根据权利要求6所述的方法，其特征在于，还包括：
    如果所述第二先入先出队列没有输出所述第二缓存信号，那么判断所述第二外部信号是否有效；
    如果所述第二外部信号有效，则所述第二控制逻辑模块确定所述第二外部信号作为所述第二输入信号； 以及
    如果所述第二外部信号无效，则所述第二控制逻辑模块读取非空的所述第二先入先出队列中缓存的第三缓存信号作为所述第二输入信号。
  8. 根据权利要求4-7任一项所述的方法，其特征在于，其中，所述第一写回信号包括所述第一写回信号的数据和第一写回使能信号，所述第一写回使能信号指示所述第一写回信号是否有效；所述第二外部信号包括所述第二外部信号的数据和第二外部使能信号，所述第二外部使能信号指示所述第二外部信号是否有效；所述第二缓存信号包括所述第二缓存信号的数据和第二缓存使能信号，所述第二缓存使能信号指示所述第二缓存信号是否有效。
  9. 根据权利要求6所述的方法，其特征在于，所述Top-K模块为最大堆，所述全局顶端最值为多个所述最大堆的堆顶元素的数据之中的最大值，
    所述第二缓存信号的数据未超过所述全局顶端最值，包括：
    所述第二缓存信号的数据小于所述最大值；
    所述第二缓存信号的数据超过或等于所述全局顶端最值，包括：
    所述第二缓存信号的数据大于或等于所述最大值。
  10. 根据权利要求6所述的方法，其特征在于，所述Top-K模块为最小堆，所述全局顶端最值为多个所述最小堆的堆顶元素的数据之中的最小值，
    所述第二缓存信号的数据未超过所述全局顶端最值，包括：
    所述第二缓存信号的数据大于所述最小值；
    所述第二缓存信号的数据超过或等于所述全局顶端最值，包括：
    所述第二缓存信号的数据小于或等于所述最小值。
  11. 根据权利要求5所述的方法，其特征在于，所述第二Top-K模块基于所述第二输入信号获得所述第二写回信号，包括：
    判断所述第二输入信号是否有效；
    如果所述第二输入信号有效，则将所述第二输入信号的数据与所述第二Top-K模块的当前的顶端元素的数据进行比较；
    如果所述第二输入信号的数据未超过所述第二Top-K模块的当前顶端元素的数据，则将所述第二输入信号的数据替换掉所述第二Top-K模块的当前顶端元素的数据以成为所述第二Top-K模块中新的元素，以及将被替换出的所述第二Top-K模块的当前顶端元素的数据作为所述第二写回信号的数据，并且使能所述第二写回信号有效；以及
    如果所述第二输入信号的数据超过或等于所述第二Top-K模块的当前顶端元素的数据，则将所述第二输入信号的数据作为所述第二写回信号的数据，并且使能所述第二写回信号有效。
  12. 根据权利要求11所述的方法，其特征在于，还包括：
    如果所述第二输入信号无效，则将所述第二输入信号的数据作为所述第二写回信号的数据，并且使能所述第二写回信号无效。
  13. 根据权利要求11或12所述的方法，其特征在于，所述方法还包括：
    所述第二Top-K模块更新所述第二Top-K模块的新的顶端元素；以及
    所述第二Top-K模块将所述第二Top-K模块的顶端元素发送给全局最值模块，所述全局最值模块用于获取所述多个Top-K模块的顶端元素，所述全局最值模块还用于选出所述多个Top-K模块的顶端元素的数据之中的最值，所述全局最值模块还用于将所述最值发送给多个缓冲器中的控制逻辑模块。
  14. 根据权利要求11所述的方法，其特征在于，所述第二Top-K模块为最大堆，
    所述第二输入信号的数据未超过所述第二Top-K模块的当前顶端元素的数据，包括：
    所述第二输入信号的数据小于所述最大堆的当前堆顶元素的数据；
    所述第二输入信号的数据超过或等于所述第二Top-K模块的当前顶端元素的数据，包括：
    所述第二输入信号的数据大于或等于所述最大堆的当前堆顶元素的数据。
  15. 根据权利要求11所述的方法，其特征在于，所述第二Top-K模块为最小堆，
    所述第二输入信号的数据未超过所述第二Top-K模块的当前顶端元素的数据，包括：
    所述第二输入信号的数据大于所述最小堆的当前堆顶元素的数据；
    所述第二输入信号的数据超过或等于所述第二Top-K模块的当前顶端元素的数据，包括：
    所述第二输入信号的数据小于或等于所述最小堆的当前堆顶元素的数据。
  16. 根据权利要求5所述的方法，其特征在于，包括：
    在第一时间周期内，所述第二缓冲器基于所述第二外部信号和/或所述第二缓存信号确定第二输入信号；以及
    在第二时间周期内，所述第二Top-K模块基于所述第二输入信号获得所述第二写回信号。
  17. 根据权利要求1-16中任一项所述的方法，其特征在于，所述多排序模块为多堆结构，所述Top-K模块为堆，所述多堆结构包括多个所述堆，多个所述堆中的每个所述堆中包括K个元素，所述多堆结构输出所述M个数据，所述M个数据为所述多堆结构的多个所述堆中的所有元素的集合。
  18. 根据权利要求17所述的方法，其特征在于，如果所述堆为最大堆，那么所述M个数据为所述多个信号中排序数据最小的前M个数据，所述最大堆的堆顶元素为所述最大堆中数据最大的元素；如果所述堆为最小堆，那么所述M个数据为所述多个信号中排序数据最大的前M个数据，所述最小堆的堆顶元素为所述最小堆中数据最小的元素。
  19. 一种信号处理装置，其特征在于，包括：
    输入模块，被配置为向多排序模块输入多个信号，所述多排序模块包括环形串联的多个排序模块，所述多个排序模块中的每个排序模块包括Top-K模块，所述多排序模块包括第一排序模块和第二排序模块，所述第一排序模块的输出作为所述第二排序模块的输入；
    处理模块，被配置为基于所述多个信号，更新多个所述Top-K模块中的元素；以及
    输出模块，被配置为输出所述多排序模块中多个所述Top-K模块中的元素。
  20. 一种电子设备，其特征在于，所述电子设备包括存储器以及耦合于所述存储器的处理器，所述存储器中存储有可执行指令，所述处理器用于调用所述可执行指令，使得所述电子设备执行根据权利要求1至18中任一项所述的方法。
  21. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行指令，所述计算机可执行指令被处理器执行时实现根据权利要求1至18中任一项所述的方法。
  22. 一种芯片，包括处理电路，被配置为执行根据权利要求1至18中任一项所述的方法。
PCT/CN2023/126090 2022-10-28 2023-10-24 信号处理方法、装置、设备、介质及芯片 Ceased WO2024088231A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101085967B1 (ko) * 2011-04-21 2011-11-22 한국과학기술원 선형 시간 Ｔｏｐ－ｋ 정렬방법
CN104317549A (zh) * 2014-10-15 2015-01-28 中国航天科技集团公司第九研究院第七七一研究所 一种实现数据排序的级联结构电路和方法
CN111913955A (zh) * 2020-06-22 2020-11-10 中科驭数（北京）科技有限公司 数据的排序处理装置、方法和存储介质
CN114547286A (zh) * 2022-02-21 2022-05-27 京东科技控股股份有限公司 一种信息搜索方法、装置及电子设备
CN114968547A (zh) * 2021-02-25 2022-08-30 华为技术有限公司 一种排序装置及方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101085967B1 (ko) * 2011-04-21 2011-11-22 한국과학기술원 선형 시간 Ｔｏｐ－ｋ 정렬방법
CN104317549A (zh) * 2014-10-15 2015-01-28 中国航天科技集团公司第九研究院第七七一研究所 一种实现数据排序的级联结构电路和方法
CN111913955A (zh) * 2020-06-22 2020-11-10 中科驭数（北京）科技有限公司 数据的排序处理装置、方法和存储介质
CN114968547A (zh) * 2021-02-25 2022-08-30 华为技术有限公司 一种排序装置及方法
CN114547286A (zh) * 2022-02-21 2022-05-27 京东科技控股股份有限公司 一种信息搜索方法、装置及电子设备

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