WO2024083418A1 - Digital-to-analog converter, circuit arrangement, discriminator and photon counting system - Google Patents

Digital-to-analog converter, circuit arrangement, discriminator and photon counting system Download PDF

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Publication number
WO2024083418A1
WO2024083418A1 PCT/EP2023/075398 EP2023075398W WO2024083418A1 WO 2024083418 A1 WO2024083418 A1 WO 2024083418A1 EP 2023075398 W EP2023075398 W EP 2023075398W WO 2024083418 A1 WO2024083418 A1 WO 2024083418A1
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WIPO (PCT)
Prior art keywords
string
resistor
coarse
fine
digital
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PCT/EP2023/075398
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French (fr)
Inventor
Fridolin Michel
Massimo Rigo
Srinidhi Koushik Kanagal Ramesh
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Ams International AG
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Ams International AG
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Priority to CN202380070775.3A priority Critical patent/CN119999095A/en
Priority to DE112023004430.9T priority patent/DE112023004430T5/en
Publication of WO2024083418A1 publication Critical patent/WO2024083418A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16—Measuring radiation intensity
    • G01T1/17—Circuit arrangements not adapted to a particular type of detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/662—Multiplexed conversion systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Definitions

  • DIGITAL-TO-ANALOG CONVERTER CIRCUIT ARRANGEMENT , DISCRIMINATOR AND PHOTON COUNTING SYSTEM
  • the present disclosure relates to a digital-to-analog voltage converter .
  • the disclosure further relates to a circuit arrangement , a discriminator, a photon counting system and a device for medical diagnostics .
  • Digital-to-analog converters are employed to represent digital values in the analog domain .
  • One category of DACs is represented by resistive DACs , which resort to a matched resistor-string connected between two reference voltages to generate a number of equally spaced intermediate voltages that are selected by an analog multiplexer or switch providing the DAC output .
  • resistive DACs which resort to a matched resistor-string connected between two reference voltages to generate a number of equally spaced intermediate voltages that are selected by an analog multiplexer or switch providing the DAC output .
  • this type of DAC tends to become area-intensive for resolutions higher than 8 bits .
  • a Digital-to-Analog Converter comprises a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 and a fine resistor-string digital- to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to lower N-bit digital data .
  • the DAC further comprises a combining unit for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to- analog conversion unit .
  • the combining unit comprises a capacitor .
  • the output of the coarse resistor-string digital- to-analog conversion unit and the output of the fine resi storstring digital-to-analog conversion unit are connectable to a first terminal of the capacitor .
  • the coarse resistor-string digital- to-analog conversion unit comprises a coarse resistor-string and a coarse multiplexer which is configured to be connected to a selected tap between resistors of the coarse resistorstring .
  • the fine resistor-string digital-to-analog conversion unit may comprise a fine resistor-string and a fine multiplexer which is configured to be selectively connected to a selected tap between resistors of the fine resistor-string .
  • the coarse resistor-string and the fine resistor-string may be connected in series .
  • the DAC may further comprise a first buf fer receiving a reference voltage and controlling a voltage supplied to the coarse resistor-string .
  • the first buf fer comprises a first buf fer capacitor for storing an of fset voltage .
  • the first buf fer may further comprise a second buf fer capacitor for storing a reference voltage .
  • the first buf fer may comprise a first buf fer circuit and a second buf fer circuit , each of the first and the second buf fer circuits comprising a first buf fer capacitor, respectively .
  • the first buf fer circuit and the second buf fer circuit may be configured to be alternatingly operated .
  • the coarse resistor-string digital- to-analog conversion unit further comprises a high-ohmic coarse resistor-string which is connected in parallel to the coarse resistor-string, a resistance of the high-ohmic coarse resistor-string being greater than the resistance of the coarse resistor-string .
  • the high-ohmic coarse resistor-string is configured to be connected to the coarse multiplexer when the coarse multiplexer is connected to the first terminal of the capacitor .
  • the fine resi stor-string digital-to-analog conversion unit may further comprise a low-ohmic fine resistor-string which is connected in parallel to the fine resistor-string, a resistance of the low-ohmic fine resistorstring being less than the resistance of the fine resistorstring .
  • the low-ohmic fine resistor-string is configured to be connected to the fine multiplexer when the fine multiplexer is connected to the first terminal of the capacitor .
  • the DAC may further comprise an additional switchable resistor-string between the coarse resistor-string and the fine resistor-string .
  • a circuit arrangement comprises a digital-to-analog converter, DAC, and a comparator .
  • the DAC comprises a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 , a fine resi stor-string digital-to-analog conversion unit for selectively outputting 2 N -level analog voltages in response to lower N-bit digital data, and a combining unit for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit .
  • the combining unit comprises a capacitor .
  • the output of the fine resistor-string digital-to-analog conversion unit is connectable to a first terminal of the capacitor, and a second terminal of the capacitor being connectable to a first input of the comparator .
  • the output of the coarse resistor-string digital- to-analog conversion unit is connectable to a second input of the comparator .
  • the output of the coarse resistorstring digital-to-analog conversion unit is connectable to a frontend circuit .
  • the frontend circuit is configured to receive an input signal and to supply a processed signal to a second input of the comparator .
  • the processed signal is generated on the basis of the input signal and the output of the coarse resistor-string digital-to-analog conversion unit .
  • the output of the coarse resistor-string digital- to-analog conversion unit may be V/ I converted before being supplied to the frontend circuit .
  • the output of the coarse resistorstring digital-to-analog conversion unit is connectable to the first terminal of the capacitor .
  • the circuit arrangement may further comprise a frontend circuit which is configured to receive an input signal and to supply a processed signal to a second input of the comparator .
  • the frontend circuit may be permanently connected to the second input of the comparator .
  • the processed signal may be based on the input signal and the output of the coarse resistor-string digital-to-analog conversion unit .
  • a discriminator comprises a plurality of discriminator stages .
  • Each of the discriminator stages comprises a comparator, a coarse multiplexer and a fine multiplexer .
  • the coarse multiplexer being connectable to a selected tap connecting resistors of a coarse resistor-string for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 .
  • the fine multiplexer is connectable to a selected tap connecting resistors of a fine resistor-string for selectively outputting 2 N -level analog voltages in response to lower N-bit digital data .
  • the discriminator stage further comprises a combining unit for combining an output of the coarse multiplexer and the output of the fine multiplexer .
  • the combining unit comprises a capacitor .
  • the output of the fine multiplexer is connectable to a first terminal of the capacitor, and a second terminal of the capacitor is connectable to a first input of the comparator .
  • the output of the coarse multiplexer is connectable to a second input of the comparator .
  • the output of the coarse multiplexer may be connectable to a frontend circuit configured to receive an input signal and to supply a processed signal to a second input of the comparator, the processed signal being based on the input signal and the output of the coarse multiplexer .
  • a photon counting system comprises the discriminator as defined above .
  • a device for medical diagnostics may comprise the photon counting system .
  • Fig . 1 shows a schematic view of a photon counting system .
  • Figs . 2A and 2B illustrate embodiments of DACs forming part of discriminator stages , respectively .
  • Figs . 3A to 3E illustrate examples of circuit arrangements forming part of discriminator stages , respectively .
  • Figs . 4A to 4C illustrate further examples of DACs forming part of discriminator stages , respectively .
  • Figs . 5A and 5B illustrate examples of DACs forming part of discriminator stages , respectively .
  • Fig. 6 shows an example of a further photon counting system.
  • Fig. 7 illustrates a device for medical diagnostics.
  • Coupled and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the “coupled” or “electrically coupled” elements.
  • electrically connected intends to describe a low-ohmic electric connection between the elements electrically connected together. According to further embodiments and where appropriate, the term “electrically connected” may mean that the respective elements are “directly connected” or are “directly and permanently connected” .
  • component A is permanently connected to component B
  • component B is intended to mean that there is a direct connection between component A and component B without a switch .
  • this feature sti ll is satis fied when a connection, e . g . a corresponding wiring is connected to component A and component B .
  • Fig . 1 shows a schematic view of a photon counting system 20 , which may comprise a digital-to-analog converter 100 that will be explained herein below .
  • a photon counting system 20 illustrated in Fig . 1 single photon events 21 are detected and counted in order to obtain intensity in spectral information .
  • the photons 21 are detected individually . Accordingly, the photon energy may be extracted .
  • the photon counting system illustrated in Fig . 1 comprises a photon detector 201 that may comprise a special sensor material which converts photons into current pulses .
  • a frontend circuit 202 e . g . a CMOS frontend circuit .
  • Signals are generated, wherein the height of the output voltage peak is related to the photon energy, thus containing spectral information.
  • Digitization of the spectral information may be performed using a discriminator 200 which comprises a plurality of comparators 105i, 1052, • • • 105 n . Different threshold voltages Vthi, Vth2, ... Vth n are supplied to the different comparators. By counting the individual discriminator outputs, the spectral distribution of the photon events may be determined.
  • the comparator thresholds in the discriminator 200 need to be defined with high resolution.
  • hundreds of channels are integrated on a single die and each channel comprises an array of DACs . Accordingly, there is a need for implementing each DAC with minimum area as possible.
  • the different threshold voltages are supplied by different DACs 100i, IOO2, ... 100 n .
  • the DACs may provide non-equally spaced threshold voltages for comparators. Due to a comparable large time between the different photon events, a refreshing of the threshold voltages is necessary. Therefore, digital-to-analog conversion has to be continuously performed.
  • a discriminator 200 comprises a multitude of DACs. Usually, clusters of DACs are implemented which are based on a shared architecture. In more detail, concepts are being developed according to which part of the circuits may be shared among the different DACs.
  • a discriminator 200 may comprise a plurality of discriminator stages 2101. Each of the discriminators stages 210i comprises a comparator 105 and elements of a DAC 1001 associated to the discriminator stage 2101. Further elements of the DAC are shared among the single discriminator stages 2101.
  • Fig . 2A shows an example of a DAC 100 according to embodiments .
  • the DAC 100 is a component of a discriminator stage 210i forming a component of the discriminator 200 .
  • the DAC 100 comprises a coarse resistor-string digital-to- analog conversion unit 121 for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 .
  • the DAC 100 further comprises a fine resistor-string digital-to- analog conversion unit 122 for selectively outputting 2 N -level analog voltages in response to lower N-bit digital data .
  • the DAC 100 further comprises a combining unit 109 for combining an output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistors- string digital-to-analog conversion unit 122 .
  • the combining unit 109 comprises a capacitor 111 .
  • the output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistor-string digital- to-analog conversion unit 122 are connectable to a first terminal 137 of the capacitor 111 .
  • a second buf fer stage may be dispensed with .
  • area may be reduced .
  • the coarse resistor-string digital-to-analog conversion unit 121 may comprise a coarse resistor-string 101 and a coarse multiplexer 107 .
  • the fine resistor-string digital-to- analog conversion unit 122 may comprise a fine resistor-string and a fine multiplexer 108 .
  • the DAC illustrated in Fig . 2A comprises a first buf fer 112 which receives a first reference voltage (Vrefp ) as an input .
  • the first reference voltage (Vrefp ) may be a positive voltage .
  • the buf fer 112 is connected to a coarse resistor-string 101 .
  • resistor-string is used herein to refer to one or more resistors connected in series .
  • the coarse resistorstring 101 comprises a plurality of resistors and operates as a coarse resistor-string .
  • the terms " coarse” and “ fine” referred to herein in relation to a resistor-string refer to the voltage step, or resolution, across each resistors of the resistor-string and not to their resistive value .
  • the plurality of resistors in the coarse resistor-string 101 may be of equal resistance value so that the potential di f ference is divided across the resistors of the coarse resistor-string 101 in equal steps .
  • the resistors of the fine resistor-string 102 may have equal resistance values so that the potential di f ference is divided across the fine resistorstring 102 in equal steps .
  • any of the transistors may have di f ferent resistance values so that a potential di f ference is divided in non-linear steps .
  • the fine resistor-string 102 covers only one coarse level . Accordingly, the fine voltage steps are used to interpolate consecutive levels of the coarse resistor-string 101 .
  • a second buf fer 113 receives a second reference voltage (Vrefn) which is lower than the first reference voltage (Vrefp ) .
  • the fine resistor-string 102 is connected to the second buf fer 113A.
  • the coarse multiplexer 107 may be implemented as a coarse switch tree .
  • the coarse resistor-string may comprise a plurality of voltage taps ( a contact that may be reached by the coarse multiplexer 107 ) and the coarse multiplexer 107 comprises a plurality of switches .
  • Each of the plurality of switches of the coarse multiplexer 107 are controllable to connect to one of the voltage taps of the coarse resistor-string 101 .
  • the fine resistor-string and the fine multiplexer 108 may b e implemented in a corresponding manner .
  • the switches of the coarse multiplexer 107 are activated in accordance with the upper bits , e . g . the upper N-bit digital data . Further, the switches of the fine multiplexer 108 are activated in accordance with the lower N-bit digital data . Accordingly, the coarse resistor-string digital-to-analog conversion unit 121 selectively outputs 2 N -level analog voltages in response to upper N-bit digital data, and the fine resistor-string digital-to-analog conversion unit 122 selectively outputs 2 N - level analog voltages in response to lower N-bit digital data .
  • the fine resistor-string 102 and the coarse resistor-string 101 are shared among a plurality of discriminator stages 2101.
  • the discriminator stage 210i further comprises a comparator 105 .
  • the comparator 105 comprises a pre-ampli fier 106 .
  • the comparator 105 outputs a comparator voltage V c , i for the respective discriminator stage 2101.
  • the comparator voltage V c , i depends on a result of comparison of a voltage input by a frontend circuit 202 with the analog threshold voltage Vth .
  • the frontend circuit 202 receives a current signal from the detector 201 .
  • the frontend circuit 202 may comprise a charge sensitive ampli bomb .
  • the inverting input of the charge sensitive amplifier may receive the current signal Ii n .
  • a feedback resistor may be connected between the inverting input of the charge sensitive amplifier and the output of the charge sensitive amplifier.
  • the frontend circuit 202 may comprise a shaping amplifier stage (not shown) , configured to receive the output of the charge sensitive amplifier and to output a voltage signal comprising bell-shaped pulses.
  • a first input of the comparator 105 or the pre-amplifier 106 is connected to a reference voltage Vref during a phase ⁇ i .
  • the first input of the comparator 105 or the pre-amplifier 106 is connected to the frontend circuit 202.
  • the output of the pre-amplifier 106 is fed back to a second input of the pre-amplifier 106.
  • the discriminator stage 210i or DAC 100 comprises a capacitor 111.
  • the first input may be a non-inverting input of the comparator, and the second input may be an inverting input of the comparator.
  • the pre-amplifier 106 may be offset compensated in an auto zero loop where the offset is stored on the capacitor 111.
  • the first input may be a noninverting or an inverting input.
  • Fig. 2A shows in the insert a time diagram of the different phases ⁇ i and 2 for operating the discriminator stage 2101.
  • the coarse voltage is sampled.
  • the coarse voltage is selected by the coarse multiplexer 107.
  • the selected coarse voltage is sampled on the capacitor 111 with respect to a reference voltage.
  • the difference between the comparator offset voltage and the coarse DAC voltage is stored on the capacitor 111.
  • complexity and capacitor area are reduced.
  • several di f ferent coarse voltages may be sampled in parallel by connecting several independent coarse multiplexers 107 to the coarse resistor-string 101 .
  • the fine voltage is added during the second phase 92 , i . e . the active photon counting phase .
  • the fine voltages for each DAC 100 in the cluster are selected by independent multiplexers 108 and are connected in series with the respective capacitors 111 holding the coarse voltages and comparator of fset voltage . Accordingly, an output voltage Vth, comp output by the pre-amplifier 106 in phase 2 is given as :
  • Vth, comp Vref - Vcoarse + Vfine .
  • the reference voltages which are applied to the coarse string 101 and the fine string 102 need not be the same . In most practical cases , they may be the same . In this case , the DAC range may be adj usted by moving the coarse voltage with respect to Vref by introducing a voltage drop via the resistor 114 on top of the coarse resistor-string 101 .
  • the combining unit 109 comprises a capacitor 111 , area of the DAC may be reduced . Further, due to the presence of the capacitor 111 , the of fset voltage may be compensated .
  • Fig . 2B shows a further example of a DAC 100 forming part of a discriminator stage 210i .
  • Embodiments illustrated in Fig . 2B are identical with components of Fig . 2A.
  • Di f fering from embodiments illustrated in Fig . 2A, the second buf fer 113 is replaced by a low-ohmic ground connection . Accordingly, the fine resistor-string 102 is connected to ground .
  • area and power may further be reduced .
  • Fig . 3A shows a circuit arrangement 115 and further a corresponding discriminator stage 210i which employs a di f ferent switching scheme .
  • the coarse voltage is applied to the non-inverting input of the pre-ampli fier 106 during phase epi .
  • the fine voltage is applied to the f irst terminal 137 of the capacitor 111 .
  • the output of the pre-ampli bomb 106 is input to the inverting input of the pre-ampli fier 106.
  • the fine multiplexer 108 is no longer connected to the capacitor 111 . Instead, the first terminal 137 of the capacitor 111 is pulled to ground or a reference voltage .
  • the DAC i s no longer needed during the counting phase 2 and may be powered down . As a result , power may be saved .
  • the switching scheme results in an ef fective comparator threshold voltage of
  • Vth, comp Vcoarse - Vf ine .
  • Fig . 3A shows a circuit arrangement 115 comprising a digital-to-analog converter DAC 100 and a comparator 105 .
  • the DAC comprises a coarse resistor-string digital-to-analog conversion unit 121 for selectively outputting 2 N -level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 , and a fine resistor-string digital-to-analog conversion unit 122 for selectively outputting 2 N -level analog voltages in response to lower n-bit digital data .
  • the DAC further comprises a combining unit for combining the output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistor-string digital- to-analog conversion unit 122 .
  • the combining unit 109 comprises a capacitor 111 .
  • the output of the fine resistorstring digital-to-analog conversion unit is connectable to a first terminal of the capacitor 111 .
  • a first terminal 137 of the capacitor 111 is connectable to a first input of the comparator 105 .
  • the frontend circuit 202 is connected via a switch 104 to the discriminator stage 210i in phase 2 •
  • This switch 104 forms an RC filter in combination with the comparator parasitic input capacitances .
  • This may cause considerable distortion and speed limitations when operating at a low supply voltage with low overdrive for a MOS transistor switch 104 .
  • the frontend circuit 202 may be directly and permanently connected to all the comparators 105 in the respective discriminator stages 2101.
  • the comparators 105 may be of fset-compensated one at a time .
  • the scheme illustrated in Figs . 2A or 2B may be used where the coarse voltage is applied to the capacitor 111 during phase ⁇ i and the fine voltage is added during the counting phase 2 •
  • the frontend circuit 202 may be directly and permanently connected to the respective comparators 105 . Further, during phase ⁇ i the coarse voltage is applied to a baseline control circuit for controlling a baseline of signals output via the frontend circuit 202 . During phase 2 a reference voltage Vb is appl ied to the baseline control circuit . This reference voltage or baseline voltage corresponds to a target voltage for the baseline . The signal input serves as a reference for the baseline control circuit . Hence , in this case , the frontend circuit 202 or the shaping circuit may act as a buf fer driving the comparators with a voltage proportional to the applied coarse or baseline reference voltage . The signal input to the frontend circuit 202 may be disconnected in phase ⁇ i in order to guarantee an undisturbed output of the frontend circuit 202 .
  • the coarse multiplexer 107 is shared among the di f ferent stages . Accordingly, the di f ferent comparators of the discriminator 210 are not calibrated in parallel but only one at a time (per frame ) .
  • the fine multiplexer 108 since the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111 and the coarse multiplexer 107 is not connected to the capacitor, the fine voltage may be resubtracted .
  • Fig . 3C shows a configuration, in which an output of the coarse multiplexer 107 is connected to the first terminal 137 of the capacitor 111 during phase ⁇ i .
  • the output of the fine multiplexer 108 is connected to the first terminal 137 of the capacitor during phase 2 •
  • the circuit arrangement 115 further comprises a voltage-current-converter 116 that is arranged between the coarse multiplexer 107 and the frontend circuit 202 .
  • the output of the coarse multiplexer 107 is converted into a current by a voltage-current converter 116 and fed to the frontend circuit 202 via a switch .
  • the coarse voltage signal is inj ected into the frontend circuit 202 as a current signal .
  • the frontend circuit 202 multiplies this coarse current with its transimpedance ZFB, providing a voltage output proportional to
  • Fig . 3E shows a further embodiment of the circuit arrangement 115 , in which the frontend circuit 202 has a control input to set its output into a high impedance state by a control circuit 118 (HZ block) .
  • the voltage may be directly overwritten at the input of the preampli bomb 106 with a reference voltage during phase ⁇ i .
  • the input to the control circuit 118 is a digital control signal ( logic 1 ) .
  • the first buf fer 112 may be of fset compensated so as to eliminate the impact of buf fer of fset .
  • Fig . 4A shows an example o f a DAC 100 which may form part of a discriminator stage 210i .
  • the DAC 100 may be implemented in any of the manners as discussed above .
  • the first buf fer 112 may be modi fied so as to be of fset compensated .
  • the buf fer 112 may be implemented as a circuit comprising an ampli bomb 131 and a first buf fer capacitor 119 .
  • Vref is applied to the inverting input of the amplifier 131.
  • Vref is applied to the non-inverting input of the amplifier 131 via a switch 123 which is closed during phase ⁇ i .
  • the first buffer capacitor 119 is arranged between an auxiliary input of the amplifier 131 and a ground terminal. An output of the amplifier 131 is fed back to the auxiliary input of the amplifier 131 via a switch 126 that is closed during phase ⁇ i .
  • phase (pi) the switches 123 and 126 are closed. Vref is applied to the inverting and to the non-inverting input of the amplifier 131. Hence, the first buffer capacitor 119 is charged with charges corresponding to the offset voltage of the amplifier 131.
  • phase 2 which corresponds to phase ⁇ i as e.g. described with reference to Fig. 2A, the switches 123 and 126 are open.
  • the output of the amplifier 131 is offset compensated due to the charges stored in the first buffer capacitor 119.
  • the output of amplifier 131 is connected to the gate electrode of transistor 134 which may be a P-MOSFET.
  • the voltage supplied to the coarse and the fine resistor-strings 101 and 102 is forced to Vref.
  • the voltage output of the coarse multiplexer 107 is stored on the capacitor 111.
  • phase 3 which refers to a photon counting phase
  • the same processes as described above with reference to Fig. 2A are performed.
  • the output of the frontend circuit 202 is denoted as Vi n .
  • a description of the frontend circuit 202 is omitted from this figure.
  • Fig. 4B shows a further example of a DAC 100 wherein the circuit implementing the first buffer 112 further comprises a second buffer capacitor 120.
  • the second buffer capacitor 120 is connected to a node between the amplifier 131 and the gate electrode of the transistor 134.
  • the circuit implementing the first the buffer 112 is further modified. Due to the presence of the second buffer capacitor 120, the DAC 100 may be operated in two phases instead of three phases.
  • offset compensation of the first buffer 112 may be performed during the DAC operation phase 2 •
  • the buffer output voltage is stored on the second buffer capacitor 120 to properly bias the transistor 134 current source during phase 2 •
  • leakage may cause significant droop in the coarse tree current.
  • the large second capacitor 120 connected to the buffer output may complicate frequency compensation .
  • Fig. 4C shows a further implementation of the first buffer 112 in which droop due to capacitor leakage may be avoided.
  • the second buffer capacitor 120 is replaced by a second buffer circuit 125.
  • the DAC comprises a first buffer circuit 124 and a second buffer circuit 125.
  • Each of the first and second buffer circuits 124, 125 comprises an amplifier and a first buffer capacitor 119.
  • the respective switches are configured to be driven at complementary phases. Accordingly, only one buffer is connected to the coarse tree at a time while the other buffer is offset compensated. Accordingly, the combination of the first and the second buffer circuits implements a ping-pong buffer. Periodic swapping of the buffers results in refreshing of the buffer out of zero state. Accordingly, the DAC 100 illustrated in Fig. 4C may be operated faster.
  • Fig. 5A illustrates a further embodiment of a DAC 100 wherein the coarse and the fine resistor-strings 101, 102 may be implemented in an alternative way.
  • the further components of the DAC may be similar to the one illustrated in e.g. Fig. 2A.
  • the DAC may further comprise a first buffer circuit 124 and a second buffer circuit 125 which has been e.g. explained with reference to Fig. 4C.
  • the voltage supply of the coarse and the fine resistor-strings 101, 102 may be implemented in any arbitrary manner .
  • variable resistance string is introduced for the coarse resistor-string 101 and the fine resistorstring 102. Thereby, the average current consumption may be further reduced.
  • the coarse resistor-string 101 is implemented with a larger number of taps compared to the fine string, for matching purposes.
  • the fine resistor-string 102 covers a small range, typically equal or larger than the coarse string resolution.
  • the fine string has a smaller resistance compared to the coarse string, making the dynamic settling in phase gy faster than the one in phase epi . Since during phase epi the capacitor 111 is charged, while during phase g>2 , only parasitic capacitances are charged, this effect is enhanced. As a consequence, during phase gy, settling is mostly limited by parasitic capacitances and the speed of the reference buffer. Considering the DAC illustrated in Fig. 4C, e.g.
  • the string current is primarily dictated by the settling requirements of the RC circuit, comprising a coarse resistorstring 101, the coarse multiplexer 107, the capacitor 111 and the pre-amplifier 106 speed and significantly less by the dynamic of the resistor fine string 102.
  • a low-ohmic fine resistor-string 129 may be added parallel to a high-ohmic fine resistor- string 102.
  • the high-ohmic fine resistor-string 102 has a larger resistance than the fine resistor-string 102 described herein before, e.g. with reference to Fig. 4C.
  • a high-ohmic coarse resistor-string 127 may be added in parallel to a low-ohmic coarse resistor-string 101.
  • the low-ohmic coarse resistor-string 101 has a smaller resistance than the coarse resistor-string 101 described hereinbefore, e.g. with reference to Fig. 4C.
  • phase ⁇ i when the fine multiplexer 108 is not connected to the capacitor 111, settling is important.
  • phase ⁇ i a low ohmic resistor-string is needed. Accordingly, the parallel low-ohmic fine resistor-string 129 is added or substituted.
  • phase 2 power consumption is a concern because phase 2 covers the majority of the frame time. Accordingly, during phase >2 the high-ohmic fine string 102 is exercised and the coarse string is substituted by a high-ohmic resistor 127.
  • a fine resistor unit may be made of several coarse resistor units in parallel to provide good matching.
  • the fine resistor-string digital-to-analog conversion unit 122 further comprises a low-ohmic fine resi stor-string 129 which is connected in parallel to the fine resistor-string 102 , a resistance of the low-ohmic fine resistor-string 129 being less than the resistance of the fine resistor-string 102 , the low-ohmic fine resistor-string 129 being configured to be connected to the fine multiplexer 108 when the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111 .
  • the coarse resi stor-string digital-to-analog conversion unit 121 further comprises a high-ohmic coarse resistor-string 127 which is connected in parallel to the coarse resistor-string 101 , a resistance of the high-ohmic coarse resistor-string 127 being greater than the resistance of the coarse resistor-string 101 , the coarse resistor-string 127 being configured to be connected to the coarse multiplexer 107 when the coarse multiplexer 107 is connected to the first terminal 137 of the capacitor 111 .
  • the reference buf fer may sti ll be operable to regulate fast output current steps .
  • the output stage si ze and compensation may be adapted to the phase dependent current .
  • this may be achieved by disabling certain PMOS transistors on the sourceside through PMOS switches , thus keeping all PMOS elements biased and allowing a fast recovery through the low-ohmic on- resistance of the switch .
  • Fig . 5B shows further embodiments according to which it is possible to mitigate the capacitor droop .
  • the DAC 100 further comprises an additional resistor-string 135 comprising switches which may be selectively switched on or of f . Due to this additional resistor-string 135 , it is possible to compensate the capacitor droop . An extended range for the fine voltage may be achieved . A sub-LSB resolution may be achieved .
  • this additional resistor-string 135 may be controlled by means of a digital word which is adj usted dynamically to compensate for droop in the sampling capacitor . A possible operation is the following : during ⁇ i, the switches of 135 are all closed .
  • a digital word is programmed to compensate the capacitor droop . In this case , positive droop can be compensated .
  • Another possible operation is the following : during ⁇ i, a portion of the switches in additional resistor-string 135 are closed .
  • the digital word i s programmed to compensate the capacitor droop . In this case , both positive and negative droops can be compensated, by closing a higher or lower number of switches in the additional resistor-string 135 .
  • the additional resistorstring 135 may be arranged above the coarse resistor-string 101 .
  • the same operation principles described above are valid .
  • the additional resistorstring 135 may be arranged below the fine resistor-string 102 .
  • the additional resistor-string 135 may implement a total resistance equal to one resistor unit of the fine resistor-string 102 , enabling a dynamic capacitor droop compensation and sub-LSB resolution over fine DAC voltage during 2 •
  • Fig. 6 shows an example of a photon counting system 20, comprising e.g. the DAC 100, which has been described above with reference to Fig. 4C.
  • the photon counting system of Fig. 6 is similar to the photon counting system illustrated in Fig. 1 so that a detailed description of the components will be omitted. Differing from embodiments illustrated in Fig.
  • a single discriminator stage 210i and further components of the DAC 100 are implemented in a manner as has been described with reference to e.g. Fig. 4C.
  • the discriminator 200 which has been described with reference to Fig. 1, comprises a plurality of discriminator stages 2101 that may be implemented in a manner shown in Fig. 6.
  • the discriminator stages 2101 and the further components of the DAC 100 may also be implemented in any other manner described herein above.
  • the left side of Fig. 6 shows the different phases for operating the discriminator. As is shown, during phase ⁇ p a , a first frame 136 is detected, and the phase (pt corresponds to the second frame 136.
  • the photon counting system 20 may e.g. be a photon counting CT detector.
  • X-ray photons are generated externally and are attenuated while traveling through the tissue or an object being analyzed.
  • a photon detector 201 converts each incoming photon 21 into a charge packet which is processed by the CMOS frontend circuit 202.
  • the amplitude of the voltage pulse resulting at the output of the frontend circuit 202 is discretized by means of an array of comparators 105, each being a component of a corresponding one of the discriminator stages 201i.
  • the array of comparators 105 is supplied with an array of threshold voltages that cover the voltage pulse amplitude discretization range.
  • the discriminator 200 comprises a cluster of n voltage DACs 100 , where the coarse resistor-string 101 and the fine resistor-string 102 are shared between all DACs 100 .
  • the coarse voltages are stored on the respective capacitors 111 of the comparators 105 .
  • the counting frontend connects to the comparator array either through a switch or directly while making the frontend circuit 102 high-ohmic during phase ⁇ i .
  • a ping-pong buf fer topology comprising a first buf fer circuit 124 and a second buf fer circuit 125 may be advantageously employed . Due to this concept , an idle buf fer circuit 124 , 125 may be of fset compensated during the full frame time while still providing an operational path by the other buf fer .
  • the photon counting system may be employed in medical applications .
  • Fig . 7 shows a device for medical diagnosis 30 comprising the photon counting system 20 described hereinabove .

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Abstract

A Digital-to-Analog Converter (100, 1001,...100n), DAC, comprises a coarse resistor-string digital-to-analog conversion unit (121) for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2, a fine resistor-string digital-to-analog conversion unit (122) for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit (109) for combining an output of the coarse resistor-string digital-to-analog conversion unit (121) and the output of the fine resistorstring digital-to-analog conversion unit (122). The combining unit (109) comprises a capacitor (111). The output of the coarse resistor-string digital-to-analog conversion unit (121) and the output of the fine resistor-string digital-to-analog conversion unit (122) are connectable to a first terminal (137) of the capacitor (111).

Description

DIGITAL-TO-ANALOG CONVERTER, CIRCUIT ARRANGEMENT , DISCRIMINATOR AND PHOTON COUNTING SYSTEM
TECHNICAL FIELD
The present disclosure relates to a digital-to-analog voltage converter . The disclosure further relates to a circuit arrangement , a discriminator, a photon counting system and a device for medical diagnostics .
BACKGROUND
Digital-to-analog converters ( DAC ) are employed to represent digital values in the analog domain . One category of DACs is represented by resistive DACs , which resort to a matched resistor-string connected between two reference voltages to generate a number of equally spaced intermediate voltages that are selected by an analog multiplexer or switch providing the DAC output . As the analog multiplexer increases in complexity with the number of DAC levels , this type of DAC tends to become area-intensive for resolutions higher than 8 bits .
It is an obj ect of the present invention to provide an improved digital-to-analog converter, an improved circuit arrangement , an improved discriminator, an improved photon counting system, and an improved device for medical diagnostics .
SUMMARY
According to embodiments , the above obj ect is achieved by the claimed matter according to the independent claims . Advantageous further developments are defined in the dependent claims . A Digital-to-Analog Converter, DAC, comprises a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 and a fine resistor-string digital- to-analog conversion unit for selectively outputting 2N-level analog voltages in response to lower N-bit digital data . The DAC further comprises a combining unit for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to- analog conversion unit . The combining unit comprises a capacitor . The output of the coarse resistor-string digital- to-analog conversion unit and the output of the fine resi storstring digital-to-analog conversion unit are connectable to a first terminal of the capacitor .
According to embodiments , the coarse resistor-string digital- to-analog conversion unit comprises a coarse resistor-string and a coarse multiplexer which is configured to be connected to a selected tap between resistors of the coarse resistorstring . Further, the fine resistor-string digital-to-analog conversion unit may comprise a fine resistor-string and a fine multiplexer which is configured to be selectively connected to a selected tap between resistors of the fine resistor-string . The coarse resistor-string and the fine resistor-string may be connected in series .
The DAC may further comprise a first buf fer receiving a reference voltage and controlling a voltage supplied to the coarse resistor-string .
According to embodiments , the first buf fer comprises a first buf fer capacitor for storing an of fset voltage . The first buf fer may further comprise a second buf fer capacitor for storing a reference voltage .
For example , the first buf fer may comprise a first buf fer circuit and a second buf fer circuit , each of the first and the second buf fer circuits comprising a first buf fer capacitor, respectively . The first buf fer circuit and the second buf fer circuit may be configured to be alternatingly operated .
According to embodiments , the coarse resistor-string digital- to-analog conversion unit further comprises a high-ohmic coarse resistor-string which is connected in parallel to the coarse resistor-string, a resistance of the high-ohmic coarse resistor-string being greater than the resistance of the coarse resistor-string . The high-ohmic coarse resistor-string is configured to be connected to the coarse multiplexer when the coarse multiplexer is connected to the first terminal of the capacitor .
Moreover, the fine resi stor-string digital-to-analog conversion unit may further comprise a low-ohmic fine resistor-string which is connected in parallel to the fine resistor-string, a resistance of the low-ohmic fine resistorstring being less than the resistance of the fine resistorstring . The low-ohmic fine resistor-string is configured to be connected to the fine multiplexer when the fine multiplexer is connected to the first terminal of the capacitor .
According to embodiments , the DAC may further comprise an additional switchable resistor-string between the coarse resistor-string and the fine resistor-string .
According to further embodiments , a circuit arrangement comprises a digital-to-analog converter, DAC, and a comparator . The DAC comprises a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 , a fine resi stor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit for combining an output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit . The combining unit comprises a capacitor . The output of the fine resistor-string digital-to-analog conversion unit is connectable to a first terminal of the capacitor, and a second terminal of the capacitor being connectable to a first input of the comparator .
For example , the output of the coarse resistor-string digital- to-analog conversion unit is connectable to a second input of the comparator .
According to embodiments , the output of the coarse resistorstring digital-to-analog conversion unit is connectable to a frontend circuit . The frontend circuit is configured to receive an input signal and to supply a processed signal to a second input of the comparator . The processed signal is generated on the basis of the input signal and the output of the coarse resistor-string digital-to-analog conversion unit .
For example , the output of the coarse resistor-string digital- to-analog conversion unit may be V/ I converted before being supplied to the frontend circuit .
According to embodiments , the output of the coarse resistorstring digital-to-analog conversion unit is connectable to the first terminal of the capacitor . The circuit arrangement may further comprise a frontend circuit which is configured to receive an input signal and to supply a processed signal to a second input of the comparator . The frontend circuit may be permanently connected to the second input of the comparator . The processed signal may be based on the input signal and the output of the coarse resistor-string digital-to-analog conversion unit .
According to further embodiments , a discriminator comprises a plurality of discriminator stages . Each of the discriminator stages comprises a comparator, a coarse multiplexer and a fine multiplexer . The coarse multiplexer being connectable to a selected tap connecting resistors of a coarse resistor-string for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 . The fine multiplexer is connectable to a selected tap connecting resistors of a fine resistor-string for selectively outputting 2N-level analog voltages in response to lower N-bit digital data . The discriminator stage further comprises a combining unit for combining an output of the coarse multiplexer and the output of the fine multiplexer . The combining unit comprises a capacitor . The output of the fine multiplexer is connectable to a first terminal of the capacitor, and a second terminal of the capacitor is connectable to a first input of the comparator .
For example , the output of the coarse multiplexer is connectable to a second input of the comparator .
Further, the output of the coarse multiplexer may be connectable to a frontend circuit configured to receive an input signal and to supply a processed signal to a second input of the comparator, the processed signal being based on the input signal and the output of the coarse multiplexer .
According to embodiments , a photon counting system comprises the discriminator as defined above . A device for medical diagnostics may comprise the photon counting system .
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description . The elements of the drawings are not necessarily to scale relative to each other . Like reference numbers designate corresponding similar parts .
Fig . 1 shows a schematic view of a photon counting system .
Figs . 2A and 2B illustrate embodiments of DACs forming part of discriminator stages , respectively .
Figs . 3A to 3E illustrate examples of circuit arrangements forming part of discriminator stages , respectively .
Figs . 4A to 4C illustrate further examples of DACs forming part of discriminator stages , respectively .
Figs . 5A and 5B illustrate examples of DACs forming part of discriminator stages , respectively . Fig. 6 shows an example of a further photon counting system.
Fig. 7 illustrates a device for medical diagnostics.
DETAILED DESCRIPTION
In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims .
The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
As employed in this specification, the terms "coupled" and/or "electrically coupled" are not meant to mean that the elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" intends to describe a low-ohmic electric connection between the elements electrically connected together. According to further embodiments and where appropriate, the term "electrically connected" may mean that the respective elements are "directly connected" or are "directly and permanently connected" .
The term "component A is permanently connected to component B" is intended to mean that there is a direct connection between component A and component B without a switch . When any of components A or B is disconnected from a power supply or an input signal , this feature sti ll is satis fied when a connection, e . g . a corresponding wiring is connected to component A and component B .
As used herein, the terms "having" , "containing" , " including" , "comprising" and the like are open ended terms that indicate the presence of stated elements or features , but do not preclude additional elements or features . The articles "a" , "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise .
Fig . 1 shows a schematic view of a photon counting system 20 , which may comprise a digital-to-analog converter 100 that will be explained herein below . In the photon counting system 20 illustrated in Fig . 1 , single photon events 21 are detected and counted in order to obtain intensity in spectral information . Whereas in a class ical image or X-ray sensor only the total input intensity is measured, in a photon counting system as illustrated in Fig . 1 , the photons 21 are detected individually . Accordingly, the photon energy may be extracted . The photon counting system illustrated in Fig . 1 , comprises a photon detector 201 that may comprise a special sensor material which converts photons into current pulses . These current pulses are converted to voltage pulses by a frontend circuit 202 , e . g . a CMOS frontend circuit . Signals are generated, wherein the height of the output voltage peak is related to the photon energy, thus containing spectral information. Digitization of the spectral information (i.e. the height of the output pulse) may be performed using a discriminator 200 which comprises a plurality of comparators 105i, 1052, • • • 105n. Different threshold voltages Vthi, Vth2, ... Vthn are supplied to the different comparators. By counting the individual discriminator outputs, the spectral distribution of the photon events may be determined.
For high performance photon counting, the comparator thresholds in the discriminator 200 need to be defined with high resolution. Typically, hundreds of channels are integrated on a single die and each channel comprises an array of DACs . Accordingly, there is a need for implementing each DAC with minimum area as possible.
The different threshold voltages are supplied by different DACs 100i, IOO2, ... 100n. For example, the DACs may provide non-equally spaced threshold voltages for comparators. Due to a comparable large time between the different photon events, a refreshing of the threshold voltages is necessary. Therefore, digital-to-analog conversion has to be continuously performed.
As is illustrated in Fig. 1, a discriminator 200 comprises a multitude of DACs. Usually, clusters of DACs are implemented which are based on a shared architecture. In more detail, concepts are being developed according to which part of the circuits may be shared among the different DACs. In particular, a discriminator 200 may comprise a plurality of discriminator stages 2101. Each of the discriminators stages 210i comprises a comparator 105 and elements of a DAC 1001 associated to the discriminator stage 2101. Further elements of the DAC are shared among the single discriminator stages 2101. Fig . 2A shows an example of a DAC 100 according to embodiments . The DAC 100 is a component of a discriminator stage 210i forming a component of the discriminator 200 .
The DAC 100 comprises a coarse resistor-string digital-to- analog conversion unit 121 for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 . The DAC 100 further comprises a fine resistor-string digital-to- analog conversion unit 122 for selectively outputting 2N-level analog voltages in response to lower N-bit digital data . The DAC 100 further comprises a combining unit 109 for combining an output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistors- string digital-to-analog conversion unit 122 . The combining unit 109 comprises a capacitor 111 .
According to embodiments illustrated in Fig . 2A, the output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistor-string digital- to-analog conversion unit 122 are connectable to a first terminal 137 of the capacitor 111 . As will be explained in the following, due to the presence of the capacitor 111 , which combines the output of the coarse resistor-string digital-to- analog conversion unit 121 and the output of the fine resistor-string digital-to-analog conversion unit 122 , a second buf fer stage may be dispensed with . Hence , area may be reduced .
The coarse resistor-string digital-to-analog conversion unit 121 may comprise a coarse resistor-string 101 and a coarse multiplexer 107 . The fine resistor-string digital-to- analog conversion unit 122 may comprise a fine resistor-string and a fine multiplexer 108 . The DAC illustrated in Fig . 2A comprises a first buf fer 112 which receives a first reference voltage (Vrefp ) as an input . The first reference voltage (Vrefp ) may be a positive voltage . The buf fer 112 is connected to a coarse resistor-string 101 . The term " resistor-string" is used herein to refer to one or more resistors connected in series . The coarse resistorstring 101 comprises a plurality of resistors and operates as a coarse resistor-string . The terms " coarse" and " fine" referred to herein in relation to a resistor-string refer to the voltage step, or resolution, across each resistors of the resistor-string and not to their resistive value . The plurality of resistors in the coarse resistor-string 101 may be of equal resistance value so that the potential di f ference is divided across the resistors of the coarse resistor-string 101 in equal steps . Likewise , the resistors of the fine resistor-string 102 may have equal resistance values so that the potential di f ference is divided across the fine resistorstring 102 in equal steps . According to further embodiments , any of the transistors may have di f ferent resistance values so that a potential di f ference is divided in non-linear steps . The fine resistor-string 102 covers only one coarse level . Accordingly, the fine voltage steps are used to interpolate consecutive levels of the coarse resistor-string 101 .
A second buf fer 113 receives a second reference voltage (Vrefn) which is lower than the first reference voltage (Vrefp ) . The fine resistor-string 102 is connected to the second buf fer 113A.
The coarse multiplexer 107 may be implemented as a coarse switch tree . For example , the coarse resistor-string may comprise a plurality of voltage taps ( a contact that may be reached by the coarse multiplexer 107 ) and the coarse multiplexer 107 comprises a plurality of switches . Each of the plurality of switches of the coarse multiplexer 107 are controllable to connect to one of the voltage taps of the coarse resistor-string 101 . The fine resistor-string and the fine multiplexer 108 may b e implemented in a corresponding manner .
When a bit string 103 is input to the DAC 100 , e . g . to the coarse multiplexer 107 , the switches of the coarse multiplexer 107 are activated in accordance with the upper bits , e . g . the upper N-bit digital data . Further, the switches of the fine multiplexer 108 are activated in accordance with the lower N-bit digital data . Accordingly, the coarse resistor-string digital-to-analog conversion unit 121 selectively outputs 2N-level analog voltages in response to upper N-bit digital data, and the fine resistor-string digital-to-analog conversion unit 122 selectively outputs 2N- level analog voltages in response to lower N-bit digital data .
As is further shown in Fig . 2A, the fine resistor-string 102 and the coarse resistor-string 101 are shared among a plurality of discriminator stages 2101.
The discriminator stage 210i further comprises a comparator 105 . The comparator 105 comprises a pre-ampli fier 106 . The comparator 105 outputs a comparator voltage Vc, i for the respective discriminator stage 2101. The comparator voltage Vc, i depends on a result of comparison of a voltage input by a frontend circuit 202 with the analog threshold voltage Vth .
The frontend circuit 202 , e . g . a CMOS frontend circuit receives a current signal from the detector 201 . The frontend circuit 202 may comprise a charge sensitive ampli fier . For example , the inverting input of the charge sensitive amplifier may receive the current signal Iin. A feedback resistor may be connected between the inverting input of the charge sensitive amplifier and the output of the charge sensitive amplifier. The frontend circuit 202 may comprise a shaping amplifier stage (not shown) , configured to receive the output of the charge sensitive amplifier and to output a voltage signal comprising bell-shaped pulses.
As is further shown in Fig. 2A, a first input of the comparator 105 or the pre-amplifier 106 is connected to a reference voltage Vref during a phase < i . During a phase 2, the first input of the comparator 105 or the pre-amplifier 106 is connected to the frontend circuit 202. During phase (pi, the output of the pre-amplifier 106 is fed back to a second input of the pre-amplifier 106. The discriminator stage 210i or DAC 100 comprises a capacitor 111. For example, the first input may be a non-inverting input of the comparator, and the second input may be an inverting input of the comparator. As will be explained in the following, due to this configuration, the pre-amplifier 106 may be offset compensated in an auto zero loop where the offset is stored on the capacitor 111. Generally, depending on a polarity of a signal output by the shaping amplifier stage, the first input may be a noninverting or an inverting input.
Fig. 2A shows in the insert a time diagram of the different phases < i and 2 for operating the discriminator stage 2101. During the first phase < i, the coarse voltage is sampled. The coarse voltage is selected by the coarse multiplexer 107. The selected coarse voltage is sampled on the capacitor 111 with respect to a reference voltage. As a result, the difference between the comparator offset voltage and the coarse DAC voltage is stored on the capacitor 111. Hence, complexity and capacitor area are reduced. In a photon counting system comprising a plurality of discriminator stages 2101, several di f ferent coarse voltages may be sampled in parallel by connecting several independent coarse multiplexers 107 to the coarse resistor-string 101 . This allows the generation of a cluster of DACs which are required for the discriminator 200 without increase in static power consumption . Consequently, this topology is highly scalable . The fine voltage is added during the second phase 92 , i . e . the active photon counting phase . The fine voltages for each DAC 100 in the cluster are selected by independent multiplexers 108 and are connected in series with the respective capacitors 111 holding the coarse voltages and comparator of fset voltage . Accordingly, an output voltage Vth, comp output by the pre-amplifier 106 in phase 2 is given as :
Vth, comp = Vref - Vcoarse + Vfine .
The reference voltages which are applied to the coarse string 101 and the fine string 102 need not be the same . In most practical cases , they may be the same . In this case , the DAC range may be adj usted by moving the coarse voltage with respect to Vref by introducing a voltage drop via the resistor 114 on top of the coarse resistor-string 101 .
Due to the configuration described above , in particular, since the combining unit 109 comprises a capacitor 111 , area of the DAC may be reduced . Further, due to the presence of the capacitor 111 , the of fset voltage may be compensated .
Fig . 2B shows a further example of a DAC 100 forming part of a discriminator stage 210i . Embodiments illustrated in Fig . 2B are identical with components of Fig . 2A. Di f fering from embodiments illustrated in Fig . 2A, the second buf fer 113 is replaced by a low-ohmic ground connection . Accordingly, the fine resistor-string 102 is connected to ground . As a result , area and power may further be reduced .
As has been explained above , according to embodiments that are illustrated in Figs . 2A and 2B, a combination of the coarse voltage and the fine voltage is achieved during phase 2 •
Fig . 3A shows a circuit arrangement 115 and further a corresponding discriminator stage 210i which employs a di f ferent switching scheme . In particular, as is shown, instead of connecting a reference voltage to the non-inverting input of the pre-ampli fier 106, the coarse voltage is applied to the non-inverting input of the pre-ampli fier 106 during phase epi . Further, during phase epi, the fine voltage is applied to the f irst terminal 137 of the capacitor 111 . During phase epi the output of the pre-ampli fier 106 is input to the inverting input of the pre-ampli fier 106. During the photon counting phase (P2 , the fine multiplexer 108 is no longer connected to the capacitor 111 . Instead, the first terminal 137 of the capacitor 111 is pulled to ground or a reference voltage . Hence , the DAC i s no longer needed during the counting phase 2 and may be powered down . As a result , power may be saved .
The switching scheme results in an ef fective comparator threshold voltage of
Vth, comp = Vcoarse - Vfine .
Accordingly, Fig . 3A shows a circuit arrangement 115 comprising a digital-to-analog converter DAC 100 and a comparator 105 . The DAC comprises a coarse resistor-string digital-to-analog conversion unit 121 for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2 , and a fine resistor-string digital-to-analog conversion unit 122 for selectively outputting 2N-level analog voltages in response to lower n-bit digital data . The DAC further comprises a combining unit for combining the output of the coarse resistor-string digital-to-analog conversion unit 121 and the output of the fine resistor-string digital- to-analog conversion unit 122 . The combining unit 109 comprises a capacitor 111 . The output of the fine resistorstring digital-to-analog conversion unit is connectable to a first terminal of the capacitor 111 . A first terminal 137 of the capacitor 111 is connectable to a first input of the comparator 105 .
As has been explained above , according to embodiments , that are illustrated in Figs . 2A, 2B and 3A, the frontend circuit 202 is connected via a switch 104 to the discriminator stage 210i in phase 2 • This switch 104 forms an RC filter in combination with the comparator parasitic input capacitances . This may cause considerable distortion and speed limitations when operating at a low supply voltage with low overdrive for a MOS transistor switch 104 . For this reason, according to further implementations , the frontend circuit 202 may be directly and permanently connected to all the comparators 105 in the respective discriminator stages 2101.
This is further explained with reference to Figs . 3B and 3C . When employing this arrangement , it may be impossible to apply individual coarse voltages for the comparators in the discriminator stage 2101 during phase < i . Hence , the comparators 105 may be of fset-compensated one at a time . Alternatively, the scheme illustrated in Figs . 2A or 2B may be used where the coarse voltage is applied to the capacitor 111 during phase < i and the fine voltage is added during the counting phase 2 •
According to an implementation, which is shown in Fig . 3B, the frontend circuit 202 may be directly and permanently connected to the respective comparators 105 . Further, during phase < i the coarse voltage is applied to a baseline control circuit for controlling a baseline of signals output via the frontend circuit 202 . During phase 2 a reference voltage Vb is appl ied to the baseline control circuit . This reference voltage or baseline voltage corresponds to a target voltage for the baseline . The signal input serves as a reference for the baseline control circuit . Hence , in this case , the frontend circuit 202 or the shaping circuit may act as a buf fer driving the comparators with a voltage proportional to the applied coarse or baseline reference voltage . The signal input to the frontend circuit 202 may be disconnected in phase < i in order to guarantee an undisturbed output of the frontend circuit 202 .
As is further shown in Fig . 3B, according to this implementation, the coarse multiplexer 107 is shared among the di f ferent stages . Accordingly, the di f ferent comparators of the discriminator 210 are not calibrated in parallel but only one at a time (per frame ) .
According to the implementation shown in Fig . 3B, since the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111 and the coarse multiplexer 107 is not connected to the capacitor, the fine voltage may be resubtracted .
Fig . 3C shows a configuration, in which an output of the coarse multiplexer 107 is connected to the first terminal 137 of the capacitor 111 during phase < i . The output of the fine multiplexer 108 is connected to the first terminal 137 of the capacitor during phase 2 •
According to embodiments illustrated in Fig . 3D, the circuit arrangement 115 further comprises a voltage-current-converter 116 that is arranged between the coarse multiplexer 107 and the frontend circuit 202 . The output of the coarse multiplexer 107 is converted into a current by a voltage-current converter 116 and fed to the frontend circuit 202 via a switch . Accordingly, the coarse voltage signal is inj ected into the frontend circuit 202 as a current signal . The frontend circuit 202 multiplies this coarse current with its transimpedance ZFB, providing a voltage output proportional to
Fig . 3E shows a further embodiment of the circuit arrangement 115 , in which the frontend circuit 202 has a control input to set its output into a high impedance state by a control circuit 118 (HZ block) . As a result , the voltage may be directly overwritten at the input of the preampli fier 106 with a reference voltage during phase < i . The input to the control circuit 118 is a digital control signal ( logic 1 ) .
According to further concepts , the first buf fer 112 may be of fset compensated so as to eliminate the impact of buf fer of fset .
Fig . 4A shows an example o f a DAC 100 which may form part of a discriminator stage 210i . The DAC 100 may be implemented in any of the manners as discussed above . Further, the first buf fer 112 may be modi fied so as to be of fset compensated . In more detail , the buf fer 112 may be implemented as a circuit comprising an ampli fier 131 and a first buf fer capacitor 119 . Vref is applied to the inverting input of the amplifier 131. Vref is applied to the non-inverting input of the amplifier 131 via a switch 123 which is closed during phase < i . The first buffer capacitor 119 is arranged between an auxiliary input of the amplifier 131 and a ground terminal. An output of the amplifier 131 is fed back to the auxiliary input of the amplifier 131 via a switch 126 that is closed during phase < i .
During phase (pi, the switches 123 and 126 are closed. Vref is applied to the inverting and to the non-inverting input of the amplifier 131. Hence, the first buffer capacitor 119 is charged with charges corresponding to the offset voltage of the amplifier 131. During phase 2, which corresponds to phase < i as e.g. described with reference to Fig. 2A, the switches 123 and 126 are open. In this phase, the output of the amplifier 131 is offset compensated due to the charges stored in the first buffer capacitor 119. The output of amplifier 131 is connected to the gate electrode of transistor 134 which may be a P-MOSFET. The voltage supplied to the coarse and the fine resistor-strings 101 and 102 is forced to Vref. The voltage output of the coarse multiplexer 107 is stored on the capacitor 111.
During phase 3 which refers to a photon counting phase, the same processes as described above with reference to Fig. 2A are performed. In the diagram of Fig. 4A, the output of the frontend circuit 202 is denoted as Vin. A description of the frontend circuit 202 is omitted from this figure.
Fig. 4B shows a further example of a DAC 100 wherein the circuit implementing the first buffer 112 further comprises a second buffer capacitor 120. The second buffer capacitor 120 is connected to a node between the amplifier 131 and the gate electrode of the transistor 134. The circuit implementing the first the buffer 112 is further modified. Due to the presence of the second buffer capacitor 120, the DAC 100 may be operated in two phases instead of three phases. Accordingly, in order to reduce the number of phases, offset compensation of the first buffer 112 may be performed during the DAC operation phase 2 • In order to keep the coarse tree operational, the buffer output voltage is stored on the second buffer capacitor 120 to properly bias the transistor 134 current source during phase 2 • Depending on the length of phase (P2, leakage may cause significant droop in the coarse tree current. Further, the large second capacitor 120 connected to the buffer output may complicate frequency compensation .
Fig. 4C shows a further implementation of the first buffer 112 in which droop due to capacitor leakage may be avoided. According to the configuration illustrated in Fig. 4C the second buffer capacitor 120 is replaced by a second buffer circuit 125. Accordingly, as is illustrated in Fig. 4C, the DAC comprises a first buffer circuit 124 and a second buffer circuit 125. Each of the first and second buffer circuits 124, 125 comprises an amplifier and a first buffer capacitor 119. The respective switches are configured to be driven at complementary phases. Accordingly, only one buffer is connected to the coarse tree at a time while the other buffer is offset compensated. Accordingly, the combination of the first and the second buffer circuits implements a ping-pong buffer. Periodic swapping of the buffers results in refreshing of the buffer out of zero state. Accordingly, the DAC 100 illustrated in Fig. 4C may be operated faster.
Fig. 5A illustrates a further embodiment of a DAC 100 wherein the coarse and the fine resistor-strings 101, 102 may be implemented in an alternative way. The further components of the DAC may be similar to the one illustrated in e.g. Fig. 2A. Moreover, the DAC may further comprise a first buffer circuit 124 and a second buffer circuit 125 which has been e.g. explained with reference to Fig. 4C. As is to be clearly understood, the voltage supply of the coarse and the fine resistor-strings 101, 102 may be implemented in any arbitrary manner .
Differing from embodiments disclosed with reference to Fig. 4C, for example, a variable resistance string is introduced for the coarse resistor-string 101 and the fine resistorstring 102. Thereby, the average current consumption may be further reduced.
Typically, the coarse resistor-string 101 is implemented with a larger number of taps compared to the fine string, for matching purposes. Also, the fine resistor-string 102 covers a small range, typically equal or larger than the coarse string resolution. As a consequence, the fine string has a smaller resistance compared to the coarse string, making the dynamic settling in phase gy faster than the one in phase epi . Since during phase epi the capacitor 111 is charged, while during phase g>2 , only parasitic capacitances are charged, this effect is enhanced. As a consequence, during phase gy, settling is mostly limited by parasitic capacitances and the speed of the reference buffer. Considering the DAC illustrated in Fig. 4C, e.g. the string current is primarily dictated by the settling requirements of the RC circuit, comprising a coarse resistorstring 101, the coarse multiplexer 107, the capacitor 111 and the pre-amplifier 106 speed and significantly less by the dynamic of the resistor fine string 102.
As is shown in Fig. 5A, a low-ohmic fine resistor-string 129 may be added
Figure imgf000023_0001
parallel to a high-ohmic fine resistor- string 102. The high-ohmic fine resistor-string 102 has a larger resistance than the fine resistor-string 102 described herein before, e.g. with reference to Fig. 4C.
Further, a high-ohmic coarse resistor-string 127 may be added in parallel to a low-ohmic coarse resistor-string 101. The low-ohmic coarse resistor-string 101 has a smaller resistance than the coarse resistor-string 101 described hereinbefore, e.g. with reference to Fig. 4C.
During phase < i, when the fine multiplexer 108 is not connected to the capacitor 111, settling is important. During phase < i, a low ohmic resistor-string is needed. Accordingly, the parallel low-ohmic fine resistor-string 129 is added or substituted. During phase 2, power consumption is a concern because phase 2 covers the majority of the frame time. Accordingly, during phase >2 the high-ohmic fine string 102 is exercised and the coarse string is substituted by a high-ohmic resistor 127. Generally, a fine resistor unit may be made of several coarse resistor units in parallel to provide good matching.
By using a fraction of the current and a higher-ohmic string in phase 92, current and area are saved, as a lower number of parallel units are used in the fine resistor-string 102.
When one of the two coarse resistor-strings 127, 128 is not selected and no current is passing through it, the resistor elements composing the two paths are charged to Vref. When toggling to the next phase, the selected Rcoarse-path settles to its final operating point through a current loop that entails the string, its parasitic capacitances and the local ground, making the transients relatively fast and independent from the reference buffer. According to embodiments illustrated in Fig . 5A, the fine resistor-string digital-to-analog conversion unit 122 further comprises a low-ohmic fine resi stor-string 129 which is connected in parallel to the fine resistor-string 102 , a resistance of the low-ohmic fine resistor-string 129 being less than the resistance of the fine resistor-string 102 , the low-ohmic fine resistor-string 129 being configured to be connected to the fine multiplexer 108 when the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111 .
Moreover, the coarse resi stor-string digital-to-analog conversion unit 121 further comprises a high-ohmic coarse resistor-string 127 which is connected in parallel to the coarse resistor-string 101 , a resistance of the high-ohmic coarse resistor-string 127 being greater than the resistance of the coarse resistor-string 101 , the coarse resistor-string 127 being configured to be connected to the coarse multiplexer 107 when the coarse multiplexer 107 is connected to the first terminal 137 of the capacitor 111 .
The reference buf fer may sti ll be operable to regulate fast output current steps . The output stage si ze and compensation may be adapted to the phase dependent current .
According to embodiments illustrated in Fig . 5A, this may be achieved by disabling certain PMOS transistors on the sourceside through PMOS switches , thus keeping all PMOS elements biased and allowing a fast recovery through the low-ohmic on- resistance of the switch .
Fig . 5B shows further embodiments according to which it is possible to mitigate the capacitor droop . As is shown, the DAC 100 further comprises an additional resistor-string 135 comprising switches which may be selectively switched on or of f . Due to this additional resistor-string 135 , it is possible to compensate the capacitor droop . An extended range for the fine voltage may be achieved . A sub-LSB resolution may be achieved . For example , this additional resistor-string 135 may be controlled by means of a digital word which is adj usted dynamically to compensate for droop in the sampling capacitor . A possible operation is the following : during < i, the switches of 135 are all closed . During 92 , a digital word is programmed to compensate the capacitor droop . In this case , positive droop can be compensated .
Another possible operation is the following : during < i, a portion of the switches in additional resistor-string 135 are closed . During 92 , the digital word i s programmed to compensate the capacitor droop . In this case , both positive and negative droops can be compensated, by closing a higher or lower number of switches in the additional resistor-string 135 .
According to further embodiments , the additional resistorstring 135 may be arranged above the coarse resistor-string 101 . During 92 , the same operation principles described above are valid .
According to further embodiments , the additional resistorstring 135 may be arranged below the fine resistor-string 102 . In such embodiments , the additional resistor-string 135 may implement a total resistance equal to one resistor unit of the fine resistor-string 102 , enabling a dynamic capacitor droop compensation and sub-LSB resolution over fine DAC voltage during 2 • Fig. 6 shows an example of a photon counting system 20, comprising e.g. the DAC 100, which has been described above with reference to Fig. 4C. The photon counting system of Fig. 6 is similar to the photon counting system illustrated in Fig. 1 so that a detailed description of the components will be omitted. Differing from embodiments illustrated in Fig. 1, a single discriminator stage 210i and further components of the DAC 100 are implemented in a manner as has been described with reference to e.g. Fig. 4C. In more detail, the discriminator 200 which has been described with reference to Fig. 1, comprises a plurality of discriminator stages 2101 that may be implemented in a manner shown in Fig. 6. As is to be clearly understood, the discriminator stages 2101 and the further components of the DAC 100 may also be implemented in any other manner described herein above. The left side of Fig. 6 shows the different phases for operating the discriminator. As is shown, during phase <pa, a first frame 136 is detected, and the phase (pt corresponds to the second frame 136.
The photon counting system 20 may e.g. be a photon counting CT detector. In such an application X-ray photons are generated externally and are attenuated while traveling through the tissue or an object being analyzed. A photon detector 201 converts each incoming photon 21 into a charge packet which is processed by the CMOS frontend circuit 202. The amplitude of the voltage pulse resulting at the output of the frontend circuit 202 is discretized by means of an array of comparators 105, each being a component of a corresponding one of the discriminator stages 201i. The array of comparators 105 is supplied with an array of threshold voltages that cover the voltage pulse amplitude discretization range. The discriminator 200 comprises a cluster of n voltage DACs 100 , where the coarse resistor-string 101 and the fine resistor-string 102 are shared between all DACs 100 . The coarse voltages are stored on the respective capacitors 111 of the comparators 105 . As is illustrated, the counting frontend connects to the comparator array either through a switch or directly while making the frontend circuit 102 high-ohmic during phase < i .
In CT applications , it is important to keep the dead time ( time when incoming x-ray cannot be used for imaging) low in order to minimi ze dose exposure to the patient . Of fset compensation of the comparator must be completed during thi s short dead time window, allowing no time for a separate buf fer compensation phase . Therefore , as is illustrated in Fig . 6 , a ping-pong buf fer topology comprising a first buf fer circuit 124 and a second buf fer circuit 125 may be advantageously employed . Due to this concept , an idle buf fer circuit 124 , 125 may be of fset compensated during the full frame time while still providing an operational path by the other buf fer .
As has been explained, due to this figuration, the photon counting system may be employed in medical applications .
Fig . 7 shows a device for medical diagnosis 30 comprising the photon counting system 20 described hereinabove .
While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein .
LIST OF REFERENCES
20 Photon counting system
21 photons
30 device for medical diagnostics
100 , 100i, 1002 , ...100n digital-to-Analog converter
101 coarse resistor-string
102 fine resistor-string
103 bit string
104 switch
105 , 105i, 1052 , ...105n comparator
106 preampli fier
107 coarse multiplexer
108 fine multiplexer
109 combining unit
110 , 110i, 1102 , . . 110n counter
111 capacitor
112 first buf fer
113 second buf fer
114 resistor
115 circuit arrangement
116 voltage-current-converter
117 baseline control circuit
118 control circuit
119 first buf fer capacitor
120 second buf fer capacitor
121 coarse resistor-string digital-to-analog conversion unit
122 fine resistor-string digital-to-analog conversion unit
123 switch
124 first buf fer circuit
125 second buf fer circuit
126 switch
127 high-ohmic coarse resistor-string 129 low-ohmic fine resistor-string
131 amp 1 i f i e r
134 transistor
135 additional resistor-string 136 frame
137 first terminal of capacitor
200 discriminator
201 photon detector
202 frontend circuit 210i, 2102 , ...210n discriminator stage

Claims

1. A circuit arrangement (115) comprising a digital-to- analog converter (100, 100i, ...100n) , DAC, and a comparator (105, 105!, 1052, ...105n) , the DAC (100, 100i, ...100n) comprising: a coarse resistor-string digital-to-analog conversion unit (121) for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2; a fine resistor-string digital-to-analog conversion unit (122) for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit (109) for combining an output of the coarse resistor-string digital-to-analog conversion unit (121) and the output of the fine resistor-string digital-to-analog conversion unit (122) , the combining unit (109) comprising a capacitor (111) , the output of the fine resistor-string digital-to- analog conversion unit (122) being connectable to a first terminal (137) of the capacitor (111) , a second terminal of the capacitor (111) being connectable to a first input of the comparator (105, 105i, 1052, ...105n) .
2. The circuit arrangement (115) according to claim 1, wherein the output of the coarse resistor-string digital-to- analog conversion unit (121) is connectable to a second input of the comparator (105, 105i, 1052, ...105n) .
3. The circuit arrangement (115) according to claim 1, wherein the output of the coarse resistor-string digital-to- analog conversion unit (121) is connectable to a frontend circuit (202) , the frontend circuit (202) being configured to receive an input signal and to supply a processed signal to a second input of the comparator (105, 105i, 1052, ...105n) , the processed signal being generated on the basis of the input signal and the output of the coarse resistor-string digital- to-analog conversion unit (121) .
4. The circuit arrangement (115) according to claim 3, further comprising a voltage-current-converter (116) arranged between the coarse multiplexer (107) and the frontend circuit (202) .
5. The circuit arrangement (115) according to claim 1, wherein the output of the coarse resistor-string digital-to- analog conversion unit (121) is connectable to the first terminal (137) of the capacitor (111) , further comprising a frontend circuit (202) configured to receive an input signal and to supply a processed signal to a second input of the comparator (105, 105i, 1052, ...105n) , the frontend circuit (202) being permanently connected to the second input of the comparator (105, 105i, 1052, ...105n) , and the processed signal is generated on the basis of the input signal and the output of the coarse resistor-string digital-to-analog conversion unit (121) .
6. A discriminator (200) comprising a plurality of discriminator stages (210i, 2102, ...210n) , each of the discriminator stages (210i, 2IO2, ...210n) comprising a comparator (105, 105i, 1052, ...105n) , a coarse multiplexer being connectable to a selected tap between resistors of a coarse resistor-string for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2; a fine multiplexer being connectable to a selected tap between resistors of a fine resistor-string for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit for combining an output of the coarse multiplexer and the output of the fine multiplexer, the combining unit comprising a capacitor, the output of the fine multiplexer being connectable to a first terminal of the capacitor, a second terminal of the capacitor being connectable to a first input of the comparator (105, 105!, 1052, ...105n) .
7. The discriminator (200) according to claim 6, wherein the output of the coarse multiplexer (107) is connectable to a second input of the comparator (105, 105i, 1052, ...105n) .
8. The discriminator (200) according to claim 6, wherein the output of the coarse multiplexer (107) is connectable to a frontend circuit (202) configured to receive an input signal and to supply a processed signal to a second input of the comparator (105, 105i, 1052, ...105n) , the processed signal being based on the input signal and the output of the coarse multiplexer (107) .
9. A photon counting system (20) comprising the discriminator (200) according to any of claims 6 to 8.
10. A device for medical diagnostics (30) comprising the photon counting system (20) according to claim 9.
11. A Digital-to-Analog Converter (100, 100i, ...100n) , DAC, comprising : a coarse resistor-string digital-to-analog conversion unit (121) for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2; a fine resistor-string digital-to-analog conversion unit (122) for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, and a combining unit (109) for combining an output of the coarse resistor-string digital-to-analog conversion unit (121) and the output of the fine resistor-string digital-to-analog conversion unit (122) , the combining unit (109) comprising a capacitor (111) , the output of the coarse resistor-string digital-to-analog conversion unit (121) and the output of the fine resistor-string digital-to-analog conversion unit (122) being connectable to a first terminal (137) of the capacitor (111) , wherein the coarse resistor-string digital-to-analog conversion unit (121) comprises a coarse resistor-string (101) and a coarse multiplexer (107) configured to be connected to a selected tap between resistors of the coarse resistor-string
(101) , and the fine resistor-string digital-to-analog conversion unit (122) comprises a fine resistor-string (102) and a fine multiplexer (108) configured to be connected to a selected tap between resistors of the fine resistor-string (102) , the coarse resistor-string (101) and the fine resistor-string
(102) being connected in series.
12. The DAC (100, 100i, ...100n) according to claim 11, further comprising a first buffer (112) receiving a reference voltage and controlling a voltage supplied to the coarse resistor-string (101) .
13. The DAC (100, 100i, ...100n) according to claim 12, wherein the first buffer (112) comprises a first buffer capacitor (119) for storing an offset voltage. 14. The DAC (100, 100i, ...100n) according to claim 13, wherein the first buffer (112) further comprises a second buffer capacitor (120) for storing a reference voltage.
15. The DAC (100, 100i, ...100n) according to claim 13, wherein first buffer (112) comprises a first buffer circuit (124) and a second buffer circuit (125) , each of the first and the second buffer circuits (124, 125) comprising a first buffer capacitor (119) , respectively, the first buffer circuit (124) and the second buffer circuit (125) being configured to be alternatingly operated.
16. The DAC (100, 100i, ...100n) according to any of claims 11 to 15, wherein the coarse resistor-string digital-to-analog conversion unit (121) further comprises a high-ohmic coarse resistor-string (127) which is connected in parallel to the coarse resistor-string (121) , a resistance of the high-ohmic coarse resistor-string (127) being greater than the resistance of the coarse resistor-string (121) , the high-ohmic coarse resistor-string (127) being configured to be connected to the coarse multiplexer (107) when the coarse multiplexer (107) is connected to the first terminal (137) of the capacitor (111) .
17. The DAC (100, 100i, ...100n) according to any of claims 11 to 16, wherein the fine resistor-string digital-to-analog conversion unit (122) further comprises a low-ohmic fine resistor-string (129) which is connected in parallel to the fine resistor-string (102) , a resistance of the low-ohmic fine resistor-string (129) being less than the resistance of the fine resistor-string (102) , the low-ohmic fine resistor-string (102) being configured to be connected to the fine multiplexer (108) when the fine multiplexer (108) is connected to the first terminal (137) of the capacitor (111) .
18. The DAC (100, 100i, ...100n) according to any of claims 11 to 17, further comprising an additional switchable resistorstring (135) between the coarse resistor-string (101) and the fine resistor-string (102) .
PCT/EP2023/075398 2022-10-20 2023-09-15 Digital-to-analog converter, circuit arrangement, discriminator and photon counting system Ceased WO2024083418A1 (en)

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Citations (4)

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US20030234736A1 (en) * 2002-06-21 2003-12-25 Fujitsu Limited A/D converter
US7075469B2 (en) * 2003-06-30 2006-07-11 Renesas Technology Corp. Semiconductor integrated circuit
US20070030191A1 (en) * 2005-07-28 2007-02-08 Kabushiki Kaisha Toshiba A/D converter
WO2022214663A1 (en) * 2021-04-09 2022-10-13 Ams International Ag Digital to analogue voltage converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030234736A1 (en) * 2002-06-21 2003-12-25 Fujitsu Limited A/D converter
US7075469B2 (en) * 2003-06-30 2006-07-11 Renesas Technology Corp. Semiconductor integrated circuit
US20070030191A1 (en) * 2005-07-28 2007-02-08 Kabushiki Kaisha Toshiba A/D converter
WO2022214663A1 (en) * 2021-04-09 2022-10-13 Ams International Ag Digital to analogue voltage converter

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