WO2024066218A1 - 掩膜版及其布局方法、芯片的排版图形 - Google Patents

掩膜版及其布局方法、芯片的排版图形 Download PDF

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Publication number
WO2024066218A1
WO2024066218A1 PCT/CN2023/080919 CN2023080919W WO2024066218A1 WO 2024066218 A1 WO2024066218 A1 WO 2024066218A1 CN 2023080919 W CN2023080919 W CN 2023080919W WO 2024066218 A1 WO2024066218 A1 WO 2024066218A1
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WIPO (PCT)
Prior art keywords
chip
area
pattern
marking
mask
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PCT/CN2023/080919
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English (en)
French (fr)
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WO2024066218A9 (zh
Inventor
金枝
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长鑫存储技术有限公司
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Publication of WO2024066218A1 publication Critical patent/WO2024066218A1/zh
Publication of WO2024066218A9 publication Critical patent/WO2024066218A9/zh

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a mask plate and a layout method thereof, and a layout pattern of a chip.
  • photolithography is the most important pattern transfer process, among which, mask is an important tool for realizing photolithography and can be used to make the circuit layout of semiconductor chips.
  • the mask mainly includes a chip pattern area, which mainly includes chip patterns and cutting lanes distributed around the periphery of each chip pattern.
  • the existing cutting lanes are relatively wide and occupy a large space, so that the number of chip patterns that can be accommodated in the mask is relatively small, and the space utilization rate of the mask is relatively low.
  • the present disclosure provides a mask and a layout method thereof, and a layout pattern of a chip, which can improve the utilization rate of the mask, reduce the number of exposures, reduce manufacturing costs, and improve production capacity.
  • a mask comprising: a chip pattern area, the chip pattern area comprising a plurality of chip pattern groups spaced apart along a first direction, the chip pattern group comprising a plurality of chip patterns spaced apart along a second direction, the first direction intersecting the second direction;
  • a cutting area is provided on the periphery of each chip pattern, in which a marking pattern is formed; a test pattern area is provided between the cutting area and the adjacent chip pattern, in which a test pattern is formed; the width of a portion extending along the second direction in the test pattern area is smaller than the width of a portion extending along the first direction, or the width of a portion extending along the first direction in the test pattern area is smaller than the width of a portion extending along the second direction.
  • the cutting area is in a ring shape surrounding the chip pattern.
  • two adjacent chip patterns share the cutting area located between the two chip patterns.
  • the shape of the marking pattern is the same as the shape of the cutting area, and the marking pattern covers the entire cutting area.
  • the cutting area is a rectangular area, the rectangular areas located at the periphery of different chip patterns are equal in size, and the cutting areas located at the edge area of the chip pattern area are connected to each other to form an edge cutting area.
  • the number of the marking patterns is four, and the four marking patterns are distributed around the chip pattern in a one-to-one correspondence.
  • the mask further includes a light-shielding area, and the light-shielding area is in a ring shape and surrounds the chip pattern area.
  • the light shielding area is disposed in the edge cutting area and is located on a side of the marking pattern away from the test pattern.
  • a mask layout method comprising:
  • a mask is provided, wherein the mask includes a chip pattern area, wherein the chip pattern area includes a plurality of chip pattern groups spaced apart along a first direction, wherein the chip pattern group includes a plurality of chip patterns spaced apart along a second direction, wherein the first direction intersects with the second direction; wherein a cutting area is provided on the periphery of each chip pattern, wherein a test pattern area is provided between the cutting area and the chip pattern adjacent thereto, wherein a width of a portion of the test pattern area extending along the second direction is smaller than a width of a portion thereof extending along the first direction, or wherein the test pattern area The width of a portion of the graphic region extending along the first direction is smaller than the width of a portion thereof extending along the second direction;
  • a test pattern is formed in the test pattern area.
  • the cutting area is in a ring shape surrounding the chip pattern.
  • two adjacent chip patterns share the cutting area located between the two chip patterns.
  • the shape of the marking pattern is the same as the shape of the cutting area, and the marking pattern covers the entire cutting area.
  • the cutting area is a rectangular area, the rectangular areas located at the periphery of different chip patterns are equal in size, and the cutting areas located at the edge area of the chip pattern area are connected to each other to form an edge cutting area.
  • the number of the marking patterns is four, and the four marking patterns are distributed around the chip pattern in a one-to-one correspondence.
  • the mask further includes a light-shielding area, and the light-shielding area is in a ring shape and surrounds the chip pattern area.
  • the light shielding area is disposed in the edge cutting area and is located on a side of the marking pattern away from the test pattern.
  • a layout pattern of a chip comprising: a plurality of chip pattern groups spaced apart along a first direction, the chip pattern groups comprising a plurality of chip patterns spaced apart along a second direction, the first direction intersecting with the second direction; a marking pattern being provided at the periphery of each of the chip patterns, a test pattern being provided between the marking pattern and the chip pattern adjacent thereto, the width of a portion of the test pattern extending along the second direction being smaller than the width of a portion thereof extending along the first direction, or the width of a portion of the test pattern extending along the first direction being smaller than the width of a portion thereof extending along the second direction.
  • the mask and layout method thereof, and the layout pattern of the chip disclosed in the present invention can be shortened because the width of the test pattern area in the first direction is smaller than the width of the test pattern area in the second direction.
  • the spacing between two adjacent chip patterns in the first direction in the chiplet pattern area saves more space in the first direction, and then a group of chip pattern groups can be added in the first direction; or, in the second direction, the width of the test pattern area is smaller than the width of the test pattern area in the first direction, which can reduce the spacing between two adjacent chip patterns in the second direction in the chip pattern area, so that more space is saved in the second direction, and then a group of chip pattern groups can be added in the second direction, which can improve the utilization rate of the mask.
  • the mask disclosed in the present invention can expose one more group of chip patterns each time during the exposure process using the mask.
  • the mask disclosed in the present invention is used to expose a whole wafer containing a larger number of chips, since each mask can expose more chip groups each time, the number of masks used can be reduced, the number of exposures can be reduced, the manufacturing cost can be reduced, and the production capacity can be improved when the total number of chip groups to be exposed remains unchanged.
  • the mark pattern in the cutting area can be used as a positioning mark to avoid offset during the use of the mask, avoid structural errors caused by mask offset, and help improve product yield.
  • FIG1 is a schematic diagram of a mask in the related art
  • FIG2 is a schematic diagram of a mask in one embodiment of the present disclosure.
  • FIG3 is an enlarged schematic diagram of area A in FIG2 ;
  • FIG4 is a schematic diagram of a mask in one embodiment of the present disclosure.
  • FIG5 is a flow chart of a mask layout method in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a layout diagram of a chip in an embodiment of the present disclosure.
  • FIG. 7 is an enlarged schematic diagram of region B in FIG. 6 .
  • the mask is one of the important tools in the semiconductor lithography process.
  • the mask can be used to layout the chip pattern.
  • the mask pattern in the mask can be transferred to the wafer to form a chip layout pattern.
  • the mask mainly includes a chip pattern area and a light shielding area located outside the chip pattern area.
  • the chip pattern area includes a plurality of chip patterns 100.
  • the cutting lanes are usually provided with marking patterns 200 and test patterns 300.
  • the cutting lanes are An increasing number of test patterns 300 need to be placed inside the cutting path, which increases the width of the cutting path and occupies a larger and larger space, thereby reducing the space in the mask plate for setting the chip pattern 100.
  • the number of chip patterns 100 in the mask plate is small, and the space utilization rate of the mask plate is low.
  • the shading area 400 is also usually set in the cutting path. Since the setting of the test pattern 300 and the mark pattern has already occupied a large space, and the setting of the shading area makes the width of the cutting path in the edge area larger, the space for setting the chip pattern 100 is further reduced, and the space utilization rate of the mask plate is low.
  • FIG2 shows a schematic diagram of the mask of the present disclosure.
  • the mask of the present disclosure may include a chip pattern area, the chip pattern area may include a plurality of chip pattern groups spaced apart along a first direction a, the chip pattern group may include a plurality of chip patterns 1 spaced apart along a second direction b, and the first direction a intersects the second direction b;
  • a cutting area 2 may be provided on the periphery of each chip pattern 1, and a marking pattern may be formed in the cutting area 2; a test pattern area 3 may be provided between the cutting area 2 and the adjacent chip pattern 1, and a test pattern may be formed in the test pattern area 3; in the first direction a, the width of the test pattern area 3 may be smaller than the width of the test pattern area 3 in the second direction b, or, in the second direction b, the width of the test pattern area 3 may be smaller than the width of the test pattern area 3 in the first direction a.
  • the mask disclosed in the present invention can reduce the distance between two adjacent chip patterns 1 in the chip pattern area in the first direction a, because the width of the test pattern area 3 in the first direction a is smaller than the width of the test pattern area 3 in the second direction b, so that more space can be saved in the first direction a, and then a group of chip pattern groups can be added in the first direction a; or, in the second direction b, the width of the test pattern area 3 is smaller than the width of the test pattern area 3 in the first direction a, so that the distance between two adjacent chip patterns 1 in the chip pattern area in the second direction b can be reduced, so that more space can be saved in the second direction b, and then a group of chip pattern groups can be added in the second direction b, which can improve the utilization rate of the mask.
  • the mask disclosed in the present invention can expose one more group of chip patterns 1 each time during the process of using the mask for exposure, and the mask disclosed in the present invention can be used for a larger number of When a whole wafer of chips is exposed, since each mask can expose more chipsets each time, the number of masks used can be reduced while the total number of chipsets to be exposed remains unchanged, the number of exposures can be reduced, the manufacturing cost can be reduced, and the production capacity can be improved.
  • the marking pattern in the cutting area 2 can be used as a positioning mark to avoid offset during the use of the mask, avoid structural errors caused by mask offset, and help improve product yield.
  • the chip pattern area may be an artificially set mask pattern area, which may be a rectangular area, a circular area, an elliptical area or an irregular pattern area, and is not particularly limited here.
  • the chip graphic area may include a plurality of chip graphics 1 distributed in an array, and the chip graphics 1 may match the shape of the chip unit that is ultimately required to be formed in the wafer.
  • the chip graphics 1 may be the same as the shape of the chip unit that is ultimately required to be formed in the wafer.
  • the shape of the chip graphics 1 may also be a rectangle; when the shape of the chip unit that is ultimately required to be formed in the wafer is a circle, the shape of the chip graphics 1 may also be a circle; when the shape of the chip unit that is ultimately required to be formed in the wafer is an ellipse, the shape of the chip graphics 1 may also be an ellipse; when the shape of the chip unit that is ultimately required to be formed in the wafer is a polygon, the shape of the chip graphics 1 may also be a polygon.
  • the shape of the chip graphics 1 may also be other shapes that match its shape, which are not listed one by one here.
  • the size of the chip pattern 1 may match the size of the chip unit that is ultimately required to be formed in the wafer.
  • the size of the chip pattern 1 may be the same as the size of the chip unit that is ultimately required to be formed in the wafer.
  • the chip pattern area may include multiple chip pattern groups, each chip pattern group may be spaced apart along a first direction a, each chip pattern group may include multiple chip patterns 1, each chip pattern 1 may be spaced apart along a second direction b.
  • the first direction a can be any direction in the extension direction of the mask, and the first direction a can intersect with the second direction b.
  • the first direction a and the second direction b can be perpendicular to each other.
  • perpendicularity can be absolutely perpendicular or approximately perpendicular.
  • the angle deviation may be caused by the manufacturing process limitation, so that the angle between the first direction a and the second direction b has a certain deviation. As long as the angle deviation between the first direction a and the second direction b is within the preset range, it can be considered that the first direction a Perpendicular to the second direction b.
  • the preset range may be 10°, that is, when the angle between the first direction a and the second direction b is greater than or equal to 80° and less than or equal to 100°, the first direction a and the second direction b may be considered perpendicular.
  • a cutting area 2 may be provided on the periphery of each chip graphic 1, and the cutting area 2 may be annular, and the annular shape may surround the chip graphic 1.
  • the cutting area 2 may be a rectangular area.
  • the cutting area 2 may be a rectangular annular area, and the sizes of the rectangular areas located on the peripheries of different chip graphics 1 may be equal.
  • the cutting areas 2 on the peripheries of different chip graphics 1 may all be rectangular annular areas, and the long sides of the rectangular annular areas located on the peripheries of different chip graphics 1 may all be equal, and at the same time, the short sides of the rectangular annular areas located on the peripheries of different chip graphics 1 may also all be equal.
  • the width of the cutting area 2 can be reduced to a certain extent.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 is equal everywhere.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can be 60um to 90um.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can be 60um, 70um, 80um or 90um.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can also be other, which will not be listed here one by one.
  • the short sides of the rectangular annular area can extend along the first direction a, and at the same time, the long sides of the rectangular annular area can extend along the second direction b; or, the short sides of the rectangular annular area can extend along the second direction b, and at the same time, the long sides of the rectangular annular area can extend along the first direction a.
  • No special limitation is made on the extension directions of the long and short sides of the rectangular annular area.
  • two adjacent chip graphics 1 can share the cutting area 2 located between the two chip graphics 1, which can reduce the distance between the two adjacent chip graphics 1, help save the space of the mask, and improve the space utilization rate of the mask.
  • the two adjacent chip graphics 1 can share the long sides of the rectangular annular area, and in the second direction b, the two adjacent chip graphics 1 can share the short sides of the rectangular annular area; for another example, when the short sides of the rectangular annular area extend in the second direction b, and the long sides of the rectangular annular area extend in the first direction b,
  • two adjacent chip patterns 1 can share the short side of the rectangular annular area, and in the second direction b, two adjacent chip patterns 1 can share the long side of the rectangular annular area.
  • a marking pattern may be formed in the cutting area 2.
  • the marking pattern may be used for alignment, and it may serve as an alignment mark to avoid shifting during the use of the mask, avoid structural errors caused by mask shifting, and help improve product yield.
  • the marking pattern may be rectangular, circular, polygonal or irregular, and is not particularly limited here.
  • the shape of the marking pattern may be the same as the shape of the cutting area 2, and the size of each area thereof may match the size of the cutting area 2, that is, the marking pattern may be a whole continuous pattern, and the pattern may cover the entire cutting area 2.
  • the marking pattern may also be in the shape of a rectangular ring, and the spacing between the inner ring and the outer ring thereof is equal to the width of the cutting area 2.
  • the number of marking graphics may be multiple, and the shapes of different marking graphics may be the same or different, and no special limitation is made here.
  • some marking graphics may be rectangular, some marking graphics may be circular, some marking graphics may be "L-shaped", and some marking graphics may be "T-shaped".
  • the marking graphics may also be other graphics, which are not listed here one by one.
  • the multiple marking graphics may also all be rectangular; or, the marking graphics may all be circular; or, the marking graphics may all be irregular graphics, and no special limitation is made here on the shape of each marking graphic.
  • At least some of the multiple marking patterns may be distributed at intervals in the cutting area 2.
  • at least some of the multiple marking patterns may be distributed at intervals along the extension direction of the cutting area 2.
  • each marking pattern may be distributed at intervals, and each marking pattern may be evenly distributed in the cutting area 2.
  • the number of the marking patterns can be four, and the four marking patterns can be distributed one by one around the chip pattern 1.
  • the marking pattern can be "L" shaped, and the four "L” shaped marking patterns can be respectively arranged at the four corners of the rectangular ring cutting area 2.
  • the extension direction of the long side of the "L” shape can be consistent with the extension direction of the long side of the rectangular ring area, and at the same time, the short side of the "L” shape can be consistent with the short side of the rectangular ring area.
  • the extension direction of the edge can be consistent with the extension direction of the short side of the rectangular annular area; or, the extension direction of the long side of the "L" shape can be consistent with the extension direction of the short side of the rectangular annular area, and at the same time, the extension direction of the short side of the "L” shape can be consistent with the extension direction of the long side of the rectangular annular area.
  • the marking pattern located in the cutting area 2 may be the first type of marking pattern 21, which may be used to perform preliminary alignment and positioning of the mask.
  • a marking pattern may also be provided between the test pattern area 3 and the chip pattern 1, which may be the second type of marking pattern 22, which may be used to accurately position the mask, thereby better avoiding mask offset.
  • the cutting areas 2 located in the edge area of the chip graphic area may be connected to each other to form an edge cutting area.
  • the edge cutting area may be an area surrounded by the boundaries of the cutting areas 2 located in the edge area of the chip graphic area away from the center of the chip graphic area.
  • the edge cutting area 2 may be a rectangle, a polygon or an irregular shape, which is not particularly limited here.
  • the edge cutting area formed by connecting the cutting areas 2 in the edge area of the chip graphic area may be a rectangular annular area, and the rectangular annular area may enclose each chip graphic 1.
  • the mask of the present disclosure may further include a light shielding area 4, which may be in a ring shape and surround the chip pattern area.
  • the light shielding area 4 may be used as a splicing area of adjacent mask plates.
  • a light shielding belt may be provided in the light shielding area 4, and the splicing area may be shielded by the light shielding belt to avoid structural defects in the final product due to repeated exposure.
  • the shading area 4 may be located in the edge cutting area, and the shading area 4 and the marking pattern in the edge cutting area may be arranged side by side, and the shading area 4 may be located on the side of the marking pattern away from the test pattern.
  • the shading areas 4 at the edges of each mask may be connected to each other, thereby forming a complete shading area 4 between the two masks.
  • the space utilization rate of the mask is improved, the empty space at the edge of the mask is reduced, and at the same time, due to the edge cutting of the mask
  • the width of the cut region 2 is relatively small, which can reduce the width of the light-shielding band to a certain extent, further saving the space of the mask.
  • test pattern area 3 there is no contact between the cutting area 2 and the chip pattern 1 adjacent thereto, and there may be a test pattern area 3 between the cutting area 2 and the chip pattern 1 adjacent thereto, and the test pattern area 3 may be an area surrounded by the outer periphery of the chip pattern 1 and the inner ring of the cutting area 2. That is, the test pattern area 3 is an area between the outer periphery of the chip pattern 1 and the inner ring of the cutting area 2, and the test pattern area 3 may be annularly surrounding the outer periphery of the chip pattern 1, and the inner ring of the test pattern area 3 may be adjacent to the chip pattern 1, and its outer ring may be adjacent to the inner ring of the cutting area 2.
  • the test pattern area 3 may also be a rectangular annular area; when the chip pattern 1 is a circle and the cutting area 2 is a circular annular area, the test pattern area 3 may also be a circular annular area; of course, when the chip pattern 1 is other shapes and the cutting area 2 is also annular areas of other shapes, the test pattern area 3 may also be annular areas of other shapes, and no special limitation is made on the shape of the test pattern area 3.
  • test pattern may be formed in the test pattern area 3, and the test pattern may be used to form a test pad, and then collect data in the chip unit through the test pad.
  • the test pattern may be rectangular, circular, polygonal or irregular, and is not particularly limited here.
  • the number of test patterns may be multiple.
  • each test pattern may be divided into two test pattern groups, and the two test pattern groups may be arranged at intervals along the second direction b, and each test pattern group may include multiple test patterns distributed along the first direction a. In the second direction b, two rows of test pattern groups may be located on both sides of the chip pattern 1.
  • each test pattern may be divided into two test pattern groups, and the two test pattern groups may be arranged at intervals along the first direction a, and each test pattern group may include multiple test patterns distributed along the second direction b. In the first direction a, two rows of test pattern groups may be located on both sides of the chip pattern 1.
  • each test pattern may be divided into four test pattern groups, wherein two test pattern groups may be arranged at intervals along the second direction b, and each test pattern group may include multiple test patterns distributed along the first direction a.
  • test pattern groups can be located on both sides of the chip pattern 1; the other two test pattern groups can be arranged at intervals along the first direction a, and each test pattern group can include multiple test patterns distributed along the second direction b. Both sides.
  • the first direction a may be the direction of the short side of the test pattern (i.e., the width direction of the chip), and the second direction b may be the direction of the long side of the test pattern (i.e., the length direction of the chip), and the test patterns may be arranged as much as possible on both sides of the width direction of the chip pattern 1, which helps to reduce the number of test patterns arranged on both sides of the length direction of the chip pattern 1, and further compress the width of the test pattern area 3 located on both sides of the length direction of the chip pattern 1 (i.e., the first direction a), and reduce the distance between two adjacent chip patterns 1 in the chip pattern area located in the first direction a, so that more space is saved in the first direction a, and further a group of chip pattern groups may be added in the first direction a (for example, in a mask, the chip pattern groups are changed from the original 3 columns to 4 columns), which can improve the utilization rate
  • the width of the portion of the test pattern area 3 extending along the second direction b may be smaller than the width of the portion extending along the first direction a (i.e., the width direction of the chip), and as many test patterns as possible may be arranged in the test pattern area 3 extending along the width direction of the chip pattern 1.
  • the first direction a may be the direction of the short side of the test pattern (i.e., the width direction of the chip), and the second direction b may be the direction of the long side of the test pattern (i.e., the length direction of the chip), and the test patterns may be arranged as much as possible on both sides of the length direction of the chip pattern 1, which helps to reduce the number of test patterns arranged on both sides of the width direction of the chip pattern 1, and further compress the width of the test pattern area 3 located on both sides of the width direction of the chip pattern 1 (i.e., the second direction b), and reduce the distance between two adjacent chip patterns 1 in the chip pattern area in the second direction b, so that more space is saved in the second direction b, and further a group of chip pattern groups may be added in the second direction b (for example, in a mask, the chip pattern groups are changed from the original 3 rows to 4 rows), which can improve the utilization rate of
  • the width of the portion of the test pattern area 3 extending along the first direction a may be smaller than the width of the portion extending along the second direction b (i.e., the length direction of the chip).
  • the width of the part can be set as much as possible in the test pattern area 3 extending along the length direction of the chip pattern 1.
  • FIG5 shows a flow chart of the mask layout method of the present disclosure.
  • the layout method includes steps S110 to S130, wherein:
  • Step S110 providing a mask, the mask comprising a chip pattern area, the chip pattern area comprising a plurality of chip pattern groups spaced apart along a first direction a, the chip pattern group comprising a plurality of chip patterns 1 spaced apart along a second direction b, the first direction a intersecting the second direction b;
  • a cutting area 2 is provided at the periphery of each chip pattern 1
  • a test pattern area 3 is provided between the cutting area 2 and the chip pattern 1 adjacent thereto, the width of a portion of the test pattern area 3 extending along the second direction b is smaller than the width of a portion thereof extending along the first direction a, or the width of a portion of the test pattern area 3 extending along the first direction a is smaller than the width of a portion thereof extending along the second direction b;
  • Step S120 forming a marking pattern in the cutting area 2;
  • Step S130 forming a test pattern in the test pattern area 3 .
  • the spacing between two adjacent chip patterns 1 in the chip pattern area in the first direction a can be reduced, so that more space can be saved in the first direction a, and then a group of chip pattern groups can be added in the first direction a; or, in the second direction b, the width of the test pattern area 3 is smaller than the width of the test pattern area 3 in the first direction a, the spacing between two adjacent chip patterns 1 in the chip pattern area in the second direction b can be reduced, so that more space can be saved in the second direction b, and then a group of chip pattern groups can be added in the second direction b, which can improve the utilization rate of the mask.
  • the mask disclosed in the present invention can expose one more group of chip patterns 1 each time during the process of using the mask for exposure.
  • the mask disclosed in the present invention is used to expose a whole wafer containing a larger number of chips, since each mask can expose more chip groups each time, the number of masks used can be reduced, the number of exposures can be reduced, the manufacturing cost can be reduced, and the production capacity can be improved.
  • the marking pattern in the cutting area 2 can be used as an alignment mark to avoid offset during the use of the mask and avoid structural errors caused by mask offset, which helps to improve product yield.
  • a mask is provided, wherein the mask includes a chip graphic area, wherein the chip graphic area includes a plurality of chip graphic groups spaced apart along a first direction a, wherein the chip graphic groups include a plurality of chip graphics 1 spaced apart along a second direction b, wherein the first direction a intersects with the second direction b; a cutting area 2 is provided on the periphery of each of the chip graphics 1, wherein a test graphic area 3 is provided between the cutting area 2 and the chip graphics 1 adjacent thereto, wherein a width of a portion of the test graphic area 3 extending along the second direction b is smaller than a width of a portion thereof extending along the first direction a, or a width of a portion of the test graphic area 3 extending along the first direction a is smaller than a width of a portion thereof extending along the second direction b.
  • the chip pattern area may be an artificially set mask pattern area, which may be a rectangular area, a circular area, an elliptical area or an irregular pattern area, and is not particularly limited here.
  • the chip graphic area may include a plurality of chip graphics 1 distributed in an array, and the chip graphics 1 may match the shape of the chip unit that is ultimately required to be formed in the wafer.
  • the chip graphics 1 may be the same as the shape of the chip unit that is ultimately required to be formed in the wafer.
  • the shape of the chip graphics 1 may also be a rectangle; when the shape of the chip unit that is ultimately required to be formed in the wafer is a circle, the shape of the chip graphics 1 may also be a circle; when the shape of the chip unit that is ultimately required to be formed in the wafer is an ellipse, the shape of the chip graphics 1 may also be an ellipse; when the shape of the chip unit that is ultimately required to be formed in the wafer is a polygon, the shape of the chip graphics 1 may also be a polygon.
  • the shape of the chip graphics 1 may also be other shapes that match its shape, which are not listed one by one here.
  • the size of the chip pattern 1 may match the size of the chip unit that is ultimately required to be formed in the wafer.
  • the size of the chip pattern 1 may be the same as the size of the chip unit that is ultimately required to be formed in the wafer.
  • the chip pattern area may include multiple chip pattern groups, each chip pattern group may be spaced apart along a first direction a, each chip pattern group may include multiple chip patterns 1, each chip pattern 1 may be spaced apart along a second direction b.
  • first direction a may be any direction in which the mask extends, and the first direction a may intersect with the second direction b.
  • first direction a and the second direction b may be perpendicular to each other.
  • the cutting area 2 may be annular, and the ring may surround the chip pattern 1.
  • the cutting area 2 may be a rectangular area.
  • the cutting area 2 may be a rectangular annular area, and the sizes of the rectangular areas located at the peripheries of different chip patterns 1 may be equal.
  • the width of the cutting area 2 can be reduced to a certain extent.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 is equal everywhere.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can be 60um to 90um.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can be 60um, 70um, 80um or 90um.
  • the spacing between the inner ring and the outer ring in the annular cutting area 2 can also be other, which will not be listed here one by one.
  • test pattern area 3 there is no contact between the cutting area 2 and the chip pattern 1 adjacent thereto, and there may be a test pattern area 3 between the cutting area 2 and the chip pattern 1 adjacent thereto, and the test pattern area 3 may be an area surrounded by the outer periphery of the chip pattern 1 and the inner ring of the cutting area 2. That is, the test pattern area 3 is an area between the outer periphery of the chip pattern 1 and the inner ring of the cutting area 2, and the test pattern area 3 may be annularly surrounding the outer periphery of the chip pattern 1, and the inner ring of the test pattern area 3 may be adjacent to the chip pattern 1, and its outer ring may be adjacent to the inner ring of the cutting area 2.
  • the test pattern area 3 may also be a rectangular annular area; when the chip pattern 1 is a circle and the cutting area 2 is a circular annular area, the test pattern area 3 may also be a circular annular area; of course, when the chip pattern 1 is other shapes and the cutting area 2 is also annular areas of other shapes, the test pattern area 3 may also be annular areas of other shapes, and no special limitation is made on the shape of the test pattern area 3.
  • step S120 a marking pattern is formed in the cutting area 2 .
  • an etching process can be used to form a marking pattern in the cutting area 2.
  • the marking pattern can be used for alignment. It can serve as an alignment mark to avoid offset during the use of the mask and avoid structural errors caused by mask offset, thereby helping to improve product yield.
  • the marking pattern may be rectangular, circular, polygonal or irregular, and is not particularly limited here.
  • the shape of the marking pattern may be consistent with the shape of the cutting area 2.
  • the size of each area can match the size of the cutting area 2, that is, the marking pattern can be a whole continuous pattern, and the pattern can cover the cutting area 2.
  • the marking pattern can also be a rectangular ring, and the distance between the inner ring and the outer ring is equal to the width of the cutting area 2.
  • the number of marking graphics may be multiple, and the shapes of different marking graphics may be the same or different, and no special limitation is made here.
  • some marking graphics may be rectangular, some marking graphics may be circular, some marking graphics may be "L-shaped", and some marking graphics may be "T-shaped”.
  • the marking graphics may also be other graphics, which are not listed here one by one.
  • the multiple marking graphics may also be rectangular; or, the marking graphics may also be circular; or, the marking graphics may also be irregular graphics, and no special limitation is made here on the shape of each marking graphic.
  • step S130 a test pattern is formed in the test pattern area 3 .
  • test pattern can be formed in the test pattern area 3 by etching or other means, and the test pattern can be used to form a test pad, and then collect data in the chip unit through the test pad.
  • the test pattern can be rectangular, circular, polygonal or irregular, and is not particularly limited here.
  • the number of test patterns can be multiple.
  • each test pattern can be divided into two test pattern groups, and the two test pattern groups can be arranged at intervals along the second direction b, and each test pattern group can include multiple test patterns distributed along the first direction a. In the second direction b, two rows of test pattern groups can be located on both sides of the chip pattern 1.
  • each test pattern can be divided into two test pattern groups, and the two test pattern groups can be arranged at intervals along the first direction a, and each test pattern group can include multiple test patterns distributed along the second direction b.
  • first direction a two rows of test pattern groups can be located on both sides of the chip pattern 1.
  • each test pattern can be divided into four test pattern groups, wherein two test pattern groups can be arranged at intervals along the second direction b, and each test pattern group can include multiple test patterns distributed along the first direction a.
  • two rows of test pattern groups can be located on both sides of the chip pattern 1 respectively; the other two test pattern groups can be arranged at intervals along the first direction a, and each test pattern group can include multiple test patterns distributed along the second direction b.
  • first direction a two rows of test pattern groups can be located on both sides of the chip pattern 1 respectively.
  • the chip layout graphic 500 of the present disclosure may include a plurality of chip graphic groups 501 spaced apart along a first direction a, the chip graphic group 501 includes a plurality of chip graphics 1 spaced apart along a second direction b, the first direction a intersects with the second direction b; a marking graphic is provided on the periphery of each chip graphic 1, a test graphic is provided between the marking graphic and the chip graphic 1 adjacent thereto, the width of a portion of the test graphic extending along the second direction b is smaller than the width of a portion thereof extending along the first direction a, or the width of a portion of the test graphic extending along the first direction a is smaller than the width of a portion thereof extending along the second direction b.
  • the chip layout pattern in the present disclosure can be transferred from the mask in any of the above-mentioned embodiments.
  • Other details and beneficial effects of the layout pattern can be referred to the mask in any of the above-mentioned embodiments, which will not be described in detail here.

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Abstract

一种掩膜版及其布局方法、芯片的排版图形（500）。掩膜版包括：芯片图形区，芯片图形区包括多个沿第一方向（a）间隔分布的芯片图形组（501），芯片图形组（501）包括多个沿第二方向（b）间隔分布的芯片图形（1），第一方向（a）与第二方向（b）相交；每个芯片图形（1）的外周均设有切割区域（2），切割区域（2）内形成有标记图形；切割区域（2）和与其相邻的芯片图形（1）之间为测试图形区域（3），测试图形区域（3）内形成有测试图形；测试图形区域（3）中沿第二方向（b）延伸的部分的宽度小于其沿第一方向（a）延伸的部分的宽度，或者，测试图形区域（3）中沿第一方向（a）延伸的部分的宽度小于其沿第二方向（b）延伸的部分的宽度。

Description

掩膜版及其布局方法、芯片的排版图形
交叉引用
本公开要求于2022年9月28日提交的申请号为202211193868.9名称为“掩膜版及其布局方法、芯片的排版图形”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种掩膜版及其布局方法、芯片的排版图形。
背景技术
在半导体制造的过程中，光刻工艺是最重要的图形转移工艺，其中，掩膜版(mask)是实现光刻工艺的重要工具，可以用于制作半导体芯片的电路版图。
掩膜版主要包括芯片图形区，该芯片图形区主要包括芯片图形及分布在各芯片图形外周的切割道，然而，现有切割道较宽，占用空间较大，使得掩膜版中能够容纳的芯片图形的数量较少，掩膜版的空间利用率较低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种掩膜版及其布局方法、芯片的排版图形，可提高掩膜版的利用率，减少曝光次数，降低制造成本，提升产能。
根据本公开的一个方面，提供一种掩膜版，包括：芯片图形区，所述芯片图形区包括多个沿第一方向间隔分布芯片图形组，所述芯片图形组包括多个沿第二方向间隔分布的芯片图形，所述第一方向与所述第二方向相交；
每个所述芯片图形的外周均设有切割区域，所述切割区域内形成有标记图形；所述切割区域和与其相邻的所述芯片图形之间为测试图形区域，所述测试图形区域内形成有测试图形；所述测试图形区域中沿所述第二方向延伸的部分的宽度小于其沿所述第一方向延伸的部分的宽度，或者，所述测试图形区域中沿所述第一方向延伸的部分的宽度小于其沿所述第二方向延伸的部分的宽度。
在本公开的一种示例性实施例中，所述切割区域呈环形围绕所述芯片图形一周。
在本公开的一种示例性实施例中，相邻的两个所述芯片图形共用位于两个所述芯片图形之间的所述切割区域。
在本公开的一种示例性实施例中，所述标记图形的形状与所述切割区域的形状相同，所述标记图形铺满所述切割区域。
在本公开的一种示例性实施例中，所述标记图形的数量为多个，各所述标记图形中至少部分所述标记图形在所述切割区域内间隔分布。
在本公开的一种示例性实施例中，所述切割区域为矩形区域，位于不同芯片图形外周的所述矩形区域的尺寸相等，且位于所述芯片图形区的边缘区域的各所述切割区域相互连接，以构成边缘切割区。
在本公开的一种示例性实施例中，所述标记图形的数量为四个，四个所述标记图形一一对应的分布于所述芯片图形的四周。
在本公开的一种示例性实施例中，所述掩膜版还包括遮光区，所述遮光区呈环形围绕所述芯片图形区一周。
在本公开的一种示例性实施例中，所述遮光区设于所述边缘切割区内，且位于所述标记图形远离所述测试图形的一侧。
根据本公开的一个方面，提供一种掩膜版的布局方法，包括：
提供掩膜版，所述掩膜版包括芯片图形区，所述芯片图形区包括多个沿第一方向间隔分布芯片图形组，所述芯片图形组包括多个沿第二方向间隔分布的芯片图形，所述第一方向与所述第二方向相交；每个所述芯片图形的外周均设有切割区域，所述切割区域和与其相邻的所述芯片图形之间为测试图形区域，所述测试图形区域中沿所述第二方向延伸的部分的宽度小于其沿所述第一方向延伸的部分的宽度，或者，所述测试 图形区域中沿所述第一方向延伸的部分的宽度小于其沿所述第二方向延伸的部分的宽度；
在所述切割区域内形成标记图形；
在所述测试图形区域内形成测试图形。
在本公开的一种示例性实施例中，所述切割区域呈环形围绕所述芯片图形一周。
在本公开的一种示例性实施例中，相邻的两个所述芯片图形共用位于两个所述芯片图形之间的所述切割区域。
在本公开的一种示例性实施例中，所述标记图形的形状与所述切割区域的形状相同，所述标记图形铺满所述切割区域。
在本公开的一种示例性实施例中，所述标记图形的数量为多个，各所述标记图形中至少部分所述标记图形在所述切割区域内间隔分布。
在本公开的一种示例性实施例中，所述切割区域为矩形区域，位于不同芯片图形外周的所述矩形区域的尺寸相等，且位于所述芯片图形区的边缘区域的各所述切割区域相互连接，以构成边缘切割区。
在本公开的一种示例性实施例中，所述标记图形的数量为四个，四个所述标记图形一一对应的分布于所述芯片图形的四周。
在本公开的一种示例性实施例中，所述掩膜版还包括遮光区，所述遮光区呈环形围绕所述芯片图形区一周。
在本公开的一种示例性实施例中，所述遮光区设于所述边缘切割区内，且位于所述标记图形远离所述测试图形的一侧。
根据本公开的一个方面，提供一种芯片的排版图形，包括：多个沿第一方向间隔分布芯片图形组，所述芯片图形组包括多个沿第二方向间隔分布的芯片图形，所述第一方向与所述第二方向相交；每个所述芯片图形的外周均设有标记图形，所述标记图形和与其相邻的所述芯片图形之间设有测试图形，所述测试图形沿所述第二方向延伸的部分的宽度小于其沿所述第一方向延伸的部分的宽度，或者，所述测试图形沿所述第一方向延伸的部分的宽度小于其沿所述第二方向延伸的部分的宽度。
本公开的掩膜版及其布局方法、芯片的排版图形，由于在第一方向上，测试图形区域的宽度小于第二方向上的测试图形区域的宽度，可缩 小芯片图形区中位于第一方向上的相邻两个芯片图形之间的间距，使得在第一方向上节省出更多的空间，进而可在第一方向上增设一组芯片图形组；或者，在第二方向上，测试图形区域的宽度小于第一方向上的测试图形区域的宽度，可缩小芯片图形区中位于第二方向上的相邻两个芯片图形之间的间距，使得在第二方向上节省出更多的空间，进而可在第二方向上增设一组芯片图形组，可提高掩膜版的利用率。即，本公开的掩膜版相比于原有掩膜版而言，在采用掩膜版进行曝光的过程中每次可多曝光一组芯片图形，在采用本公开的掩膜版对包含更多数量的芯片的一整片晶圆进行曝光时，由于每一个掩膜版每次可多曝光一些芯片组，在需要曝光的芯片组总数不变的情况下，可减少掩膜版的使用数量，减少曝光次数，降低制造成本，提升产能。此外，切割区域中的标记图形可作为对位标记，以避免在使用掩膜版的过程中出现偏移，避免因掩膜版偏移而产生结构误差，有助于提高产品良率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中掩膜版的示意图；
图2为本公开一实施方式中掩膜版的示意图；
图3为图2中A区域的放大示意图；
图4本公开一实施方式中掩膜版的示意图；
图5为本公开实施方式中掩膜版布局方法的流程图；
图6为本公开实施方式中芯片的排版图形示意图；
图7为图6中B区域的放大示意图。
附图标记说明：
100、芯片图形；200、标记图形；300、测试图形；400、遮光区；1、芯片图形；2、切割区域；21、第一类标记图形；22、第二类标记图形；3、测试图形区域；4、遮光区；500、芯片的排版图形；501、芯片图形组；a、第一方向；b、第二方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”仅作为标记使用，不是对其对象的数量限制。
掩膜版是半导体光刻工艺中的重要工具之一，可采用掩膜版对芯片图形进行排版，例如，可将掩膜版中的掩膜图形转移至晶圆内，进而形成芯片排版图形。在一些制程中，如图1所示，掩膜版主要包括芯片图形区和位于芯片图形区外周的遮光区，其中，芯片图形区包括多个芯片图形100，相邻的芯片图形100之间设有切割道，切割道内通常设置有标记图形200和测试图形300，然而，随着半导体技术的发展，切割道 内需要放置的测试图形300的数量越来越多，使得切割道的宽度日益增加，切割道占据的空间越来越大，进而使得掩膜版中用于设置芯片图形100的空间减小，掩膜版中的芯片图形100的数量较少，掩膜版的空间利用率较低，在需要曝光的芯片图形100的总数不变的情况下，需要的掩膜版的数量较多，曝光次数也一并增多，制造成本较高；同时，遮光区400也通常设置于切割道内，由于测试图形300和标记图形的设置已经占用了较大空间，再加上遮光区的设置使得边缘区域的切割道的宽度更大，进一步缩减了用于设置芯片图形100的空间，掩膜版的空间利用率较低。
基于此，本公开实施方式提供了一种掩膜版，图2示出了本公开的掩膜版的示意图，如图2所示，本公开的掩膜版可包括芯片图形区，芯片图形区可包括多个沿第一方向a间隔分布芯片图形组，芯片图形组可包括多个沿第二方向b间隔分布的芯片图形1，第一方向a与第二方向b相交；
每个芯片图形1的外周均可设有切割区域2，切割区域2内可形成有标记图形；切割区域2和与其相邻的芯片图形1之间可为测试图形区域3，测试图形区域3内可形成有测试图形；在第一方向a上，测试图形区域3的宽度可小于第二方向b上的测试图形区域3的宽度，或者，在第二方向b上，测试图形区域3的宽度可小于第一方向a上的测试图形区域3的宽度。
本公开的掩膜版，由于在第一方向a上，测试图形区域3的宽度小于第二方向b上的测试图形区域3的宽度，可缩小芯片图形区中位于第一方向a上的相邻两个芯片图形1之间的间距，使得在第一方向a上节省出更多的空间，进而可在第一方向a上增设一组芯片图形组；或者，在第二方向b上，测试图形区域3的宽度小于第一方向a上的测试图形区域3的宽度，可缩小芯片图形区中位于第二方向b上的相邻两个芯片图形1之间的间距，使得在第二方向b上节省出更多的空间，进而可在第二方向b上增设一组芯片图形组，可提高掩膜版的利用率。即，本公开的掩膜版相比于原有掩膜版而言，在采用掩膜版进行曝光的过程中每次可多曝光一组芯片图形1，在采用本公开的掩膜版对包含更多数量的 芯片的一整片晶圆进行曝光时，由于每一个掩膜版每次可多曝光一些芯片组，在需要曝光的芯片组总数不变的情况下，可减少掩膜版的使用数量，减少曝光次数，降低制造成本，提升产能。此外，切割区域2中的标记图形可作为对位标记，以避免在使用掩膜版的过程中出现偏移，避免因掩膜版偏移而产生结构误差，有助于提高产品良率。
下面对本公开的掩膜版的具体细节进行详细说明：
芯片图形区可为人为设定的掩膜图案区域，其可为矩形区域、圆形区域、椭圆形区域或不规则图形区域，在此不做特殊限定。
芯片图形区可包括多个呈阵列分布的芯片图形1，芯片图形1可与晶圆中最终需要形成的芯片单元的形状相匹配，举例而言，芯片图形1可与晶圆中最终需要形成的芯片单元的形状相同，例如，当晶圆中最终需要形成的芯片单元的形状为矩形时，芯片图形1的形状也可为矩形；当晶圆中最终需要形成的芯片单元的形状为圆形时，芯片图形1的形状也可为圆形；当晶圆中最终需要形成的芯片单元的形状为椭圆形时，芯片图形1的形状也可为椭圆形；当晶圆中最终需要形成的芯片单元的形状为多边形时，芯片图形1的形状也可为多边形，当然，当晶圆中最终需要形成的芯片单元的形状为其它形状时，芯片图形1的形状也可为与其形状相匹配的其它形状，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片图形1的尺寸可与晶圆中最终需要形成的芯片单元的尺寸相匹配，例如，芯片图形1的尺寸可与晶圆中最终需要形成的芯片单元的尺寸相同。
在本公开的一些实施方式中，芯片图形区可包括多个芯片图形组，各芯片图形组可沿第一方向a间隔分布，每个芯片图形组均可包括多个芯片图形1，各芯片图形1可沿第二方向b间隔分布。
需要说明的是，第一方向a可以是掩膜版延伸方向中的任一方向，第一方向a可与第二方向b相交，例如，第一方向a与第二方向b可相互垂直。需要说明的是，垂直可以是绝对垂直，也可以是大致垂直，在制造过程中难免会有偏差，在本公开中，可能由于制作工艺限制引起角度的偏差，使得第一方向a和第二方向b的夹角有一定的偏差，只要第一方向a和第二方向b的角度偏差在预设范围内，均可认为第一方向a 与第二方向b垂直。举例而言，预设范围可为10°，即：第一方向a和第二方向b的夹角在大于或等于80°，小于或等于100°的范围内时均可认为第一方向a和第二方向b垂直。
在本公开的一些实施方式中，每个芯片图形1的外周均可设有切割区域2，切割区域2可呈环形，该环形可围绕芯片图形1一周。在本公开的一些实施方式中，切割区域2可为矩形区域，举例而言，切割区域2可为矩形环状区域，位于不同的芯片图形1外周的矩形区域的尺寸可相等。例如，不同的芯片图形1的外周的切割区域2均可为长方形环状区域，位于不同的芯片图形1外周的长方形环状区域的长边均可相等，与此同时，位于不同的芯片图形1外周的长方形环状区域的短边也可均相等。
在本公开的一些实施方式中，由于切割区域2内无需放置测试图形，可在一定程度上减小切割区域2的宽度。在一实施方式中，环形切割区域2中内环和外环之间的间距处处相等，举例而言，环形切割区域2中内环和外环之间的间距可为60um～90um，例如，环形切割区域2中内环和外环之间的间距可为60um、70um、80um或90um，当然，环形切割区域2中内环和外环之间的间距也可为其他，在此不再一一列举。
在本公开的一些实施方式中，长方形环状区域的短边均可沿第一方向a延伸，同时，长方形环状区域的长边均可沿第二方向b延伸；或者，长方形环状区域的短边均可沿在第二方向b延伸，同时，长方形环状区域的长边均可沿在第一方向a延伸，在此不对长方形环状区域的长边和短边的延伸方向做特殊限定。
在本公开的一种示例性实施方式中，相邻的两个芯片图形1可共用位于两个芯片图形1之间的切割区域2，可减小相邻两个芯片图形1之间的间距，有助于节省掩膜版的空间，提升掩膜版的空间利用率。例如，当长方形环状区域的短边均沿在第一方向a延伸，同时，长方形环状区域的长边均沿在第二方向b延伸时，在第一方向a上，相邻的两个芯片图形1可共用长方形环状区域的长边，在第二方向b上，相邻的两个芯片图形1可共用长方形环状区域的短边；又如，当长方形环状区域的短边均沿在第二方向b延伸，同时，长方形环状区域的长边均沿在第一方 向a延伸时，在第一方向a上，相邻的两个芯片图形1可共用长方形环状区域的短边，在第二方向b上，相邻的两个芯片图形1可共用长方形环状区域的长边。
在本公开的一种示例性实施方式中，切割区域2内可形成有标记图形。标记图形可用于对位，其可作为对位标记，以避免在使用掩膜版的过程中出现偏移，避免因掩膜版偏移而产生结构误差，有助于提高产品良率。
标记图形可呈矩形、圆形、多边形或不规则图形，在此不做特殊限定。在本公开的一些实施方式中，如图2及图3所示，标记图形的形状可与切割区域2的形状相同，其各区域的尺寸可与切割区域2的尺寸相匹配，即，标记图形可为一整个连续的图形，该图形可铺满切割区域2。举例而言，当切割区域2的形状为矩形环状区域时，标记图形也可呈矩形环状，且其内环与外环之间的间距与切割区域2的宽度相等。
在本公开的另一些实施方式中，如图4所示，标记图形的数量可为多个，不同的标记图形的形状可以相同，也可以不同，在此不做特殊限定。以各标记图形不完全相同为例，多个标记图形中，一些标记图形可为矩形，一些标记图形可为圆形，一些标记图形可为“L型”，一些标记图形可为“T”型，当然，标记图形还可为其他图形，在此不再一一列举。当然，多个标记图形还可均为矩形；或者，各标记图形还可均为圆形；又或者，各标记图形还可均为不规则图形，在此不对各标记图形的形状做特殊限定。
在本公开的一些实施方式中，继续参见图4所示，多个标记图形中至少部分标记图形在切割区域2内可间隔分布。举例而言，多个标记图形中至少部分标记图形可沿切割区域2的延伸方向间隔分布。优选的，各标记图形均可间隔分布，且各标记图形可均匀分布于切割区域2内。
举例而言，标记图形的数量可为四个，四个标记图形均可一一对应的分布于芯片图形1的四周。举例而言，当切割区域2的形状为矩形环状区域时，标记图形可呈“L”型，四个“L”型的标记图形可分别设置于矩形环状切割区域2的四个拐角处。具体而言，“L”型的长边的延伸方向可与矩形环状区域的长边的延伸方向保持一致，同时，“L”型的短 边的延伸方向可与矩形环状区域的短边的延伸方向保持一致；或者，“L”型的长边的延伸方向可与矩形环状区域的短边的延伸方向保持一致，同时，“L”型的短边的延伸方向可与矩形环状区域的长边的延伸方向保持一致。
在本公开的一些实施方式中，继续参见图4所示，可将位于切割区域2内的标记图形即为第一类标记图形21，第一类标记图形21可用于对掩膜版进行初步对位定位，在该实施方式中，测试图形区域3与芯片图形1之间也可设有标记图形，可将该标记图形即为第二类标记图形22、第二类标记图形22可用于对掩膜版进行精准定位，进而更好的避免掩膜版偏移。
在本公开的一些实施方式中，位于芯片图形区的边缘区域的各切割区域2可相互连接，进而构成边缘切割区，需要说明的是，边缘切割区可以是位于芯片图形区的边缘区域的各切割区域2中远离芯片图形区的中心一侧的边界围成的区域。边缘切割区域2可以是矩形、多边形或不规则图形，在此不做特殊限定。举例而言，当芯片图形区中的各切割区域2均为矩形环状区域时，芯片图形区的边缘区域的各切割区域2连接形成的边缘切割区可呈矩形环状区域，该矩形环状区域可将各芯片图形1包围在内。
在本公开的一种示例性实施方式中，本公开的掩膜版还可包括遮光区4，遮光区4可呈环形围绕芯片图形区一周。遮光区4可作为相邻的掩膜版的拼接区域，在采用掩膜版进行图案转移的过程中，可在遮光区4中设置遮光带，通过遮光带对拼接区域进行遮光，以避免最终形成的产品因重复曝光而产生结构缺陷。
在本公开的一些实施方式中，遮光区4可位于边缘切割区内，遮光区4与边缘切割区内的标记图形可并排分布，且其可位于标记图形远离测试图形的一侧。在需要使用多个掩膜版同时进行图形转移时，各掩膜版边缘的遮光区4可相互对接，进而在两个掩膜版之间形成一个完整的遮光区4。
在本公开实施方式中，由于增设了一组芯片图形1，提高了掩膜版的空间利用率，掩膜版边缘空余的位置减小，同时，由于掩膜版边缘切 割区域2的宽度较小，可在一定程度上缩小遮光带的宽度，进一步节省掩膜版的空间。
在本公开的一种示例性实施方式中，如图2-图4所示，切割区域2和与其相邻的芯片图形1之间无接触，切割区域2和与其相邻的芯片图形1之间可为测试图形区域3，测试图形区域3可以是芯片图形1的外周与切割区域2的内环围成的区域。即，测试图形区域3为芯片图形1的外周与切割区域2的内环之间的区域，测试图形区域3可呈环形围绕在芯片图形1的外周，且测试图形区域3的内环可与芯片图形1邻接，其外环可与切割区域2的内环邻接。
举例而言，当芯片图形1为矩形，切割区域2为矩形环状区域时，测试图形区域3也可为矩形环状区域；当芯片图形1为圆形，切割区域2为圆形环状区域时，测试图形区域3也可为圆形环状区域；当然，当芯片图形1为其他形状，切割区域2也为其他形状的环状区域时，测试图形区域3也可为其他形状的环形区域，在此不对测试图形区域3的形状做特殊限定。
测试图形区域3内可形成有测试图形，测试图形可用于形成测试垫，进而通过测试垫收集芯片单元中的数据。测试图形可呈矩形、圆形、多边形或不规则图形，在此不做特殊限定。测试图形的数量可为多个，在本公开的一些实施方式中，可将各测试图形分成两个测试图形组，两个测试图形组可沿第二方向b间隔排布，每个测试图形组中可包括多个沿第一方向a分布的测试图形。在第二方向b上，两排测试图形组可分别位于芯片图形1的两侧。或者，可将各测试图形分成两个测试图形组，两个测试图形组可沿第一方向a间隔排布，每个测试图形组中可包括多个沿第二方向b分布的测试图形。在第一方向a上，两排测试图形组可分别位于芯片图形1的两侧。又或者，可将各测试图形分成四个测试图形组，其中，两个测试图形组可沿第二方向b间隔排布，每个测试图形组中可包括多个沿第一方向a分布的测试图形。在第二方向b上，两排测试图形组可分别位于芯片图形1的两侧；另外两个测试图形组可沿第一方向a间隔排布，每个测试图形组中可包括多个沿第二方向b分布的测试图形。在第一方向a上，两排测试图形组可分别位于芯片图形1的 两侧。
在本公开的一种示例性实施方式中，以测试图形区域3为矩形环状区域为例，第一方向a可为测试图形的短边所在方向(即芯片的宽度方向)，第二方向b可为测试图形的长边所在方向(即芯片的长度方向)，可将测试图形尽可能多的设置于芯片图形1的宽度方向的两侧，有助于减少设置于芯片图形1的长度方向两侧的测试图形的数量，进而可压缩位于芯片图形1的长度方向两侧(即，第一方向a)的测试图形区域3的宽度，缩小芯片图形区中位于第一方向a上的相邻两个芯片图形1之间的间距，使得在第一方向a上节省出更多的空间，进而可在第一方向a上增设一组芯片图形组(例如，在一掩膜版中芯片图形组由原有的3列变成了4列)，可提高掩膜版的利用率，使得现有的掩膜版的利用率在原有掩膜版的基础上增加33％。相比于现有技术，采用本公开的掩膜版进行曝光，其曝光的次数可减少，在一些实施例中，可由原来的150减少至120，有助于降低生产成本及制程效率。
举例而言，测试图形区域3中沿第二方向b(即芯片的长度方向)延伸的部分的宽度可小于其沿第一方向a(即芯片的宽度方向)延伸的部分的宽度，可将测试图形尽可能多的设置于沿芯片图形1的宽度方向延伸的测试图形区域3内。
在本公开的另一种示例性实施方式中，以测试图形区域3为矩形环状区域为例，第一方向a可为测试图形的短边所在方向(即芯片的宽度方向)，第二方向b可为测试图形的长边所在方向(即芯片的长度方向)，可将测试图形尽可能多的设置于芯片图形1的长度方向的两侧，有助于减少设置于芯片图形1的宽度方向两侧的测试图形的数量，进而可压缩位于芯片图形1的宽度方向两侧(即，第二方向b)的测试图形区域3的宽度，缩小芯片图形区中位于第二方向b上的相邻两个芯片图形1之间的间距，使得在第二方向b上节省出更多的空间，进而可在第二方向b上增设一组芯片图形组(例如，在一掩膜版中芯片图形组由原有的3排变成了4排)，可提高掩膜版的利用率。
举例而言，测试图形区域3中沿第一方向a(即芯片的宽度方向)延伸的部分的宽度可小于其沿第二方向b(即芯片的长度方向)延伸的 部分的宽度，可将测试图形尽可能多的设置于沿芯片图形1的长度方向延伸的测试图形区域3内。
本公开还提供了一种掩膜版的布局方法，该布局方法可用于布局上述任一实施方式中的掩膜版，图5示出了本公开的掩膜版的布局方法的流程图，参见图5所示，该布局方法包括步骤S110-步骤S130，其中：
步骤S110，提供掩膜版，所述掩膜版包括芯片图形区，所述芯片图形区包括多个沿第一方向a间隔分布芯片图形组，所述芯片图形组包括多个沿第二方向b间隔分布的芯片图形1，所述第一方向a与所述第二方向b相交；每个所述芯片图形1的外周均设有切割区域2，所述切割区域2和与其相邻的所述芯片图形1之间为测试图形区域3，所述测试图形区域3中沿所述第二方向b延伸的部分的宽度小于其沿所述第一方向a延伸的部分的宽度，或者，所述测试图形区域3中沿所述第一方向a延伸的部分的宽度小于其沿所述第二方向b延伸的部分的宽度；
步骤S120，在所述切割区域2内形成标记图形；
步骤S130，在所述测试图形区域3内形成测试图形。
本公开的掩膜版的布局方法，由于在第一方向a上，测试图形区域3的宽度小于第二方向b上的测试图形区域3的宽度，可缩小芯片图形区中位于第一方向a上的相邻两个芯片图形1之间的间距，使得在第一方向a上节省出更多的空间，进而可在第一方向a上增设一组芯片图形组；或者，在第二方向b上，测试图形区域3的宽度小于第一方向a上的测试图形区域3的宽度，可缩小芯片图形区中位于第二方向b上的相邻两个芯片图形1之间的间距，使得在第二方向b上节省出更多的空间，进而可在第二方向b上增设一组芯片图形组，可提高掩膜版的利用率。即，本公开的掩膜版相比于原有掩膜版而言，在采用掩膜版进行曝光的过程中每次可多曝光一组芯片图形1，在采用本公开的掩膜版对包含更多数量的芯片的一整片晶圆进行曝光时，由于每一个掩膜版每次可多曝光一些芯片组，在需要曝光的芯片组总数不变的情况下，可减少掩膜版的使用数量，减少曝光次数，降低制造成本，提升产能。此外，切割区域2中的标记图形可作为对位标记，以避免在使用掩膜版的过程中出现偏移，避免因掩膜版偏移而产生结构误差，有助于提高产品良率。
如图5所示，在步骤S110中，提供掩膜版，所述掩膜版包括芯片图形区，所述芯片图形区包括多个沿第一方向a间隔分布芯片图形组，所述芯片图形组包括多个沿第二方向b间隔分布的芯片图形1，所述第一方向a与所述第二方向b相交；每个所述芯片图形1的外周均设有切割区域2，所述切割区域2和与其相邻的所述芯片图形1之间为测试图形区域3，所述测试图形区域3中沿所述第二方向b延伸的部分的宽度小于其沿所述第一方向a延伸的部分的宽度，或者，所述测试图形区域3中沿所述第一方向a延伸的部分的宽度小于其沿所述第二方向b延伸的部分的宽度。
芯片图形区可为人为设定的掩膜图案区域，其可为矩形区域、圆形区域、椭圆形区域或不规则图形区域，在此不做特殊限定。
芯片图形区可包括多个呈阵列分布的芯片图形1，芯片图形1可与晶圆中最终需要形成的芯片单元的形状相匹配，举例而言，芯片图形1可与晶圆中最终需要形成的芯片单元的形状相同，例如，当晶圆中最终需要形成的芯片单元的形状为矩形时，芯片图形1的形状也可为矩形；当晶圆中最终需要形成的芯片单元的形状为圆形时，芯片图形1的形状也可为圆形；当晶圆中最终需要形成的芯片单元的形状为椭圆形时，芯片图形1的形状也可为椭圆形；当晶圆中最终需要形成的芯片单元的形状为多边形时，芯片图形1的形状也可为多边形，当然，当晶圆中最终需要形成的芯片单元的形状为其它形状时，芯片图形1的形状也可为与其形状相匹配的其它形状，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片图形1的尺寸可与晶圆中最终需要形成的芯片单元的尺寸相匹配，例如，芯片图形1的尺寸可与晶圆中最终需要形成的芯片单元的尺寸相同。
在本公开的一些实施方式中，芯片图形区可包括多个芯片图形组，各芯片图形组可沿第一方向a间隔分布，每个芯片图形组均可包括多个芯片图形1，各芯片图形1可沿第二方向b间隔分布。
需要说明的是，第一方向a可以是掩膜版延伸方向中的任一方向，第一方向a可与第二方向b相交，例如，第一方向a与第二方向b可相互垂直。
在本公开的一些实施方式中，切割区域2可呈环形，该环形可围绕芯片图形1一周。在本公开的一些实施方式中，切割区域2可为矩形区域，举例而言，切割区域2可为矩形环状区域，位于不同的芯片图形1外周的矩形区域的尺寸可相等。
在本公开的一些实施方式中，由于切割区域2内无需放置测试图形，可在一定程度上减小切割区域2的宽度。在一实施方式中，环形切割区域2中内环和外环之间的间距处处相等，举例而言，环形切割区域2中内环和外环之间的间距可为60um～90um，例如，环形切割区域2中内环和外环之间的间距可为60um、70um、80um或90um，当然，环形切割区域2中内环和外环之间的间距也可为其他，在此不再一一列举。
在本公开的一种示例性实施方式中，如图2-图4所示，切割区域2和与其相邻的芯片图形1之间无接触，切割区域2和与其相邻的芯片图形1之间可为测试图形区域3，测试图形区域3可以是芯片图形1的外周与切割区域2的内环围成的区域。即，测试图形区域3为芯片图形1的外周与切割区域2的内环之间的区域，测试图形区域3可呈环形围绕在芯片图形1的外周，且测试图形区域3的内环可与芯片图形1邻接，其外环可与切割区域2的内环邻接。
举例而言，当芯片图形1为矩形，切割区域2为矩形环状区域时，测试图形区域3也可为矩形环状区域；当芯片图形1为圆形，切割区域2为圆形环状区域时，测试图形区域3也可为圆形环状区域；当然，当芯片图形1为其他形状，切割区域2也为其他形状的环状区域时，测试图形区域3也可为其他形状的环形区域，在此不对测试图形区域3的形状做特殊限定。
如图5所示，在步骤S120中，在所述切割区域2内形成标记图形。
在本公开的一种示例性实施方式中，可采用蚀刻工艺在切割区域2内形成标记图形，标记图形可用于对位，其可作为对位标记，以避免在使用掩膜版的过程中出现偏移，避免因掩膜版偏移而产生结构误差，有助于提高产品良率。
标记图形可呈矩形、圆形、多边形或不规则图形，在此不做特殊限定。在本公开的一些实施方式中，标记图形的形状可与切割区域2的形 状相同，其各区域的尺寸可与切割区域2的尺寸相匹配，即，标记图形可为一整个连续的图形，该图形可铺满切割区域2。举例而言，当切割区域2的形状为矩形环状区域时，标记图形也可呈矩形环状，且其内环与外环之间的间距与切割区域2的宽度相等。
在本公开的另一些实施方式中，标记图形的数量可为多个，不同的标记图形的形状可以相同，也可以不同，在此不做特殊限定。以各标记图形不完全相同为例，多个标记图形中，一些标记图形可为矩形，一些标记图形可为圆形，一些标记图形可为“L型”，一些标记图形可为“T”型，当然，标记图形还可为其他图形，在此不再一一列举。当然，多个标记图形还可均为矩形；或者，各标记图形还可均为圆形；又或者，各标记图形还可均为不规则图形，在此不对各标记图形的形状做特殊限定。
如图5所示，在步骤S130中，在所述测试图形区域3内形成测试图形。
可通过蚀刻或其他方式在测试图形区域3内形成测试图形，测试图形可用于形成测试垫，进而通过测试垫收集芯片单元中的数据。测试图形可呈矩形、圆形、多边形或不规则图形，在此不做特殊限定。测试图形的数量可为多个，在本公开的一些实施方式中，可将各测试图形分成两个测试图形组，两个测试图形组可沿第二方向b间隔排布，每个测试图形组中可包括多个沿第一方向a分布的测试图形。在第二方向b上，两排测试图形组可分别位于芯片图形1的两侧。或者，可将各测试图形分成两个测试图形组，两个测试图形组可沿第一方向a间隔排布，每个测试图形组中可包括多个沿第二方向b分布的测试图形。在第一方向a上，两排测试图形组可分别位于芯片图形1的两侧。又或者，可将各测试图形分成四个测试图形组，其中，两个测试图形组可沿第二方向b间隔排布，每个测试图形组中可包括多个沿第一方向a分布的测试图形。在第二方向b上，两排测试图形组可分别位于芯片图形1的两侧；另外两个测试图形组可沿第一方向a间隔排布，每个测试图形组中可包括多个沿第二方向b分布的测试图形。在第一方向a上，两排测试图形组可分别位于芯片图形1的两侧。
本公开的掩膜版的其他细节已经在对应的掩膜版的实施方式中进行 了详细说明，因此，此处不再赘述。
需要说明的是，尽管在附图中以特定顺序描述了本公开中掩膜版的布局方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开还提供了一种芯片的排版图形500，如图6及图7所示，本公开的芯片的排版图形500可包括多个沿第一方向a间隔分布芯片图形组501，芯片图形组501包括多个沿第二方向b间隔分布的芯片图形1，第一方向a与第二方向b相交；每个芯片图形1的外周均设有标记图形，标记图形和与其相邻的芯片图形1之间设有测试图形，测试图形沿第二方向b延伸的部分的宽度小于其沿第一方向a延伸的部分的宽度，或者，测试图形沿第一方向a延伸的部分的宽度小于其沿第二方向b延伸的部分的宽度。
本公开中的芯片排版图形可通过上述任一实施方式中的掩膜版转移而来，该排版图形的其他细节及有益效果可参考上述任一实施方式中的掩膜版，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种掩膜版，其特征在于，包括：芯片图形区，所述芯片图形区包括多个沿第一方向(a)间隔分布芯片图形组(501)，所述芯片图形组(501)包括多个沿第二方向(b)间隔分布的芯片图形(1)，所述第一方向(a)与所述第二方向(b)相交；
    每个所述芯片图形(1)的外周均设有切割区域(2)，所述切割区域(2)内形成有标记图形；所述切割区域(2)和与其相邻的所述芯片图形(1)之间为测试图形区域(3)，所述测试图形区域(3)内形成有测试图形；所述测试图形区域(3)中沿所述第二方向(b)延伸的部分的宽度小于其沿所述第一方向(a)延伸的部分的宽度，或者，所述测试图形区域(3)中沿所述第一方向(a)延伸的部分的宽度小于其沿所述第二方向(b)延伸的部分的宽度。
  2. 根据权利要求1所述的掩膜版，其特征在于，所述切割区域(2)呈环形围绕所述芯片图形(1)一周。
  3. 根据权利要求2所述的掩膜版，其特征在于，相邻的两个所述芯片图形(1)共用位于两个所述芯片图形(1)之间的所述切割区域(2)。
  4. 根据权利要求2所述的掩膜版，其特征在于，所述标记图形的形状与所述切割区域(2)的形状相同，所述标记图形铺满所述切割区域(2)。
  5. 根据权利要求2所述的掩膜版，其特征在于，所述标记图形的数量为多个，各所述标记图形中至少部分所述标记图形在所述切割区域(2)内间隔分布。
  6. 根据权利要求5所述的掩膜版，其特征在于，所述切割区域(2)为矩形区域，位于不同芯片图形(1)外周的所述矩形区域的尺寸相等，且位于所述芯片图形区的边缘区域的各所述切割区域(2)相互连接，以构成边缘切割区。
  7. 根据权利要求6所述的掩膜版，其特征在于，所述标记图形的数量为四个，四个所述标记图形一一对应的分布于所述芯片图形(1)的四周。
  8. 根据权利要求6所述的掩膜版，其特征在于，所述掩膜版还包括遮光区(4)，所述遮光区(4)呈环形围绕所述芯片图形区一周。
  9. 根据权利要求8所述的掩膜版，其特征在于，所述遮光区(4)设于所述边缘切割区内，且位于所述标记图形远离所述测试图形的一侧。
  10. 一种掩膜版的布局方法，其特征在于，包括：
    提供掩膜版，所述掩膜版包括芯片图形区，所述芯片图形区包括多个沿第一方向(a)间隔分布芯片图形组(501)，所述芯片图形组(501)包括多个沿第二方向(b)间隔分布的芯片图形(1)，所述第一方向(a)与所述第二方向(b)相交；每个所述芯片图形(1)的外周均设有切割区域(2)，所述切割区域(2)和与其相邻的所述芯片图形(1)之间为测试图形区域(3)，所述测试图形区域(3)中沿所述第二方向(b)延伸的部分的宽度小于其沿所述第一方向(a)延伸的部分的宽度，或者，所述测试图形区域(3)中沿所述第一方向(a)延伸的部分的宽度小于其沿所述第二方向(b)延伸的部分的宽度；
    在所述切割区域(2)内形成标记图形；
    在所述测试图形区域(3)内形成测试图形。
  11. 根据权利要求10所述的布局方法，其特征在于，所述切割区域(2)呈环形围绕所述芯片图形(1)一周。
  12. 根据权利要求11所述的布局方法，其特征在于，相邻的两个所述芯片图形(1)共用位于两个所述芯片图形(1)之间的所述切割区域(2)。
  13. 根据权利要求11所述的布局方法，其特征在于，所述标记图形的形状与所述切割区域(2)的形状相同，所述标记图形铺满所述切割区域(2)。
  14. 根据权利要求11所述的布局方法，其特征在于，所述标记图形的数量为多个，各所述标记图形中至少部分所述标记图形在所述切割区域(2)内间隔分布。
  15. 根据权利要求14所述的布局方法，其特征在于，所述切割区域(2)为矩形区域，位于不同芯片图形(1)外周的所述矩形区域的尺寸相等，且位于所述芯片图形区的边缘区域的各所述切割区域(2)相互连接，以构成边缘切割区。
  16. 根据权利要求15所述的布局方法，其特征在于，所述标记图形 的数量为四个，四个所述标记图形一一对应的分布于所述芯片图形(1)的四周。
  17. 根据权利要求15所述的布局方法，其特征在于，所述掩膜版还包括遮光区(4)，所述遮光区(4)呈环形围绕所述芯片图形区一周。
  18. 根据权利要求17所述的布局方法，其特征在于，所述遮光区(4)设于所述边缘切割区内，且位于所述标记图形远离所述测试图形的一侧。
  19. 一种芯片的排版图形(500)，其特征在于，包括：多个沿第一方向(a)间隔分布芯片图形组(501)，所述芯片图形组(501)包括多个沿第二方向(b)间隔分布的芯片图形(1)，所述第一方向(a)与所述第二方向(b)相交；每个所述芯片图形(1)的外周均设有标记图形，所述标记图形和与其相邻的所述芯片图形(1)之间设有测试图形，所述测试图形沿所述第二方向(b)延伸的部分的宽度小于其沿所述第一方向(a)延伸的部分的宽度，或者，所述测试图形沿所述第一方向(a)延伸的部分的宽度小于其沿所述第二方向(b)延伸的部分的宽度。
PCT/CN2023/080919 2022-09-28 2023-03-10 掩膜版及其布局方法、芯片的排版图形 WO2024066218A1 (zh)

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