WO2024033739A1 - 半導体装置、及び、半導体装置の作製方法 - Google Patents

半導体装置、及び、半導体装置の作製方法 Download PDF

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Publication number
WO2024033739A1
WO2024033739A1 PCT/IB2023/057609 IB2023057609W WO2024033739A1 WO 2024033739 A1 WO2024033739 A1 WO 2024033739A1 IB 2023057609 W IB2023057609 W IB 2023057609W WO 2024033739 A1 WO2024033739 A1 WO 2024033739A1
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Prior art keywords
layer
conductive layer
semiconductor
transistor
conductive
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PCT/IB2023/057609
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English (en)
French (fr)
Japanese (ja)
Inventor
神長正美
中田昌孝
島行徳
土橋正佳
肥塚純一
黒崎大輔
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2024540071A priority Critical patent/JPWO2024033739A1/ja
Priority to CN202380058212.2A priority patent/CN119678672A/zh
Priority to US18/998,211 priority patent/US20250338717A1/en
Priority to KR1020257005884A priority patent/KR20250048716A/ko
Publication of WO2024033739A1 publication Critical patent/WO2024033739A1/ja
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.
  • One embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), and electronic devices including them. Examples include devices, their driving methods, or their manufacturing methods.
  • Semiconductor devices having transistors are widely applied to display devices and electronic devices, and there is a demand for higher integration and higher speed of semiconductor devices. For example, when applying a semiconductor device to a high-definition display device, a highly integrated semiconductor device is required. 2. Description of the Related Art As one means of increasing the degree of integration of transistors, development of microsized transistors is underway.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • Display devices for XR are desired to have high definition and high color reproducibility in order to enhance the sense of reality and immersion.
  • Examples of devices that can be applied to the display device include a liquid crystal display device, an organic EL (Electro Luminescence) device, or a light emitting device including a light emitting device (also referred to as a light emitting element) such as a light emitting diode (LED).
  • LED light emitting diode
  • Patent Document 1 discloses a display device for VR using an organic EL device (also referred to as an organic EL element).
  • An object of one embodiment of the present invention is to provide a semiconductor device having a microsized transistor and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a small-sized semiconductor device and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current, and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a high-performance semiconductor device and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.
  • an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • an object of one embodiment of the present invention is to provide a novel semiconductor device and a method for manufacturing the same.
  • One embodiment of the present invention includes a first transistor and a second transistor, and the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, and a second conductive layer. It has an insulating layer, a first semiconductor layer, and a second semiconductor layer, and the second conductive layer is provided on the first conductive layer and has an opening in a region overlapping with the first conductive layer. , the first semiconductor layer is provided covering the opening and being in contact with the top surface of the first conductive layer and the top surface and side surfaces of the second conductive layer, and the second semiconductor layer is provided in contact with the top surface of the first conductive layer and the top surface and side surfaces of the second conductive layer.
  • the first region of the first insulating layer is provided in contact with the upper surface of the second semiconductor layer, and the third conductive layer is provided in contact with the upper surface of the second semiconductor layer through the first region.
  • the second transistor is provided to overlap the first semiconductor layer and the second semiconductor layer, and the second transistor includes the first insulating layer, the third semiconductor layer, the fourth conductive layer, the fifth conductive layer, and , a sixth conductive layer, the fourth conductive layer and the fifth conductive layer are provided in contact with different upper surfaces of the third semiconductor layer, and the second region of the first insulating layer is The sixth conductive layer is provided between the fourth conductive layer and the fifth conductive layer, in contact with the upper surface of the third semiconductor layer, and the sixth conductive layer is provided in contact with the upper surface of the second region, and the sixth conductive layer is provided in contact with the upper surface of the second region.
  • the semiconductor layer and the second semiconductor layer each have different materials, and the second semiconductor layer and the third semiconductor layer are semiconductor devices that have the same material.
  • one embodiment of the present invention includes a first transistor and a second transistor, and the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, and a second conductive layer.
  • the second transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a first insulating layer.
  • the second conductive layer is provided on the first conductive layer and has a first opening in a region overlapping with the first conductive layer;
  • the semiconductor layer covers the first opening and is provided in contact with the top surface of the first conductive layer and the top surface and side surfaces of the second conductive layer, and the second semiconductor layer.
  • the first region of the first insulating layer is provided in contact with the top surface of the second semiconductor layer, and the third conductive layer is provided in contact with the top surface of the second semiconductor layer.
  • the fifth conductive layer is provided on the fourth conductive layer and has a second conductive layer in a region overlapping with the fourth conductive layer.
  • the third semiconductor layer has an opening, is provided to cover the second opening, is in contact with the top surface of the fourth conductive layer, and the top surface and side surfaces of the fifth conductive layer, and is provided with the first insulating layer
  • the second region is provided in contact with the upper surface of the third semiconductor layer, and the sixth conductive layer overlaps the third semiconductor layer through the second region within the second opening.
  • a semiconductor device is provided in which the first semiconductor layer and the second semiconductor layer have different materials, and the second semiconductor layer and the third semiconductor layer have the same material.
  • the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each contain a metal oxide.
  • a second insulating layer is provided on the first conductive layer, and the second insulating layer includes the first layer, the second layer on the first layer, and the second insulating layer.
  • the first layer has a region with a higher film density than the second layer
  • the third layer has a region with a higher film density than the second layer.
  • a second insulating layer is provided on the first conductive layer, and the second insulating layer includes the first layer, the second layer on the first layer, and the second insulating layer.
  • the first layer has a region with a higher nitrogen content than the second layer; and the third layer has a region with a higher nitrogen content than the second layer. It is preferable to have the following.
  • the second transistor has a third insulating layer, and a third semiconductor layer is provided on the third insulating layer.
  • the second transistor has a seventh conductive layer and a second insulating layer on the seventh conductive layer, and the seventh conductive layer has a second insulating layer and a third insulating layer. It is preferable that the semiconductor layer be provided to overlap with the sixth conductive layer via the semiconductor layer.
  • the third semiconductor layer has a region sandwiched between the second region of the first insulating layer and the fourth conductive layer, and a region sandwiched between the second region of the first insulating layer and the fourth conductive layer in plan view. It is preferable that the semiconductor layer has a pair of regions consisting of a region sandwiched between conductive layers No. 5 and a region sandwiched between conductive layers No. 5, and the pair of regions preferably has a lower resistance than the region overlapping the conductive layer No. 6 in the third semiconductor layer.
  • a second insulating layer is provided on the first conductive layer and the fourth conductive layer, and the second insulating layer includes the first layer, the second layer on the first layer, and a third layer on the second layer, the first layer having a region having a higher film density than the second layer, and the third layer having a film density higher than that of the second layer. It is preferable to have a high area.
  • a second insulating layer is provided on the first conductive layer and the fourth conductive layer, and the second insulating layer includes the first layer, the second layer on the first layer, and a third layer on the second layer, the first layer having a region with a higher nitrogen content than the second layer, and the third layer having a nitrogen content higher than the second layer. It is preferable to have a region with a high content of.
  • one embodiment of the present invention includes forming a first conductive film, processing the first conductive film to form a first conductive layer and a second conductive layer, and forming a first conductive layer and a second conductive layer on the first conductive layer.
  • a first insulating film is formed on the second conductive layer
  • a second insulating film is formed on the first insulating film
  • the second insulating film is processed to form a second conductive layer.
  • Overlapping first insulating layers are formed, a second conductive film is formed on the first insulating layer and the first insulating film, and the first insulating film and the second conductive film are processed.
  • a second insulating layer and a third conductive layer having an opening in a region overlapping with the first conductive layer are formed, and a third conductive layer is formed on the first conductive layer, on the second insulating layer, and on the third conductive layer so as to cover the opening.
  • a first metal oxide film is formed on the layer and the first insulating layer, and the first metal oxide film is processed to form an upper surface of the first conductive layer and a side surface of the second insulating layer. , and a first semiconductor layer in contact with the top surface and side surfaces of the third conductive layer, and the first semiconductor layer, the third conductive layer, the first insulating layer, and the second insulating layer.
  • a second metal oxide film is formed on the layer, and the second metal oxide film is processed to form a second semiconductor layer overlapping the first semiconductor layer, a second conductive layer, and a first insulating layer.
  • a third semiconductor layer overlapping the first semiconductor layer, the second semiconductor layer, the third conductive layer, the third semiconductor layer, the first insulating layer, and , a third insulating film is formed on the second insulating layer, and the third insulating film is processed to form the first conductive layer, the first semiconductor layer, the second semiconductor layer, and the third insulating layer.
  • a third insulating layer having a region overlapping with the conductive layer and a fourth insulating layer having a region overlapping with the second conductive layer and the third semiconductor layer are formed;
  • a third conductive film is formed on the insulating layer, and the third conductive film is processed to form a fourth conductive layer overlapping the first semiconductor layer and the second semiconductor layer, and a second conductive layer.
  • the impurity is preferably one or more selected from boron, phosphorus, aluminum, magnesium, and silicon.
  • the first conductive film is processed to form a first conductive layer and a second conductive layer, and a second conductive layer is formed on the first conductive layer and the second conductive layer.
  • a first insulating film is formed, a second conductive film is formed on the first insulating film, and the first insulating film and the second conductive film are processed to form a region overlapping with the first conductive layer.
  • a first metal oxide film is formed on the first insulating layer, and the first metal oxide film is processed to form a top surface of the first conductive layer, a side surface of the first insulating layer, and a first metal oxide film.
  • a first semiconductor layer is formed in contact with the top surface and side surfaces of the conductive layer of No.
  • a second metal oxide film is formed on the first insulating layer, and the second metal oxide film is processed to form a second semiconductor layer overlapping the first semiconductor layer and an upper surface of the second conductive layer.
  • a third semiconductor layer in contact with the side surfaces of the first insulating layer and the top and side surfaces of the fourth conductive layer
  • a second insulating layer is formed on the conductive layer, the third semiconductor layer, the fourth conductive layer, and the first insulating layer, and a third conductive film is formed on the second insulating layer.
  • a semiconductor device having a microsized transistor and a method for manufacturing the same can be provided.
  • a small-sized semiconductor device and a method for manufacturing the same can be provided.
  • a semiconductor device including a transistor with a large on-current and a method for manufacturing the same can be provided.
  • a high-performance semiconductor device and a method for manufacturing the same can be provided.
  • a highly reliable semiconductor device and a method for manufacturing the same can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a novel semiconductor device and a method for manufacturing the same can be provided.
  • FIG. 1A is a plan view showing an example of a semiconductor device.
  • 1B and 1C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 2A is a plan view showing an example of a semiconductor device.
  • FIG. 2B is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 3A is a plan view showing an example of a semiconductor device.
  • 3B and 3C are cross-sectional views showing an example of a semiconductor device.
  • 4A and 4B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 5A is a plan view showing an example of a semiconductor device.
  • 5B and 5C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 6A is a plan view showing an example of a semiconductor device.
  • FIG. 6B and 6C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 7A is a plan view showing an example of a semiconductor device.
  • 7B and 7C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 8A is a plan view showing an example of a semiconductor device.
  • 8B and 8C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 9A is a plan view showing an example of a semiconductor device.
  • 9B and 9C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 10A is a plan view showing an example of a semiconductor device.
  • 10B and 10C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 11A is a plan view showing an example of a semiconductor device.
  • FIG. 11B and 11C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 12A is a plan view showing an example of a semiconductor device.
  • 12B and 12C are cross-sectional views showing an example of a semiconductor device.
  • FIG. 13A is a plan view showing an example of a semiconductor device.
  • 13B and 13C are cross-sectional views showing an example of a semiconductor device.
  • 14A to 14E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 15A to 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 17A to 17C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 18A and 18B are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 19A to 19E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 20A to 20C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 21A to 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 22 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 23A is a perspective view showing an example of a display device.
  • FIG. 23B is a block diagram of the display device.
  • FIG. 23A is a perspective view showing an example of a display device.
  • FIG. 24A is a circuit diagram of a latch circuit.
  • FIG. 24B is a circuit diagram of the inverter circuit.
  • 25A and 25B are circuit diagrams of pixel circuits.
  • FIG. 25C is a cross-sectional view showing an example of a pixel circuit.
  • FIG. 26 is a cross-sectional view showing an example of a display device.
  • FIG. 27 is a cross-sectional view showing an example of a display device.
  • FIG. 28 is a cross-sectional view showing an example of a display device.
  • 29A to 29C are cross-sectional views showing an example of a display device.
  • FIG. 30 is a cross-sectional view showing an example of a display device.
  • FIG. 31 is a cross-sectional view showing an example of a display device.
  • 32 is a cross-sectional view showing an example of a display device.
  • 33A to 33F are cross-sectional views illustrating an example of a method for manufacturing a display device.
  • 34A to 34D are diagrams illustrating an example of an electronic device.
  • 35A to 35F are diagrams illustrating an example of an electronic device.
  • 36A to 36G are diagrams illustrating an example of an electronic device.
  • 37A and 37B are diagrams showing Id-Vg characteristics of a transistor.
  • film and “layer” can be interchanged depending on the situation or circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • a device manufactured using a metal mask or FMM fine metal mask, high-definition metal mask
  • a device with a MM (metal mask) structure is sometimes referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • materials and configurations can be optimized for each light emitting device, which increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability.
  • holes or electrons may be referred to as “carriers”.
  • a hole injection layer or an electron injection layer is called a “carrier injection layer”
  • a hole transport layer or an electron transport layer is called a “carrier transport layer”
  • a hole blocking layer or an electron blocking layer is called a “carrier injection layer.”
  • the carrier injection layer, carrier transport layer, and carrier block layer described above may not be clearly distinguishable depending on their respective cross-sectional shapes or characteristics.
  • one layer may serve as two or three functions among a carrier injection layer, a carrier transport layer, and a carrier block layer.
  • a light emitting device has an EL layer between a pair of electrodes.
  • the EL layer has at least a light emitting layer.
  • the layers (also referred to as functional layers) included in the EL layer include a light emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and Examples include carrier block layers (hole block layer and electron block layer).
  • a light-receiving device (also referred to as a light-receiving element) has an active layer that functions as at least a photoelectric conversion layer between a pair of electrodes.
  • island-like refers to a state in which two or more layers formed in the same process and using the same material are physically separated.
  • an island-shaped light emitting layer indicates that the light emitting layer and an adjacent light emitting layer are physically separated.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • it refers to a shape having a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (also referred to as a taper angle) is less than 90 degrees.
  • the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be substantially planar with a minute curvature or substantially planar with minute irregularities.
  • a sacrificial layer (also referred to as a mask layer) is a layer located above at least a light emitting layer (more specifically, a layer that is processed into an island shape among the layers constituting the EL layer). , has a function of protecting the light emitting layer during the manufacturing process.
  • step breakage refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step difference).
  • the shapes in plan view substantially match means that at least a portion of the outlines of the laminated layers overlap. For example, this includes a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case, it is also said that the "shapes in plan view approximately match".
  • FIG. 1A A plan view (also referred to as a top view) of the semiconductor device 10 is shown in FIG. 1A.
  • FIG. 1B A cross-sectional view taken along the dashed-dotted line A1-A2 shown in FIG. 1A is shown in FIG. 1B, and a cross-sectional view taken along the dashed-dotted line B1-B2 and dashed-dotted line B3-B4 shown in FIG. 1A is shown in FIG. 1C.
  • FIG. 1A some of the constituent elements (such as an insulating layer) of the semiconductor device 10 are omitted.
  • FIG. 1A some of the constituent elements (such as an insulating layer) of the semiconductor device 10 are omitted.
  • FIG. 1A some of the constituent elements (such as an insulating layer) of the semiconductor device 10 are omitted.
  • FIG. 1A some of the constituent elements are omitted in the subsequent drawings as well as in FIG. 1A.
  • the semiconductor device 10 includes a transistor 100 and a transistor 200.
  • Transistor 100 and transistor 200 are each provided on substrate 102.
  • the transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a semiconductor layer 105, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 112a functions as either a source electrode or a drain electrode, and the conductive layer 112b functions as the other source electrode or drain electrode.
  • the semiconductor layer 105 and the semiconductor layer 108 the entire region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel formation region. Further, in the semiconductor layer 105, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.
  • a conductive layer 112a is provided on the substrate 102.
  • An insulating layer 110 (an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c) is provided on the conductive layer 112a.
  • a conductive layer 112b is provided on the insulating layer 110.
  • the insulating layer 110 has a region sandwiched between a conductive layer 112a and a conductive layer 112b.
  • the conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween.
  • the insulating layer 110 has an opening 141 in a region overlapping with the conductive layer 112a. In the opening 141, the upper surface of the conductive layer 112a is exposed.
  • the conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a.
  • the opening 143 is provided in a region overlapping with the opening 141.
  • the semiconductor layer 105 is provided to cover the openings 141 and 143.
  • the semiconductor layer 105 has a region in contact with the top and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.
  • the semiconductor layer 108 is provided to cover the semiconductor layer 105.
  • the semiconductor layer 108 has a region in contact with the top surface and side surfaces of the semiconductor layer 105, and the top surface of the conductive layer 112b.
  • the semiconductor layer 105 and the semiconductor layer 108 are electrically connected to the conductive layer 112a through the opening 141 and the opening 143.
  • the semiconductor layer 105 and the semiconductor layer 108 have shapes along the top and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.
  • FIG. 1B and the like show an example in which the end of the semiconductor layer 108 is located outside the end of the semiconductor layer 105, this is not the case.
  • the position of the end of the semiconductor layer 108 and the position of the end of the semiconductor layer 105 may be approximately aligned. Further, the end of the semiconductor layer 108 may be located inside the end of the semiconductor layer 105.
  • the transistor 100 has two stacked semiconductor layers (a semiconductor layer 105 and a semiconductor layer 108). It is preferable that the semiconductor layer 105 and the semiconductor layer 108 are formed from materials having different compositions or film qualities. For example, it is preferable to use a material with higher mobility for the first semiconductor layer (semiconductor layer 105) than for the second semiconductor layer (semiconductor layer 108). As a result, a transistor with higher on-current can be realized than when only the semiconductor layer 108 is used. Note that the number of semiconductor layers included in the transistor 100 is not limited to two, and may have a stacked structure of three or more layers.
  • a part of the insulating layer 106 functions as a gate insulating layer of the transistor 100.
  • the insulating layer 106 is provided to cover the openings 141 and 143 with the semiconductor layer 105 and the semiconductor layer 108 interposed therebetween.
  • the insulating layer 106 is provided over the semiconductor layer 105, the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110.
  • the insulating layer 106 has a region in contact with the top surface of the semiconductor layer 108, the side surface of the conductive layer 112b, and the top surface of the insulating layer 110.
  • the insulating layer 106 has a shape along the top surface of the insulating layer 110, the side surface of the conductive layer 112b, and the top surface of the semiconductor layer 108.
  • a conductive layer 104 functioning as a gate electrode of the transistor 100 is provided in contact with the upper surface of the insulating layer 106.
  • the conductive layer 104 has a region overlapping with the semiconductor layer 105 and the semiconductor layer 108 with the insulating layer 106 interposed therebetween.
  • the conductive layer 104 has a shape along the top surface of the insulating layer 106.
  • the transistor 100 is a so-called top-gate transistor that has a gate electrode above the semiconductor layer 108. Further, since the lower surface of the semiconductor layer 105 (the surface on the substrate 102 side) is in contact with the source electrode and the drain electrode, it can be called a TGBC (Top Gate Bottom Contact) transistor.
  • TGBC Top Gate Bottom Contact
  • the transistor 100 since the source electrode and the drain electrode are located at different heights with respect to the substrate surface, the drain current flows in the height direction (vertical direction). Therefore, the transistor 100 can also be called a vertical transistor, a vertical channel transistor, a vertical channel transistor, a VFET (Vertical Field Effect Transistor), or the like.
  • the channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length smaller than the resolution limit of an exposure apparatus used for manufacturing the transistor can be manufactured with high precision. Furthermore, since an extremely small channel length can be formed, a transistor with a large on-current can be realized. Further, the transistor 100 includes two stacked semiconductor layers (a semiconductor layer 105 and a semiconductor layer 108). As described above, when the semiconductor layer of the transistor 100 has a two-layer stacked structure, the on-state current can be increased in some cases than when the semiconductor layer has a single-layer structure. Therefore, by appropriately selecting materials for the semiconductor layer 105 and the semiconductor layer 108, a transistor with even higher on-state current can be realized.
  • the channel length of the transistor 100 can be controlled simply by adjusting the thickness of the insulating layer 110 during formation, when a plurality of transistors 100 are manufactured, variations in characteristics among the transistors can be reduced. You can also do it. Therefore, the operation of the semiconductor device including the transistor 100 is stabilized, and reliability can be improved. Furthermore, when characteristic variations are reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device can be lowered. Therefore, power consumption of the semiconductor device can be reduced.
  • the transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, a conductive layer 212b, an insulating layer 120, and an insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c). ) and a conductive layer 202a.
  • the conductive layer 204 functions as a first gate electrode (also referred to as a top gate electrode).
  • a part of the insulating layer 106 (a region different from the region functioning as a gate insulating layer of the transistor 100) functions as a first gate insulating layer.
  • the conductive layer 212a functions as either a source electrode or a drain electrode, and the conductive layer 212b functions as the other source electrode or drain electrode.
  • a portion of the insulating layer 120 and a portion of the insulating layer 110 function as a second gate insulating layer.
  • the conductive layer 202a functions as a second gate electrode (also referred to as a bottom gate electrode or back gate electrode).
  • a portion of the semiconductor layer 208 that overlaps with at least one of the conductive layer 204 and the conductive layer 202a between the region in contact with the source electrode and the region in contact with the drain electrode functions as a channel formation region.
  • a portion of the semiconductor layer 208 that overlaps with the conductive layer 204 may be referred to as a channel formation region, but in reality, a portion that does not overlap with the conductive layer 204 but overlaps with the conductive layer 202a. Channels can also be formed.
  • the semiconductor layer 208 has a pair of regions 208D, which, in plan view, include a region sandwiched between the first gate insulating layer and the source electrode, and a region sandwiched between the first gate insulating layer and the drain electrode. , and has a pair of regions 208L in a region sandwiched between a channel forming region (a portion of the semiconductor layer 208 overlapping with the conductive layer 204) and a region 208D.
  • the region 208L can also be referred to as a region of the semiconductor layer 208 that overlaps with the first gate insulating layer and does not overlap with the first gate electrode.
  • a region in contact with the source electrode functions as a source region
  • a region in contact with the drain electrode functions as a drain region.
  • the semiconductor layer 208 has a channel formation region, a pair of regions 208L sandwiching the channel formation region, a pair of regions 208D outside the channel formation region, and a source region and a drain region outside the region 208L.
  • the region 208L and the region 208D function as a buffer region for relaxing the drain electric field. Since the region 208L and the region 208D are regions that do not overlap with the conductive layer 204, a channel is hardly formed even when a gate voltage is applied to the conductive layer 204. It is preferable that the carrier concentration of the region 208L and the region 208D is higher than that of the channel formation region. Thereby, the region 208L and the region 208D can function as LDD (Lightly Doped Drain) regions.
  • LDD Lightly Doped Drain
  • the region 208L and the region 208D are regions containing impurity elements.
  • impurity element one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gas can be used.
  • noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity element.
  • the region 208L is also referred to as a region with the same or lower resistance, a region with the same or higher carrier concentration, a region with the same or higher oxygen defect density, and a region with the same or higher impurity concentration than the channel forming region. Can be done.
  • the region 208D can also be referred to as a region with the same or lower resistance, a region with the same or higher carrier concentration, a region with the same or higher oxygen defect density, or a region with the same or higher impurity concentration than the region 208L. can.
  • the region 208L and the region 208D that function as LDD regions between the channel forming region and the source and drain regions high source-drain breakdown voltage, large on-current, and high reliability can be achieved. , a highly reliable transistor 200 can be realized.
  • the impurity element when adding the impurity element described above to the semiconductor layer 208 to form the region 208L and the region 208D, the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask. good.
  • a region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104.
  • the region 108L does not need to be formed.
  • the conductive layer 104 extends to cover the end of the semiconductor layer 108, the entire semiconductor layer 108 is masked by the conductive layer 104, so impurity elements are not supplied to the semiconductor layer 108, and the region 108L is formed. Not done.
  • a conductive layer 202a is provided on the substrate 102 in a region different from the conductive layer 112a.
  • the conductive layer 202a can be formed using the same material and in the same process as the conductive layer 112a.
  • An insulating layer 110 is provided on the conductive layer 202a.
  • An insulating layer 120 is provided on the insulating layer 110.
  • a semiconductor layer 208 is provided on the insulating layer 120 so as to have a region overlapping with the conductive layer 202a.
  • the semiconductor layer 208 can be formed using the same material and in the same process as the semiconductor layer 108.
  • an insulating layer 106, a conductive layer 212a, and a conductive layer 212b are provided.
  • a partial region of the insulating layer 106 functioning as the first gate insulating layer of the transistor 200 (a region different from the region functioning as the gate insulating layer of the transistor 100) has a region overlapping with the conductive layer 202a. It is provided between the conductive layer 212a and the conductive layer 212b in contact with the upper surface of the semiconductor layer 208.
  • an opening 147a and an opening 147b are provided in the insulating layer 106 so as to sandwich the conductive layer 204 therebetween.
  • the opening 147a and the opening 147b are openings that reach above the source region and drain region in the semiconductor layer 208 and above the region 208D.
  • the conductive layer 212a functioning as one of the source electrode and the drain electrode of the transistor 200 is in contact with the upper surface (one of the source region and the drain region) of the semiconductor layer 208.
  • the conductive layer 212b functioning as the other of the source electrode or the drain electrode of the transistor 200 is in contact with the upper surface of the semiconductor layer 208 (the other of the source region or the drain region).
  • a conductive layer 204 functioning as a first gate electrode of the transistor 200 is provided in contact with the upper surface of the insulating layer 106.
  • the conductive layer 204 has a region overlapping with the conductive layer 202a with the insulating layer 106 and the semiconductor layer 208 interposed therebetween.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed using the same material and in the same process as the conductive layer 104, respectively.
  • the conductive layer 204 is electrically connected to the conductive layer 202a through openings 149 provided in the insulating layer 110, the insulating layer 120, and the insulating layer 106. Good too. Thereby, the same potential can be applied to the conductive layer 204 and the conductive layer 202a. By applying the same potential to the conductive layer 204 and the conductive layer 202a, the current that can flow when the transistor 200 is in the on state (on current) can be increased. Further, leakage current between the source and drain (also referred to as off-state current) when the transistor 200 is off can be reduced.
  • the conductive layer 204 is provided to cover the opening 149 and has a region in contact with the conductive layer 202a.
  • the conductive layer 204 and the conductive layer 202a protrude outward from the end of the semiconductor layer 208 in the channel width direction of the transistor 200.
  • the entire semiconductor layer 208 in the channel width direction is covered with the conductive layer 204 and the conductive layer 202a via the insulating layer 106, the insulating layer 110, and the insulating layer 120. becomes.
  • the semiconductor layer 208 can be electrically surrounded by an electric field generated by the pair of gate electrodes.
  • the conductive layer 204 and the conductive layer 202a may be configured not to be connected. At this time, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 200 may be applied to the other. At this time, the threshold voltage when the transistor 200 is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.
  • the conductive layer 202a may be electrically connected to the conductive layer 212a or the conductive layer 212b. At this time, the conductive layer 212a or 212b and the conductive layer 202a may be electrically connected to each other through openings provided in the insulating layer 106, the insulating layer 120, and the insulating layer 110.
  • the transistor 200 is a transistor that has a first gate electrode and a second gate electrode above and below the semiconductor layer 208, respectively.
  • the region 208D and the region 208L functioning as the LDD region can be formed in a self-aligned manner. . Therefore, the transistor 200 can be called a TGSA (Top Gate Self-Aligned) transistor.
  • the channel length of the transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of the transistor 200 has a value greater than or equal to the resolution limit of an exposure apparatus used for manufacturing the transistor. By increasing the channel length, a transistor with high saturation characteristics can be obtained.
  • the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate by using some steps in common. For example, by applying the transistor 100 to a transistor that requires a large on-current and applying the transistor 200 to a transistor that requires high saturation characteristics, the semiconductor device 10 with high performance can be realized.
  • the transistor 100 is applied to a selection transistor included in a pixel circuit included in the display device, and the transistor 200 is applied to a pixel circuit included in the display device. It can be applied to the included drive transistors. Further, the transistor 100 is applied to a transistor that configures a drive circuit (for example, a gate line drive circuit or a source line drive circuit) included in the display device, and the transistor 200 is applied to a transistor that configures a pixel circuit included in the display device. It can also be applied.
  • a drive circuit for example, a gate line drive circuit or a source line drive circuit
  • each opening in plan view can be, for example, circular or elliptical.
  • the shape of each opening in plan view may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, or a shape with rounded corners of these polygons.
  • the shapes of the openings 141 and 143 in plan view are preferably circular, as shown in FIG. 1A.
  • the end of the conductive layer 112b on the opening 143 side coincides with or approximately coincides with the end of the insulating layer 110 on the opening 141 side. It can be said that the shape of the opening 143 in plan view matches or approximately matches the shape of the opening 141 in plan view.
  • the end of the conductive layer 112b on the opening 143 side refers to the lower end of the conductive layer 112b on the opening 143 side.
  • the lower surface of the conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the end of the insulating layer 110 on the opening 141 side refers to the end of the upper surface of the insulating layer 110 on the opening 141 side.
  • the upper surface of the insulating layer 110 refers to the surface on the conductive layer 112b side.
  • the shape of the opening 143 in plan view refers to the shape of the lower end of the conductive layer 112b on the opening 143 side.
  • the shape of the opening 141 in plan view refers to the shape of the upper end of the insulating layer 110 on the opening 141 side.
  • the opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, an insulating film that will become the insulating layer 110, a conductive film that will become the conductive layer 112b over the insulating film, and a resist mask over the conductive film are formed. After forming an opening 143 in the conductive film that will become the conductive layer 112b using the resist mask, the opening 141 is formed in the insulating film that will become the insulating layer 110 using the resist mask. The end portion and the end portion of the opening 143 may match or substantially match. With such a configuration, the process can be simplified.
  • the opening 141 may be formed in a process different from that for the opening 143. Furthermore, the order in which the openings 141 and 143 are formed is not particularly limited. For example, after the opening 141 is formed in the insulating film that will become the insulating layer 110, a conductive film that will become the conductive layer 112b may be formed, and the opening 143 may be formed in the conductive film.
  • the end of the conductive layer 112b on the opening 143 side does not have to coincide with the end of the insulating layer 110 on the opening 141 side. That is, the shape of the opening 143 in plan view does not have to match the shape of the opening 141 in plan view. It is preferable that the opening 143 includes the opening 141 in a plan view. The end of the conductive layer 112b on the opening 143 side may be located outside the end of the insulating layer 110 on the opening 141 side. In this case, the semiconductor layer 105 has a region in contact with the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.
  • the covering properties of the layers formed on the conductive layer 112a, the insulating layer 110, and the conductive layer 112b can be improved, and occurrence of defects such as breakage or gaps in the layers can be suppressed.
  • the transistor 100 includes a first region in which the insulating layer 110 is provided over the conductive layer 112a, and a second region in which the insulating layer 110 is not provided over the conductive layer 112a. good.
  • the semiconductor layer 105 and the semiconductor layer 108 may be provided in a step between the first region and the second region.
  • the insulating layer 106 may be provided over the semiconductor layer 105 and the semiconductor layer 108, and the conductive layer 104 may be provided so as to overlap the semiconductor layer 105 and the semiconductor layer 108 with the insulating layer 106 interposed therebetween.
  • the semiconductor layer 105 covers the end of the conductive layer 112b on the opening 143 side.
  • FIG. 1B and the like show a structure in which the end portion of the semiconductor layer 105 is located on the conductive layer 112b. It can also be said that the end of the semiconductor layer 105 is in contact with the upper surface of the conductive layer 112b. Note that the semiconductor layer 105 may extend and cover the end of the conductive layer 112b on the side that does not face the opening 143. An end of the semiconductor layer 105 may be in contact with the upper surface of the insulating layer 110.
  • the semiconductor layer 105 is provided to cover the openings 141 and 143. As shown in FIG. 1B and the like, in the opening 141, the semiconductor layer 105 has a region in contact with the upper surface of the conductive layer 112a.
  • the semiconductor layer 108 is provided to cover the semiconductor layer 105. 1B and the like show a configuration in which the semiconductor layer 108 is in contact with the top and side surfaces of the semiconductor layer 105 and the top surface of the conductive layer 112b. Note that the end of the semiconductor layer 108 does not need to be located on the upper surface of the conductive layer 112b. The end of the semiconductor layer 108 may be located on the side surface of the semiconductor layer 105 or may be located on the top surface of the semiconductor layer 105.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108. As shown in FIG. 1B and the like, the semiconductor layer 208 is provided on the insulating layer 120. Note that the semiconductor layer 108 and the semiconductor layer 208 may be formed in different steps. Different materials may be used for the semiconductor layer 108 and the semiconductor layer 208.
  • the semiconductor layer 108 and the semiconductor layer 208 are each shown to have a single-layer structure in FIG. 1B and the like, one embodiment of the present invention is not limited to this.
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure of two or more layers.
  • a part of the insulating layer 106 is provided on the semiconductor layer 108, and another region is provided on the semiconductor layer 208.
  • the conductive layer 104 is provided to cover the openings 141 and 143 with the insulating layer 106 in between.
  • the conductive layer 204 is provided over the insulating layer 106 so as to have a region overlapping with the semiconductor layer 208.
  • the conductive layer 204 can be formed in the same process as the conductive layer 104.
  • the conductive layer 104 has regions that overlap with the semiconductor layer 105 and the semiconductor layer 108 with the insulating layer 106 in between in the opening 141 and the opening 143. Further, the conductive layer 104 has a region overlapping with the conductive layer 112a and a region overlapping with the conductive layer 112b via the insulating layer 106, the semiconductor layer 108, and the semiconductor layer 105. The conductive layer 104 preferably covers the end of the conductive layer 112b on the opening 143 side. With this configuration, the entire region of the semiconductor layer 105 and the semiconductor layer 108 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. be able to. Note that the conductive layer 104 may extend and cover the end of the conductive layer 112b on the side that does not face the opening 143. Further, the conductive layer 104 may extend to and cover the ends of the semiconductor layer 108.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each function as wiring.
  • the transistor 100 can be provided in a region where these wirings overlap, and in a circuit including the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a compact semiconductor device can be realized.
  • the semiconductor device 10 of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be realized.
  • the semiconductor device 10 of one embodiment of the present invention is applied to a driver circuit of a display device (for example, a gate line driver circuit or a source line driver circuit), the area occupied by the driver circuit can be reduced, and A display device can be realized.
  • a driver circuit of a display device for example, a gate line driver circuit or a source line driver circuit
  • the conductive layer 112a which also functions as a wiring
  • the conductive layer 112b, the conductive layer 104, and the conductive layer 204 are provided in different layers. Therefore, since wiring can be arranged in each layer, the degree of freedom in layout is increased and the area occupied by the circuit can be reduced.
  • FIG. 2A is a plan view of transistor 100.
  • FIG. 2B is an enlarged view of transistor 100 shown in FIG. 1B.
  • a region in contact with the conductive layer 112a functions as either a source region or a drain region, and a region in contact with the conductive layer 112b functions as the other source region or drain region. Further, in the semiconductor layer 105 and the semiconductor layer 108, a region between the source region and the drain region functions as a channel formation region.
  • the channel length of the transistor 100 is the distance between the source region and the drain region.
  • the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow.
  • the channel length L100 is the distance between the end of the region where the semiconductor layer 105 and the conductive layer 112a are in contact with each other and the end of the region where the semiconductor layer 105 and the conductive layer 112b are in contact in a cross-sectional view.
  • the channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110 on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110 of the insulating layer 110 and the angle ⁇ 110 between the side surface of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is formed (here, the upper surface of the conductive layer 112a). It is fixed and is not affected by the performance of the exposure equipment used to fabricate the transistor. Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure apparatus, and a fine-sized transistor can be realized.
  • the channel length L100 is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and less than 3.0 ⁇ m, further preferably 0.10 ⁇ m or more and less than 3.0 ⁇ m, and even more preferably 0.15 ⁇ m or more.
  • Less than 3.0 ⁇ m is preferred, more preferably 0.20 ⁇ m or more and less than 3.0 ⁇ m, further preferably 0.20 ⁇ m or more and 2.5 ⁇ m or less, even more preferably 0.20 ⁇ m or more and 2.0 ⁇ m or less, and even more preferably 0.20 ⁇ m or more and less than 2.0 ⁇ m.
  • the thickness is preferably 0.40 ⁇ m or more and 1.0 ⁇ m or less, more preferably 0.50 ⁇ m or more and 1.0 ⁇ m or less.
  • the film thickness T110 of the insulating layer 110 is indicated by a double-dotted chain arrow.
  • the on-current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit that can operate at high speed can be manufactured. Furthermore, it becomes possible to reduce the area occupied by the circuit. Therefore, a compact semiconductor device can be realized. For example, when the semiconductor device 10 of one embodiment of the present invention is applied to a large-sized display device or a high-definition display device, even if the number of wires increases, signal delay in each wire can be reduced, and the display Unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be made narrower.
  • the channel length L100 can be controlled.
  • the thickness T110 of the insulating layer 110 is preferably 0.010 ⁇ m or more and less than 3.0 ⁇ m, more preferably 0.050 ⁇ m or more and 2.5 ⁇ m or less, and even more preferably 0.10 ⁇ m or more and 2.0 ⁇ m or less, and 0.010 ⁇ m or more and less than 3.0 ⁇ m. .15 ⁇ m or more and 1.5 ⁇ m or less, more preferably 0.20 ⁇ m or more and 1.2 ⁇ m or less, further preferably 0.30 ⁇ m or more and 1.0 ⁇ m or less, and even more preferably 0.40 ⁇ m or more and 1.0 ⁇ m or less, and is preferably 0.50 ⁇ m or more and 1.0 ⁇ m or less.
  • the side surface of the insulating layer 110 on the opening 141 side has a tapered shape.
  • the angle ⁇ 110 between the side surface of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is formed is preferably less than 90 degrees.
  • the coverage of the layer provided on the insulating layer 110 (for example, the semiconductor layer 105) can be improved.
  • the angle ⁇ 110 is made small, the contact area between the semiconductor layer 105 and the conductive layer 112a becomes small, and the contact resistance between the semiconductor layer 105 and the conductive layer 112a may become high.
  • the angle ⁇ 110 is, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, and 60 degrees.
  • the angle may be greater than or equal to 80 degrees, greater than or equal to 65 degrees and less than or equal to 80 degrees, or greater than or equal to 70 degrees and less than or equal to 80 degrees. Further, the angle ⁇ 110 may be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.
  • the angle ⁇ 110 within the above range, it is possible to improve the coverage of the layer (for example, the semiconductor layer 105) formed on the conductive layer 112a and the insulating layer 110, and prevent defects such as breaks or holes in the layer. This can be prevented from occurring. Further, contact resistance between the semiconductor layer 105 and the conductive layer 112a can be reduced.
  • FIG. 2B and the like show a configuration in which the shape of the side surface of the insulating layer 110 on the opening 141 side is a straight line in cross-sectional view
  • one embodiment of the present invention is not limited to this.
  • the side surface of the insulating layer 110 on the opening 141 side may have a curved shape, or may have both a straight region and a curved region.
  • the conductive layer 112b is not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side.
  • the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110 on the opening 141 side, which may make it difficult to control the channel length L100. Therefore, it is preferable that the shape of the opening 143 in plan view matches the shape of the opening 141 in plan view, or that the opening 143 includes the opening 141 in plan view.
  • the channel width of the transistor 100 is the width (length) of the source region or the width (length) of the drain region in the direction perpendicular to the channel length direction.
  • the channel width is the width (length) of the region where the semiconductor layer 105 and the conductive layer 112a are in contact, or the width (length) of the region where the semiconductor layer 105 and the conductive layer 112b are in contact in the direction perpendicular to the channel length direction.
  • the channel width of the transistor 100 will be described as the width (length) of a region where the semiconductor layer 105 and the conductive layer 112b are in contact with each other in a direction perpendicular to the channel length direction. In FIGS.
  • the channel width W100 of the transistor 100 is indicated by a solid double-headed arrow.
  • the channel width W100 is the circumferential length of the opening 143 in plan view. Specifically, the channel width W100 is the length of the end of the lower surface (the surface on the insulating layer 110 side) of the conductive layer 112b on the opening 143 side in plan view.
  • the channel width W100 is determined by the shape of the opening 143 in plan view.
  • the width D143 of the opening 143 is indicated by a two-dot chain double-headed arrow.
  • the width D143 refers to the length of the short side of the minimum rectangle circumscribing the opening 143 in plan view.
  • the width D143 of the opening 143 is equal to or larger than the resolution limit of the exposure apparatus.
  • the width D143 is, for example, preferably 0.01 ⁇ m or more and less than 5.0 ⁇ m, more preferably 0.01 ⁇ m or more and less than 4.5 ⁇ m, further preferably 0.01 ⁇ m or more and less than 4.0 ⁇ m, and even more preferably 0.01 ⁇ m or more and less than 4.0 ⁇ m. It is preferably less than .5 ⁇ m, more preferably 0.01 ⁇ m or more and less than 3.0 ⁇ m, further preferably 0.01 ⁇ m or more and 2.5 ⁇ m or less, even more preferably 0.01 ⁇ m or more and 2.0 ⁇ m or less, and even more preferably 0.01 ⁇ m.
  • 1.5 ⁇ m or less is preferable, more preferably 0.30 ⁇ m or more and 1.5 ⁇ m or less, further preferably 0.30 ⁇ m or more and 1.2 ⁇ m or less, even more preferably 0.40 ⁇ m or more and 1.2 ⁇ m or less, and even more preferably 0.30 ⁇ m or more and 1.2 ⁇ m or less, and even more preferably
  • the thickness is preferably .40 ⁇ m or more and 1.0 ⁇ m or less, and more preferably 0.50 ⁇ m or more and 1.0 ⁇ m or less. Note that when the opening 143 has a circular shape in plan view, the width D143 corresponds to the diameter of the opening 143, and the channel width W100 can be calculated as "D143 ⁇ ".
  • FIG. 3A is a top view of transistor 200.
  • FIG. 3B is an enlarged view of transistor 200 shown in FIG. 1B.
  • FIG. 3C is an enlarged view of transistor 200 shown in FIG. 1C.
  • a region in contact with the conductive layer 212a functions as either a source region or a drain region, and a region in contact with the conductive layer 212b functions as the other source region or drain region.
  • a pair of regions 208D is located inside the source region and the drain region, and a pair of regions 208L is located inside the region 208D.
  • Region 208D and region 208L function as LDD regions.
  • the inner side of the pair of regions 208L in plan view, that is, the region overlapping with the conductive layer 204 functions as a channel forming region.
  • the channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap (that is, the channel formation region) between the pair of regions 208L.
  • the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L200 of the transistor 200 is determined by the length of the conductive layer 204, and has a value greater than or equal to the resolution limit of an exposure apparatus used for manufacturing the transistor.
  • the channel length L200 can be 1.5 ⁇ m or more.
  • the channel width of the transistor 200 is the width (length) of the region where the semiconductor layer 208 and the conductive layer 204 overlap in the direction perpendicular to the channel length direction.
  • the channel width W200 of the transistor 200 is indicated by a solid double-headed arrow.
  • the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure apparatus, and the channel length L200 of the transistor 200 can be set to a value greater than or equal to the limit resolution of the exposure apparatus.
  • the transistor 100 by applying the transistor 100 to a transistor that requires a large on-current and applying the transistor 200 to a transistor that requires high saturation characteristics, a high-performance semiconductor device 10 that takes advantage of the advantages of each transistor can be realized. Can be done.
  • the transistor 100 and the transistor 200 which have different structures and channel lengths, can be formed over the substrate 102 by using some steps in common.
  • the conductive layer 112a and the conductive layer 202a can be formed in the same process.
  • the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same process.
  • the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process. Therefore, the manufacturing cost of the semiconductor device 10 can be reduced.
  • semiconductor layer 105, semiconductor layer 108, semiconductor layer 208 Semiconductor materials that can be used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 are not particularly limited.
  • an elemental semiconductor or a compound semiconductor can be used.
  • silicon or germanium can be used as the single semiconductor.
  • gallium arsenide or silicon germanium can be used.
  • an organic substance having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor materials used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 is not particularly limited. (a semiconductor partially having a crystalline region) may be used. It is preferable to use a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.
  • Silicon can be used for each of the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208.
  • Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • a transistor using amorphous silicon for the semiconductor layer can be formed on a large glass substrate and can be manufactured at low cost.
  • a transistor using polycrystalline silicon for a semiconductor layer has high field effect mobility and can operate at high speed.
  • a transistor using microcrystalline silicon for a semiconductor layer has higher field effect mobility than a transistor using amorphous silicon, and can operate at high speed.
  • the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than the covalent bond or ionic bond, such as van der Waals force.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenide.
  • a chalcogenide is a compound containing chalcogen (an element belonging to Group 16).
  • examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ) .
  • tungsten sulfide typically WS 2
  • tungsten selenide typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenide typically HfSe 2
  • zirconium sulfide typically ZrS 2
  • zirconium selenide typically ZrSe 2
  • the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 each contain a metal oxide (oxide semiconductor).
  • metal oxides that can be used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 include indium oxide, gallium oxide, and zinc oxide. It is preferable that the metal oxide contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification, etc. may include semimetal elements. .
  • the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 are each made of, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), and indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (also written as Ga-Zn oxide, GZO), aluminum zinc oxide (Al-Zn oxide), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide In-Ga-Sn-Zn oxide (also referred to as IGZTO), indium gallium aluminum zinc
  • compositions of metal oxides included in the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 greatly affect the electrical characteristics and reliability of the transistor 100 and the transistor 200.
  • the metal oxide may contain one or more metal elements having a large number of periods in the periodic table.
  • metal elements having a large number of periods include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more nonmetallic elements.
  • the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the atomic ratio of indium is greater than or equal to the atomic ratio of zinc.
  • the atomic ratio of indium is greater than or equal to the atomic ratio of tin.
  • In-M-Zn oxide for the semiconductor layer, use a metal oxide in which the atomic ratio of indium to the sum of the atomic numbers of all metal elements contained is higher than the atomic ratio of element M. Can be done. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M.
  • the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of aluminum.
  • the atomic ratio of indium, element M, and zinc is within the above-mentioned range.
  • the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of tin.
  • the atomic ratio of indium, element M, and zinc is within the above-mentioned range.
  • the ratio of the number of atoms of indium to the sum of the number of atoms of all metal elements contained in the metal oxide is 30 atom % or more and 100 atom % or less, preferably 30 atom % or more and 95 atom % or less, more preferably 35 atom %. % or more and 95 atom% or less, more preferably 35 atom% or more and 90 atom% or less, more preferably 40 atom% or more and 90 atom% or less, more preferably 45 atom% or more and 90 atom% or less, more preferably 50 atom% or more.
  • a metal oxide having a content of 80 atom % or less more preferably 60 atom % or more and 80 atom % or less, more preferably 70 atom % or more and 80 atom % or less.
  • the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is within the above range.
  • the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained is sometimes referred to as the indium content rate. The same applies to other metal elements.
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS Inductively Coupled Plasma-Mass Spectrometry
  • ICP-AES Inductively Coupled Plasma-Atomic Em
  • analysis may be performed by combining two or more of these methods. Note that for elements with a low content rate, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of indium when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1. 2 or less, including cases where the atomic ratio of zinc is greater than 0.1 and 2 or less.
  • a sputtering method or an atomic layer deposition (ALD) method can be preferably used to form the metal oxide.
  • the atomic ratio of the target and the atomic ratio of the metal oxide may be different.
  • the atomic ratio of the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc contained in the target may be about 40% or more and 90% or less.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTS Negative Bias Temperature Stress
  • the PBTS test and NBTS test performed under light irradiation are called PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature) test, respectively. It is called the Illumination Stress test.
  • n-type transistor In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (state where current flows), so the amount of variation in threshold voltage in the PBTS test is an indicator of the reliability of the transistor. This is one of the important items to pay attention to.
  • a transistor with high reliability against application of a positive bias can be obtained.
  • a transistor with a small threshold voltage variation in the PBTS test can be obtained.
  • the gallium content is lower than the indium content.
  • One of the factors that causes the threshold voltage to fluctuate in the PBTS test is the trapping of carriers (electrons in this case) in defect levels at or near the interface between the semiconductor layer and the gate insulating layer.
  • the higher the defect level density the more carriers are trapped at the above-mentioned interface, so the deterioration in the PBTS test becomes more significant.
  • By lowering the gallium content in the region of the semiconductor layer that is in contact with the gate insulating layer it is possible to suppress the generation of the defect level, thereby suppressing fluctuations in the threshold voltage in the PBTS test. can.
  • threshold voltage fluctuations in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer.
  • Gallium contained in metal oxides has a property of attracting oxygen more easily than other metal elements (for example, indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to generate carrier (electron in this case) trap sites. . Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which may cause the threshold voltage to fluctuate.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be applied to the semiconductor layer.
  • a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium it is preferable to apply a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga to the semiconductor layer.
  • the ratio of the number of gallium atoms to the sum of the number of atoms of all metal elements contained is higher than 0 atom % and less than 50 atom %, preferably 0.1 atom % or more and less than 40 atom %, or more.
  • 0.1 atomic % or more and 35 atomic % or less Preferably 0.1 atomic % or more and 30 atomic % or less, more preferably 0.1 atomic % or more and 25 atomic % or less, more preferably 0.1 atomic % or more It is preferable to use a metal oxide having a content of 20 atomic % or less, more preferably 0.1 atomic % or more and 15 atomic % or less, and even more preferably 0.1 atomic % or more and 10 atomic % or less.
  • V O oxygen vacancy
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer.
  • In--Zn oxide can be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of atoms of indium to the sum of the number of atoms of all metal elements contained in the metal oxide.
  • the metal oxide becomes highly crystalline, which suppresses fluctuations in the electrical characteristics of the transistor. Reliability can be increased.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, it is possible to make threshold voltage fluctuations extremely small, especially in PBTS tests.
  • an oxide containing indium and zinc can be used for the semiconductor layer.
  • the present invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M to the semiconductor layer. Further, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the electrical characteristics of the transistor may change.
  • a transistor applied to a region where light can enter has small fluctuations in electrical characteristics under light irradiation and high reliability against light. Reliability with respect to light can be evaluated, for example, by the amount of variation in threshold voltage in an NBTIS test.
  • a transistor with high reliability against light can be obtained.
  • a transistor whose threshold voltage fluctuates in the NBTIS test can be small.
  • a metal oxide in which the atomic ratio of element M is greater than or equal to that of indium has a larger band gap, making it possible to reduce the amount of variation in threshold voltage in transistor NBTIS tests.
  • the band gap of the metal oxide of the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, further preferably 3.0 eV or more, further preferably 3.2 eV or more, and still more preferably 3.0 eV or more. It is preferably 3 eV or more, more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.
  • the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained is 20 at% or more and 70 at% or less, preferably 30 at% or more and 70 at% or less, or more.
  • a metal oxide having a content of preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and even more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.
  • the metal oxide becomes highly crystalline, and diffusion of impurities in the metal oxide can be suppressed. Therefore, by applying a metal oxide with a high zinc content to the semiconductor layer, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, it is possible to realize a semiconductor device that has both excellent electrical characteristics and high reliability.
  • the semiconductor layer may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • the same sputtering target can be used to form the layers, so that manufacturing costs can be reduced.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • a first metal oxide layer having a composition of In:M:Zn 1:3:4 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer.
  • a stacked structure including a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used.
  • the element M it is particularly preferable to use gallium or aluminum.
  • a laminated structure of one selected from indium oxide, indium gallium oxide, and IGZO and one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used. good.
  • the two or more metal oxide layers included in the semiconductor layer may have a stacked structure of a metal oxide layer not containing element M and a metal oxide layer containing element M.
  • a first metal oxide layer having a composition of In:M:Zn 4:0:1 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer.
  • a stacked structure including a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used.
  • a structure may be adopted in which a metal oxide not containing the element M is stacked on a metal oxide layer containing the element M.
  • the transistor 100 has two semiconductor layers, the semiconductor layer 105 and the semiconductor layer 108, each having a different composition, and the transistor 200 has a single semiconductor layer having the same composition as the semiconductor layer 108. It turns out.
  • the transistor 100 including the semiconductor layer 105 having a higher proportion of indium atoms than the semiconductor layer 208 can obtain a larger on-state current than the transistor 200.
  • the semiconductor layer 105 a metal oxide layer having a composition used only for the transistor 100 is used, and for the semiconductor layer 108 and the semiconductor layer 208, metal oxide layers commonly used for the transistor 100 and the transistor 200, respectively, are used. Therefore, the compositions of the metal oxide layers used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 can be appropriately selected depending on the electrical characteristics required for each of the transistors 100 and 200.
  • the semiconductor layer 105 is a metal oxide layer having a higher proportion of indium atoms than the semiconductor layer 108 and the semiconductor layer 208, but the present invention is not limited to this.
  • a metal oxide containing a higher proportion of indium atoms than the semiconductor layer 105 may be used for the semiconductor layer 108 and the semiconductor layer 208.
  • a metal oxide layer with crystallinity As the semiconductor layer, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, a nano-crystalline (NC) structure, or the like can be used.
  • CAAC C-Axis Aligned Crystal
  • NC nano-crystalline
  • the semiconductor layer may have a stacked structure of two or more metal oxide layers having different crystallinity.
  • the layered structure includes a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer
  • the structure can include a region having higher crystallinity than the oxide layer.
  • the second metal oxide layer can have a region having lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • a stacked structure of two or more metal oxide layers having different crystallinity can be formed.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • the thickness of the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, and even more preferably 10 nm or more and 70 nm or less. is preferable, more preferably 15 nm or more and 70 nm or less, further preferably 15 nm or more and 50 nm or less, further preferably 20 nm or more and 50 nm or less, further preferably 20 nm or more and 40 nm or less, and even more preferably 25 nm or more and 40 nm or less.
  • the substrate temperature during the formation of the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 is preferably at least room temperature (25°C) and at most 200°C, more preferably at least room temperature and at most 130°C.
  • V O oxygen vacancies
  • a defect in which hydrogen is present in an oxygen vacancy (hereinafter referred to as V OH ) may function as a donor, and electrons, which are carriers, may be generated.
  • a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.
  • V OH can function as a donor for the oxide semiconductor.
  • V OH in the semiconductor layer when using an oxide semiconductor for the semiconductor layer, it is preferable to reduce V OH in the semiconductor layer as much as possible to make the semiconductor layer highly pure or substantially pure.
  • impurities e.g., water and hydrogen
  • oxygenation treatment By using an oxide semiconductor in which oxygen vacancies (V O ), V O H, and impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be provided. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies (V O ) may be referred to as oxygenation treatment.
  • the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, and less than 1 ⁇ 10 17 cm ⁇ 3 More preferably, it is less than 1 ⁇ 10 16 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but can be set to 1 ⁇ 10 ⁇ 9 cm ⁇ 3 , for example.
  • the electrical resistance of the channel forming region in a state where no channel is formed is as high as possible.
  • the value of the sheet resistance of the channel forming region is preferably 1 ⁇ 10 9 ⁇ / ⁇ or more, more preferably 5 ⁇ 10 9 ⁇ / ⁇ or more, and even more preferably 1 ⁇ 10 10 ⁇ / ⁇ or more.
  • the electrical resistance of the channel forming region in the state where no channel is formed is preferably as high as possible, it is not necessary to set an upper limit value.
  • the value of the sheet resistance of the channel forming region is preferably 1 ⁇ 10 9 ⁇ / ⁇ or more and 1 ⁇ 10 12 ⁇ / ⁇ or less, and 5 ⁇ 10 9 ⁇ / ⁇ or more and 1 ⁇ 10 It is more preferably 12 ⁇ / ⁇ or less, and even more preferably 1 ⁇ 10 10 ⁇ / ⁇ or more and 1 ⁇ 10 12 ⁇ / ⁇ or less.
  • a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field effect mobility compared to a transistor using amorphous silicon.
  • OS transistors have extremely low leakage current between the source and drain (also referred to as off-state current) in the off state, and can retain the charge accumulated in the capacitor connected in series with the transistor for a long period of time. It is. Further, by applying an OS transistor to a semiconductor device, power consumption of the semiconductor device can be reduced.
  • a semiconductor device of one embodiment of the present invention can be applied to, for example, a display device.
  • a display device In order to increase the luminance of light emitted by a light emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light emitting device.
  • the source-drain voltage of the drive transistor included in the pixel circuit OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), so a high voltage can be applied between the source and drain of the OS transistor. . Therefore, by using an OS transistor as the drive transistor included in the pixel circuit, the amount of current flowing through the light emitting device can be increased, and the luminance of the light emitting device can be increased.
  • the OS transistor When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current smaller than the Si transistor with respect to the change in the gate-source voltage. Therefore, by applying an OS transistor as a drive transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, so the amount of current flowing through the light emitting device can be controlled. can be controlled. Therefore, the number of gradations in the pixel circuit can be increased.
  • OS transistors are able to flow a more stable current (saturation current) than Si transistors even when the source-drain voltage gradually increases. can. Therefore, by using an OS transistor as a drive transistor, a stable current can be passed through the light-emitting device even if, for example, there are variations in the current-voltage characteristics of the light-emitting device. That is, when the OS transistor operates in the saturation region, the source-drain current does not substantially change even if the source-drain voltage is increased, so that the luminance of the light-emitting device can be stabilized.
  • OS transistors as drive transistors included in pixel circuits, it is possible to "suppress black floating,” “increase luminance,” “multiple gradations,” and “suppress variations in light-emitting devices.” can be achieved.
  • OS transistors Since OS transistors have small fluctuations in electrical characteristics due to radiation irradiation, that is, have high resistance to radiation, they can be suitably used even in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation.
  • an OS transistor can be suitably used in a pixel circuit of an X-ray flat panel detector.
  • OS transistors can be suitably used in semiconductor devices used in outer space. Radiation includes electromagnetic radiation (eg, x-rays, and gamma rays), and particle radiation (eg, alpha, beta, proton, and neutron radiation).
  • Insulating layer 110 an inorganic insulating material or an organic insulating material can be used.
  • the insulating layer 110 may have a laminated structure of an inorganic insulating material and an organic insulating material.
  • An inorganic insulating material can be suitably used for the insulating layer 110.
  • the inorganic insulating material one or more of oxides, oxynitrides, nitrided oxides, and nitrides can be used.
  • the insulating layer 110 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, and nitride oxide.
  • silicon and aluminum nitride can be used.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • a nitrided oxide refers to a material whose composition contains more nitrogen than oxygen.
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectrometry
  • SIMS X-ray photoelectron spectrometry
  • the insulating layer 110 may have a laminated structure of two or more layers. 1B and the like show a structure in which the insulating layer 110 has a stacked structure of an insulating layer 110a, an insulating layer 110b over the insulating layer 110a, and an insulating layer 110c over the insulating layer 110b. Materials that can be used for the above-described insulating layer 110 can be used for each of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c. Note that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c may each use the same material or different materials. Note that each of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c may have a stacked structure of two or more layers.
  • the thickness of the insulating layer 110b can be configured to be thicker than the thickness of the insulating layer 110a. Further, the thickness of the insulating layer 110b can be made thicker than the thickness of the insulating layer 110c.
  • the deposition rate of the insulating layer 110b is preferably fast. In particular, when the insulating layer 110b is thick, it is preferable that the film formation rate of the insulating layer 110b is fast. By increasing the deposition rate of the insulating layer 110b, productivity can be increased. For example, by increasing the power when forming the insulating layer 110b, the deposition rate can be increased.
  • the insulating layer 110b may have a laminated structure of two or more layers. For example, when the thickness of the insulating layer 110b is increased, the stress in the insulating layer 110b increases, which may cause the substrate to warp. By forming the insulating layer 110b in multiple steps, it may be possible to suppress the occurrence of problems during the process due to stress. Note that in a transmission electron microscopy (TEM) image of a cross section, the boundaries between the layers constituting the insulating layer 110b may become unclear.
  • TEM transmission electron microscopy
  • the insulating layer 110b has low stress.
  • the stress in the insulating layer 110b increases, which may cause the substrate to warp.
  • By reducing the stress in the insulating layer 110b it is possible to suppress the occurrence of problems during the process due to stress, such as warping of the substrate.
  • the insulating layer 110a and the insulating layer 110c each function as a blocking film that suppresses desorption of gas from the insulating layer 110b. It is preferable to use a material in which gas is difficult to diffuse, respectively, for the insulating layer 110a and the insulating layer 110c. It is preferable that the insulating layer 110a and the insulating layer 110c each have a region having a higher film density than the insulating layer 110b. By increasing the film density of the insulating layer 110a and the insulating layer 110c, blocking properties against impurities (for example, water and hydrogen) can be improved. Note that the film density may be different between the insulating layer 110a and the insulating layer 110c.
  • a material containing more nitrogen than the insulating layer 110b can be used for each of the insulating layer 110a and the insulating layer 110c.
  • a material containing more nitrogen than the insulating layer 110b can be used for each of the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 110a and the insulating layer 110c each have a thickness that functions as a blocking film that suppresses gas desorption from the insulating layer 110b, and can be thinner than the insulating layer 110b. .
  • the insulating layer 110a and the insulating layer 110c may have different thicknesses. It is preferable that the deposition rate of the insulating layer 110a and the insulating layer 110c is slower than the deposition rate of the insulating layer 110b, respectively. Note that by slowing down the film formation speed of the insulating layer 110a and the insulating layer 110c, the film density can be increased and the blocking property against impurities can be improved. Similarly, by increasing the substrate temperature during film formation of the insulating layer 110a and the insulating layer 110c, the film density can be increased and the blocking property against impurities can be improved.
  • the difference in film density may be evaluated using a cross-sectional TEM image.
  • TEM observation when the film density is high, the transmission electron (TE) image becomes dense (dark), and when the film density is low, the transmission electron (TE) image becomes pale (bright). Therefore, in a transmission electron (TE) image, the insulating layer 110a and the insulating layer 110c may appear darker (darker) than the insulating layer 110b.
  • the difference in nitrogen content between the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be confirmed by, for example, EDX.
  • EDX EDX
  • the ratio of the peak height of nitrogen to the peak height of silicon in the insulating layer 110a is the peak height of silicon in the insulating layer 110b. is higher than the ratio of the height of the nitrogen peak to the height of the nitrogen peak.
  • the ratio of the peak height of nitrogen to the peak height of silicon in the insulating layer 110c is the height of the silicon peak in the insulating layer 110b. It is higher than the ratio of the height of the nitrogen peak to the height of the nitrogen peak.
  • the peak of a certain element is the peak of a certain element when the count number of the element reaches the maximum value in the spectrum where the horizontal axis shows the energy of the characteristic X-ray and the vertical axis shows the count number (detected value) of the characteristic X-ray.
  • the difference in nitrogen content may be confirmed by the ratio of the count number of nitrogen to the count number of silicon using the count number at the energy of the characteristic X-ray unique to the element.
  • counts at 1.739 keV (Si-K ⁇ ) can be used for silicon
  • counts at 0.392 keV (N-K ⁇ ) can be used for nitrogen.
  • the ratio of the nitrogen count to the silicon count in the insulating layer 110a is higher than the ratio of the nitrogen count to the silicon count in the insulating layer 110b.
  • the ratio of the nitrogen count to the silicon count in the insulating layer 110c is higher than the ratio of the nitrogen count to the silicon count in the insulating layer 110b.
  • the insulating layer 110a and the insulating layer 110c may each have a region where the hydrogen concentration in the film is lower than that in the insulating layer 110b.
  • the difference in hydrogen concentration between the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be evaluated by SIMS, for example.
  • the insulating layer 110 (the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c) will be specifically described using a structure in which a metal oxide is used for a semiconductor layer of a transistor as an example.
  • an inorganic insulating material can be suitably used for each of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c.
  • an oxide or an oxynitride for the insulating layer 110b. It is preferable to use a film that releases oxygen when heated for the insulating layer 110b.
  • silicon oxide or silicon oxynitride can be suitably used for the insulating layer 110b.
  • the insulating layer 110b releases oxygen, oxygen can be supplied from the insulating layer 110b to the semiconductor layer.
  • oxygen vacancies (V O ) and V O H in the semiconductor layer can be reduced, exhibiting good electrical characteristics, In addition, a highly reliable transistor can be realized.
  • the insulating layer 110b preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 110b, oxygen can be easily diffused in the insulating layer 110b, and oxygen can be efficiently supplied from the insulating layer 110b to the semiconductor layer.
  • other treatments for supplying oxygen to the semiconductor layer include heat treatment in an oxygen-containing atmosphere, plasma treatment in an oxygen-containing atmosphere, and the like.
  • Oxygen vacancies (V O ) and V O H in the channel formation region of the transistor are preferably small.
  • oxygen vacancies (V O ) and V O H in the channel formation region have a large influence on the electrical characteristics and reliability of the transistor.
  • V O oxygen vacancies
  • V O H oxygen vacancies
  • the carrier concentration in the channel formation region increases, which may cause a change in the threshold voltage of the transistor or a decrease in reliability.
  • the shorter the channel length the greater the influence of such V O H diffusion on the electrical characteristics and reliability of the transistor.
  • oxygen vacancies (V O ) and V OH can be reduced. Therefore, a transistor with a short channel length and good electrical characteristics and high reliability can be realized.
  • the insulating layer 110b releases little impurity (for example, water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 110b, diffusion of the impurities into the semiconductor layer is suppressed, and a transistor with good electrical characteristics and high reliability can be achieved.
  • impurity for example, water and hydrogen
  • silicon oxide or silicon oxynitride using a PECVD method can be suitably used for the insulating layer 110b.
  • a mixed gas of a gas containing silicon and a gas containing oxygen as the raw material gas.
  • the gas containing silicon for example, one or more of silane, disilane, trisilane, and fluorinated silane can be used.
  • a gas containing oxygen for example, one or more of oxygen (O 2 ), ozone (O 3 ), dinitrogen monoxide (N 2 O), nitrogen monoxide (NO), or nitrogen dioxide (NO 2 ) can be used. Note that by increasing the power during formation of the insulating layer 110b, the amount of impurities (for example, water and hydrogen) released from the insulating layer 110b can be reduced.
  • the insulating layer 110a and the insulating layer 110c each have difficulty in permeating oxygen.
  • the insulating layer 110a and the insulating layer 110c function as a blocking film that suppresses desorption of oxygen from the insulating layer 110b. Further, it is preferable that the insulating layer 110a and the insulating layer 110c each have difficulty in permeating hydrogen.
  • the insulating layer 110a and the insulating layer 110c function as a blocking film that suppresses hydrogen from diffusing from outside the transistor into the semiconductor layer.
  • the film density of the insulating layer 110a and the insulating layer 110c is preferably high. By increasing the film density of the insulating layer 110a and the insulating layer 110c, blocking properties of oxygen and hydrogen can be improved.
  • the film density of the insulating layer 110a and the insulating layer 110c is preferably higher than that of the insulating layer 110b.
  • silicon oxide or silicon oxynitride is used for the insulating layer 110b
  • silicon nitride, silicon nitride oxide, or aluminum oxide can be suitably used for the insulating layer 110a and the insulating layer 110c, respectively.
  • the insulating layer 110a and the insulating layer 110c each have a region containing more nitrogen than the insulating layer 110b, for example.
  • a material containing more nitrogen than the insulating layer 110b can be used for each of the insulating layer 110a and the insulating layer 110c.
  • nitride or nitride oxide for each of the insulating layer 110a and the insulating layer 110c.
  • silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 110a and the insulating layer 110c.
  • the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer decreases. There are cases.
  • oxygen contained in the insulating layer 110b can be suppressed from diffusing upward from a region of the insulating layer 110 that is not in contact with the semiconductor layer.
  • oxygen contained in the insulating layer 110b can be suppressed from diffusing downward from a region of the insulating layer 110 that is not in contact with the semiconductor layer. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer increases, and oxygen vacancies (V O ) and V O H in the semiconductor layer can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.
  • the conductive layer 112a and the conductive layer 112b may be oxidized by oxygen contained in the insulating layer 110b, and the resistance of the conductive layer may increase. Further, the conductive layers 112a and 112b are oxidized by the oxygen contained in the insulating layer 110b, so that the amount of oxygen supplied from the insulating layer 110b to the semiconductor layers (semiconductor layer 105 and semiconductor layer 108) decreases. There are cases where this happens. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112a, oxidation of the conductive layer 112a and increase in resistance can be suppressed.
  • the insulating layer 110c between the insulating layer 110b and the conductive layer 112b, oxidation of the conductive layer 112b and increase in resistance can be suppressed.
  • the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer increases, making it possible to reduce oxygen vacancies (V O ) and V O H in the semiconductor layer, exhibiting good electrical characteristics, and improving reliability. It is possible to realize a transistor with high performance.
  • the insulating layer 110a and the insulating layer 110c preferably have a thickness that functions as an oxygen and hydrogen blocking film. If the thickness of the insulating layer 110a and the insulating layer 110c is thin, the function as a blocking film may be reduced. On the other hand, when the insulating layer 110a and the insulating layer 110c are thick, the area of the semiconductor layer (for example, the semiconductor layer 105) in contact with the insulating layer 110b becomes narrower, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer becomes smaller. It may become less. The thickness of the insulating layer 110a and the insulating layer 110c may be thinner than the thickness of the insulating layer 110b.
  • the thickness of the insulating layer 110a and the insulating layer 110c is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, further preferably 10 nm or more and 70 nm or less, and even more preferably 10 nm or more and 50 nm or less.
  • the thickness is preferably 20 nm or more and 50 nm or less, and more preferably 20 nm or more and 40 nm or less.
  • the insulating layer 110a and the insulating layer 110c preferably release little impurity (for example, water and hydrogen) from themselves. By reducing the release of impurities from the insulating layer 110a and the insulating layer 110c, diffusion of the impurity into the semiconductor layer is suppressed, and a transistor with good electrical characteristics and high reliability can be achieved.
  • impurity for example, water and hydrogen
  • the semiconductor layer in the region in contact with the insulating layer 110a and the semiconductor layer in the region in contact with the insulating layer 110c can also be used as channel formation regions. can function.
  • impurities for example, water and hydrogen
  • the semiconductor layer in the region in contact with the insulating layer 110a and the semiconductor layer in the region in contact with the insulating layer 110c can also be used as channel formation regions. can function.
  • a region of the semiconductor layer in contact with the insulating layer 110a can function as a source region or a drain region. The same applies to the insulating layer 110c.
  • Oxygen may be desorbed from the semiconductor layer due to heat applied in steps subsequent to the formation of the semiconductor layer.
  • increases in oxygen vacancies (V O ) and V OH in the semiconductor layer can be suppressed.
  • the degree of freedom in processing temperature can be increased in steps subsequent to the formation of the semiconductor layer. Specifically, the processing temperature can be increased even in steps subsequent to the formation of the semiconductor layer. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be formed.
  • a configuration may be adopted in which one or more of the insulating layer 110a and the insulating layer 110c is not provided.
  • a configuration may be adopted in which neither the insulating layer 110a nor the insulating layer 110c is provided.
  • the insulating layer 120 a material that can be used for the insulating layer 110 can be used. Note that although the insulating layer 120 is shown to have a single-layer structure in FIG. 1B and the like, one embodiment of the present invention is not limited to this.
  • the insulating layer 120 may have a laminated structure of two or more layers.
  • an insulating layer containing oxygen for the insulating layer 120 in contact with the semiconductor layer 208 it is preferable to use an oxide or an oxynitride for the insulating layer 120.
  • an oxide or an oxynitride for the insulating layer 120 it is preferable to use a film that releases oxygen when heated.
  • silicon oxide or silicon oxynitride can be suitably used for the insulating layer 120.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 that function as a source electrode, a drain electrode, or a gate electrode are chromium, copper, aluminum, Formed using one or more of gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above-mentioned metals.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 each contain one or more of copper, silver, gold, or aluminum, and have low resistance. Any conductive material can be suitably used. In particular, copper or aluminum is preferable because it is excellent in mass productivity.
  • a metal oxide film (also referred to as an oxide conductor) can be used for each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204.
  • the oxide conductor for example, In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide. , In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.
  • oxide conductor (OC)
  • OC oxide conductor
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 are respectively a conductive film containing the aforementioned oxide conductor (metal oxide) and a metal.
  • a stacked structure of conductive films containing an alloy may be used. By using a conductive film containing metal or an alloy, wiring resistance can be reduced.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 each have a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may also be applied.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti
  • the Cu-X alloy film it can be processed by a wet etching process, so it is possible to suppress manufacturing costs.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 202a, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may each use the same material or different materials. .
  • the conductive layer 112a and the conductive layer 112b will be specifically described using a structure in which a metal oxide is used for the semiconductor layer 105 as an example.
  • the conductive layers 112a and 112b may be oxidized by oxygen contained in the semiconductor layer 105, resulting in increased resistance.
  • Oxygen contained in the insulating layer 110b may oxidize the conductive layer 112a and the conductive layer 112b, resulting in increased resistance.
  • oxygen vacancies (V O ) in the semiconductor layer 105 may increase.
  • the conductive layers 112a and 112b are oxidized by oxygen contained in the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 105 may decrease.
  • the transistor 100 Since the transistor 100 has a shorter channel length than the transistor 200, oxygen vacancies (V O ) and V O H in the channel formation region have a greater influence on the electrical characteristics and reliability of the transistor. For example, the diffusion of V O H from the source or drain region to the channel formation region increases the carrier concentration in the channel formation region, which may cause a fluctuation in the threshold voltage of the transistor 100 or a decrease in reliability. . The shorter the channel length, the greater the influence of such V O H diffusion on the electrical characteristics and reliability of the transistor. Therefore, it is preferable to use a material that is difficult to oxidize for each of the conductive layer 112a and the conductive layer 112b that have a region in contact with the semiconductor layer 105.
  • an oxide conductor for each of the conductive layer 112a and the conductive layer 112b.
  • ITO In-Sn oxide
  • ITSO In-Sn-Si oxide
  • a nitride conductor may be used for each of the conductive layer 112a and the conductive layer 112b. Examples of nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 112a and the conductive layer 112b may each have a stacked structure of the aforementioned materials. Note that the conductive layer 112a and the conductive layer 112b may be made of the same material or different materials.
  • the conductive layer 112a and the conductive layer 112b By using a material that is difficult to oxidize for the conductive layer 112a and the conductive layer 112b, the conductive layer is prevented from being oxidized by oxygen contained in the semiconductor layer 105 or oxygen contained in the insulating layer 110b, and the resistance increases. be able to. Further, an increase in oxygen vacancies (V O ) in the semiconductor layer 105 can be suppressed, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 105 can be increased. Therefore, oxygen vacancies (V O ) and V O H in the semiconductor layer 105 can be reduced, and the transistor 100 exhibiting good electrical characteristics and high reliability can be realized.
  • a material that is not easily oxidized may be used for the conductive layer 212a and the conductive layer 212b.
  • Materials that can be used for the conductive layer 112a and the conductive layer 112b can be used for the conductive layer 212a and the conductive layer 212b, respectively.
  • the conductive layer 112a that functions as one of the source electrode or the drain electrode of the transistor 100 and the conductive layer 202a that functions as the second gate electrode of the transistor 200 are each made of one or more of an oxide conductor and a nitride conductor. A plurality of them can be suitably used.
  • each of the conductive layer 112a and the conductive layer 202a may have a two-layer stacked structure, and the above material may be used for the first layer, and a material with lower resistance may be used for the second layer.
  • the second layer one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above-mentioned metals can be suitably used.
  • In-Sn-Si oxide can be suitably used for the first layer and tungsten can be suitably used for the second layer.
  • the configurations of the conductive layer 112a and the conductive layer 202a may be determined depending on the wiring resistance required for the conductive layer 112a and the conductive layer 202a. For example, if the length of the wiring (the conductive layer 112a and the conductive layer 202a) is short and the required wiring resistance is relatively high, the conductive layer 112a and the conductive layer 202a should have a single layer structure and be made of a material that is difficult to oxidize. Good too.
  • the conductive layer 112a and the conductive layer 202a are made of a material that is difficult to oxidize and a material that has low resistance.
  • a laminated structure is applied.
  • the structures of the conductive layer 112a and the conductive layer 202a can be applied to other conductive layers.
  • the conductive layer 112b has a stacked structure of a first conductive layer and a second conductive layer on the first conductive layer, and a part of the second conductive layer is removed to form the first conductive layer. A region is provided where the conductive layer is exposed. The first conductive layer and the semiconductor layer 105 may be in contact with each other in this region.
  • the insulating layer 106 that functions as a gate insulating layer of each of the transistor 100 and the transistor 200 preferably has a low defect density. Since the defect density of the insulating layer 106 is low, the transistor 100 and the transistor 200 can have good electrical characteristics. Further, it is preferable that the insulating layer 106 has a high dielectric strength voltage. Since the insulating layer 106 has a high dielectric strength voltage, the transistors 100 and 200 can have high reliability.
  • the insulating layer 106 one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties can be used, for example.
  • the insulating layer 106 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, and yttrium oxide. , yttrium oxynitride, and Ga-Zn oxide can be used.
  • the insulating layer 106 may be a single layer or a laminated layer.
  • the insulating layer 106 may have a stacked structure of oxide and nitride, for example.
  • a material with a high dielectric constant also referred to as a high-k material
  • the insulating layer 106 preferably releases little impurity (for example, water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 106, diffusion of impurities into the semiconductor layer 108 and the semiconductor layer 208 is suppressed, and the transistors 100 and 200 exhibit good electrical characteristics and are highly reliable. be able to.
  • impurity for example, water and hydrogen
  • the film is preferably formed under conditions that cause less damage to the semiconductor layer 108 and the semiconductor layer 208.
  • the film formation rate also referred to as film formation rate
  • damage to the semiconductor layer 108 and the semiconductor layer 208 can be reduced by forming the insulating layer 106 under low power conditions.
  • the insulating layer 106 will be specifically explained, taking as an example a structure in which a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208.
  • an oxide is added to at least the side of the insulating layer 106 in contact with the semiconductor layer 108 and the semiconductor layer 208, respectively.
  • oxynitride it is preferable to use oxynitride.
  • silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106.
  • the insulating layer 106 may have a stacked structure.
  • the insulating layer 106 can have a stacked structure of an oxide film in contact with the semiconductor layer 108 and the semiconductor layer 208, and a nitride film in contact with the conductive layer 104 and the conductive layer 204.
  • the oxide film for example, one or more of silicon oxide and silicon oxynitride can be suitably used. Silicon nitride can be suitably used as the nitride film.
  • Substrate 102 There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate, It may also be used as the substrate 102.
  • a substrate on which a semiconductor element is provided may be used as the substrate 102. Note that the shapes of the semiconductor substrate and the insulating substrate may be circular or square.
  • a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistor 100 or the like. The peeling layer can be used to separate a semiconductor device from the substrate 102 and transfer it to another substrate after partially or completely completing a semiconductor device thereon. In this case, the transistor 100 and the like can be transferred to a substrate with poor heat resistance or a flexible substrate.
  • FIG. 1B and the like show a structure in which the thickness of a region of the conductive layer 112a in contact with the semiconductor layer 105 and the thickness of a region of the conductive layer 112a not in contact with the semiconductor layer 105 are equal or approximately equal in the transistor 100.
  • the thickness of a region of the conductive layer 112a that is in contact with the semiconductor layer 105 may be different from the thickness of a region of the conductive layer 112a that is not in contact with the semiconductor layer 105.
  • the thickness of a region of the conductive layer 112a that is in contact with the semiconductor layer 105 is preferably thinner than the thickness of a region of the conductive layer 112a that is not in contact with the semiconductor layer 105.
  • the distance from the surface on which the conductive layer 112a is formed (here, the top surface of the substrate 102) to the lowest position of the bottom surface of the conductive layer 104 (the surface on the insulating layer 106 side) is shown as a height H104.
  • the distance from the surface on which the conductive layer 112a is formed (here, the upper surface of the substrate 102) to the highest position of the region where the conductive layer 112a and the semiconductor layer 105 are in contact is shown as a height H112a.
  • the height H104 is preferably equal to or approximately equal to the height H112a.
  • FIG. 4A the height H104 is preferably equal to or approximately equal to the height H112a.
  • the height H104 is preferably lower (shorter) than the height H112a.
  • the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a can be strengthened, and the on-state current of the transistor 100 can be increased. can be increased.
  • the electric field of the gate electrode applied to the channel formation region can be made more uniform.
  • the electric field of the gate electrode applied to the channel formation region is non-uniform
  • the electrical characteristics when the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode and when the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the drain electrode.
  • the electrical characteristics when the source electrode is used as the source electrode may differ. Since the electric field of the gate electrode applied to the channel formation region of the transistor 100 becomes more uniform, the electric characteristics of the transistors can be made equal. Therefore, the transistor 100 can be suitably used in a circuit configuration in which the source and drain are interchanged.
  • the thickness of the conductive layer 112a may be adjusted as appropriate so that the height H104 is equal to the height H112a or is lower (shorter) than the height H112a.
  • FIG. 5A A plan view of the semiconductor device 10A is shown in FIG. 5A.
  • FIG. 5B A cross-sectional view taken along the dashed-dotted line C1-C2 shown in FIG. 5A is shown in FIG. 5B, and a cross-sectional view taken along the dashed-dotted line D1-D2 and dashed-dotted line D3-D4 shown in FIG. 5A is shown in FIG. 5C.
  • the semiconductor device 10A includes a transistor 100 and a transistor 200A.
  • the transistor 200A is different from the transistor 200 (TGSA type transistor) included in the semiconductor device 10 shown in ⁇ Configuration Example 1> described above in that it is a vertical channel type transistor.
  • the semiconductor device 10A differs from the semiconductor device 10 in that the transistor 100 and the transistor 200A are both vertical channel transistors.
  • the transistor 200A includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 202a, an insulating layer 110 (an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c), and a conductive layer 202b.
  • Conductive layer 204 functions as a gate electrode.
  • a portion of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 202a functions as either a source electrode or a drain electrode, and the conductive layer 202b functions as the other source electrode or drain electrode.
  • the insulating layer 110 functions as an interlayer film between the source electrode and the drain electrode.
  • the entire region that overlaps with the gate electrode with the gate insulating layer interposed between the region in contact with the source electrode and the region in contact with the drain electrode functions as a channel formation region. Further, in the semiconductor layer 208, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.
  • a conductive layer 202a is provided on the substrate 102 in a region overlapping with the transistor 200A.
  • An insulating layer 110 is provided on the conductive layer 202a.
  • a conductive layer 202b is provided on the insulating layer 110.
  • the insulating layer 110 has a region sandwiched between a conductive layer 202a and a conductive layer 202b.
  • the conductive layer 202a has a region overlapping with the conductive layer 202b with the insulating layer 110 interposed therebetween.
  • the insulating layer 110 has an opening 241 in a region overlapping with the conductive layer 202a. In the opening 241, the upper surface of the conductive layer 202a is exposed.
  • the conductive layer 202b has an opening 243 in a region overlapping with the conductive layer 202a.
  • the opening 243 is provided in a region overlapping with the opening 241.
  • the semiconductor layer 208 is provided to cover the openings 241 and 243.
  • the semiconductor layer 208 has a region in contact with the top and side surfaces of the conductive layer 202b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 202a.
  • the semiconductor layer 208 is electrically connected to the conductive layer 202a through the opening 241 and the opening 243.
  • the semiconductor layer 208 has a shape along the top and side surfaces of the conductive layer 202b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 202a.
  • the transistor 200A is a vertical channel transistor and has the same structure as the transistor 100 except that it has only one semiconductor layer. Therefore, except for the above-mentioned differences, the content described for the transistor 100 can also be applied to the transistor 200A.
  • the area occupied by the transistor 200A is smaller than the area occupied by the transistor 200 in plan view. Therefore, the semiconductor device 10A including the transistor 100 and the transistor 200A can occupy a smaller area as a whole than the semiconductor device 10 including the transistor 100 and the transistor 200. That is, the semiconductor device 10A can be made smaller than the semiconductor device 10.
  • FIG. 6A A plan view of the semiconductor device 10B is shown in FIG. 6A.
  • FIG. 6B shows a cross-sectional view taken along the dashed-dotted line E1-E2 shown in FIG. 6A
  • FIG. 6C shows a cross-sectional view taken along the dashed-dotted line F1-F2 and dashed-dotted line F3-F4 shown in FIG. 6A.
  • the semiconductor device 10B includes a transistor 100 and a transistor 200B.
  • the transistor 200B is a TGSA transistor, but differs from the transistor 200 in that it does not include a conductive layer 202a.
  • the content described for the transistor 200 can be referred to with respect to the differences other than the above-described differences.
  • the transistor 200B does not have the conductive layer 202a, a structure can be formed on the substrate 102 with better coverage than the transistor 200.
  • FIG. 7A A plan view of the semiconductor device 10C is shown in FIG. 7A.
  • FIG. 7B A cross-sectional view taken along the dashed-dotted line G1-G2 shown in FIG. 7A is shown in FIG. 7B, and a cross-sectional view taken along the dashed-dotted line H1-H2 and dashed-dotted line H3-H4 shown in FIG. 7A is shown in FIG. 7C.
  • the semiconductor device 10C includes a transistor 100A and a transistor 200C.
  • the transistor 100A differs from the transistor 100 in that an insulating layer 207 and a conductive layer 103 are provided between a conductive layer 112a and an insulating layer 110a.
  • the transistor 200C differs from the transistor 200 in that an insulating layer 207 is provided between the conductive layer 202a and the insulating layer 110a.
  • the insulating layer 207 is provided to cover the top and side surfaces of the conductive layer 112a, the top and side surfaces of the conductive layer 202a, and the top surface of the substrate 102.
  • the conductive layer 103 is provided on the insulating layer 207 in a region overlapping with the conductive layer 112a.
  • An opening 148 is provided in the conductive layer 103 in a region overlapping with the opening 141 and the opening 143.
  • the insulating layer 110 is provided to cover the conductive layer 112a, the conductive layer 202a, the insulating layer 207, and the conductive layer 103.
  • the conductive layer 103 has a function as a second gate electrode. Further, a part of the insulating layer 110 (a region sandwiched between the semiconductor layer 105 and the conductive layer 103 in plan view) functions as a second gate insulating layer. Since the transistor 100A includes the conductive layer 103 that functions as a second gate electrode, an electric field can be applied to the semiconductor layer 105 and the semiconductor layer 108 from both the conductive layer 104 and the conductive layer 103. , carrier controllability in the channel forming region can be improved. Therefore, the transistor 100A can achieve higher saturation characteristics than the transistor 100.
  • the contents described with respect to the transistor 100 and the transistor 200 can be referred to, respectively, except for the points mentioned above.
  • FIG. 8A A plan view of the semiconductor device 10D is shown in FIG. 8A.
  • FIG. 8B shows a cross-sectional view along the dashed-dotted line I1-I2 shown in FIG. 8A
  • FIG. 8C shows a cross-sectional view taken along the dashed-dotted line J1-J2 and the dashed-dotted line J3-J4 shown in FIG. 8A.
  • the semiconductor device 10D includes a transistor 100A and a transistor 200D.
  • the transistor 200D differs from the transistor 200B described in ⁇ Configuration Example 3> above in that it includes an insulating layer 207.
  • the semiconductor device 10D includes the transistor 100A and the transistor 200D, the semiconductor device 10D has the effect obtained by the transistor 100A described in ⁇ Configuration Example 4> and the effect obtained by the transistor 200B described in ⁇ Configuration Example 3>. You can enjoy both.
  • FIG. 9A A plan view of the semiconductor device 10E is shown in FIG. 9A.
  • FIG. 9B A cross-sectional view taken along the dashed-dotted line K1-K2 shown in FIG. 9A is shown in FIG. 9B, and a cross-sectional view taken along the dashed-dotted line L1-L2 and dashed-dotted line L3-L4 shown in FIG. 9A is shown in FIG. 9C.
  • the semiconductor device 10E includes a transistor 100B and a transistor 200E.
  • the transistor 100B differs from the transistor 100 in that it has only one semiconductor layer.
  • the transistor 200E differs from the transistor 200 in that it includes two semiconductor layers.
  • the transistor 100B has only one semiconductor layer, the semiconductor layer 108.
  • the semiconductor layer 108 For other configurations, reference can be made to the description of the transistor 100.
  • the transistor 200E has a two-layer stacked structure including a semiconductor layer 215 and a semiconductor layer 208 on the semiconductor layer 215. For other configurations, reference can be made to the description of the transistor 200.
  • the same material that can be used for the semiconductor layer 105 can be used for the semiconductor layer 215, for example.
  • a material having a higher proportion of indium atoms than the semiconductor layer 208 can be used for the semiconductor layer 215.
  • the transistor 200 has a stacked structure including the semiconductor layer 215 and the semiconductor layer 208, a higher on-state current can be obtained than when the transistor 200 includes only the semiconductor layer 208.
  • a material having a lower proportion of indium atoms than the semiconductor layer 208 may be used.
  • the semiconductor layer of the transistor 100 which is a vertical channel transistor
  • the semiconductor layer of the transistor 200 which is a TGSA type transistor
  • the semiconductor layer of the transistor 100B which is a vertical channel transistor
  • the semiconductor layer of the transistor 200E which is a TGSA type transistor
  • FIG. 10A A plan view of the semiconductor device 10F is shown in FIG. 10A.
  • FIG. 10B shows a cross-sectional view along the dashed-dot line M1-M2 shown in FIG. 10A
  • FIG. 10C shows a cross-sectional view along the dashed-dotted line N1-N2 and N3-N4 shown in FIG. 10A.
  • the semiconductor device 10F includes a transistor 100C and a transistor 200F.
  • the transistor 100C differs from the transistor 100 in that it includes a conductive layer 112s over the conductive layer 112a.
  • the transistor 200F differs from the transistor 200 in that a conductive layer 202s is provided over the conductive layer 202a.
  • the conductive layer 112s is provided on the conductive layer 112a so as to have an opening at a position overlapping the openings 141 and 143.
  • the conductive layer 202s is provided on the conductive layer 202a.
  • the insulating layer 110 is provided to cover the conductive layer 112a and the conductive layer 112s, as well as the conductive layer 202a and the conductive layer 202s.
  • the conductive layer 112s and the conductive layer 202s can be formed using the same material and in the same process.
  • the stack of the conductive layer 112a and the conductive layer 112s and the stack of the conductive layer 202a and the conductive layer 202s can be stretched and used as wiring.
  • FIG. 11A A plan view of the semiconductor device 10G is shown in FIG. 11A.
  • FIG. 11B shows a cross-sectional view taken along the dashed-dotted line O1-O2 shown in FIG. 11A
  • FIG. 11C shows a cross-sectional view taken along the dashed-dotted line P1-P2 and dashed-dotted line P3-P4 shown in FIG. 11A.
  • the semiconductor device 10G includes the transistor 100C described in ⁇ Configuration Example 7> and the transistor 200B described in ⁇ Configuration Example 3>.
  • the semiconductor device 10G includes the transistor 100C and the transistor 200B, the semiconductor device 10G has the effect obtained by the transistor 100C described in ⁇ Configuration Example 7> and the effect obtained by the transistor 200B described in ⁇ Configuration Example 3>. You can enjoy both.
  • FIG. 12A A plan view of the semiconductor device 10H is shown in FIG. 12A.
  • FIG. 12B shows a cross-sectional view along the dashed-dotted line Q1-Q2 shown in FIG. 12A
  • FIG. 12C shows a cross-sectional view taken along the dashed-dotted line R1-R2 and the dashed-dotted line R3-R4 shown in FIG. 12A.
  • the semiconductor device 10H includes the transistor 100A and the transistor 200G described in ⁇ Configuration Example 4>.
  • the transistor 200G differs from the transistor 200A described in ⁇ Structure Example 2> in that an insulating layer 207 and a conductive layer 203 are provided between the conductive layer 202a and the insulating layer 110a.
  • the insulating layer 207 is provided to cover the top and side surfaces of the conductive layer 112a, the top and side surfaces of the conductive layer 202a, and the top surface of the substrate 102.
  • a conductive layer 203 is provided on the insulating layer 207 in a region overlapping with the conductive layer 202a.
  • the conductive layer 203 can be formed using the same material and in the same process as the conductive layer 103.
  • An opening 248 is provided in the conductive layer 203 in a region overlapping with the opening 241 and the opening 243.
  • the insulating layer 110 is provided to cover the conductive layer 112a, the conductive layer 103, the conductive layer 202a, the conductive layer 203, and the insulating layer 207.
  • the conductive layer 203 has a function as a second gate electrode. Further, a part of the insulating layer 110 (a region sandwiched between the semiconductor layer 208 and the conductive layer 203 in plan view) has a function as a second gate insulating layer. Since the transistor 200G includes the conductive layer 203 that functions as a second gate electrode, an electric field can be applied to the semiconductor layer 208 from both the conductive layer 204 and the conductive layer 203, and the channel formation region The controllability of the carrier can be improved. Therefore, the transistor 200G can achieve higher saturation characteristics than the transistor 200A.
  • the semiconductor device 10H is similar to the semiconductor device 10A described in ⁇ Configuration Example 2> in that the two transistors (transistor 100A and transistor 200G) included in the semiconductor device are both vertical channel transistors. However, while neither of the two transistors (transistor 100 and transistor 200A) included in the semiconductor device 10A has a second gate electrode, in the semiconductor device 10H, both the transistor 100A and the transistor 200G have a second gate electrode. The difference is that it has two gate electrodes. Therefore, the two transistors included in the semiconductor device 10H can achieve higher saturation characteristics than the two transistors included in the semiconductor device 10A.
  • FIG. 13A A plan view of the semiconductor device 10I is shown in FIG. 13A.
  • FIG. 13B A cross-sectional view along the dashed-dotted line S1-S2 shown in FIG. 13A is shown in FIG. 13B, and a cross-sectional view taken along the dashed-dotted line T1-T2 and the dashed-dotted line T3-T4 shown in FIG. 13A is shown in FIG. 13C.
  • the semiconductor device 10I includes the transistor 100C and the transistor 200H described in ⁇ Configuration Example 7>.
  • the transistor 200H differs from the transistor 200A described in ⁇ Structure Example 2> in that a conductive layer 202t is provided over the conductive layer 202a.
  • the conductive layer 202t is provided on the conductive layer 202a so as to have an opening at a position overlapping the openings 241 and 243.
  • the insulating layer 110 is provided to cover the conductive layer 112a and the conductive layer 112s, as well as the conductive layer 202a and the conductive layer 202t.
  • the conductive layer 112s and the conductive layer 202t can be formed using the same material and in the same process.
  • the stack of the conductive layer 112a and the conductive layer 112s and the stack of the conductive layer 202a and the conductive layer 202t can be stretched and used as wiring.
  • the semiconductor device 10I is similar to the semiconductor device 10A described in ⁇ Configuration Example 2> in that the two transistors (transistor 100C and transistor 200H) included in the semiconductor device are both vertical channel transistors. However, in the semiconductor device 10I, the conductive layer 112s is provided on the conductive layer 112a that functions as one of the source electrode or the drain electrode of the transistor 100C, and the conductive layer 112s is provided on the conductive layer 202a that functions as one of the source electrode or the drain electrode of the transistor 200H.
  • the semiconductor device 10A is different from the two transistors (the transistor 100 and the transistor 200A) in that it includes a conductive layer 202t. Therefore, in the semiconductor device 10I, the stack of the conductive layer 112a and the conductive layer 112s, and the stack of the conductive layer 202a and the conductive layer 202t can be extended to function as wiring.
  • ⁇ Production method example 1> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, a manufacturing method will be described using as an example a structure in which oxide semiconductors are used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 of the semiconductor device 10 illustrated in FIG. 1B.
  • thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method. ) method, ALD method, or the like.
  • CVD method include a plasma enhanced CVD (PECVD) method and a thermal CVD method.
  • PECVD plasma enhanced CVD
  • thermal CVD methods is a metal organic chemical vapor deposition (MOCVD) method.
  • Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be manufactured using spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc. It can be formed by a method such as coating.
  • a photolithography method or the like can be used when processing the thin film that constitutes the semiconductor device.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film forming method using a shielding mask such as a metal mask.
  • One method is to form a resist mask on a thin film to be processed, process the thin film by etching or the like, and then remove the resist mask.
  • the other method is to form a photosensitive thin film, then perform exposure and development to process the thin film into a desired shape.
  • the light used for exposure can be, for example, i-line (wavelength: 365 nm), g-line (wavelength: 436 nm), h-line (wavelength: 405 nm), or a mixture of these.
  • ultraviolet rays, KrF laser light, ArF laser light, etc. can also be used.
  • exposure may be performed using immersion exposure technology.
  • extreme ultraviolet (EUV) light or X-rays may be used.
  • an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or electron beams because extremely fine processing becomes possible. Note that when exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.
  • etching the thin film for example, a dry etching method, a wet etching method, or a sandblasting method can be used.
  • FIGS. 14A to 18B is a diagram illustrating a method for manufacturing the semiconductor device 10. Each figure shows a cross-sectional view taken along the dashed-dotted line A1-A2.
  • a conductive film 112af which becomes the conductive layer 112a and the conductive layer 202a, is formed on the substrate 102 (FIG. 14A).
  • a sputtering method can be suitably used to form the conductive film 112af.
  • a resist mask (not shown) is formed on the conductive film 112af by a photolithography process, and then the conductive layer 112a and the conductive layer 202a are formed by processing the conductive film 112af (FIG. 14B).
  • a wet etching method and a dry etching method may be used.
  • a conductive layer 112a that functions as one of a source electrode or a drain electrode of the transistor 100 and a conductive layer 202a that functions as a second gate electrode of the transistor 200 are formed.
  • a PECVD method can be suitably used to form the insulating film 110af and the insulating film 110bf.
  • After forming the insulating film 110af it is preferable to continuously form the insulating film 110bf in a vacuum without exposing the surface of the insulating film 110af to the atmosphere.
  • By continuously forming the insulating film 110af and the insulating film 110bf attachment of impurities derived from the atmosphere to the surface of the insulating film 110af can be suppressed. Examples of such impurities include water and organic substances.
  • the substrate temperature during formation of the insulating film 110af and the insulating film 110bf is preferably 180° C. or more and 450° C. or less, more preferably 200° C. or more and 450° C. or less, further preferably 250° C. or more and 450° C. or less, and The temperature is preferably 300°C or more and 450°C or less, more preferably 300°C or more and 400°C or less, and even more preferably 350°C or more and 400°C or less.
  • the substrate temperature at the time of forming the insulating film 110af and the insulating film 110bf within the above range, it is possible to reduce the release of impurities (for example, water and hydrogen) from the insulating film 110af and the insulating film 110bf. Diffusion can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.
  • impurities for example, water and hydrogen
  • the insulating film 110af and the insulating film 110bf are formed before the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208, the semiconductor layer 105, the semiconductor layer 110bf are There is no need to be concerned about oxygen desorption from the layer 108 and the semiconductor layer 208.
  • Heat treatment may be performed after forming the insulating film 110af and the insulating film 110bf. By performing the heat treatment, water and hydrogen can be released from the surface and inside of the insulating film 110af and the insulating film 110bf.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 450°C or lower, and even more preferably 300°C or higher and 450°C or lower. Further, the temperature is preferably 300°C or more and 400°C or less, and even more preferably 350°C or more and 400°C or less.
  • the heat treatment can be performed in an atmosphere containing one or more of noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) may be used as the atmosphere containing nitrogen or the atmosphere containing oxygen. Note that it is preferable that the content of hydrogen, water, etc. in the atmosphere is as low as possible.
  • the atmosphere it is preferable to use a high-purity gas having a dew point of -60°C or lower, preferably -100°C or lower.
  • a high-purity gas having a dew point of -60°C or lower, preferably -100°C or lower.
  • an atmosphere containing as little hydrogen, water, or the like as possible it is possible to prevent hydrogen, water, and the like from being taken into the insulating film 110af and the insulating film 110bf as much as possible.
  • an oven or a rapid thermal annealing (RTA) device can be used. By using an RTA device, the heat treatment time can be shortened.
  • a metal oxide layer 180 is formed on the insulating film 110bf (FIG. 14C).
  • the metal oxide layer 180 may be an insulating layer or a conductive layer.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used for the metal oxide layer 180.
  • the metal oxide layer 180 it is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 105, the semiconductor layer 108, or the semiconductor layer 208. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 105, the semiconductor layer 108, or the semiconductor layer 208.
  • a metal oxide film formed using a sputtering target having the same composition as the semiconductor layer 105, the semiconductor layer 108, or the semiconductor layer 208 can be applied. It is preferable to use sputtering targets with the same composition because the manufacturing equipment and sputtering targets can be used in common.
  • the content of gallium is higher than that of the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208.
  • a material with a high oxidation rate can be used for the metal oxide layer 180. It is preferable to use a material with a high gallium content for the metal oxide layer 180 because it can further improve the blocking property against oxygen.
  • the metal oxide layer 180 is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form by sputtering in an atmosphere containing oxygen. Thereby, when forming the metal oxide layer 180, oxygen can be suitably supplied to the insulating film 110bf.
  • the metal oxide layer 180 may be formed by a reactive sputtering method using oxygen as a film-forming gas and a metal target.
  • a reactive sputtering method using oxygen as a film-forming gas and a metal target.
  • oxygen as a film-forming gas
  • metal target aluminum oxide film can be formed.
  • oxygen flow rate ratio the higher the ratio of the oxygen flow rate to the total flow rate of the film-forming gas introduced into the processing chamber of the film-forming apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure within the processing chamber, the higher the concentration of oxygen in the insulating film 110bf. can increase the amount of oxygen supplied to the
  • the oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and still more preferably 90% or more and 100% or less.
  • heat treatment may be performed.
  • the above description can be referred to, so a detailed explanation will be omitted.
  • oxygen may be further supplied to the insulating film 110bf via the metal oxide layer 180.
  • a method for supplying oxygen for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used.
  • the plasma treatment an apparatus that turns oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that turn gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.
  • the metal oxide layer 180 is removed.
  • a wet etching method can be suitably used.
  • the wet etching method it is possible to suppress etching of the insulating film 110bf when removing the metal oxide layer 180. Thereby, it is possible to suppress the film thickness of the insulating film 110bf from becoming thinner, and it is possible to make the film thickness of the insulating layer 110b uniform.
  • the process for supplying oxygen to the insulating film 110bf is not limited to the above-mentioned method.
  • oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc. are supplied to the insulating film 110bf by ion doping, ion implantation, plasma treatment, or the like.
  • oxygen may be supplied to the insulating film 110bf through the film.
  • the film is removed after supplying oxygen.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten is used as the film for suppressing the above-mentioned oxygen desorption. be able to.
  • insulating film 110cf and insulating film 120f [Formation of insulating film 110cf and insulating film 120f] Subsequently, an insulating film 110cf that becomes the insulating layer 110c and an insulating film 120f that becomes the insulating layer 120 are formed on the insulating film 110bf (FIG. 14D).
  • the description regarding the formation of the insulating film 110af and the insulating film 110bf can be referred to, so a detailed description thereof will be omitted.
  • the insulating film 120f is processed to form the insulating layer 120 so as to have a region overlapping with the conductive layer 202a (FIG. 14E).
  • the insulating layer 120 is provided in a region where the semiconductor layer 208 will be provided later.
  • a wet etching method and a dry etching method can be used.
  • a dry etching method can be suitably used.
  • a conductive film 112f which becomes the conductive layer 112b, is formed over the insulating layer 120 and the insulating film 110cf (FIG. 15A).
  • a sputtering method can be suitably used to form the conductive film 112f.
  • the conductive film 112f is processed to form a conductive layer 112B in a region overlapping with the conductive layer 112a (FIG. 15B).
  • a wet etching method and a dry etching method can be used.
  • a wet etching method can be suitably used to form the conductive layer 112B.
  • a portion of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143 (FIG. 15C).
  • a wet etching method and a dry etching method can be used.
  • a wet etching method can be suitably used to form the opening 143.
  • the insulating film 110f (insulating film 110af, insulating film 110bf, and insulating film 110cf) in the region overlapping with the opening 143 is removed, and the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c) having the opening 141 is removed. ) (Fig. 15C).
  • a wet etching method and a dry etching method can be used.
  • a dry etching method can be suitably used to form the opening 141.
  • the conductive layer 112a is exposed.
  • the opening 141 can be formed using, for example, a resist mask (not shown) used to form the opening 143. Specifically, a resist mask is formed on the conductive layer 112B, a part of the conductive layer 112B is removed using the resist mask to form an opening 143, and a part of the insulating film 110f is removed using the resist mask. can be removed to form the opening 141.
  • the opening 141 may be formed using a resist mask different from the resist mask used to form the opening 143.
  • a metal oxide film 105f that will become the semiconductor layer 105 is formed to cover the openings 141 and 143 (FIG. 15D).
  • the metal oxide film 105f is provided in contact with the top surface and side surfaces of the insulating layer 120, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.
  • the metal oxide film 105f is preferably formed by a sputtering method using a metal oxide target.
  • the metal oxide film 105f is preferably a dense film with as few defects as possible. Further, it is preferable that the metal oxide film 105f is a highly pure film in which impurities including hydrogen element are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 105f.
  • oxygen gas when forming the metal oxide film 105f.
  • oxygen gas when forming the metal oxide film 105f oxygen can be suitably supplied into the insulating layer 120 and the insulating layer 110.
  • oxygen when using an oxide for the insulating layer 120, oxygen can be suitably supplied into the insulating layer 120.
  • oxygen when an oxide is used for the insulating layer 110b, oxygen can be suitably supplied into the insulating layer 110b.
  • oxygen is supplied to the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 in a later step. Oxygen vacancies (V O ) and V O H in 208 can be reduced.
  • oxygen gas and an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • oxygen flow rate ratio for example, helium gas, argon gas, xenon gas, etc.
  • the higher the proportion of oxygen gas in the entire deposition gas (oxygen flow rate ratio) when depositing the metal oxide film 105f the higher the crystallinity of the metal oxide film 105f, and the higher the reliability.
  • a transistor can be realized.
  • the lower the oxygen flow rate ratio the lower the crystallinity of the metal oxide film 105f, making it possible to realize a transistor with a large on-current.
  • a stacked structure of two or more metal oxide layers having different crystallinity can be formed.
  • the substrate temperature during formation of the metal oxide film 105f may be between room temperature and 250°C, preferably between room temperature and 200°C, more preferably between room temperature and 140°C.
  • the ALD method When using the ALD method to form the metal oxide film 105f, it is preferable to use a film forming method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method.
  • a thermal ALD method is preferable because it shows extremely high step coverage.
  • the PEALD method is preferable because it shows high step coverage and also enables low-temperature film formation.
  • the metal oxide film can be formed, for example, by an ALD method using a precursor containing a metal element constituting the metal oxide film and an oxidizing agent.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • a precursor containing indium a precursor containing gallium
  • a precursor containing zinc a precursor containing zinc
  • two precursors may be used, one containing indium and the other containing gallium and zinc.
  • precursors containing indium include triethyl indium, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid) indium, cyclopentadienyl indium, indium (III) chloride, and (3 -(dimethylamino)propyl)dimethylindium.
  • precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5- Gallium (III) heptanedioate, dimethylchlorogallium, diethylchlorogallium, and gallium (III) chloride.
  • precursors containing zinc include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioic acid)zinc, and zinc chloride.
  • oxidizing agent examples include ozone, oxygen, and water.
  • adjusting one or more of the type of source gas, the flow rate ratio of the source gas, the time for flowing the source gas, and the order in which the source gases are flowed By adjusting these, it is also possible to form a film whose composition changes continuously. Furthermore, it becomes possible to successively form films having different compositions.
  • the semiconductor layer 105 has a laminated structure, after the first metal oxide film is formed, the next metal oxide film is formed successively without exposing the surface to the atmosphere. It is preferable.
  • treatment is performed to remove impurities (for example, water, hydrogen, and organic substances) adsorbed on the surface of the insulating layer 120 and the surface of the insulating layer 110, and the insulating layer 120 is It is preferable to perform at least one of the following: and a treatment for supplying oxygen into the insulating layer 110.
  • the heat treatment can be performed at a temperature of 70° C. or more and 200° C. or less in a reduced pressure atmosphere.
  • plasma treatment may be performed in an atmosphere containing oxygen.
  • oxygen may be supplied to the insulating layer 120 and the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as dinitrogen monoxide (N 2 O).
  • an oxidizing gas such as dinitrogen monoxide (N 2 O).
  • the metal oxide film 105f is processed into an island shape to form the semiconductor layer 105 (FIG. 16A).
  • the semiconductor layer 105 is formed to have a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, and the side surface and top surface of the conductive layer 112b.
  • a wet etching method and a dry etching method can be used.
  • a wet etching method can be suitably used to form the semiconductor layer 105.
  • a portion of the conductive layer 112b in a region that does not overlap with the semiconductor layer 105 may be etched and become thinner.
  • the insulating layer 120 may be etched and its thickness may be reduced.
  • a portion of the insulating layer 110 (specifically, the insulating layer 110c) in a region that does not overlap with the conductive layer 112b and the insulating layer 120 may be etched and become thinner. Note that in etching the metal oxide film 105f, by using a material with a high selectivity for the insulating layer 110c, it is possible to prevent the thickness of the insulating layer 110c from becoming thin.
  • heat treatment it is preferable to perform heat treatment after forming the metal oxide film 105f or after processing the metal oxide film 105f into the semiconductor layer 105.
  • the heat treatment hydrogen and water contained in the metal oxide film 105f or the semiconductor layer 105 or adsorbed on the surface can be removed. Further, the heat treatment may improve the film quality of the metal oxide film 105f or the semiconductor layer 105 (for example, reduce defects and improve crystallinity).
  • oxygen can also be supplied from the insulating layer 110 to the metal oxide film 105f or the semiconductor layer 105. At this time, it is more preferable to perform heat treatment before processing into the semiconductor layer 105.
  • the above description can be referred to, so a detailed explanation will be omitted.
  • the heat treatment does not need to be performed if unnecessary. Further, the heat treatment may not be performed here, but may also serve as the heat treatment performed in a later step. Further, in some cases, the heat treatment can also be used as a treatment at a high temperature in a later process (for example, a film forming process).
  • a metal oxide film 108f which will become the semiconductor layer 108 and the semiconductor layer 208, is formed so as to cover the semiconductor layer 105, the conductive layer 112b, the insulating layer 120, and the insulating layer 110 (FIG. 16B).
  • the metal oxide film 108f is provided in contact with the top surface and side surfaces of the semiconductor layer 105, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the insulating layer 120, and the top surface of the insulating layer 110.
  • the metal oxide film 108f is formed using a material different in composition, crystallinity, etc. from the semiconductor layer 105.
  • the method for forming the metal oxide film 108f and the heat treatment for the metal oxide film 108f please refer to the above-mentioned method for forming the metal oxide film 105f and the heat treatment for the metal oxide film 105f. It is possible to apply the contents that can be described.
  • the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 16C).
  • the semiconductor layer 108 is formed to have a region overlapping with the semiconductor layer 105.
  • the semiconductor layer 208 is provided so as to have a region overlapping with the conductive layer 202a and the insulating layer 120.
  • the semiconductor layer 108 is a semiconductor layer that functions as a channel formation region of the transistor 100.
  • the semiconductor layer 208 is a semiconductor layer that functions as a channel formation region of the transistor 200.
  • the semiconductor layer 108 and the semiconductor layer 208 each of which functions as a channel formation region of a different transistor, can be formed at the same time. Accordingly, the number of masks required for processing the semiconductor layers can be reduced compared to the case where the semiconductor layer of the transistor 100 and the semiconductor layer of the transistor 200 are formed in separate steps. Furthermore, the total number of steps can be reduced.
  • an insulating film 106f that will become the insulating layer 106 is formed to cover the semiconductor layer 105, the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the insulating layer 120, and the insulating layer 110 (FIG. 17A).
  • PECVD or ALD can be suitably used to form the insulating film 106f.
  • the insulating layer 106 When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses diffusion of oxygen. Since the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is diffused into the conductive layer 104 and the conductive layer 204, respectively, via the insulating layer 106. oxidation of the conductive layer 104 and the conductive layer 204 can be suppressed. As a result, the transistor 100 and the transistor 200 exhibiting good electrical characteristics and high reliability can be realized.
  • barrier film refers to a film that has barrier properties.
  • an insulating layer having barrier properties can be called a barrier insulating layer.
  • barrier property refers to the function of suppressing the diffusion of the corresponding substance (also referred to as low permeability) and the function of capturing or fixing the corresponding substance (also referred to as gettering). Refers to one or both of the following.
  • the insulating layer 106 By increasing the temperature during formation of the insulating film 106f that becomes the gate insulating layer (insulating layer 106) of the transistors 100 and 200, the insulating layer 106 can have fewer defects. However, if the temperature during formation of the insulating film 106f is high, oxygen is desorbed from the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208, resulting in oxygen vacancies in the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208. (V O ) and V O H may increase.
  • the substrate temperature during formation of the insulating film 106f is preferably 180°C or more and 450°C or less, more preferably 200°C or more and 450°C or less, further preferably 250°C or more and 450°C or less, and even more preferably 300°C or more and 450°C or less. is preferable, and more preferably 300°C or more and 400°C or less.
  • plasma treatment may be performed on the surface of the semiconductor layer 108 and the surface of the semiconductor layer 208.
  • impurities for example, water
  • impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and a highly reliable transistor can be achieved. This is particularly suitable when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating film 106f.
  • Plasma treatment can be performed, for example, in an atmosphere containing one or more of oxygen, ozone, nitrogen, dinitrogen monoxide, and argon. Further, it is preferable that the plasma treatment and the formation of the insulating film 106f are performed continuously without exposure to the atmosphere.
  • the insulating film 106f is processed to form the insulating layer 106 (FIG. 17B).
  • the insulating layer 106 is provided so as to have a region overlapping with the conductive layer 112a, the semiconductor layer 105, the semiconductor layer 108, and the conductive layer 112b. Further, the insulating layer 106 is provided so as to have a region overlapping with the conductive layer 202a and the semiconductor layer 208.
  • the insulating layer 106 is provided with an opening 147a and an opening 147b that reach the semiconductor layer 208.
  • a wet etching method and a dry etching method can be used. In particular, a dry etching method can be suitably used.
  • a conductive film 104f which becomes the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, is formed over the insulating layer 106 and the semiconductor layer 208 (FIG. 17C).
  • a sputtering method can be suitably used to form the conductive film 104f.
  • a resist mask (not shown) is formed on the conductive film 104f by a photolithography process, and the conductive film 104f is processed to form the conductive layer 104 (of the transistor 100) that overlaps the semiconductor layer 105 and the semiconductor layer 108.
  • a conductive layer 204 (functions as a first gate electrode of the transistor 200) overlaps with the conductive layer 202a (functions as a gate electrode), a conductive layer 212a (functions as a source of the transistor 200) contacts the upper surface of the semiconductor layer 208 with the conductive layer 204 in between.
  • a conductive layer 212b (functioning as one of the source electrode and the drain electrode of the transistor 200) is formed (FIG. 18A).
  • a wet etching method and a dry etching method can be used for processing the conductive film 104f. Note that due to the processing, the thickness of the insulating layer 106 in the portions that do not overlap with the conductive layer 104, the conductive layer 212a, and the conductive layer 212b may become thinner than the thickness in the portions that overlap. Similarly, a portion of the insulating layer 106 that does not overlap with the conductive layer 204 may be thinner than a portion that overlaps.
  • the transistor 100 can be manufactured.
  • a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106, and the conductive layer 204, the conductive layer 212a, and the conductive layer 212b
  • a region 208L is formed in a region that does not overlap with any of the insulating layer 106 and overlaps with the insulating layer 106 (FIG. 1B).
  • conditions for supplying the impurity 190 are determined in consideration of the material and thickness of the conductive layer 204 serving as a mask so that the impurity 190 is not supplied to the region of the semiconductor layer 208 overlapping with the conductive layer 204 as much as possible. is preferred. Thereby, a channel formation region with a sufficiently reduced impurity concentration can be formed in a region of the semiconductor layer 208 overlapping with the conductive layer 204.
  • impurities may be supplied to the semiconductor layer 108 using the conductive layer 104 as a mask.
  • a region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104 and overlaps with the insulating layer 106 (FIG. 1B).
  • a plasma ion doping method or an ion implantation method can be suitably used. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose amount, and the like. Productivity can be increased by using the plasma ion doping method. Further, by using an ion implantation method using mass separation, the purity of the supplied impurity 190 can be increased.
  • the impurity 190 it is preferable to adjust supply conditions so that the impurity concentration at the surface of the semiconductor layer 208 or a portion close to the surface is highest.
  • the gas containing the impurity element described in Embodiment 1 can be used as a raw material for the impurity 190.
  • the gas containing the impurity element described in Embodiment 1 typically one or more of B 2 H 6 gas and BF 3 gas can be used.
  • B 2 H 6 gas and BF 3 gas can be used as the impurity 190.
  • PH 3 gas can be used as the impurity 190.
  • a mixed gas obtained by diluting these source gases with a noble gas may be used.
  • Examples of raw materials for the impurity 190 include CH 4 , N 2 , NH 3 , AlH 3 , AlCl 3 , SiH 4 , Si 2 H 6 , F 2 , HF, H 2 , (C 5 H 5 ) 2 Mg, and noble Gas can be used. Note that the raw material is not limited to gas, and solid or liquid may be heated and vaporized before use.
  • the addition of the impurity 190 can be controlled by setting conditions such as the accelerating voltage and the dose amount, taking into consideration the composition, density, thickness, etc. of the insulating layer 106 and the semiconductor layer 208.
  • the acceleration voltage can be in the range of, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less.
  • the dose amount is, for example, 1 ⁇ 10 13 ions/cm 2 or more and 1 ⁇ 10 17 ions/cm 2 or less, preferably 1 ⁇ 10 14 ions/cm 2 or more and 5 ⁇ 10 16 ions/cm 2 or less, more preferably can be in the range of 1 ⁇ 10 15 ions/cm 2 or more and 3 ⁇ 10 16 ions/cm 2 or less.
  • the accelerating voltage can be, for example, in the range of 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less.
  • the dose amount is, for example, 1 ⁇ 10 13 ions/cm 2 or more and 1 ⁇ 10 17 ions/cm 2 or less, preferably 1 ⁇ 10 14 ions/cm 2 or more and 5 ⁇ 10 16 ions/cm 2 or less, more preferably can be in the range of 1 ⁇ 10 15 ions/cm 2 or more and 3 ⁇ 10 16 ions/cm 2 or less.
  • the method for supplying the impurity 190 is not limited to this, and for example, plasma treatment or treatment using thermal diffusion by heating may be used.
  • the impurity 190 can be added by generating plasma in a gas atmosphere containing the impurity 190 to be added and performing plasma treatment.
  • a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, etc. can be used as the device for generating the plasma.
  • the transistor 200 can be manufactured.
  • the semiconductor device 10 can be manufactured (FIG. 1B).
  • ⁇ Production method example 2> A manufacturing method will be described below, taking as an example a structure in which oxide semiconductors are used for the semiconductor layer 105, the semiconductor layer 108, and the semiconductor layer 208 of the semiconductor device 10A illustrated in FIG. 5B.
  • FIGS. 19A to 22 is a diagram illustrating a method for manufacturing the semiconductor device 10A. Each figure shows a cross-sectional view taken along the dashed-dotted line C1-C2.
  • the steps from forming the conductive film 112af to forming and removing the metal oxide layer 180 are the same as the manufacturing method shown in ⁇ Manufacturing Method Example 1> described above. Therefore, regarding this step, the description regarding the method for manufacturing the semiconductor device 10 according to FIGS. 14A to 14C can be referred to.
  • the conductive film 112f is processed to form a conductive layer 112B in a region overlapping with the conductive layer 112a and a conductive layer 204B in a region overlapping with the conductive layer 202a (FIG. 19E).
  • the description regarding the formation of the conductive layer 112B (FIG. 15B) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the conductive layer 204B can also be formed at the same time as the conductive layer 112B by applying the same formation conditions as the conductive layer 112B.
  • a portion of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. Furthermore, a portion of the conductive layer 204B is removed to form a conductive layer 202b having an opening 243 (FIG. 20A).
  • the description regarding the formation of the opening 143 (FIG. 15C) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the opening 243 can also be formed at the same time as the opening 143 by applying the same formation conditions as the opening 143.
  • the insulating film 110f (insulating film 110af, insulating film 110bf, and insulating film 110cf) in the regions overlapping with the opening 143 and the opening 243, respectively, is removed, and the insulating layer 110 (insulating layer 110a, insulating film 110cf) having the opening 141 and the opening 241 is removed.
  • layer 110b and insulating layer 110c) are formed (FIG. 20A).
  • the description regarding the formation of the opening 141 (FIG. 15C) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the opening 241 can also be formed at the same time as the opening 141 by applying the same formation conditions as the opening 141.
  • the conductive layer 112a is exposed in the opening 141, and the conductive layer 202a is exposed in the opening 241.
  • a metal oxide film 105f that will become the semiconductor layer 105 is formed so as to cover the openings 141 and 143, and the openings 241 and 243 (FIG. 20B).
  • the metal oxide film 105f is provided in contact with the top surface and side surfaces of the conductive layer 112b, the top surface of the conductive layer 112a, the top surface and side surfaces of the conductive layer 202b, the top surface of the conductive layer 202a, and the top surface and side surfaces of the insulating layer 110.
  • the description regarding the formation of the metal oxide film 105f (FIG. 15D) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the metal oxide film 105f is processed into an island shape to form the semiconductor layer 105 (FIG. 20C).
  • the semiconductor layer 105 is formed to have a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110, and the side surface and top surface of the conductive layer 112b.
  • the description regarding the formation of the semiconductor layer 105 (FIG. 16A) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the heat treatment can be performed under the same conditions as the heat treatment conditions that can be applied to the metal oxide film 105f or the semiconductor layer 105 shown in ⁇ Manufacturing Method Example 1>.
  • a metal oxide film 108f which will become the semiconductor layer 108 and the semiconductor layer 208, is formed so as to cover the semiconductor layer 105, the conductive layer 112b, the conductive layer 202b, the conductive layer 202a, and the insulating layer 110 (FIG. 21A).
  • the metal oxide film 108f is provided in contact with the top surface and side surfaces of the semiconductor layer 105, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the conductive layer 202b, the top surface of the conductive layer 202a, and the top surface and side surfaces of the insulating layer 110. It will be done.
  • the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 21B).
  • the semiconductor layer 108 is formed to have a region overlapping with the semiconductor layer 105.
  • the semiconductor layer 208 is formed to have a region in contact with the top surface of the conductive layer 202a, the side surface of the insulating layer 110, and the side surface and top surface of the conductive layer 202b.
  • the semiconductor layer 108 is a semiconductor layer that functions as a channel formation region of the transistor 100.
  • the semiconductor layer 208 is a semiconductor layer that functions as a channel formation region of the transistor 200A.
  • the semiconductor layer 108 and the semiconductor layer 208 each of which functions as a channel formation region of a different transistor, can be formed at the same time. Accordingly, the number of masks required for processing the semiconductor layers can be reduced compared to the case where the semiconductor layer of the transistor 100 and the semiconductor layer of the transistor 200A are formed in separate steps. Furthermore, the total number of steps can be reduced.
  • the insulating layer 106 is formed to cover the semiconductor layer 105, the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the conductive layer 202b, and the insulating layer 110 (FIG. 21C).
  • the description regarding the formation of the insulating film 106f (FIG. 17A) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • a conductive film 104f that becomes the conductive layer 104 and the conductive layer 204 is formed on the insulating layer 106 (FIG. 22).
  • the description regarding the formation of the conductive film 104f (FIG. 17C) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • a resist mask (not shown) is formed on the conductive film 104f by a photolithography process, and then the conductive film 104f is processed to form the conductive layer 104 functioning as the gate electrode of the transistor 100 and the transistor 200A.
  • a conductive layer 204 is formed to function as a gate electrode (FIG. 5B).
  • the description regarding the formation of the conductive layer 104 (FIG. 18A) shown in ⁇ Manufacturing Method Example 1> can be referred to.
  • the conductive layer 204 can also be formed at the same time as the conductive layer 104 by applying the same formation conditions as the conductive layer 104. Note that due to the processing, the thickness of the insulating layer 106 in a portion that does not overlap with the conductive layer 104 and the conductive layer 204 may become thinner than the thickness in a portion where they overlap.
  • the transistor 100 and the transistor 200A can be manufactured.
  • the semiconductor device 10A can be manufactured (FIG. 5B).
  • the display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used, for example, on relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines.
  • the present invention can be used in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in a display unit of an information terminal (wearable device) such as a wristwatch type or a bracelet type, as well as a device for VR such as a head mounted display (HMD), and glasses. It can be used in the display section of wearable devices that can be worn on the head, such as AR devices.
  • an information terminal such as a wristwatch type or a bracelet type
  • VR head mounted display (HMD)
  • AR devices head mounted display
  • a semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device.
  • the module having the display device includes a module in which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached to the display device, or a COG (Chip On Glass) module. Examples include modules in which integrated circuits (ICs) are mounted using a COF (Chip On Film) method or the like.
  • FIG. 23A shows a perspective view of the display device 50A.
  • the display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together.
  • the substrate 152 is indicated by a broken line.
  • the display device 50A includes a display section 162, a connection section 140, a peripheral circuit section 164, wiring 165, and the like.
  • FIG. 23A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 23A can also be called a display module that includes the display device 50A, an IC, and an FPC.
  • the connecting section 140 is provided outside the display section 162.
  • the connecting portion 140 can be provided along one side or a plurality of sides of the display portion 162.
  • the connecting portion 140 may be singular or plural.
  • FIG. 23A shows an example in which connection parts 140 are provided so as to surround the four sides of the display part.
  • the connection part 140 the common electrode of the display element and the conductive layer are electrically connected, and a potential can be supplied to the common electrode.
  • the peripheral circuit section 164 includes, for example, a scanning line drive circuit (also referred to as a gate driver). Furthermore, the peripheral circuit section 164 may include both a scanning line drive circuit and a signal line drive circuit (also referred to as a source driver).
  • a scanning line drive circuit also referred to as a gate driver
  • the peripheral circuit section 164 may include both a scanning line drive circuit and a signal line drive circuit (also referred to as a source driver).
  • the wiring 165 has a function of supplying signals and power to the display section 162 and the peripheral circuit section 164.
  • the signal and power are input to the wiring 165 from the outside via the FPC 172, or input to the wiring 165 from the IC 173.
  • FIG. 23A shows an example in which the IC 173 is provided on the substrate 151 by a COG method, a COF method, or the like.
  • a COG method a COG method
  • COF method a COF method
  • an IC having one or both of a scanning line drive circuit and a signal line drive circuit can be applied to the IC 173.
  • the display device 50A and the display module may have a configuration in which no IC is provided.
  • the IC may be mounted on the FPC using a COF method or the like.
  • the transistor of one embodiment of the present invention can be applied to one or both of the display portion 162 and the peripheral circuit portion 164 of the display device 50A, for example.
  • the display section 162 is an area for displaying images in the display device 50A, and has a plurality of periodically arranged pixels 230.
  • FIG. 23A shows an enlarged view of one pixel 230.
  • the arrangement of pixels in the display device of this embodiment is not particularly limited, and various arrangements can be applied.
  • Examples of pixel arrays include stripe array, S-stripe array, matrix array, delta array, Bayer array, and pentile array.
  • the pixel 230 shown in FIG. 23A includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. Pixel 230R, pixel 230G, and pixel 230B each function as a subpixel.
  • the pixel 230R, the pixel 230G, and the pixel 230B each include a display element and a circuit that controls driving of the display element.
  • Various elements can be used as the display element, such as liquid crystal elements and light emitting elements.
  • a display element using a shutter method or optical interference method MEMS (Micro Electro Mechanical Systems) element, a microcapsule method, an electrophoresis method, an electrowetting method, an electronic powder fluid (registered trademark) method, etc. may be used. You can also do it.
  • a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material may be used.
  • Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and transflective liquid crystal display devices.
  • the light-emitting element examples include self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers.
  • LEDs Light Emitting Diodes
  • OLEDs Organic LEDs
  • semiconductor lasers As the LED, for example, a mini LED, a micro LED, etc. can be used.
  • Examples of the light-emitting substance included in the light-emitting element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF)). materials), and inorganic compounds (quantum dot materials, etc.).
  • the emitted light color of the light emitting element can be infrared, red, green, blue, cyan, magenta, yellow, white, or the like. Furthermore, color purity can be increased by providing a microcavity structure to the light emitting element.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • FIG. 23B is a block diagram illustrating the display device 50A.
  • the display device 50A includes a display section 162 and a peripheral circuit section 164.
  • the display section 162 has a plurality of pixels 230 arranged periodically.
  • the peripheral circuit section 164 includes a first drive circuit section 231 and a second drive circuit section 232.
  • FIG. 23B shows an example in which the display section 162 has pixels 230 arranged in m rows and n columns (m and n are integers of 1 or more).
  • pixel 230 [m, 1] corresponds to the pixel 230 in the m row and 1st column
  • pixel 230 [1, n] corresponds to the pixel 230 in the 1st row and n column
  • the pixel 230 [m, n ] corresponds to the pixel 230 in the mth row and nth column.
  • the circuit included in the first drive circuit section 231 functions as, for example, a scanning line drive circuit.
  • the circuit included in the second drive circuit section 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit section 231 with the display section 162 in between. Some kind of circuit may be provided at a position facing the second drive circuit section 232 with the display section 162 in between.
  • peripheral circuit section 164 Various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, a logic circuit, etc. can be used for the peripheral circuit section 164.
  • transistors, capacitive elements, and the like can be used for the peripheral circuit section 164.
  • the transistor included in the peripheral circuit portion 164 may be formed in the same process as the transistor included in the pixel 230.
  • the display device 50A is arranged substantially parallel to the wirings 236, each of which is arranged substantially in parallel, and whose potential is controlled by a circuit included in the first drive circuit section 231, and the second drive circuit section 231.
  • a wiring 238 whose potential is controlled by a circuit included in the circuit portion 232.
  • FIG. 23B shows an example in which a wiring 236 and a wiring 238 are connected to the pixel 230.
  • the wiring 236 and the wiring 238 are just an example, and the wiring connected to the pixel 230 is not limited to the wiring 236 and the wiring 238.
  • a configuration example will be described using a latch circuit as an example of a circuit that can be used as a peripheral drive circuit.
  • FIG. 24A is a circuit diagram showing a configuration example of the latch circuit LAT.
  • the latch circuit LAT shown in FIG. 24A includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV.
  • a node N is a node where one of the source or drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitor C31 are electrically connected.
  • the transistor Tr33 when a high potential signal is input to the terminal SMP, the transistor Tr33 is turned on. As a result, the potential of the node N becomes a potential corresponding to the potential of the terminal ROUT, and data corresponding to the signal input from the terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After writing data to the latch circuit LAT, when the potential of the terminal SMP is set to a low potential, the transistor Tr33 is turned off. As a result, the potential of node N is held, and the data written in latch circuit LAT is held.
  • the latch circuit LAT when the potential of the node N is a low potential, data with a value of "0" is held in the latch circuit LAT, and when the potential of the node N is a high potential, the latch circuit LAT holds data with a value of "0". It can be assumed that data with a value of "1" is held in the circuit LAT.
  • transistor Tr33 It is preferable to use a transistor with a small off-state current as the transistor Tr33.
  • An OS transistor can be suitably used as the transistor Tr33. This allows the latch circuit LAT to hold data for a long period of time. Therefore, the frequency of rewriting data to the latch circuit LAT can be reduced.
  • writing data such that a signal input from the terminal SP2 is output to the terminal LIN to the latch circuit LAT is sometimes simply referred to as "writing data to the latch circuit LAT.” That is, for example, writing data with a value of "1" to the latch circuit LAT may be simply referred to as “writing data to the latch circuit LAT.”
  • a semiconductor device can be suitably used for the latch circuit LAT.
  • the transistor 100 or the transistor 200 shown in FIG. 1B or the like can be applied to one or more of the transistor Tr31, the transistor Tr33, the transistor Tr35, and the transistor Tr36.
  • the inverter circuit INV includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitor C41.
  • all the transistors included in the latch circuit LAT can be transistors of the same polarity, such as n-channel type transistors. It can be a transistor. Thereby, for example, in addition to the transistor Tr33, the transistor Tr31, the transistor Tr35, the transistor Tr36, the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47 can be used as OS transistors. Therefore, all the transistors included in the latch circuit LAT can be manufactured in the same process.
  • a semiconductor device can be suitably used in the inverter circuit INV.
  • the transistor 100 or the transistor 200 shown in FIG. 1B or the like can be applied to one or more of the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47.
  • the transistors 100, 100A to 100C, and 200A which are vertical channel transistors, and one or more of the transistors 200G and 200H, the occupied area can be reduced, and a display device with a narrow frame can be realized. It can be done. Furthermore, one or more of the above-described transistors can be suitably used for a transistor that requires a large on-state current. Furthermore, one or more of the transistors 200 and 200B to 200F, which are TGSA type transistors, can be suitably used as a transistor that is required to have high saturation characteristics. Thereby, a high performance display device can be realized.
  • the pixel 230 includes a pixel circuit 51 and a light emitting device 61.
  • the pixel circuit 51 shown in FIG. 25A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.
  • One of the source and drain of the transistor 52A is electrically connected to the gate (first gate) of the transistor 52B and one terminal of the capacitor 53, and the other of the source and drain is electrically connected to the wiring SL. .
  • a gate of the transistor 52A is electrically connected to the wiring GL.
  • One of the source and drain of the transistor 52B and the other terminal of the capacitor 53 are electrically connected to the anode of the light emitting device 61.
  • the other of the source and drain of the transistor 52B is electrically connected to the wiring ANO.
  • the cathode of the light emitting device 61 is electrically connected to the wiring VCOM.
  • the wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238 (see FIG. 23B).
  • the wiring VCOM is a wiring that provides a potential for supplying current to the light emitting device 61.
  • the transistor 52A has a function of controlling the conducting state or non-conducting state between the wiring SL and the gate (first gate) of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.
  • the transistor 52B has a function of controlling the amount of current flowing to the light emitting device 61.
  • the capacitor 53 has a function of holding the gate (first gate) potential of the transistor 52B.
  • the intensity of light emitted by the light emitting device 61 is controlled according to the image signal supplied to the gate (first gate) of the transistor 52B.
  • a second gate may be provided in some or all of the transistors included in the pixel circuit 51.
  • the pixel circuit 51 shown in FIG. 25A has a configuration in which the transistor 52B has a second gate, and the second gate is electrically connected to either the source or the drain of the transistor 52B. Note that the second gate of the transistor 52B may be electrically connected to the first gate of the transistor 52B.
  • the aforementioned semiconductor device can be suitably used for the pixel circuit 51.
  • the transistor 100 shown in FIG. 1B or the like can be used as the transistor 52A, and the transistor 200 can be used as the transistor 52B.
  • the pixel 230 includes a pixel circuit 51A and a light emitting device 61.
  • the pixel circuit 51A shown in FIG. 25B mainly differs from the pixel circuit 51 shown in FIG. 25A in that it includes a transistor 52C.
  • the pixel circuit 51A is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53.
  • One of the source and drain of the transistor 52C is electrically connected to one of the source and drain of the transistor 52B.
  • the other of the source and drain of the transistor 52C is electrically connected to the wiring V0.
  • a reference potential is supplied to the wiring V0.
  • the transistor 52C has a function of controlling the conducting state or non-conducting state between one of the source or drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL.
  • the reference potential of the wiring V0 provided via the transistor 52C can suppress variations in the potential between the gate (first gate) and the source of the transistor 52B.
  • the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light emitting device 61 to the outside.
  • the current output to the wiring V0 is converted into a voltage by the source follower circuit, and can be output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.
  • the aforementioned semiconductor device can be suitably used for the pixel circuit 51A.
  • the transistor 100 shown in FIG. 1B or the like can be used as the transistor 52A and the transistor 52C, and the transistor 200 can be used as the transistor 52B.
  • the pixel circuit that can be applied to the display device of one embodiment of the present invention is not particularly limited.
  • FIG. 25C is a cross-sectional view of the pixel circuit 51A.
  • FIG. 25C shows a configuration in which the semiconductor device 10 shown in FIG. 1B etc. is applied to the pixel circuit 51A. Specifically, a configuration is shown in which the transistor 100 is applied to the transistor 52A and the transistor 52C, and the transistor 200 is applied to the transistor 52B.
  • the transistor 52B which functions as a drive transistor to control the current flowing to the light emitting device 61, has higher saturation characteristics than the transistor 52A, which functions as a selection transistor to control the selection state of the pixel 230.
  • the transistor 52B which functions as a drive transistor to control the current flowing to the light emitting device 61
  • the transistor 52A which functions as a selection transistor to control the selection state of the pixel 230.
  • the transistor 100 may be applied to the transistor 52B.
  • a vertical channel type transistor 100 with a short channel length as the transistor 52B, a display device with high brightness can be realized. Further, the area occupied by the pixel circuit 51A can be reduced, and a high-definition display device can be realized.
  • the conductive layer 212b of the transistor 52B is electrically connected to the conductive layer 202a through the opening 139 provided in the insulating layer 120 and the insulating layer 110. Further, the conductive layer 212b is electrically connected to the conductive layer 112b included in the transistor 52C. Note that in FIG. 25C, the electrical connection between the transistor 52A and the transistor 52B is omitted. For example, a first opening reaching the conductive layer 112b of the transistor 52A and a second opening reaching the conductive layer 204 of the transistor 52B are provided in the insulating layer 195.
  • the conductive layer 112b of the transistor 52A and the conductive layer of the transistor 52B can be connected to each other via the first wiring.
  • the layer 204 can be electrically connected.
  • the capacitor 53 is omitted.
  • the capacitor 53 is located, for example, in a region where the insulating layer 106 is sandwiched between the conductive layer 204 that functions as the gate electrode of the transistor 52B and the conductive layer 112b that functions as either the source electrode or the drain electrode of the transistor 52C. can be formed. Note that the configuration of the capacitor 53 is not particularly limited.
  • An insulating layer 195 is provided to cover the transistors 52A, 52B, 52C, and the capacitor 53, and an insulating layer 235 is provided to cover the insulating layer 195.
  • a light emitting device 61 can be provided on the insulating layer 235.
  • FIG. 25C shows the pixel electrode 111 functioning as one electrode of the light emitting device 61.
  • the pixel electrode 111 is electrically connected to the conductive layer 112b of the transistor 52C through an opening 135 provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the insulating layer 195 functions as a protective layer for the transistor 52A, the transistor 52B, and the transistor 52C.
  • the insulating layer 195 By providing the insulating layer 195, diffusion of impurities (for example, water and hydrogen) from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.
  • the insulating layer 235 has a function of reducing unevenness caused by the transistors 52A, 52B, and 52C, and making the surface on which the light-emitting device 61 is formed more flat. Note that in this specification and the like, the insulating layer 235 is sometimes referred to as a planarization layer.
  • the insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material.
  • an inorganic material such as an oxide, an oxynitride, a nitride oxide, or a nitride can be suitably used. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • the organic material for example, one or more of acrylic resin and polyimide resin can be used. A photosensitive material may be used as the organic material. Further, two or more of the above-mentioned insulating layers may be stacked and used.
  • the insulating layer 195 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.
  • an insulating layer containing an organic material can be suitably used. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin. Note that in this specification and the like, acrylic resin does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to the entire acrylic polymer in a broad sense.
  • the insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film.
  • examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may have a stacked structure of an organic insulating film and an inorganic insulating film.
  • the outermost layer of the insulating layer 235 preferably functions as an etching protection layer. Thereby, formation of a recess in the insulating layer 235 can be suppressed during processing of the pixel electrode 111. Alternatively, a recess may be provided in the insulating layer 235 when the pixel electrode 111 is processed.
  • the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer.
  • the insulating layer 235 can have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer.
  • an inorganic insulating layer on the outermost surface of the insulating layer 235, it can function as an etching protection layer. This can prevent a portion of the insulating layer 235 from being etched when forming the pixel electrode 111 and reducing the flatness of the insulating layer 235.
  • the display device of one embodiment of the present invention is a top emission type display device that emits light in the opposite direction to the substrate on which the light-emitting device is formed, and a display device that emits light in the opposite direction to the substrate on which the light-emitting device is formed. It may be either a bottom emission type (bottom emission type) or a double emission type (dual emission type) that emits light on both sides.
  • FIG. 26 shows a part of the area including the FPC 172, a part of the peripheral circuit part 164, a part of the display part 162, a part of the connection part 140, and a part of the area including the end of the display device 50A. An example of a cross section when each is cut is shown.
  • the display device 50A shown in FIG. 26 includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light emitting element 130R, a light emitting element 130G, a light emitting element 130B, etc. between the substrate 151 and the substrate 152.
  • the light emitting element 130R is a display element included in the pixel 230R that emits red light
  • the light emitting element 130G is a display element included in the pixel 230G that emits green light
  • the light emitting element 130B is a display element included in the pixel 230B that emits blue light. This is a display element possessed by
  • the SBS structure is applied to the display device 50A.
  • materials and configurations can be optimized for each light emitting element, which increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability.
  • the display device 50A is a top emission type.
  • a transistor or the like can be placed overlapping the light-emitting region of the light-emitting element, so the aperture ratio of the pixel can be increased compared to the bottom-emission type.
  • the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed on the substrate 151. These transistors can be manufactured using the same material and the same process.
  • An OS transistor can be suitably used as the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B.
  • the transistor of one embodiment of the present invention can be used as the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B.
  • the display device 50A includes the transistor of one embodiment of the present invention in both the display portion 162 and the peripheral circuit portion 164. Note that although FIG. 26 shows an example in which a TGSA type transistor is used in the display portion 162 and a vertical channel type transistor is used in the peripheral circuit portion 164, the present invention is not limited to this.
  • a vertical channel transistor may be used in the display portion 162, and a TGSA transistor may be used in the peripheral circuit portion 164.
  • the vertical channel type transistors can be used.
  • the pixel size can be reduced and the definition can be improved.
  • the vertical channel transistor of one embodiment of the present invention in the peripheral circuit portion 164 the area occupied by the peripheral circuit portion 164 can be reduced, and the frame can be made narrower.
  • the description of the previous embodiment can be referred to.
  • the transistor provided in the peripheral circuit portion 164 may require a larger on-state current. It is preferable to use a transistor with a short channel length in the peripheral circuit section 164.
  • the peripheral circuit section 164 one or more of the transistors 100, 100A to 100C, the transistor 200A, the transistor 200G, and the transistor 200H described above can be suitably used.
  • the occupied area can be reduced, and a display device with a narrow frame can be realized.
  • the transistor provided in the display portion 162 one or more of the transistors 200 and 200B to 200F described above can be suitably used. FIG.
  • 26 shows a structure in which the above-described transistor 100 is applied to the transistor 205D, and the transistor 200 is applied to the transistor 205R, the transistor 205G, and the transistor 205B.
  • the display section 162 may use one or more of the transistors 100, 100A to 100C, the transistor 200A, the transistor 200G, and the transistor 200H, and the peripheral circuit section 164 may include the transistor 200, the transistor 200B to the transistor One or more types of 200F may be used.
  • the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention.
  • a transistor according to one embodiment of the present invention and a transistor having another structure may be combined.
  • the display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistor included in the display device of this embodiment may be either a top gate type or a bottom gate type.
  • gate electrodes may be provided above and below the semiconductor layer in which the channel is formed.
  • the display device of this embodiment may include a transistor using silicon for a channel formation region (Si transistor).
  • silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon.
  • a transistor having LTPS in a semiconductor layer hereinafter also referred to as an LTPS transistor
  • LTPS transistors have high field effect mobility and good frequency characteristics.
  • the OS transistor When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current smaller than the Si transistor with respect to the change in the gate-source voltage. Therefore, by applying an OS transistor as a drive transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the voltage between the gate and source. can be controlled. Therefore, the number of gradations in the pixel circuit can be increased.
  • OS transistors are able to flow a more stable current (saturation current) than Si transistors even when the source-drain voltage gradually increases. can. Therefore, by using the OS transistor as a drive transistor, a stable current can be passed through the light emitting element even if, for example, variations occur in the current-voltage characteristics of the EL element. That is, when the OS transistor operates in the saturation region, the source-drain current does not substantially change even if the source-drain voltage changes, so that the luminance of the light emitting element can be stabilized.
  • the transistors included in the peripheral circuit section 164 and the transistors included in the display section 162 may have the same structure, or may have different structures.
  • the plurality of transistors included in the peripheral circuit section 164 may all have the same structure, or may have two or more types.
  • the plurality of transistors included in the display section 162 may all have the same structure, or may have two or more types.
  • All of the transistors included in the display section 162 may be OS transistors, all of the transistors included in the display section 162 may be Si transistors, or some of the transistors included in the display section 162 may be OS transistors and the rest may be Si transistors. good.
  • an LTPS transistor for example, by using both an LTPS transistor and an OS transistor in the display section 162, a display device with low power consumption and high driving ability can be realized. Furthermore, a configuration in which an LTPS transistor and an OS transistor are combined is sometimes referred to as an LTPO.
  • An insulating layer 195 is provided to cover the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, and an insulating layer 235 is provided over the insulating layer 195.
  • a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided on the insulating layer 235.
  • the light emitting element 130R includes a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light emitting element 130R shown in FIG. 26 emits red light (R).
  • the EL layer 113R has a light emitting layer that emits red light.
  • the light emitting element 130G includes a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light emitting element 130G shown in FIG. 26 emits green light (G).
  • the EL layer 113G has a light emitting layer that emits green light.
  • the light emitting element 130B includes a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light emitting element 130B shown in FIG. 26 emits blue light (B).
  • the EL layer 113B has a light emitting layer that emits blue light.
  • the thickness is not limited to this.
  • the thicknesses of the EL layer 113R, EL layer 113G, and EL layer 113B may be different.
  • the pixel electrode 111R is electrically connected to the conductive layer 212b of the transistor 205R through openings provided in the insulating layer 195 and the insulating layer 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 212b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 212b of the transistor 205B.
  • the ends of each of the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall (also referred to as a bank, bank, or spacer).
  • the insulating layer 237 can be provided in a single layer structure or a laminated structure using one or both of an inorganic insulating material and an organic insulating material. For example, a material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Further, the insulating layer 237 can electrically insulate adjacent light emitting elements from each other.
  • the common electrode 115 is a continuous film provided in common to the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B.
  • the common electrode 115 shared by the plurality of light emitting elements is electrically connected to the conductive layer 123 provided in the connection part 140.
  • the conductive layer 123 it is preferable to use a conductive layer formed of the same material and in the same process as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.
  • a conductive film that transmits visible light is used for the light extraction side of the pixel electrode and the common electrode. Further, it is preferable to use a conductive film that reflects visible light for the electrode on the side from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the material for forming the pair of electrodes of the light emitting element metals, alloys, electrically conductive compounds, mixtures thereof, and the like can be used as appropriate.
  • the materials include aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, and yttrium. , metals such as neodymium, and alloys containing these in appropriate combinations.
  • such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and Examples include In-W-Zn oxide.
  • such materials include alloys containing aluminum (aluminum alloys) such as alloys of aluminum, nickel, and lanthanum (Al-Ni-La), alloys of silver and magnesium, and alloys of silver, palladium, and copper ( Examples include alloys containing silver such as Ag-Pd-Cu (also referred to as APC).
  • such materials include elements belonging to Group 1 or Group 2 of the Periodic Table of Elements (for example, lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, and appropriate combinations of these.
  • Examples include alloys containing carbon dioxide, graphene, etc.
  • a micro optical resonator (microcavity) structure is applied to the light emitting element. Therefore, one of the pair of electrodes included in the light emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent/semi-reflective electrode), and the other is an electrode that is reflective to visible light ( A reflective electrode) is preferable. Since the light emitting element has a microcavity structure, the light emitted from the light emitting layer can resonate between both electrodes, and the light emitted from the light emitting element can be intensified.
  • the light transmittance of the transparent electrode is 40% or more.
  • an electrode having a transmittance of visible light (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more as the transparent electrode of the light emitting element.
  • the visible light reflectance of the semi-transparent/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layer 113R, EL layer 113G, and EL layer 113B are each provided in an island shape.
  • the ends of the adjacent EL layers 113R and the ends of the EL layers 113G overlap, and the ends of the adjacent EL layers 113G and the ends of the EL layers 113B overlap.
  • the ends of the adjacent EL layers 113R and the ends of the EL layers 113B overlap.
  • the ends of adjacent EL layers may overlap each other, as shown in FIG. 26, but the invention is not limited to this. That is, adjacent EL layers do not overlap and may be spaced apart from each other.
  • the EL layer 113R, EL layer 113G, and EL layer 113B each have at least a light emitting layer.
  • the luminescent layer contains one or more luminescent substances.
  • a substance exhibiting a luminescent color such as blue, violet, blue-violet, green, yellow-green, yellow, orange, or red is appropriately used.
  • a substance that emits near-infrared light can also be used as the light-emitting substance.
  • Examples of light-emitting substances include fluorescent materials, phosphorescent materials, TADF materials, quantum dot materials, and the like.
  • the light emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light emitting substance (guest material).
  • organic compounds host material, assist material, etc.
  • one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transporting properties and hole transporting properties
  • a TADF material may be used as one or more kinds of organic compounds.
  • the light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that tends to form an exciplex.
  • ExTET Exciplex-Triplet Energy Transfer
  • a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest energy absorption band of the light-emitting substance energy transfer becomes smoother and luminescence can be efficiently obtained.
  • high efficiency, low voltage drive, and long life of the light emitting element can be achieved at the same time.
  • the EL layer includes a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transporting material (hole transport layer), and a substance with high electron blocking properties.
  • hole injection layer a layer containing a substance with high hole injection properties
  • hole transport layer a layer containing a hole transporting material
  • hole blocking layer a layer containing a substance with high electron blocking property
  • the EL layer may include one or both of a bipolar material and a TADF material.
  • the light-emitting element can use either a low-molecular compound or a high-molecular compound, and may also contain an inorganic compound.
  • the layers constituting the light emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a single structure (a structure having only one light emitting unit) or a tandem structure (a structure having a plurality of light emitting units) may be applied to the light emitting element.
  • the light emitting unit has at least one light emitting layer.
  • the tandem structure is a structure in which a plurality of light emitting units are connected in series via a charge generation layer.
  • the charge generation layer has a function of injecting electrons into one of the two light emitting units and injecting holes into the other when a voltage is applied between the pair of electrodes.
  • the EL layer 113R has a structure that has a plurality of light emitting units that emit red light
  • the EL layer 113G has a structure that has a plurality of light emitting units that emit green light
  • the EL layer 113B preferably has a structure including a plurality of light emitting units that emit blue light.
  • a protective layer 131 is provided on the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B.
  • the protective layer 131 and the substrate 152 are bonded to each other via an adhesive layer 142.
  • a light shielding layer 117 is provided on the substrate 152.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light emitting element.
  • the space between substrate 152 and substrate 151 is filled with adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon) and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap the light emitting element.
  • the space may be filled with a resin different from that of the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display section 162, and is preferably provided so as to cover the entire display section 162. It is preferable that the protective layer 131 is provided so as to cover not only the display section 162 but also the connection section 140 and the peripheral circuit section 164. Moreover, it is preferable that the protective layer 131 is provided up to the end of the display device 50A. On the other hand, in the connecting portion 168, there is a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light emitting elements can be improved.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 does not matter. As the protective layer 131, at least one of an insulating film, a semiconductor film, and a conductive film can be used.
  • the protective layer 131 includes an inorganic film, it prevents the common electrode 115 from being oxidized, prevents impurities (water, oxygen, etc.) from entering the light emitting element, suppresses deterioration of the light emitting element, and improves the reliability of the display device. You can increase your sexuality.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be used.
  • the protective layer 131 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably a nitride insulating film.
  • an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like can also be used. It is preferable that the inorganic film has a high resistance, and specifically, it is preferable that the inorganic film has a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 When emitting light from the light emitting element is extracted through the protective layer 131, the protective layer 131 preferably has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that are highly transparent to visible light.
  • the protective layer 131 for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. .
  • the laminated structure it is possible to suppress impurities (water, oxygen, etc.) from entering the EL layer side.
  • the protective layer 131 may include an organic film.
  • the protective layer 131 may include both an organic film and an inorganic film.
  • Examples of the organic film that can be used for the protective layer 131 include an organic insulating film that can be used for the insulating layer 235.
  • a connecting portion 168 is provided in a region of the substrate 151 where the substrate 152 does not overlap.
  • the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 166 has a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 168. Thereby, the connection portion 168 and the FPC 172 can be electrically connected via the connection layer 242.
  • the wiring 165 is electrically connected to a transistor included in the peripheral circuit section 164.
  • FIG. 26 shows a structure in which the conductive layer 112b of the transistor 205D is extended and functions as a wiring 165. Note that the configuration of the wiring 165 is not limited to this.
  • the display device 50A is a top emission type. Light emitted by the light emitting element is emitted to the substrate 152 side.
  • the substrate 152 is preferably made of a material that is highly transparent to visible light.
  • the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B include a material that reflects visible light, and the counter electrode (common electrode 115) includes a material that transmits visible light.
  • the light shielding layer 117 can be provided between adjacent light emitting elements, at the connection portion 140, the peripheral circuit portion 164, and the like.
  • a colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. By providing a color filter overlapping the light emitting element, the color purity of light emitted from the pixel can be increased.
  • optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151).
  • the optical member include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an antireflection layer, and a light collecting film.
  • surface protection is provided such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that prevents dirt from adhering, a hard coat film that suppresses the occurrence of scratches due to use, and a shock absorption layer. Layers may be arranged.
  • a glass layer or a silica layer (SiO x layer) as the surface protective layer, since surface contamination and scratches can be suppressed.
  • the surface protective layer DLC (diamond-like carbon), aluminum oxide (AlO x ), a polyester material, a polycarbonate material, or the like may be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protective layer. Moreover, it is preferable to use a material with high hardness for the surface protective layer.
  • the substrate 151 and the substrate 152 glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc. can be used, respectively.
  • a material that transmits the light is used for the substrate on the side from which the light from the light emitting element is extracted.
  • a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device increases and a flexible display can be realized.
  • a polarizing plate may be used as at least one of the substrate 151 and the substrate 152.
  • the substrate 151 and the substrate 152 are made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, or polyether sulfone, respectively.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyacrylonitrile resin
  • acrylic resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • PC polycarbonate
  • PC polyether sulfone
  • PS polyamide resin
  • polysiloxane resin polysiloxane resin
  • cycloolefin resin polystyrene resin
  • polyamideimide resin polyurethane resin
  • polyvinyl chloride resin polyvinylidene chloride resin
  • polypropylene resin polytetrafluoroethylene (PTFE) resin
  • PTFE polytetrafluoroethylene
  • ABS resin cellulose
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also referred to as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • various curable adhesives such as a photo-curable adhesive such as an ultraviolet curable adhesive, a reaction-curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used.
  • these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin are preferred.
  • a two-liquid mixed type resin may be used.
  • an adhesive sheet or the like may be used.
  • connection layer 242 an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or the like can be used.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • the display device 50B shown in FIG. 27 mainly differs from the display device 50A in that a light emitting element having a common EL layer 113 and a colored layer (color filter, etc.) are used for each color subpixel. . Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.
  • a display device 50B shown in FIG. 27 includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light emitting element 130R, a light emitting element 130G, a light emitting element 130B, and a coloring device that transmits red light between a substrate 151 and a substrate 152. It includes a layer 132R, a colored layer 132G that transmits green light, a colored layer 132B that transmits blue light, and the like.
  • the light emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.
  • the light emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.
  • the light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.
  • the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B each share the EL layer 113 and the common electrode 115.
  • a configuration in which a common EL layer 113 is provided for subpixels of each color can reduce the number of manufacturing steps, compared to a configuration in which different EL layers are provided for subpixels of each color.
  • a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B shown in FIG. 27 emit white light.
  • the white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, so that light of a desired color can be obtained.
  • the light emitting element that emits white light includes two or more light emitting layers.
  • the light-emitting layers may be selected such that the emission colors of the two light-emitting layers are complementary colors. For example, by making the light emitting color of the first light emitting layer and the light emitting color of the second light emitting layer complementary, it is possible to obtain a configuration in which the light emitting element as a whole emits white light.
  • the light emitting element as a whole may be configured to emit white light by combining the emitted light colors of the three or more light emitting layers.
  • the EL layer 113 preferably has, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light with a longer wavelength than blue light.
  • the EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure for the light emitting element that emits white light.
  • a two-stage tandem structure having a light emitting unit that emits yellow light and a light emitting unit that emits blue light, a light emitting unit that emits red and green light, and a light emitting unit that emits blue light
  • a two-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, a three-stage tandem structure,
  • a three-stage tandem comprising, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits red light, and a light-emitting unit that emits blue light.
  • the number of stacked layers and the order of colors of the light emitting units are: a two-tiered structure of B and Y, a two-tiered structure of B and the light-emitting unit X, a three-tiered structure of B, Y, and B, B, X
  • the three-layer structure of B is listed, and the order of the number and color of the light emitting layers in the light emitting unit X is, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, and a two-layer structure of G and R
  • the structure can be a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Further, another layer may be provided between the two light emitting layers.
  • the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B shown in FIG. 27 emit blue light.
  • the EL layer 113 has one or more light emitting layers that emit blue light.
  • the blue light emitted by the light emitting element 130B can be extracted.
  • the light emitting element 130R by providing a color conversion layer between the light emitting element 130R or the light emitting element 130G and the substrate 152, the light emitting element 130R Alternatively, the blue light emitted by the light emitting element 130G can be converted into light with a longer wavelength to extract red or green light.
  • a colored layer 132R is provided between the color conversion layer and the substrate 152
  • a colored layer 132G is provided between the color conversion layer and the substrate 152. It is preferable to provide one. A part of the light emitted by the light emitting element may be transmitted as is without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer through the colored layer, the colored layer absorbs light of a color other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.
  • the display device 50C shown in FIG. 28 is mainly different from the display device 50B in that it is a bottom emission type display device.
  • the light emitted by the light emitting element is emitted to the substrate 151 side. It is preferable to use a material that has high transparency to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 does not matter.
  • a light shielding layer 117 is formed between the substrate 151 and the transistor.
  • a light shielding layer 117 is provided on a substrate 151, an insulating layer 153 is provided on the light blocking layer 117, and a transistor 205D, a transistor 205R (not shown), a transistor 205G, a transistor 205B, etc. are provided on the insulating layer 153.
  • a colored layer 132R (not shown), a colored layer 132G, and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 235 is provided on the colored layer 132R, the colored layer 132G, and the colored layer 132B.
  • the light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.
  • the light emitting element 130B that overlaps the colored layer 132B includes a pixel electrode 111B, an EL layer 113, and a common electrode 115.
  • the light emitting element 130R that overlaps the colored layer 132R includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.
  • a material having high transparency to visible light is used for each of the pixel electrode 111R (not shown), the pixel electrode 111G, and the pixel electrode 111B. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom emission type display device, a metal with low resistivity or the like can be used for the common electrode 115, so it is possible to suppress the voltage drop caused by the resistance of the common electrode 115, and achieve high display quality. can do.
  • FIG. 28 shows an example in which a TGSA type transistor is used in the display section 162 and a vertical channel type transistor is used in the peripheral circuit section 164
  • the present invention is not limited to this.
  • a vertical channel transistor can be used for both the display portion 162 and the peripheral circuit portion 164. Therefore, for example, by using the vertical channel transistor of one embodiment of the present invention in the display portion 162, the aperture ratio of the pixel can be increased or the size of the pixel can be reduced in a display device with a bottom emission structure. Can be done.
  • the display device 50D shown in FIG. 29A is mainly different from the display device 50A in that it includes a light receiving element 130S.
  • the display device 50D has a light emitting element and a light receiving element in the pixel.
  • the organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.
  • the display section 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all the subpixels included in the display device 50D, some subpixels exhibit light as a light source, some other subpixels perform light detection, and the remaining subpixels You can also display images.
  • the display device 50D it is not necessary to provide a light receiving section and a light source separately from the display device 50D, and the number of parts of the electronic device can be reduced. For example, there is no need to separately provide a biometric authentication device provided in the electronic device or a capacitive touch panel for scrolling or the like. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing cost.
  • the display device 50D can capture an image using the light receiving element.
  • an image sensor can be used to capture images for personal authentication using a fingerprint, a palm print, an iris, a pulse shape (including a vein shape and an artery shape), or a face.
  • the light receiving element can be used as a touch sensor (also referred to as a direct touch sensor) or a non-contact sensor (also referred to as a hover sensor, a hover touch sensor, a touchless sensor), or the like.
  • a touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object (such as a finger, hand, or pen) come into direct contact with each other.
  • a non-contact sensor can detect an object even if the object does not come into contact with the display device.
  • the light receiving element 130S includes a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S.
  • Light Lin enters the functional layer 113S from outside the display device 50D.
  • the pixel electrode 111S is electrically connected to the conductive layer 212b of the transistor 205S through openings provided in the insulating layer 195 and the insulating layer 235.
  • the end of the pixel electrode 111S is covered with an insulating layer 237.
  • the common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B.
  • a common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection part 140.
  • the functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer).
  • the active layer includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors containing organic compounds.
  • an organic semiconductor is used as the semiconductor included in the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (eg, vacuum evaporation method), and a common manufacturing apparatus can be used, which is preferable.
  • the functional layer 113S includes a layer containing a substance with high hole transport properties, a substance with high electron transport properties, a bipolar substance (substance with high electron transport properties and high hole transport properties), etc. as a layer other than the active layer. You may further have it. Furthermore, the layer is not limited to the above, and may further include a layer containing a substance with high hole injection property, a hole blocking material, a substance with high electron injection property, an electron blocking material, or the like. For layers other than the active layer included in the light-receiving element, materials that can be used in the above-mentioned light-emitting element can be used, for example.
  • the light-receiving element can use either a low-molecular compound or a high-molecular compound, and may also contain an inorganic compound.
  • the layers constituting the light-receiving element can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the display device 50D shown in FIGS. 29B and 29C has a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element between the substrate 151 and the substrate 152.
  • the layer 353 includes, for example, the light receiving element 130S.
  • Layer 357 includes, for example, light emitting elements 130R, 130G, and 130B.
  • the circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element.
  • the circuit layer 355 includes, for example, a transistor 205R, a transistor 205G, and a transistor 205B.
  • the circuit layer 355 can be provided with one or more of a switch, a capacitor, a resistor, a wiring, a terminal, and the like.
  • FIG. 29B is an example in which the light receiving element 130S is used as a touch sensor. As shown in FIG. 29B, when the finger 352 in contact with the display device 50D reflects the light emitted by the light emitting element in the layer 357, the light receiving element in the layer 353 detects the reflected light. Thereby, it is possible to detect that the finger 352 has touched the display device 50D.
  • FIG. 29C is an example in which the light receiving element 130S is used as a non-contact sensor. As shown in FIG. 29C, the light emitted by the light emitting element in the layer 357 is reflected by the finger 352 that is close to (that is, not in contact with) the display device 50D, and the light receiving element in the layer 353 reflects the light. Detect light.
  • a display device 50E shown in FIG. 30 is an example of a display device to which the MML structure is applied. That is, the display device 50E has a light emitting element manufactured without using a fine metal mask. Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, so their explanation will be omitted.
  • a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B are provided on the insulating layer 235.
  • the light emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode on the common layer 114. 115.
  • the light emitting element 130R shown in FIG. 30 emits red light (R).
  • Layer 133R has a light emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively called an EL layer.
  • one or both of the conductive layer 124R and the conductive layer 126R can be called a pixel electrode.
  • the light emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode on the common layer 114. 115.
  • the light emitting element 130G shown in FIG. 30 emits green light (G).
  • Layer 133G has a light emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124G and the conductive layer 126G can be called a pixel electrode.
  • the light emitting element 130B includes a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode on the common layer 114. 115.
  • the light emitting element 130B shown in FIG. 30 emits blue light (B).
  • Layer 133B has a light emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124B and the conductive layer 126B can be called a pixel electrode.
  • a layer provided in an island shape for each light emitting element is referred to as a layer 133B, a layer 133G, or a layer 133R, and a layer shared by a plurality of light emitting elements is referred to as a common layer. It is shown as 114. Note that in this specification and the like, the layers 133R, 133G, and 133B may be referred to as an island-shaped EL layer, an island-shaped EL layer, or the like, without including the common layer 114.
  • the layer 133R, the layer 133G, and the layer 133B are spaced apart from each other.
  • the EL layer in an island shape for each light emitting element, leakage current between adjacent light emitting elements can be suppressed. Thereby, crosstalk caused by unintended light emission can be prevented, and a display device with extremely high contrast can be realized.
  • the layer 133R, the layer 133G, and the layer 133B are all shown to have the same thickness, but the thickness is not limited to this.
  • the layer 133R, layer 133G, and layer 133B may have different thicknesses.
  • the conductive layer 124R is electrically connected to the conductive layer 212b of the transistor 205R through openings provided in the insulating layer 195 and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 212b included in the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 212b included in the transistor 205B.
  • the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B are formed to cover the openings provided in the insulating layer 195 and the insulating layer 235.
  • a layer 128 is embedded in each of the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • the layer 128 has a function of flattening the recessed portions of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • a conductive layer 126R, a conductive layer 126G, and a conductive layer are electrically connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, respectively.
  • a layer 126B is provided.
  • the regions of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B that overlap with the recessed portions can also be used as light emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R, the conductive layer 124G and the conductive layer 126G, and the conductive layer 124B and the conductive layer 126B.
  • the layer 128 may be an insulating layer or a conductive layer.
  • various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate.
  • layer 128 is preferably formed using an insulating material, and particularly preferably formed using an organic insulating material.
  • an organic insulating material that can be used for the above-described insulating layer 237 can be applied to the layer 128.
  • FIG. 30 shows an example in which the upper surface of the layer 128 has a flat portion
  • the shape of the layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curve, a concave curve, and a flat surface.
  • the height of the top surface of the layer 128 and the height of the top surface of the conductive layer 124R may match or approximately match, or may be different from each other.
  • the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side surface of the end of the conductive layer 124R. It is preferable that each end of the conductive layer 124R and the conductive layer 126R has a tapered shape. Specifically, each end of the conductive layer 124R and the conductive layer 126R preferably has a tapered shape with a taper angle of less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode also has a tapered shape. By tapering the side surfaces of the pixel electrode, it is possible to improve the coverage of the EL layer provided along the side surfaces of the pixel electrode.
  • the conductive layer 124G, the conductive layer 126G, the conductive layer 124B, and the conductive layer 126B are also the same as the conductive layer 124R and the conductive layer 126R, so a detailed description thereof will be omitted.
  • the top and side surfaces of the conductive layer 126R are covered with a layer 133R.
  • the top and side surfaces of conductive layer 126G are covered by layer 133G
  • the top and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire region where the conductive layer 126R, conductive layer 126G, and conductive layer 126B are provided can be used as the light emitting region of the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B, respectively, so that the aperture ratio of the pixel can be reduced. can be increased.
  • a portion of the upper surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with an insulating layer 125 and an insulating layer 127.
  • a common layer 114 is provided over the layers 133R, 133G, and 133B, as well as the insulating layers 125 and 127, and the common electrode 115 is provided on the common layer 114.
  • the common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light emitting elements.
  • the insulating layer 237 shown in FIG. 26 and the like is not provided between the conductive layer 126R and the layer 133R.
  • the display device 50E is not provided with an insulating layer (also referred to as a partition wall, bank, spacer, etc.) that is in contact with the pixel electrode and covers the upper end of the pixel electrode. Therefore, the interval between adjacent light emitting elements can be made extremely narrow. Therefore, a high definition or high resolution display device can be realized. Further, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.
  • the layer 133R, the layer 133G, and the layer 133B each have a light emitting layer. It is preferable that the layer 133R, the layer 133G, and the layer 133B each include a light emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light emitting layer. Alternatively, each of the layers 133R, 133G, and 133B preferably includes a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably includes a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layer 133R, layer 133G, and layer 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light emitting layer, the light emitting layer is placed on the outermost surface. Exposure can be suppressed and damage to the light emitting layer can be reduced. Thereby, the reliability of the light emitting element can be improved.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B.
  • each of the layers 133R, 133G, and 133B are covered with an insulating layer 125.
  • the insulating layer 127 covers each side surface of the layer 133R, layer 133G, and layer 133B with the insulating layer 125 interposed therebetween.
  • the common layer 114 (or common electrode 115) is covered with at least one of the insulating layer 125 and the insulating layer 127, so that the side surfaces (and part of the top surface) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127. , the layer 133R, the layer 133G, and the side surface of the layer 133B, thereby suppressing short-circuiting of the light emitting element. Thereby, the reliability of the light emitting element can be improved.
  • the insulating layer 125 is in contact with each side surface of the layer 133R, layer 133G, and layer 133B.
  • the insulating layer 125 By configuring the insulating layer 125 to be in contact with the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light emitting element can be improved. .
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recessed portion of the insulating layer 125.
  • the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the space between adjacent island-like layers can be filled, so that the surface on which layers (for example, carrier injection layer, common electrode, etc.) to be formed on the island-like layer can be formed. It is possible to reduce unevenness with large height differences and make the surface more flat. Therefore, coverage of the carrier injection layer, the common electrode, etc. can be improved.
  • layers for example, carrier injection layer, common electrode, etc.
  • the common layer 114 and the common electrode 115 are provided on the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127.
  • the step before providing the insulating layer 125 and the insulating layer 127 there are a region where the pixel electrode and the island-shaped EL layer are provided, a region where the pixel electrode and the island-like EL layer are not provided (a region between the light emitting elements), There is a step caused by this. Since the display device of one embodiment of the present invention includes the insulating layer 125 and the insulating layer 127, the step can be flattened, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, connection failures due to disconnection between the common layer 114 and the common electrode 115 can be suppressed. Furthermore, it is possible to suppress the common electrode 115 from becoming locally thin due to the difference in level, thereby preventing an increase in electrical resistance.
  • the upper surface of the insulating layer 127 preferably has a shape with higher flatness.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 preferably has a smooth shape with high flatness.
  • the insulating layer 125 can be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be used.
  • the insulating layer 125 may have a single layer structure or a laminated structure.
  • aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer in forming an insulating layer 127 to be described later.
  • an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method to the insulating layer 125
  • an insulating layer with few pinholes and an excellent function of protecting the EL layer can be obtained.
  • 125 can be formed.
  • the insulating layer 125 may have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method.
  • the insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen. Further, the insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. Further, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.
  • the insulating layer 125 has a function as a barrier insulating layer or a gettering function, thereby suppressing the intrusion of impurities (typically, at least one of water and oxygen) that can diffuse into each light emitting element from the outside.
  • impurities typically, at least one of water and oxygen
  • the insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and deteriorating the EL layer. Furthermore, by lowering the impurity concentration in the insulating layer 125, barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has sufficiently low hydrogen concentration and carbon concentration, preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has a function of flattening unevenness with a large height difference in the insulating layer 125 formed between adjacent light emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, etc. good. Further, as the insulating layer 127, an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used. Furthermore, a photoresist may be used as the photosensitive resin. As the photosensitive organic resin, either a positive type material or a negative type material may be used.
  • the insulating layer 127 may be made of a material that absorbs visible light. Since the insulating layer 127 absorbs light emitted from the light emitting element, light leakage (stray light) from the light emitting element to an adjacent light emitting element via the insulating layer 127 can be suppressed. Thereby, the display quality of the display device can be improved. Furthermore, since display quality can be improved without using a polarizing plate in the display device, a lightweight and thin display device can be realized.
  • Materials that absorb visible light include materials that contain pigments such as black, materials that contain dyes, resin materials that have light-absorbing properties (for example, polyimide, etc.), and resin materials that can be used for color filters (color filter materials).
  • pigments such as black
  • resin materials that contain dyes for example, polyimide, etc.
  • resin materials that can be used for color filters color filter materials.
  • by mixing color filter materials of three or more colors it is possible to form a black or nearly black resin layer.
  • a display device 50F shown in FIG. 31 mainly differs from a display device 50E in that a light emitting element having a layer 133 and a colored layer (color filter or the like) are used for each color subpixel.
  • a display device 50F shown in FIG. 31 includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light emitting element 130R, a light emitting element 130G, a light emitting element 130B, and a light emitting element 130B that transmits red light between a substrate 151 and a substrate 152.
  • the colored layer 132R transmits green light
  • the colored layer 132G transmits blue light
  • the colored layer 132B transmits blue light.
  • the light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R.
  • the light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G.
  • the light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.
  • the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B each have a layer 133. These three layers 133 are formed using the same process and the same material. Furthermore, these three layers 133 are spaced apart from each other. By providing the EL layer in an island shape for each light emitting element, leakage current between adjacent light emitting elements can be suppressed. Thereby, crosstalk caused by unintended light emission can be prevented, and a display device with extremely high contrast can be realized.
  • a light emitting element 130R, a light emitting element 130G, and a light emitting element 130B shown in FIG. 31 each emit white light.
  • the white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, so that light of a desired color can be obtained.
  • the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B shown in FIG. 31 each emit blue light.
  • the layer 133 has one or more light emitting layers that emit blue light.
  • the blue light emitted by the light emitting element 130B can be extracted.
  • the light emitting element 130R by providing a color conversion layer between the light emitting element 130R or the light emitting element 130G and the substrate 152, the light emitting element 130R Alternatively, the blue light emitted by the light emitting element 130G can be converted into light with a longer wavelength to extract red or green light.
  • a colored layer 132R is provided between the color conversion layer and the substrate 152
  • a colored layer 132G is provided between the color conversion layer and the substrate 152. It is preferable to provide one. By extracting the light transmitted through the color conversion layer through the colored layer, the colored layer absorbs light of a color other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.
  • the display device 50G shown in FIG. 32 is mainly different from the display device 50F in that it is a bottom emission type display device.
  • the light emitted by the light emitting element is emitted to the substrate 151 side. It is preferable to use a material that has high transparency to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 does not matter.
  • a light shielding layer 117 is formed between the substrate 151 and the transistor.
  • a light shielding layer 117 is provided on a substrate 151, an insulating layer 153 is provided on the light blocking layer 117, and a transistor 205D, a transistor 205R (not shown), a transistor 205G, a transistor 205B, etc. are provided on the insulating layer 153.
  • a colored layer 132R (not shown), a colored layer 132G, and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 235 is provided on the colored layer 132R, the colored layer 132G, and the colored layer 132B.
  • the light emitting element 130G overlapping the colored layer 132G includes a conductive layer 124G, a conductive layer 126G, an EL layer 113, a common layer 114, and a common electrode 115.
  • the light emitting element 130B that overlaps the colored layer 132B includes a conductive layer 124B, a conductive layer 126B, an EL layer 113, a common layer 114, and a common electrode 115.
  • the light emitting element 130R overlapping the colored layer 132R includes a conductive layer 124R, a conductive layer 126R, an EL layer 113, a common layer 114, and a common electrode 115.
  • a material having high transparency to visible light is used for each of the conductive layer 124R (not shown), the conductive layer 124G, the conductive layer 124B, the conductive layer 126R (not shown), the conductive layer 126G, and the conductive layer 126B. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom emission type display device, a metal with low resistivity or the like can be used for the common electrode 115, so it is possible to suppress the voltage drop caused by the resistance of the common electrode 115, and achieve high display quality. can do.
  • FIG. 32 shows an example in which a TGSA type transistor is used in the display section 162 and a vertical channel type transistor is used in the peripheral circuit section 164
  • the present invention is not limited to this.
  • a vertical channel transistor can be used for both the display portion 162 and the peripheral circuit portion 164. Therefore, for example, by using the vertical channel transistor of one embodiment of the present invention in the display portion 162, the aperture ratio of the pixel can be increased or the size of the pixel can be reduced in a display device with a bottom emission structure. Can be done.
  • Example of manufacturing method of display device> A method for manufacturing a display device to which an MML structure is applied will be described below with reference to FIGS. 33A to 33F. Here, a process for manufacturing a light emitting element without using a fine metal mask will be described in detail.
  • 33A to 33F show cross-sectional views of three light emitting elements included in the display section 162 and the connection section 140 in each step.
  • a vacuum process such as a vapor deposition method, and a solution process such as a spin coating method or an inkjet method can be used to manufacture a light emitting element.
  • the vapor deposition method include physical vapor deposition methods (PVD method) such as sputtering method, ion plating method, ion beam vapor deposition method, molecular beam vapor deposition method, and vacuum vapor deposition method, and chemical vapor deposition method (CVD method).
  • PVD method physical vapor deposition methods
  • CVD method chemical vapor deposition method
  • the functional layers (hole injection layer, hole transport layer, hole block layer, light emitting layer, electron block layer, electron transport layer, electron injection layer, charge generation layer, etc.) included in the EL layer are formed using the vapor deposition method ( vacuum evaporation method, etc.), coating method (dip coating method, die coating method, bar coating method, spin coating method, spray coating method, etc.), printing method (inkjet method, screen (stencil printing) method, offset (lithographic printing) method, It can be formed by a method such as a flexo (letterpress printing) method, a gravure method, or a microcontact method.
  • the island-like layer (layer containing a light-emitting layer) manufactured by the display device manufacturing method described below is not formed using a fine metal mask, but is formed by forming a light-emitting layer over one surface, and then It is formed by processing using a lithography method. Therefore, it is possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to realize up to now. Furthermore, since the light-emitting layer can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Furthermore, by providing a sacrificial layer over the light-emitting layer, damage to the light-emitting layer during the manufacturing process of a display device can be reduced, and reliability of the light-emitting element can be improved.
  • the display device is composed of three types of light-emitting elements: a light-emitting element that emits blue light, a light-emitting element that emits green light, and a light-emitting element that emits red light
  • the film formation of the light-emitting layer and the photolithography By repeating the process three times, three types of island-shaped light emitting layers can be formed.
  • the pixel electrode 111R, the pixel electrode 111G, the pixel electrode 111B, and the conductive layer 123 are formed on the substrate 151 on which the transistor 205R, the transistor 205G, the transistor 205B, etc. (all not shown) are provided. ( Figure 33A).
  • a sputtering method or a vacuum evaporation method can be used to form the conductive film that will become the pixel electrode.
  • the pixel electrode 111R, the pixel electrode 111G, the pixel electrode 111B, and the conductive layer 123 can be formed by processing the conductive film.
  • a wet etching method and a dry etching method can be used.
  • Film 133Bf (later layer 133B) includes a light-emitting layer that emits blue light.
  • an example will be described in which an island-shaped EL layer of a light-emitting element that emits blue light is first formed, and then an island-shaped EL layer of a light-emitting element that emits light of another color is formed. show.
  • the pixel electrodes of the light emitting elements of the second and subsequent colors may be damaged by the previous step. As a result, the driving voltage of the light emitting elements of the second and subsequent colors may become higher.
  • the display device of one embodiment of the present invention it is preferable to manufacture the display device from an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength (for example, a blue light-emitting element).
  • the island-shaped EL layers be produced in the order of blue, green, and red, or in the order of blue, red, and green.
  • the state of the interface between the pixel electrode and the EL layer can be maintained in good condition, and the driving voltage of the blue light emitting element can be prevented from increasing. Furthermore, the life of the blue light emitting element can be extended and its reliability can be improved. Note that red and green light-emitting elements are less affected by increases in drive voltage than blue light-emitting elements, so the drive voltage of the entire display device can be lowered and reliability can be increased. can.
  • the order in which the island-shaped EL layers are produced is not limited to the above, and may be, for example, in the order of red, green, and blue.
  • the film 133Bf is not formed on the conductive layer 123.
  • the film 133Bf can be formed only in a desired region.
  • a light emitting element can be manufactured through a relatively simple process.
  • the heat resistance temperature of each compound contained in the film 133Bf is preferably 100°C or more and 180°C or less, more preferably 120°C or more and 180°C or less, and even more preferably 140°C or more and 180°C or less.
  • the reliability of the light emitting element can be improved.
  • the upper limit of the temperature that can be applied in the manufacturing process of a display device can be increased. Therefore, the range of selection of materials and forming methods used in the display device can be expanded, and yield and reliability can be improved.
  • the heat-resistant temperature can be, for example, any one of the glass transition point, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, preferably the lowest temperature among these.
  • the film 133Bf can be formed by, for example, a vapor deposition method, specifically, a vacuum vapor deposition method. Further, the film 133Bf may be formed by a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a sacrificial layer 118B is formed on the film 133Bf and the conductive layer 123 (FIG. 33A).
  • the sacrificial layer 118B can be formed by forming a resist mask on the film to be the sacrificial layer 118B by a photolithography process and then processing the film.
  • the sacrificial layer 118B is preferably provided so as to cover the end of the pixel electrode 111B.
  • the end of the layer 133B to be formed in a later step is located outside the end of the pixel electrode 111B. Since the entire upper surface of the pixel electrode 111B can be used as a light emitting region, the aperture ratio of the pixel can be increased. Further, the end portion of the layer 133B located outside the end portion of the pixel electrode 111B may be damaged during formation of the layer 133B, so it is preferable not to use it as a light emitting region. Thereby, variations in characteristics of the light emitting elements can be suppressed and reliability can be improved.
  • each step after forming the layer 133B can be performed without exposing the pixel electrode 111B. If the end of the pixel electrode 111B is exposed, corrosion may occur during an etching process or the like. By suppressing corrosion of the pixel electrode 111B, the yield and characteristics of the light emitting element can be improved.
  • the sacrificial layer 118B is also provided at a position overlapping the conductive layer 123. Thereby, damage to the conductive layer 123 during the manufacturing process of the display device can be suppressed.
  • a film with high resistance to the processing conditions of the film 133Bf specifically, a film with a high etching selectivity with respect to the film 133Bf is used.
  • the sacrificial layer 118B is formed at a temperature lower than the allowable temperature limit of each compound included in the film 133Bf.
  • the substrate temperature when forming the sacrificial layer 118B is typically 200°C or lower, preferably 150°C or lower, more preferably 120°C or lower, more preferably 100°C or lower, and still more preferably 80°C or lower. be.
  • the temperature limit of the compound included in the film 133Bf is high because the temperature at which the sacrificial layer 118B is formed can be increased.
  • the substrate temperature when forming the sacrificial layer 118B can be set to 100° C. or higher, 120° C. or higher, or 140° C. or higher.
  • the higher the film formation temperature the denser the inorganic insulating film and the higher the barrier properties. Therefore, by forming the sacrificial layer 118B at such a temperature, damage to the film 133Bf can be further reduced, and the reliability of the light emitting element can be improved.
  • a sputtering method for example, a sputtering method, an ALD method (including a thermal ALD method and a PEALD method), a CVD method, or a vacuum evaporation method can be used.
  • the film may be formed using the wet film forming method described above.
  • the sacrificial layer 118B (if the sacrificial layer 118B has a layered structure, the layer provided in contact with the film 133Bf) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, it is preferable to use an ALD method or a vacuum evaporation method rather than a sputtering method.
  • the sacrificial layer 118B can be processed by a wet etching method or a dry etching method.
  • the sacrificial layer 118B is preferably processed by anisotropic etching.
  • the wet etching method By using the wet etching method, it is possible to reduce damage to the film 133Bf when processing the sacrificial layer 118B, compared to when using the dry etching method.
  • a wet etching method for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these can be used. preferable.
  • TMAH tetramethylammonium hydroxide
  • a mixed acid chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may be used. Note that the chemical solution used in the wet etching process may be alkaline or acidic.
  • the sacrificial layer 118B for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film can be used.
  • the sacrificial layer 118B includes, for example, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or the metal. Alloy materials including materials can be used.
  • the sacrificial layer 118B includes In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), and indium tin zinc oxide (In-Sn -Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon. objects can be used.
  • the element M is aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, One or more selected from tungsten and magnesium may be used.
  • a semiconductor material such as silicon or germanium can be used as a material that is highly compatible with semiconductor manufacturing processes.
  • oxides or nitrides of the above semiconductor materials can be used.
  • a nonmetallic material such as carbon or a compound thereof can be used.
  • metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these may be used.
  • oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides, such as titanium nitride, chromium nitride, or tantalum nitride, can be used.
  • Various inorganic insulating films that can be used for the protective layer 131 can be used as the sacrificial layer 118B.
  • an oxide insulating film is preferable because it has higher adhesion to the film 133Bf than a nitride insulating film.
  • an inorganic insulating material such as aluminum oxide, hafnium oxide, silicon oxide, etc. can be used for the sacrificial layer 118B.
  • an aluminum oxide film can be formed using, for example, an ALD method. It is preferable to use the ALD method because damage to the underlying layer (particularly the film 133Bf) can be reduced.
  • an inorganic insulating film for example, an aluminum oxide film
  • an inorganic film for example, an In-Ga-Zn oxide film, a silicon film, or a tungsten film
  • the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 to be formed later.
  • an aluminum oxide film formed using an ALD method can be used for both the sacrificial layer 118B and the insulating layer 125.
  • the same film forming conditions may be applied to the sacrificial layer 118B and the insulating layer 125, or different film forming conditions may be applied to the sacrificial layer 118B and the insulating layer 125.
  • the sacrificial layer 118B can be an insulating layer with high barrier properties against at least one of water and oxygen.
  • the sacrificial layer 118B is a layer that will be mostly or completely removed in a later step, it is preferably easy to process. Therefore, the sacrificial layer 118B is preferably formed under conditions where the substrate temperature during film formation is lower than that of the insulating layer 125.
  • An organic material may be used for the sacrificial layer 118B.
  • a material that can be dissolved in a solvent that is chemically stable for at least the film located at the top of the film 133Bf may be used.
  • materials that dissolve in water or alcohol can be suitably used.
  • the material be dissolved in a solvent such as water or alcohol, applied by a wet film forming method, and then heat treated to evaporate the solvent.
  • the solvent can be removed at a low temperature and in a short time, so thermal damage to the film 133Bf can be reduced, which is preferable.
  • the sacrificial layer 118B is made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or fluororesin such as perfluoropolymer. may also be used.
  • PVA polyvinyl alcohol
  • polyvinyl butyral polyvinylpyrrolidone
  • polyethylene glycol polyglycerin
  • pullulan polyethylene glycol
  • polyglycerin polyglycerin
  • pullulan polyethylene glycol
  • pullulan polyglycerin
  • water-soluble cellulose water-soluble cellulose
  • alcohol-soluble polyamide resin or fluororesin such as perfluoropolymer.
  • an organic film e.g., PVA film
  • an inorganic film e.g., silicon nitride film
  • part of the film that serves as the sacrificial layer may remain as the sacrificial layer.
  • the film 133Bf is processed to form a layer 133B (FIG. 33B).
  • the laminated structure of the layer 133B and the sacrificial layer 118B remains on the pixel electrode 111B. Further, the pixel electrode 111R and the pixel electrode 111G are exposed. Further, in a region corresponding to the connection portion 140, the sacrificial layer 118B remains on the conductive layer 123.
  • the processing of the film 133Bf is preferably performed by anisotropic etching.
  • anisotropic dry etching is preferred.
  • wet etching may be used.
  • the layers 133R and 133B are formed on the pixel electrode 111R.
  • a laminated structure of a sacrificial layer 118R is formed, and a laminated structure of a layer 133G and a sacrificial layer 118G is formed on the pixel electrode 111G (FIG. 33C).
  • the layer 133R is formed to include a light emitting layer that emits red light
  • the layer 133G is formed to include a light emitting layer that emits green light.
  • Materials that can be used for the sacrificial layer 118B can be applied to the sacrificial layer 118R and the sacrificial layer 118G, and the same material or different materials may be used for both.
  • the side surfaces of the layer 133B, the layer 133G, and the layer 133R are each preferably perpendicular or approximately perpendicular to the surface on which they are formed.
  • the angle between the surface to be formed and these side surfaces be 60 degrees or more and 90 degrees or less.
  • the distance between two adjacent layers is 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, or 1 ⁇ m or less.
  • the distance can be defined as, for example, the distance between two adjacent opposing ends of the layer 133B, the layer 133G, and the layer 133R. In this way, by narrowing the distance between the island-shaped EL layers, a display device with high definition and a large aperture ratio can be provided.
  • an insulating film 125f that will later become the insulating layer 125 is formed so as to cover the pixel electrode, the layer 133B, the layer 133G, the layer 133R, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, and on the insulating film 125f. , forming an insulating layer 127 (FIG. 33D).
  • an insulating film having a thickness of 3 nm or more and 200 nm or less, 5 nm or more and 150 nm or less, 10 nm or more and 100 nm or less, or 10 nm or more and 50 nm or less as the insulating film 125f.
  • the insulating film 125f is preferably formed using, for example, an ALD method. It is preferable to use the ALD method because damage to the film can be reduced and a film with high coverage can be formed. As the insulating film 125f, it is preferable to form an aluminum oxide film using, for example, an ALD method.
  • the insulating film 125f may be formed using a sputtering method, a CVD method, or a PECVD method, which has a faster deposition rate than the ALD method. Thereby, a highly reliable display device can be manufactured with high productivity.
  • the insulating film that becomes the insulating layer 127 is preferably formed by the above-mentioned wet film forming method (for example, spin coating) using, for example, a photosensitive resin composition containing an acrylic resin.
  • a photosensitive resin composition containing an acrylic resin After film formation, it is preferable to perform heat treatment (also referred to as pre-baking) to remove the solvent contained in the insulating film.
  • heat treatment also referred to as pre-baking
  • a part of the insulating film is exposed to light by irradiating visible light or ultraviolet rays.
  • development is performed to remove the exposed area of the insulating film.
  • heat treatment also referred to as post-bake
  • the insulating layer 127 shown in FIG. 33D can be formed.
  • the shape of the insulating layer 127 is not limited to the shape shown in FIG. 33D.
  • the upper surface of the insulating layer 127 may have one or more of a convex curved surface, a concave curved surface, and a flat surface.
  • the insulating layer 127 may cover the side surface of at least one end of the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.
  • etching is performed using the insulating layer 127 as a mask to remove the insulating film 125f and parts of the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.
  • openings are formed in the insulating film 125f, and in each of the sacrificial layers 118B, 118G, and 118R, and the upper surfaces of the layers 133B, 133G, 133R, and the conductive layer 123 are exposed.
  • parts of the insulating film 125f, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R remain at positions overlapping with the insulating layer 127 (the insulating layer 125, the sacrificial layer 119B, the sacrificial layer 119G, and the sacrificial layer 119R).
  • the etching process can be performed by a dry etching method or a wet etching method. Note that it is preferable that the insulating film 125f is formed using the same material as the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R because the etching process can be performed at once.
  • each light emitting element is divided into the common layer 114 and common electrode 115 that will be formed later. It is possible to suppress the occurrence of connection failures caused by areas where the film is thin and increases in electrical resistance caused by areas where the film thickness is locally thin. Thereby, the display device of one embodiment of the present invention can improve display quality.
  • a common layer 114 and a common electrode 115 are formed in this order on the insulating layer 127, layer 133B, layer 133G, and layer 133R (FIG. 33F).
  • the common layer 114 can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a sputtering method or a vacuum evaporation method can be used for forming the common electrode 115.
  • a film formed by a vapor deposition method and a film formed by a sputtering method may be stacked.
  • the island-shaped layer 133B, the island-shaped layer 133G, and the island-shaped layer 133R are not formed using a fine metal mask. Since it is formed by forming a film over one surface and then processing it, it is possible to form an island-like layer with a uniform thickness. In addition, a high-definition display device or a display device with a high aperture ratio can be realized. Furthermore, even if the definition or aperture ratio is high and the distance between subpixels is extremely short, it is possible to prevent the layers 133B, 133G, and 133R from coming into contact with each other in adjacent subpixels. Therefore, generation of leakage current between subpixels can be suppressed. Thereby, crosstalk caused by unintended light emission can be prevented, and a display device with extremely high contrast can be realized.
  • the display device of one embodiment of the present invention can achieve both high definition and high display quality.
  • the electronic device of this embodiment includes the display device of one embodiment of the present invention in the display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in display units of various electronic devices.
  • Examples of electronic devices include electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and digital cameras. , digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like.
  • the display device of one embodiment of the present invention can improve definition, so it can be suitably used for electronic devices having a relatively small display portion.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), VR devices such as head-mounted displays, glasses-type AR devices, MR devices, and other head-mounted devices. Examples include wearable devices that can be attached to the device.
  • the display device of one embodiment of the present invention includes HD (number of pixels 1280 x 720), FHD (number of pixels 1920 x 1080), WQHD (number of pixels 2560 x 1440), WQXGA (number of pixels 2560 x 1600), and 4K (number of pixels It is preferable to have an extremely high resolution such as 3840 ⁇ 2160) or 8K (pixel count 7680 ⁇ 4320). In particular, it is preferable to set the resolution to 4K, 8K, or higher.
  • the pixel density (definition) in the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, and 3000 ppi or more. More preferably, it is 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage). , power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared rays).
  • the electronic device of this embodiment can have various functions. For example, functions that display various information (still images, videos, text images, etc.) on the display, touch panel functions, calendars, functions that display date or time, etc., functions that execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, etc.
  • FIGS. 34A to 34D An example of a wearable device that can be worn on the head will be described using FIGS. 34A to 34D.
  • These wearable devices have at least one of a function of displaying AR content, a function of displaying VR content, a function of displaying SR content, and a function of displaying MR content.
  • an electronic device has a function of displaying at least one content such as AR, VR, SR, and MR, it becomes possible to enhance the user's immersive feeling.
  • An electronic device 700A shown in FIG. 34A and an electronic device 700B shown in FIG. 34B each include a pair of display panels 751, a pair of casings 721, a communication section (not shown), and a pair of mounting sections 723. , a control section (not shown), an imaging section (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of extremely high definition display can be achieved.
  • the electronic device 700A and the electronic device 700B can each project the image displayed on the display panel 751 onto the display area 756 of the optical member 753. Since the optical member 753 has translucency, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.
  • the electronic device 700A and the electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Further, the electronic device 700A and the electronic device 700B are each equipped with an acceleration sensor such as a gyro sensor to detect the direction of the user's head and display an image corresponding to the direction in the display area 756. You can also.
  • an acceleration sensor such as a gyro sensor to detect the direction of the user's head and display an image corresponding to the direction in the display area 756. You can also.
  • the communication unit has a wireless communication device, and can supply video signals and the like through the wireless communication device.
  • a connector to which a cable to which a video signal and a power supply potential are supplied may be connected may be provided.
  • the electronic device 700A and the electronic device 700B are provided with batteries, and can be charged wirelessly and/or by wire.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a user's tap operation, slide operation, etc., and execute various processes. For example, a tap operation can be used to pause or restart a video, and a slide operation can be used to fast-forward or rewind a video. Further, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be applied as the touch sensor module.
  • various methods such as a capacitance method, a resistive film method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, an optical method, etc. can be adopted.
  • a photoelectric conversion element When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element one or both of an inorganic semiconductor and an organic semiconductor can be used.
  • the electronic device 800A shown in FIG. 34C and the electronic device 800B shown in FIG. 34D each include a pair of display sections 820, a housing 821, a communication section 822, a pair of mounting sections 823, a control section 824, It has a pair of imaging units 825 and a pair of lenses 832.
  • a display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of extremely high definition display can be achieved. This allows the user to feel highly immersive.
  • the display section 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Furthermore, by displaying different images on the pair of display units 820, three-dimensional display using parallax can be performed.
  • the electronic device 800A and the electronic device 800B can each be said to be an electronic device for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • the electronic device 800A and the electronic device 800B each have a mechanism that can adjust the left and right positions of the lens 832 and the display unit 820 so that they are in optimal positions according to the position of the user's eyes. It is preferable that you do so. Further, it is preferable to have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display section 820.
  • the mounting portion 823 allows the user to wear the electronic device 800A or the electronic device 800B on the head.
  • the shape is exemplified as a temple of glasses, but the shape is not limited to this.
  • the mounting portion 823 only needs to be worn by the user, and may have a helmet-shaped or band-shaped shape, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • a plurality of cameras may be provided so as to be able to handle a plurality of angles of view such as telephoto and wide angle.
  • a distance measuring sensor (hereinafter also referred to as a detection unit) that can measure the distance to an object may be provided. That is, the imaging unit 825 is one aspect of a detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as LIDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be obtained and more precise gesture operations can be performed.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having the vibration mechanism can be applied to one or more of the display section 820, the housing 821, and the mounting section 823.
  • the electronic device 800A and the electronic device 800B may each have an input terminal.
  • a cable for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device can be connected to the input terminal.
  • An electronic device may have a function of wirelessly communicating with the earphone 750.
  • Earphone 750 includes a communication section (not shown) and has a wireless communication function.
  • Earphone 750 can receive information (eg, audio data) from an electronic device using a wireless communication function.
  • electronic device 700A shown in FIG. 34A has a function of transmitting information to earphone 750 using a wireless communication function.
  • electronic device 800A shown in FIG. 34C has a function of transmitting information to earphone 750 using a wireless communication function.
  • the electronic device may have an earphone section.
  • Electronic device 700B shown in FIG. 34B includes earphone section 727.
  • the earphone section 727 and the control section can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone section 727 and the control section may be arranged inside the housing 721 or the mounting section 723.
  • the electronic device 800B shown in FIG. 34D has an earphone section 827.
  • the earphone section 827 and the control section 824 can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone section 827 and the control section 824 may be arranged inside the housing 821 or the mounting section 823.
  • the earphone section 827 and the mounting section 823 may include magnets. Thereby, the earphone part 827 can be fixed to the mounting part 823 by magnetic force, which is preferable because storage becomes easy.
  • the electronic device may have an audio output terminal to which earphones, headphones, or the like can be connected. Further, the electronic device may have one or both of an audio input terminal and an audio input mechanism.
  • the audio input mechanism for example, a sound collection device such as a microphone can be used.
  • the electronic device may be provided with a function as a so-called headset.
  • both glasses type (electronic device 700A and electronic device 700B, etc.) and goggle type (electronic device 800A and electronic device 800B, etc.) are suitable for the electronic device of one embodiment of the present invention. It is.
  • An electronic device can transmit information to earphones by wire or wirelessly.
  • An electronic device 6500 shown in FIG. 35A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display section 6502 has a touch panel function.
  • a display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 35B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a light-transmitting protection member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, A printed circuit board 6517, a battery 6518, etc. are arranged.
  • a display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 with an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded part.
  • An IC6516 is mounted on the FPC6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • a flexible display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging the connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.
  • FIG. 35C shows an example of a television device.
  • a television device 7100 has a display section 7000 built into a housing 7101. Here, a configuration in which a casing 7101 is supported by a stand 7103 is shown.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 35C can be operated using an operation switch included in the housing 7101 and a separate remote controller 7111.
  • the display section 7000 may include a touch sensor, and the television device 7100 may be operated by touching the display section 7000 with a finger or the like.
  • the remote control device 7111 may have a display unit that displays information output from the remote control device 7111. Using operation keys or a touch panel included in the remote controller 7111, the channel and volume can be controlled, and the video displayed on the display section 7000 can be controlled.
  • the television device 7100 is configured to include a receiver, a modem, and the like.
  • the receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem, information can be communicated in one direction (from a sender to a receiver) or in two directions (between a sender and a receiver, or between receivers, etc.). is also possible.
  • FIG. 35D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display unit 7000 is incorporated into the housing 7211.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • FIGS. 35E and 35F An example of digital signage is shown in FIGS. 35E and 35F.
  • the digital signage 7300 shown in FIG. 35E includes a housing 7301, a display section 7000, a speaker 7303, and the like. Furthermore, it can have an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.
  • FIG. 35F shows a digital signage 7400 attached to a cylindrical pillar 7401.
  • Digital signage 7400 has a display section 7000 provided along the curved surface of pillar 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the wider the display section 7000 is, the more information that can be provided at once can be increased. Furthermore, the wider the display section 7000 is, the easier it is to attract people's attention, and for example, the effectiveness of advertising can be increased.
  • a touch panel By applying a touch panel to the display section 7000, not only images or videos can be displayed on the display section 7000, but also the user can operate it intuitively, which is preferable. Further, when used for providing information such as route information or traffic information, usability can be improved by intuitive operation.
  • the digital signage 7300 or the digital signage 7400 can cooperate with an information terminal 7311 or an information terminal 7411 such as a smartphone owned by the user by wireless communication.
  • advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched.
  • the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in FIGS. 36A to 36G includes a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, Speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared rays. (including a function of detecting, detecting, or measuring), a microphone 9008, and the like.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in FIGS. 36A to 36G have various functions. For example, functions to display various information (still images, videos, text images, etc.) on a display unit, touch panel functions, functions to display a calendar, date or time, etc., functions to control processing using various software (programs), It can have a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and can have various functions.
  • the electronic device may have multiple display units. Furthermore, the electronic device may be equipped with a camera, etc., and have the function of taking still images or videos and saving them on a recording medium (external or built into the camera), the function of displaying the taken images on a display unit, etc. .
  • FIG. 36A is a perspective view showing the mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces thereof.
  • FIG. 36A shows an example in which three icons 9050 are displayed.
  • information 9051 indicated by a dashed rectangle can also be displayed on another surface of the display section 9001. Examples of the information 9051 include notification of incoming e-mail, SNS, telephone, etc., title of e-mail or SNS, sender's name, date and time, remaining battery level, radio field strength, and the like.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • FIG. 36B is a perspective view showing the mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are displayed on different surfaces.
  • the user can check the information 9053 displayed at a position visible from above the mobile information terminal 9102 while storing the mobile information terminal 9102 in the chest pocket of clothes. The user can check the display without taking out the mobile information terminal 9102 from his pocket and determine, for example, whether to accept a call.
  • FIG. 36C is a perspective view showing the tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display section 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000, an operation key 9005 as an operation button on the side of the housing 9000, and a connection terminal 9006 on the bottom. has.
  • FIG. 36D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
  • the mobile information terminal 9200 can also make a hands-free call by mutually communicating with a headset capable of wireless communication, for example.
  • the mobile information terminal 9200 can also perform data transmission and charging with other information terminals through the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.
  • FIG. 36E to 36G are perspective views showing a foldable portable information terminal 9201. Further, FIG. 36E is a perspective view of the portable information terminal 9201 in an unfolded state, FIG. 36G is a folded state, and FIG. 36F is a perspective view of a state in the middle of changing from one of FIGS. 36E and 36G to the other.
  • the portable information terminal 9201 has excellent portability in the folded state, and has excellent display visibility due to its wide seamless display area in the unfolded state.
  • a display portion 9001 included in a mobile information terminal 9201 is supported by three casings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • a sample that is a semiconductor device that is one embodiment of the present invention was manufactured.
  • the configuration of the sample reference can be made to the description of the semiconductor device 10 shown in FIGS. 1A to 1C.
  • the method of manufacturing the sample reference can be made to the description of the method of manufacturing the semiconductor device 10 shown in FIGS. 14A to 18B.
  • a copper film with a thickness of 300 nm is formed on the substrate 102 by a sputtering method, and after processing this, an In-Sn-Si oxide (ITSO) film with a thickness of 100 nm is formed on this by a sputtering method.
  • ITSO In-Sn-Si oxide
  • the insulating film 110af includes a silicon nitride film (first silicon nitride film) with a thickness of 70 nm and a silicon nitride film (second silicon nitride film) with a thickness of 100 nm on the first silicon nitride film. It has a laminated structure.
  • the first silicon nitride film was formed in a state in which NH 3 was mixed in the film formation gas, and the second silicon nitride film was formed in a state in which NH 3 was not mixed in the film formation gas.
  • a silicon oxynitride film with a thickness of 500 nm was formed on the insulating film 110af by the PECVD method to obtain an insulating film 110bf.
  • a physical layer was formed on the insulating film 110bf.
  • heat treatment was performed to supply oxygen from the first metal oxide layer to the insulating film 110bf.
  • the heat treatment was performed at 250° C. for 1 hour in a dry air atmosphere.
  • An oven device was used for the heat treatment.
  • a metal oxide layer was formed on the insulating film 110bf.
  • the insulating film 110bf was subjected to oxygen plasma treatment for 300 seconds using a plasma ashing device through the second metal oxide layer.
  • first metal oxide layer and the second metal oxide layer in this example correspond to the metal oxide layer 180 shown in FIG. 14C.
  • the insulating film 110cf includes a silicon nitride film (third silicon nitride film) with a thickness of 50 nm and a silicon nitride film (fourth silicon nitride film) with a thickness of 150 nm on the third silicon nitride film. It has a laminated structure.
  • the third silicon nitride film was formed in a state in which NH 3 was not mixed in the film formation gas, and the fourth silicon nitride film was formed in a state in which NH 3 was mixed in the film formation gas.
  • a silicon nitride film with a thickness of 60 nm and a silicon oxynitride film with a thickness of 50 nm were stacked and formed on the insulating film 110cf by the PECVD method, to obtain an insulating film 120f.
  • the insulating film 120f was processed to obtain the insulating layer 120.
  • an ITSO film with a thickness of 100 nm was formed on the insulating layer 120 and the insulating film 110cf by sputtering to obtain a conductive film 112f.
  • the conductive film 112f was processed to obtain a conductive layer 112B.
  • the conductive layer 112B was processed to form an opening 143 and to obtain a conductive layer 112b.
  • a wet etching method was used to form the opening 143.
  • the insulating film 110f (insulating film 110cf, insulating film 110bf, and insulating film 110af) is processed to form an opening 141, and the insulating layer 110 (insulating layer 110c, insulating layer 110b, and insulating layer 110a) is processed. Obtained. A dry etching method was used to form the opening 141.
  • planar shapes of the openings 143 and 141 were circular.
  • a metal oxide film 105f with a thickness of 10 nm was formed on the conductive layer 112a, the insulating layer 110, the conductive layer 112b, and the insulating layer 120, covering the openings 143 and 141.
  • the metal oxide film 105f was processed to obtain the semiconductor layer 105.
  • a metal oxide film 108f with a thickness of 10 nm was formed on the semiconductor layer 105, the conductive layer 112b, the insulating layer 120, and the insulating layer 110.
  • the metal oxide film 108f was processed to obtain the semiconductor layer 108 and the semiconductor layer 208.
  • a silicon oxynitride film with a thickness of 50 nm was formed on the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, the insulating layer 120, and the insulating layer 110 by the PECVD method to obtain an insulating film 106f.
  • the insulating film 106f was processed to form an opening 147a and an opening 147b, and to obtain the insulating layer 106.
  • a dry etching method was used to form the openings 147a and 147b.
  • a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 200 nm, and a titanium film with a thickness of 50 nm are stacked on the insulating layer 106 and the semiconductor layer 208 by a sputtering method, and a conductive film 104f is formed. I got it.
  • the conductive film 104f was processed to obtain the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b.
  • a dry etching method was used for the processing.
  • a process was performed to supply the impurity 190 to the semiconductor layer 208.
  • Boron was used as the impurity 190 and was supplied to the semiconductor layer 208 by a plasma ion doping method. Note that the acceleration voltage during plasma ion doping was 15 kV, and the dose was 1 ⁇ 10 15 ions/cm 2 .
  • a region 208D and a region 208L were formed in the semiconductor layer 208.
  • the transistor 100 and the transistor 200 were formed.
  • a silicon nitride oxide film with a thickness of 300 nm was formed as a protective layer over the transistors 100 and 200 by PECVD.
  • a polyimide resin was formed as a flattening layer on the protective layer to a thickness of 1.5 ⁇ m.
  • the Id-Vg characteristics of the transistor were measured by applying a voltage to the gate electrode (hereinafter also referred to as gate voltage (Vg)) from -10V to +10V in steps of 0.1V. Further, the voltage applied to the source electrode (hereinafter also referred to as source voltage (Vs)) is 0V (common), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) is 0.1V. and 5.1V.
  • the transistor 100 shown in FIG. 1A was measured in which the width (diameter) of the opening 143 was 2.0 ⁇ m (channel width 6.3 ⁇ m) (channel length was 0.5 ⁇ m).
  • the transistor 200 was measured to have a channel length of 3.0 ⁇ m and a channel width of 3.0 ⁇ m. Further, the number of measurements was 10 for both the transistor 100 and the transistor 200.
  • the Id-Vg characteristics of the transistor 100 are shown in FIG. 37A, and the Id-Vg characteristics of the transistor 200 are shown in FIG. 37B.
  • the horizontal axis represents the gate voltage (Vg), and the vertical axis represents the drain current (Id).
  • the Id-Vg characteristic results of 10 transistors are shown in an overlapping manner.
  • both the transistor 100 and the transistor 200 exhibited switching characteristics with good on/off characteristics. It was also confirmed that the transistor 100 has a larger on-state current than the transistor 200.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2023/057609 2022-08-09 2023-07-27 半導体装置、及び、半導体装置の作製方法 Ceased WO2024033739A1 (ja)

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US18/998,211 US20250338717A1 (en) 2022-08-09 2023-07-27 Semiconductor device and method for manufacturing semiconductor device
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WO2026047499A1 (ja) * 2024-08-30 2026-03-05 株式会社半導体エネルギー研究所 半導体装置

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JP2017017208A (ja) * 2015-07-02 2017-01-19 株式会社ジャパンディスプレイ 半導体装置
JP2017168761A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
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JP2017017208A (ja) * 2015-07-02 2017-01-19 株式会社ジャパンディスプレイ 半導体装置
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