WO2024024307A1 - Fin-type field effect transistor - Google Patents

Fin-type field effect transistor Download PDF

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Publication number
WO2024024307A1
WO2024024307A1 PCT/JP2023/021931 JP2023021931W WO2024024307A1 WO 2024024307 A1 WO2024024307 A1 WO 2024024307A1 JP 2023021931 W JP2023021931 W JP 2023021931W WO 2024024307 A1 WO2024024307 A1 WO 2024024307A1
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Prior art keywords
fin
fins
source electrode
finfet
field effect
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PCT/JP2023/021931
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French (fr)
Japanese (ja)
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大樹 脇本
広信 宮本
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株式会社ノベルクリスタルテクノロジー
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Publication of WO2024024307A1 publication Critical patent/WO2024024307A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a fin field effect transistor.
  • Non-Patent Document 1 a fin field effect transistor (FinFET) using Ga 2 O 3 as a semiconductor layer is known (see Non-Patent Document 1).
  • FinFET fin field effect transistor
  • Non-Patent Document 1 fins are formed using lithography and dry etching, similar to a general FinFET manufacturing method.
  • the outermost fin when forming fins by processing a semiconductor layer by dry etching, the outermost fin is generally thicker than the other fins, or the outermost fin is thicker than the other fins. Problems such as roughened side surfaces and reduced thickness uniformity tend to occur. Since the thickness of the fin, including the channel region, affects the magnitude of the FinFET's threshold voltage, any deviation or non-uniformity in the thickness of the outermost fin will result in a deviation in the FinFET's threshold voltage.
  • an inverted MOS channel FET is formed in which a portion corresponding to the trench portion between the fins of a FinFET is a p-type semiconductor region as an inverted MOS channel. can do.
  • a p-type semiconductor region as an inversion MOS channel is formed by implanting acceptor impurities into a semiconductor material, and the threshold voltage of the inversion MOS channel FET can be adjusted by adjusting the concentration of the acceptor impurities.
  • gallium oxide semiconductors such as Ga 2 O 3 into p-type semiconductors
  • An object of the present invention is to provide a FinFET using a gallium oxide-based semiconductor in the semiconductor layer, in which the influence on the threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed. be.
  • one embodiment of the present invention provides the following fin-type field effect transistor.
  • a semiconductor layer made of a gallium oxide-based semiconductor and having a plurality of fins, a gate electrode formed on each side surface of the plurality of fins via a gate insulating film, and the plurality of fins of the semiconductor layer.
  • a source electrode connected to one side of the semiconductor layer, and a drain electrode connected to an opposite side of the plurality of fins of the semiconductor layer, the outermost fin of the plurality of fins being connected to the source electrode electrically.
  • a fin-type field effect transistor which is a dummy fin that is not connected to the fin.
  • a FinFET that uses a gallium oxide-based semiconductor as a semiconductor layer, and in which the influence on the threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed. can.
  • FIG. 1A is a vertical cross-sectional view of a fin field effect transistor (FinFET) according to a first embodiment of the present invention.
  • FIG. 1B is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in the FinFET according to the first embodiment of the present invention.
  • FIG. 1C is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in the FinFET according to the first embodiment of the present invention.
  • FIG. 2 is an image observed by a scanning electron microscope (SEM) of a cross section of the epitaxial layer immediately after fins have been formed by dry etching.
  • SEM scanning electron microscope
  • FIG. 3A is a graph showing gate current Ig and drain current Id versus gate voltage in a comparative sample.
  • FIG. 3B is a graph showing gate current I g and drain current I d versus gate voltage in a FinFET having a source electrode having the shape shown in FIG. 1B.
  • FIG. 4 is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in a modified example of the FinFET according to the first embodiment of the present invention.
  • FIG. 5A is a vertical cross-sectional view of a FinFET according to a second embodiment of the invention.
  • FIG. 5B is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the insulating film in the FinFET according to the second embodiment of the present invention.
  • FIG. 5C is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the insulating film in the FinFET according to the second embodiment of the present invention.
  • FIG. 6 is a vertical sectional view of a modification of the FinFET according to the second embodiment of the invention.
  • FIG. 7A is a vertical cross-sectional view of a FinFET according to a third embodiment of the present invention.
  • FIG. 7B is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the high resistance region in the FinFET according to the third embodiment of the present invention.
  • FIG. 7C is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the high resistance region in the FinFET according to the third embodiment of the present invention.
  • FIG. 1A is a vertical cross-sectional view of a fin field effect transistor (FinFET) 1 according to a first embodiment of the present invention.
  • the FinFET 1 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
  • the gallium oxide semiconductor refers to Ga 2 O 3 or Ga 2 O 3 to which elements such as Al and In are added.
  • a gallium oxide semiconductor has a composition expressed as (Ga x Al y In (1-x-y) ) 2 O 3 (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1). have When Al is added to Ga 2 O 3 , the band gap is widened, and when In is added, the band gap is narrowed.
  • the FinFET 1 is made of a gallium oxide based semiconductor, and includes a semiconductor layer 10 having a plurality of fins 120, a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13, and a gate electrode 14 of the semiconductor layer 10.
  • an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
  • the outermost one of the plurality of fins 120 is called a fin 120b, and the innermost one of the fins 120b is called a fin 120a.
  • the source electrode 15 does not cover the top of the fin 120b and is not in contact with the fin 120b. That is, in the FinFET 1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected.
  • each of the plurality of fins 120 has a linear pattern and is arranged parallel to each other.
  • the semiconductor layer 10 is typically composed of a substrate 11 made of a gallium oxide semiconductor and an epitaxial layer 12 made of a gallium oxide semiconductor formed on the substrate 11, as shown in FIG. 1A. In this case, a plurality of fins 120 are formed in the epitaxial layer 12.
  • the semiconductor layer 10 is an n-type layer containing donor impurities such as Si and Sn.
  • An n + region 121 having a particularly high concentration of donor impurities is formed at the upper end of the fin 120a, and the source electrode 15 is connected to the n + region 121.
  • an n + region 121 with a high concentration of donor impurities may be formed also at the upper end of the fin 120b, which is a dummy fin, but the source electrode 15 is not connected to the n + region 121 of the fin 120b.
  • the fin 120 is formed by processing the semiconductor layer 10 using lithography such as electron beam lithography or photolithography and dry etching. As described above, when the fins 120 are formed by dry etching, the outermost fins 120b may become thicker than the inner fins 120a, and the outer side surfaces of the fins 120b may become rough, reducing the uniformity of the thickness. Problems are likely to occur.
  • FIG. 2 is an image observed by a scanning electron microscope (SEM) of a cross section of the epitaxial layer 12 immediately after the fin 120 is formed by dry etching.
  • the mask 50 on the fin 120 is an etching mask used for patterning the epitaxial layer 12 by dry etching.
  • the thickness of the outermost fin 120b of the fins 120 is larger than the thickness of the inner fin 120a, and the outer side surface 122 of the fin 120b is roughened to form unevenness, and the thickness of the fin 120b is larger than that of the inner fin 120a.
  • the uniformity of the thickness of the fins 120a is lower than that of the fins 120a.
  • FinFETs unlike inverted MOS channel FETs manufactured using semiconductor materials that can be converted to p-type, such as Si, it is difficult to adjust the threshold voltage using a p-type semiconductor region. Therefore, in order to obtain the desired threshold voltage in FinFETs that can be manufactured using gallium oxide semiconductors, the thickness of the fins must be accurately controlled, and the thickness of the outermost fin must be controlled accurately. Misalignment and non-uniformity become major obstacles to obtaining the desired threshold voltage.
  • the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, deviations in the threshold voltage of the FinFET 1 due to deviations or non-uniformity in the thickness of the fin 120b can be avoided. Prevents defects.
  • 1B and 1C are schematic diagrams each showing an example of the positional relationship in the planar direction between the fin 120 and the source electrode 15 in the FinFET 1.
  • 1B and 1C show the shapes and positions of the fin 120 and the source electrode 15 when viewed from above the FinFET 1.
  • the source electrode 15 does not cover the top of the fin 120b and is not in contact with the fin 120b.
  • the region 151 of the source electrode 15 is a region provided at a position apart from the region covering the upper part of the fin 120 for connecting a contact plug or a lead wire from above.
  • the source electrode 15 does not cover part of the planar end portions of the fin 120a (that is, the right end and left end in FIG. 1C), and does not contact there. Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 1 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 does not cover at least a portion of the end portion of the fin 120a in the planar direction and is not electrically connected.
  • the length L1 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set within a range of 1 to 10 ⁇ m, for example.
  • the source electrode 15 shown in FIGS. 1B and 1C does not need to include the region 151.
  • a contact plug or a lead wire is connected to a region of the source electrode 15 that covers the upper part of the fin 120.
  • the gate insulating film 13 is made of an insulator such as HfO 2 , Al 2 O 3 , or SiO 2 .
  • the gate electrode 14 is preferably made of a metal with a high work function, such as Cr, Pt, or Ni.
  • the source electrode 15 and the drain electrode 16 are made of an electrode stacked structure made of, for example, Ti/Au, Ti/Al, etc. and in ohmic contact with the semiconductor layer 10 .
  • the interlayer insulating film 17 is made of an insulator such as SiO 2 , SiN, HfO 2 , or the like.
  • the FinFET 1 may have either normally-off characteristics or normally-on characteristics.
  • normally-off characteristics when the FinFET 1 has normally-off characteristics, when a voltage is applied to the gate electrode 14, a channel is formed in each of the fins 120 sandwiched by the gate electrode 14 from both sides, and a channel is formed between the source electrode 15 and the drain electrode 16. Current will begin to flow.
  • the donor concentration of the substrate 11 is 5 ⁇ 10 17 cm ⁇ 3 or more
  • the donor concentration of the n + region 121 is 1 ⁇ 10 18 cm ⁇ 3 or more
  • the height of the fin 120 is 1 ⁇ m or more.
  • the donor concentration of the epitaxial layer 12 is 1 ⁇ 10 16 cm ⁇ 3 or less
  • the gate insulating film 13 is an HfO 2 film with a thickness of 100 nm or less
  • the gate electrode 14 is made of Cr
  • the thickness of the fin 120a is 500 nm or less.
  • the threshold voltage V th of the FinFET 1 is determined by the following equation (1).
  • ⁇ B is the barrier height determined by the material of the gate electrode 14 and the gate insulating film 13
  • VOX is the donor concentration of the fin 120, the material of the gate insulating film 13, and the thickness of the gate insulating film 13.
  • ⁇ EC is the amount of band discontinuity on the conductor side determined by the material of the gate insulating film 13 and the material of the fin 120
  • ⁇ S is the voltage of the gate insulating film 13 determined by the donor concentration, thickness, and dielectric value of the fin 120.
  • E F is the Fermi energy determined by the donor concentration and temperature of the fin 120.
  • the distance between the fins 120a and 120b is small to some extent, for example, 10 ⁇ m or less.
  • the fins 120 are all equally spaced. In this case, it is preferable that the interval between the fins 120 is 10 ⁇ m or less.
  • the characteristics of a FinFET 1 in which the fin 120b is a dummy fin and a FinFET as a comparative example (hereinafter referred to as a comparative sample) in which the source electrode 15 covers the upper part of the fin 120b and is connected to the fin 120b were measured and compared.
  • the configuration of the comparative sample is similar to the configuration of FinFET 1 except that the fin 120b is connected to the source electrode 15.
  • FIG. 3A is a graph showing gate current Ig and drain current Id versus gate voltage in a comparative sample.
  • FIG. 3B is a graph showing the gate current I g and drain current I d with respect to the gate voltage in the FinFET 1 having the source electrode 15 having the shape shown in FIG. 1B.
  • FIG. 3A from when the drain current I d starts to increase until it is saturated, there is a large step that is considered to be due to a deviation or non-uniformity in the thickness of the fin 120b.
  • FIG. 3B there is no step between the time when the drain current I d starts to increase and the time when it is saturated. This is considered to be because the source electrode 15 is not connected to the fin 120b, so there is no influence from deviation or non-uniformity in the thickness of the fin 120b.
  • FIG. 4 is a schematic diagram showing an example of the positional relationship in the planar direction between the fin 120 and the source electrode 15 in a modified example of the FinFET 1.
  • FIG. 4 shows the shapes of the fin 120 and the source electrode 15 when viewed from above the FinFET 1.
  • a fin 120b which is a dummy fin, may be arranged to surround the inner fin 120a from all sides.
  • the fins 120b so as to surround the fins 120a from all sides, it is possible to suppress an increase in thickness and roughness of the side surfaces at the ends of the fins 120a in the planar direction (that is, the right and left ends in FIG. 4).
  • the fins 120b surrounding the fins 120a from all sides are composed of one continuous dummy fin, but they may be composed of a plurality of dummy fins.
  • the second embodiment of the present invention differs from the first embodiment in the structure for avoiding electrical connection between the source electrode 15 and the fin 120b. Descriptions of the same points as in the first embodiment will be omitted or simplified.
  • FIG. 5A is a vertical cross-sectional view of the FinFET 2 according to the second embodiment of the present invention.
  • the FinFET 2 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
  • FinFET2 like FinFET1, is made of a gallium oxide semiconductor and includes a semiconductor layer 10 having a plurality of fins 120, and a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13. , a source electrode 15 connected to the side of the plurality of fins 120 of the semiconductor layer 10, and a drain electrode 16 connected to the side of the semiconductor layer 10 opposite to the plurality of fins 120. Furthermore, an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
  • the source electrode 15 covers the top of the fin 120b, but an insulating film 21 is formed between the upper end of the fin 120b and the source electrode 15, and the insulating film 21 insulates the source electrode 15 and the fin 120b.
  • the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected.
  • the insulating film 21 is made of an insulator such as SiO 2 , SiN, HfO 2 , Al 2 O 3 or the like.
  • FinFET2 similarly to FinFET1, by using the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, the threshold voltage of FinFET2 due to deviation or non-uniformity in the thickness of the fin 120b can be reduced. This prevents defects such as misalignment.
  • FIGS. 5B and 5C are schematic diagrams showing an example of the positional relationship in the planar direction of the fin 120, the source electrode 15, and the insulating film 21 in the FinFET 2.
  • FIG. 5B shows the shapes and positions of the fin 120, the source electrode 15, and the insulating film 21 when viewed from above the FinFET 2.
  • the source electrode 15 covers the fin 120b, but the source electrode 15 and the fin 120b are insulated by the insulating film 21.
  • an insulating film 21 is also formed between the upper end of the fin 120a in the planar direction (that is, the right end and left end in FIG. 5C) and the source electrode 15 to insulate them. There is. Therefore, even if the end portion of the fin 120a in the planar direction has an increased thickness or roughened side surface, the source electrode 15 is not electrically connected to this portion, so that the end portion of the fin 120a in the planar direction is It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 2 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the insulating film 21.
  • the length L2 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set, for example, within a range of 1 to 10 ⁇ m.
  • the source electrode 15 shown in FIGS. 5B and 5C has a region 151 provided at a position apart from the region covering the upper part of the fin 120 for connecting a contact plug or a lead wire from above. Good too.
  • FIG. 6 is a vertical cross-sectional view of a modification of the FinFET 2.
  • the height of the fin 120b may be lower than the height of the fin 120a.
  • an interlayer insulating film 17 is formed between the upper end of the fin 120b and the source electrode 15 covering the upper end of the fin 120b, and the interlayer insulating film 17 insulates the source electrode 15 and the fin 120b.
  • the height of at least a portion of the end portion of the fin 120a in the planar direction may be lowered similarly to the height of the fin 120b.
  • the interlayer insulating film 17 is also formed between the upper end of the lower end of the fin 120a in the planar direction and the source electrode 15 covering the upper end. Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 2 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the interlayer insulating film 17.
  • the third embodiment of the present invention differs from the first embodiment in the structure for avoiding electrical connection between the source electrode 15 and the fin 120b. Descriptions of the same points as in the first embodiment will be omitted or simplified.
  • FIG. 7A is a vertical cross-sectional view of the FinFET 3 according to the third embodiment of the present invention.
  • the FinFET 3 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
  • the FinFET 3 is made of a gallium oxide semiconductor, and includes a semiconductor layer 10 having a plurality of fins 120, and a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13. , a source electrode 15 connected to the side of the plurality of fins 120 of the semiconductor layer 10, and a drain electrode 16 connected to the side of the semiconductor layer 10 opposite to the plurality of fins 120. Furthermore, an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
  • a high resistance region 123 containing acceptor impurities is formed at the upper end of the fin 120b, and the source electrode 15 is in contact with the high resistance region 123. Therefore, although the source electrode 15 is in contact with the fin 120b, it is insulated by the high resistance region 123. That is, in FinFET3, like FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected.
  • the high resistance region 123 is formed, for example, by ion implantation of acceptor impurities such as N and Mg.
  • FinFET3 similarly to FinFET1, by using the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, the threshold voltage of FinFET3 due to deviation or non-uniformity in the thickness of the fin 120b can be reduced. This prevents defects such as misalignment.
  • 7B and 7C are schematic diagrams showing an example of the positional relationship in the planar direction of the fin 120, the source electrode 15, and the high resistance region 123 in the FinFET 3.
  • 7B and 7C show the shapes and positions of the fin 120, the source electrode 15, and the high resistance region 123 when viewed from above the FinFET 3.
  • the source electrode 15 covers the fin 120b, but the source electrode 15 and the fin 120b are insulated by the high resistance region 123.
  • high resistance regions 123 that insulate the fin 120a and the source electrode 15 are also formed at the upper ends of the planar ends of the fin 120a (i.e., the right and left ends in FIG. 7C). . Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 3 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the high resistance region 123.
  • the length L3 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set within a range of 1 to 10 ⁇ m, for example. Note that the length L3 is equal to the length of the high resistance region 123 in the fin 120a in the planar direction.
  • the source electrode 15 shown in FIGS. 7B and 7C does not need to include the region 151.
  • a contact plug or a lead wire is connected to a region of the source electrode 15 that covers the upper part of the fin 120.
  • the outermost fin 120b of the plurality of fins 120 is used as a dummy fin to which the source electrode 15 is not electrically connected.
  • the influence on the threshold voltage due to thickness deviation or non-uniformity can be suppressed.
  • the influence on the threshold voltage due to deviation or non-uniformity in the thickness of the end portion of the fin 120a in the planar direction can be avoided. can be suppressed.

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Abstract

Provided is a fin-type field effect transistor 1 comprising: a semiconductor layer 10 made of a gallium oxide based semiconductor and having a plurality of fins 120; a gate electrode 14 formed on the side surface of each of the plurality of fins 120 with a gate insulating film 13 interposed therebetween; a source electrode 15 connected to the semiconductor layer 10 on the side of the plurality of fins 120; and a drain electrode 16 connected to the semiconductor layer 10 on the side opposite to that of the plurality of fins 120, wherein an outermost fin 120b of the plurality of fins 120 is a dummy fin to which the source electrode 15 is not electrically connected.

Description

フィン型電界効果トランジスタFin field effect transistor
　本発明は、フィン型電界効果トランジスタに関する。 The present invention relates to a fin field effect transistor.
　従来、Ｇａ２Ｏ３を半導体層に用いたフィン型電界効果トランジスタ（ＦｉｎＦＥＴ）が知られている（非特許文献１を参照）。非特許文献１によれば、一般的なＦｉｎＦＥＴの製造方法と同様に、リソグラフィーとドライエッチングを用いてフィンを形成している。 Conventionally, a fin field effect transistor (FinFET) using Ga 2 O 3 as a semiconductor layer is known (see Non-Patent Document 1). According to Non-Patent Document 1, fins are formed using lithography and dry etching, similar to a general FinFET manufacturing method.
　しかしながら、ＦｉｎＦＥＴの製造工程においては、ドライエッチングにより半導体層を加工してフィンを形成する場合、一般的に、最も外側のフィンが他のフィンに比べて厚くなったり、最も外側のフィンの外側の側面が荒れて厚さの均一性が低下したりという問題が生じやすい。チャネル領域を含むフィンの厚さはＦｉｎＦＥＴの閾値電圧の大きさに影響を与えるため、最も外側のフィンの厚さのずれや不均一性は、ＦｉｎＦＥＴの閾値電圧のずれを生む。 However, in the FinFET manufacturing process, when forming fins by processing a semiconductor layer by dry etching, the outermost fin is generally thicker than the other fins, or the outermost fin is thicker than the other fins. Problems such as roughened side surfaces and reduced thickness uniformity tend to occur. Since the thickness of the fin, including the channel region, affects the magnitude of the FinFET's threshold voltage, any deviation or non-uniformity in the thickness of the outermost fin will result in a deviation in the FinFET's threshold voltage.
　ここで、Ｓｉなどのｐ型化が可能な半導体材料を用いる場合は、ＦｉｎＦＥＴのフィン間のトレンチ部分に相当する部分が反転ＭＯＳチャネルとしてのｐ型半導体領域で構成される反転ＭＯＳチャネルＦＥＴを形成することができる。反転ＭＯＳチャネルとしてのｐ型半導体領域は、半導体材料にアクセプター不純物を注入することにより形成され、アクセプター不純物の濃度により反転ＭＯＳチャネルＦＥＴの閾値電圧を調整することができる。 Here, when using a semiconductor material that can be converted to p-type, such as Si, an inverted MOS channel FET is formed in which a portion corresponding to the trench portion between the fins of a FinFET is a p-type semiconductor region as an inverted MOS channel. can do. A p-type semiconductor region as an inversion MOS channel is formed by implanting acceptor impurities into a semiconductor material, and the threshold voltage of the inversion MOS channel FET can be adjusted by adjusting the concentration of the acceptor impurities.
　一方、Ｇａ２Ｏ３などの酸化ガリウム系半導体はｐ型化が不可能又は非常に困難であるため、酸化ガリウム系半導体を用いる場合は、ｐ型半導体領域で構成される反転ＭＯＳチャネルＦＥＴを備えた反転ＭＯＳチャネルＦＥＴを製造することが難しく、ｐ型半導体領域を利用した閾値電圧の調整が難しい。このため、酸化ガリウム系半導体を用いて製造することができるＦｉｎＦＥＴにおいて目的の閾値電圧を得るためには、フィンの厚さを正確に制御しなくてはならず、最も外側のフィンの厚さのずれや不均一性が目的の閾値電圧を得るための大きな障害になる。 On the other hand, since it is impossible or extremely difficult to convert gallium oxide semiconductors such as Ga 2 O 3 into p-type semiconductors, when using gallium oxide semiconductors, it is necessary to provide an inverted MOS channel FET consisting of a p-type semiconductor region. It is difficult to manufacture an inverted MOS channel FET, and it is difficult to adjust the threshold voltage using a p-type semiconductor region. Therefore, in order to obtain the desired threshold voltage in FinFETs that can be manufactured using gallium oxide semiconductors, the thickness of the fins must be precisely controlled, and the thickness of the outermost fin must be controlled accurately. Misalignment and non-uniformity become major obstacles to obtaining the desired threshold voltage.
　本発明の目的は、酸化ガリウム系半導体を半導体層に用いたＦｉｎＦＥＴであって、最も外側のフィンの厚さのずれや不均一性による閾値電圧への影響が抑えられたＦｉｎＦＥＴを提供することにある。 An object of the present invention is to provide a FinFET using a gallium oxide-based semiconductor in the semiconductor layer, in which the influence on the threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed. be.
　本発明の一態様は、上記目的を達成するために、下記のフィン型電界効果トランジスタを提供する。 In order to achieve the above object, one embodiment of the present invention provides the following fin-type field effect transistor.
［１］酸化ガリウム系半導体からなり、複数のフィンを有する半導体層と、前記複数のフィンの各々の側面上にゲート絶縁膜を介して形成されたゲート電極と、前記半導体層の前記複数のフィン側に接続されたソース電極と、前記半導体層の前記複数のフィンの反対側に接続されたドレイン電極と、を備え、前記複数のフィンのうちの最も外側のフィンが、前記ソース電極が電気的に接続されないダミーフィンである、フィン型電界効果トランジスタ。
［２］前記ソース電極が、前記複数のフィンのうちの前記ダミーフィンの内側のフィンの平面方向の端部の少なくとも一部に電気的に接続されない、上記［１］に記載のフィン型電界効果トランジスタ。
［３］前記ソース電極が前記ダミーフィンの上方を覆い、前記ダミーフィンの上端と前記ソース電極との間に絶縁膜が形成された、上記［１］又は［２］に記載のフィン型電界効果トランジスタ。
［４］前記ダミーフィンの高さが、前記複数のフィンのうちのその他のフィンの高さよりも低い、上記［３］に記載のフィン型電界効果トランジスタ。
［５］前記ダミーフィンの上端にアクセプター不純物を含む高抵抗領域が形成され、前記高抵抗領域に前記ソース電極が接触している、上記［１］又は［２］に記載のフィン型電界効果トランジスタ。
［６］前記ソース電極が前記ダミーフィンの上方を覆わない、上記［１］又は［２］に記載のフィン型電界効果トランジスタ。
［７］前記ダミーフィンが、前記複数のフィンのうちの前記ダミーフィンの内側のフィンを四方から囲むように配置された、上記［６］に記載のフィン型電界効果トランジスタ。 [1] A semiconductor layer made of a gallium oxide-based semiconductor and having a plurality of fins, a gate electrode formed on each side surface of the plurality of fins via a gate insulating film, and the plurality of fins of the semiconductor layer. a source electrode connected to one side of the semiconductor layer, and a drain electrode connected to an opposite side of the plurality of fins of the semiconductor layer, the outermost fin of the plurality of fins being connected to the source electrode electrically. A fin-type field effect transistor, which is a dummy fin that is not connected to the fin.
[2] The fin-type field effect according to [1] above, wherein the source electrode is not electrically connected to at least a part of an end in a planar direction of a fin inside the dummy fin of the plurality of fins. transistor.
[3] The fin-type field effect according to [1] or [2] above, wherein the source electrode covers above the dummy fin, and an insulating film is formed between the upper end of the dummy fin and the source electrode. transistor.
[4] The fin-type field effect transistor according to [3] above, wherein the height of the dummy fin is lower than the height of other fins among the plurality of fins.
[5] The fin type field effect transistor according to [1] or [2] above, wherein a high resistance region containing an acceptor impurity is formed at the upper end of the dummy fin, and the source electrode is in contact with the high resistance region. .
[6] The fin-type field effect transistor according to [1] or [2] above, wherein the source electrode does not cover above the dummy fin.
[7] The fin-type field effect transistor according to [6], wherein the dummy fin is arranged to surround from all sides an inner fin of the dummy fin of the plurality of fins.
　本発明によれば、酸化ガリウム系半導体を半導体層に用いたＦｉｎＦＥＴであって、最も外側のフィンの厚さのずれや不均一性による閾値電圧への影響が抑えられたＦｉｎＦＥＴを提供することができる。 According to the present invention, it is possible to provide a FinFET that uses a gallium oxide-based semiconductor as a semiconductor layer, and in which the influence on the threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed. can.
図１Ａは、本発明の第１の実施の形態に係るフィン型電界効果トランジスタ（ＦｉｎＦＥＴ）の垂直断面図である。FIG. 1A is a vertical cross-sectional view of a fin field effect transistor (FinFET) according to a first embodiment of the present invention. 図１Ｂは、本発明の第１の実施の形態に係るＦｉｎＦＥＴにおけるフィンとソース電極の平面方向の位置関係の例を示す模式図である。FIG. 1B is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in the FinFET according to the first embodiment of the present invention. 図１Ｃは、本発明の第１の実施の形態に係るＦｉｎＦＥＴにおけるフィンとソース電極の平面方向の位置関係の例を示す模式図である。FIG. 1C is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in the FinFET according to the first embodiment of the present invention. 図２は、ドライエッチングによってフィンが形成された直後のエピタキシャル層の断面の走査電子顕微鏡（ＳＥＭ）による観察画像である。FIG. 2 is an image observed by a scanning electron microscope (SEM) of a cross section of the epitaxial layer immediately after fins have been formed by dry etching. 図３Ａは、比較試料における、ゲート電圧に対するゲート電流Ｉｇとドレイン電流Ｉｄを示すグラフである。FIG. 3A is a graph showing gate current Ig and drain current Id versus gate voltage in a comparative sample. 図３Ｂは、図１Ｂに示される形状のソース電極を備えたＦｉｎＦＥＴにおける、ゲート電圧に対するゲート電流Ｉｇとドレイン電流Ｉｄを示すグラフである。FIG. 3B is a graph showing gate current I g and drain current I d versus gate voltage in a FinFET having a source electrode having the shape shown in FIG. 1B. 図４は、本発明の第１の実施の形態に係るＦｉｎＦＥＴの変形例におけるフィンとソース電極の平面方向の位置関係の例を示す模式図である。FIG. 4 is a schematic diagram showing an example of the positional relationship in the planar direction between the fin and the source electrode in a modified example of the FinFET according to the first embodiment of the present invention. 図５Ａは、本発明の第２の実施の形態に係るＦｉｎＦＥＴの垂直断面図である。FIG. 5A is a vertical cross-sectional view of a FinFET according to a second embodiment of the invention. 図５Ｂは、本発明の第２の実施の形態に係るＦｉｎＦＥＴにおけるフィン、ソース電極、及び絶縁膜の平面方向の位置関係の例を示す模式図である。FIG. 5B is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the insulating film in the FinFET according to the second embodiment of the present invention. 図５Ｃは、本発明の第２の実施の形態に係るＦｉｎＦＥＴにおけるフィン、ソース電極、及び絶縁膜の平面方向の位置関係の例を示す模式図である。FIG. 5C is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the insulating film in the FinFET according to the second embodiment of the present invention. 図６は、本発明の第２の実施の形態に係るＦｉｎＦＥＴの変形例の垂直断面図である。FIG. 6 is a vertical sectional view of a modification of the FinFET according to the second embodiment of the invention. 図７Ａは、本発明の第３の実施の形態に係るＦｉｎＦＥＴの垂直断面図である。FIG. 7A is a vertical cross-sectional view of a FinFET according to a third embodiment of the present invention. 図７Ｂは、本発明の第３の実施の形態に係るＦｉｎＦＥＴにおけるフィン、ソース電極、及び高抵抗領域の平面方向の位置関係の例を示す模式図である。FIG. 7B is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the high resistance region in the FinFET according to the third embodiment of the present invention. 図７Ｃは、本発明の第３の実施の形態に係るＦｉｎＦＥＴにおけるフィン、ソース電極、及び高抵抗領域の平面方向の位置関係の例を示す模式図である。FIG. 7C is a schematic diagram showing an example of the positional relationship in the planar direction of the fin, the source electrode, and the high resistance region in the FinFET according to the third embodiment of the present invention.
〔第１の実施の形態〕
（フィン型電界効果トランジスタの構成）
　図１Ａは、本発明の第１の実施の形態に係るフィン型電界効果トランジスタ（ＦｉｎＦＥＴ）１の垂直断面図である。ＦｉｎＦＥＴ１は、酸化ガリウム系半導体からなる半導体層を備えた縦型のＦｉｎＦＥＴである。 [First embodiment]
(Configuration of fin field effect transistor)
FIG. 1A is a vertical cross-sectional view of a fin field effect transistor (FinFET) 1 according to a first embodiment of the present invention. The FinFET 1 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
　酸化ガリウム系半導体とは、Ｇａ２Ｏ３、又は、Ａｌ、Ｉｎなどの元素が添加されたＧａ２Ｏ３をいう。例えば、酸化ガリウム系半導体は、（ＧａｘＡｌｙＩｎ（１－ｘ－ｙ））２Ｏ３（０＜ｘ≦１、０≦ｙ≦１、０＜ｘ＋ｙ≦１）で表される組成を有する。Ｇａ２Ｏ３にＡｌを添加した場合にはバンドギャップが広がり、Ｉｎを添加した場合にはバンドギャップが狭くなる。 The gallium oxide semiconductor refers to Ga 2 O 3 or Ga 2 O 3 to which elements such as Al and In are added. For example, a gallium oxide semiconductor has a composition expressed as (Ga x Al y In (1-x-y) ) 2 O 3 (0<x≦1, 0≦y≦1, 0<x+y≦1). have When Al is added to Ga 2 O 3 , the band gap is widened, and when In is added, the band gap is narrowed.
　ＦｉｎＦＥＴ１は、酸化ガリウム系半導体からなり、複数のフィン１２０を有する半導体層１０と、複数のフィン１２０の各々の側面上にゲート絶縁膜１３を介して形成されたゲート電極１４と、半導体層１０の複数のフィン１２０側（すなわち、図１Ａの上側）に接続されたソース電極１５と、半導体層１０の複数のフィン１２０の反対側（すなわち、図１Ａの下側）に接続されたドレイン電極１６と、を備える。また、複数のフィン１２０の間及び周囲に層間絶縁膜１７が形成される。 The FinFET 1 is made of a gallium oxide based semiconductor, and includes a semiconductor layer 10 having a plurality of fins 120, a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13, and a gate electrode 14 of the semiconductor layer 10. A source electrode 15 connected to the side of the plurality of fins 120 (that is, the upper side of FIG. 1A), and a drain electrode 16 connected to the side of the semiconductor layer 10 opposite to the plurality of fins 120 (that is, the lower side of FIG. 1A). , is provided. Furthermore, an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
　ここで、複数のフィン１２０のうちの最も外側のものをフィン１２０ｂ、フィン１２０ｂの内側のものをフィン１２０ａとする。ＦｉｎＦＥＴ１においては、ソース電極１５がフィン１２０ｂの上方を覆っておらず、フィン１２０ｂに接触していない。すなわち、ＦｉｎＦＥＴ１においては、最も外側のフィン１２０ｂが、ソース電極１５が電気的に接続されないダミーフィンである。典型的には、複数のフィン１２０の各々は直線状のパターンを有し、互いに平行に並べられる。 Here, the outermost one of the plurality of fins 120 is called a fin 120b, and the innermost one of the fins 120b is called a fin 120a. In the FinFET 1, the source electrode 15 does not cover the top of the fin 120b and is not in contact with the fin 120b. That is, in the FinFET 1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. Typically, each of the plurality of fins 120 has a linear pattern and is arranged parallel to each other.
　半導体層１０は、典型的には、図１Ａに示されるように、酸化ガリウム系半導体からなる基板１１と、基板１１上に形成される酸化ガリウム系半導体からなるエピタキシャル層１２から構成される。この場合、複数のフィン１２０はエピタキシャル層１２に形成される。 The semiconductor layer 10 is typically composed of a substrate 11 made of a gallium oxide semiconductor and an epitaxial layer 12 made of a gallium oxide semiconductor formed on the substrate 11, as shown in FIG. 1A. In this case, a plurality of fins 120 are formed in the epitaxial layer 12.
　半導体層１０は、Ｓｉ、Ｓｎなどのドナー不純物を含むｎ型の層である。フィン１２０ａの上端には、特にドナー不純物の濃度が高いｎ＋領域１２１が形成され、ｎ＋領域１２１にソース電極１５が接続される。なお、製造工程上、ダミーフィンであるフィン１２０ｂの上端にもドナー不純物の濃度が高いｎ＋領域１２１が形成されてもよいが、フィン１２０ｂのｎ＋領域１２１にはソース電極１５が接続されない。 The semiconductor layer 10 is an n-type layer containing donor impurities such as Si and Sn. An n + region 121 having a particularly high concentration of donor impurities is formed at the upper end of the fin 120a, and the source electrode 15 is connected to the n + region 121. Note that, due to the manufacturing process, an n + region 121 with a high concentration of donor impurities may be formed also at the upper end of the fin 120b, which is a dummy fin, but the source electrode 15 is not connected to the n + region 121 of the fin 120b.
　フィン１２０は、電子線リソグラフィーやフォトリソグラフィーなどのリソグラフィーとドライエッチングを用いて半導体層１０を加工することにより形成される。上述のように、ドライエッチングによりフィン１２０を形成すると、最も外側のフィン１２０ｂが内側のフィン１２０ａに比べて厚くなったり、フィン１２０ｂの外側の側面が荒れて厚さの均一性が低下したりという問題が生じやすい。 The fin 120 is formed by processing the semiconductor layer 10 using lithography such as electron beam lithography or photolithography and dry etching. As described above, when the fins 120 are formed by dry etching, the outermost fins 120b may become thicker than the inner fins 120a, and the outer side surfaces of the fins 120b may become rough, reducing the uniformity of the thickness. Problems are likely to occur.
　図２は、ドライエッチングによってフィン１２０が形成された直後のエピタキシャル層１２の断面の走査電子顕微鏡（ＳＥＭ）による観察画像である。フィン１２０上のマスク５０は、ドライエッチングによるエピタキシャル層１２のパターン加工に用いられたエッチングマスクである。図２は、フィン１２０のうちの最も外側のフィン１２０ｂの厚さが内側のフィン１２０ａの厚さよりも大きく、また、フィン１２０ｂの外側の側面１２２が荒れて凹凸が形成され、フィン１２０ｂの厚さの均一性がフィン１２０ａの厚さの均一性よりも低いことを示している。 FIG. 2 is an image observed by a scanning electron microscope (SEM) of a cross section of the epitaxial layer 12 immediately after the fin 120 is formed by dry etching. The mask 50 on the fin 120 is an etching mask used for patterning the epitaxial layer 12 by dry etching. In FIG. 2, the thickness of the outermost fin 120b of the fins 120 is larger than the thickness of the inner fin 120a, and the outer side surface 122 of the fin 120b is roughened to form unevenness, and the thickness of the fin 120b is larger than that of the inner fin 120a. The uniformity of the thickness of the fins 120a is lower than that of the fins 120a.
　上述のように、ＦｉｎＦＥＴにおいては、Ｓｉなどのｐ型化が可能な半導体材料を用いて製造する反転ＭＯＳチャネルＦＥＴと異なり、ｐ型半導体領域を利用した閾値電圧の調整が難しい。このため、酸化ガリウム系半導体を用いて製造することができるＦｉｎＦＥＴにおいて目的の閾値電圧を得るためには、フィンの厚さを正確に制御しなくてはならず、最も外側のフィンの厚さのずれや不均一性が目的の閾値電圧を得るための大きな障害になる。 As described above, in FinFETs, unlike inverted MOS channel FETs manufactured using semiconductor materials that can be converted to p-type, such as Si, it is difficult to adjust the threshold voltage using a p-type semiconductor region. Therefore, in order to obtain the desired threshold voltage in FinFETs that can be manufactured using gallium oxide semiconductors, the thickness of the fins must be accurately controlled, and the thickness of the outermost fin must be controlled accurately. Misalignment and non-uniformity become major obstacles to obtaining the desired threshold voltage.
　そこで、ＦｉｎＦＥＴ１においては、最も外側のフィン１２０ｂをソース電極１５が電気的に接続されないダミーフィンとすることにより、フィン１２０ｂの厚さのずれや不均一性に起因するＦｉｎＦＥＴ１の閾値電圧のずれなどの不良を防いでいる。 Therefore, in the FinFET 1, by using the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, deviations in the threshold voltage of the FinFET 1 due to deviations or non-uniformity in the thickness of the fin 120b can be avoided. Prevents defects.
　図１Ｂ、図１Ｃは、それぞれＦｉｎＦＥＴ１におけるフィン１２０とソース電極１５の平面方向の位置関係の例を示す模式図である。図１Ｂ、図１Ｃは、ＦｉｎＦＥＴ１の上方から視たときのフィン１２０とソース電極１５の形状と位置を示している。図１Ｂ、図１Ｃの例で示されるように、ＦｉｎＦＥＴ１においては、ソース電極１５がフィン１２０ｂの上方を覆っておらず、フィン１２０ｂに接触していない。なお、ソース電極１５の領域１５１は、上方からコンタクトプラグや引き出し用ワイヤーを接続するための、フィン１２０の上方を覆う領域から外れた位置に設けられる領域である。 1B and 1C are schematic diagrams each showing an example of the positional relationship in the planar direction between the fin 120 and the source electrode 15 in the FinFET 1. 1B and 1C show the shapes and positions of the fin 120 and the source electrode 15 when viewed from above the FinFET 1. As shown in the examples of FIGS. 1B and 1C, in the FinFET 1, the source electrode 15 does not cover the top of the fin 120b and is not in contact with the fin 120b. Note that the region 151 of the source electrode 15 is a region provided at a position apart from the region covering the upper part of the fin 120 for connecting a contact plug or a lead wire from above.
　また、図１Ｃに示される例では、ソース電極１５がフィン１２０ａの平面方向の端部（すなわち図１Ｃの右端と左端）の一部の上方も覆っておらず、そこに接触していない。このため、フィン１２０ａの平面方向の端部において厚さの増加や側面の荒れが生じている場合であっても、この部分にソース電極１５が電気的に接続されないため、フィン１２０ａの平面方向の端部の厚さのずれや不均一性に起因するＦｉｎＦＥＴ１の閾値電圧のずれなどの不良を防ぐことができる。したがって、ソース電極１５が、フィン１２０ａの平面方向の端部の少なくとも一部の上方を覆っておらず、電気的に接続されていないことが好ましい。 Furthermore, in the example shown in FIG. 1C, the source electrode 15 does not cover part of the planar end portions of the fin 120a (that is, the right end and left end in FIG. 1C), and does not contact there. Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 1 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 does not cover at least a portion of the end portion of the fin 120a in the planar direction and is not electrically connected.
　図１Ｃに示されるように、フィン１２０ａの平面方向の端部にソース電極１５が接続されない領域を設ける場合、この領域が小さすぎるとこの領域を設けることによる上記の効果が不十分になり、大きすぎるとＦｉｎＦＥＴ１の動作への影響が生じるおそれがある。このため、このフィン１２０ａの平面方向の端部のソース電極１５が接続されない領域の、平面方向の長さＬ１は、例えば、１～１０μｍの範囲内に設定される。 As shown in FIG. 1C, when a region to which the source electrode 15 is not connected is provided at the end of the fin 120a in the planar direction, if this region is too small, the above effect of providing this region will be insufficient, If it is too high, the operation of the FinFET 1 may be affected. Therefore, the length L1 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set within a range of 1 to 10 μm, for example.
　なお、図１Ｂ、図１Ｃに示されるソース電極１５は、領域１５１を含まなくてもよい。この場合、ソース電極１５のフィン１２０の上方を覆う領域にコンタクトプラグや引き出し用ワイヤーを接続する。 Note that the source electrode 15 shown in FIGS. 1B and 1C does not need to include the region 151. In this case, a contact plug or a lead wire is connected to a region of the source electrode 15 that covers the upper part of the fin 120.
　ゲート絶縁膜１３は、ＨｆＯ２、Ａｌ２Ｏ３、ＳｉＯ２などの絶縁体からなる。ゲート電極１４は、Ｃｒ、Ｐｔ、Ｎｉなどの仕事関数が高い金属からなることが好ましい。ソース電極１５、ドレイン電極１６は、例えば、Ｔｉ／Ａｕ、Ｔｉ／Ａｌなどの半導体層１０とオーミック接触する電極積層構造からなる。また、層間絶縁膜１７は、ＳｉＯ２、ＳｉＮ、ＨｆＯ２などの絶縁体からなる。 The gate insulating film 13 is made of an insulator such as HfO 2 , Al 2 O 3 , or SiO 2 . The gate electrode 14 is preferably made of a metal with a high work function, such as Cr, Pt, or Ni. The source electrode 15 and the drain electrode 16 are made of an electrode stacked structure made of, for example, Ti/Au, Ti/Al, etc. and in ohmic contact with the semiconductor layer 10 . Furthermore, the interlayer insulating film 17 is made of an insulator such as SiO 2 , SiN, HfO 2 , or the like.
　ＦｉｎＦＥＴ１は、ノーマリーオフ特性とノーマリーオン特性のいずれを有してもよい。例えば、ＦｉｎＦＥＴ１がノーマリーオフ特性を有する場合は、ゲート電極１４に電圧を印加すると、ゲート電極１４に両側から挟まれたフィン１２０の各々にチャネルが形成され、ソース電極１５とドレイン電極１６の間に電流が流れるようになる。 The FinFET 1 may have either normally-off characteristics or normally-on characteristics. For example, when the FinFET 1 has normally-off characteristics, when a voltage is applied to the gate electrode 14, a channel is formed in each of the fins 120 sandwiched by the gate electrode 14 from both sides, and a channel is formed between the source electrode 15 and the drain electrode 16. Current will begin to flow.
　ＦｉｎＦＥＴ１において、例えば、基板１１のドナー濃度は５×１０１７ｃｍ－３以上であり、ｎ＋領域１２１のドナー濃度は１×１０１８ｃｍ－３以上であり、フィン１２０の高さは１μｍ以上である。また、ＦｉｎＦＥＴ１がノーマリーオフ特性を有する場合には、例えば、エピタキシャル層１２のドナー濃度が１×１０１６ｃｍ－３以下であり、ゲート絶縁膜１３が厚さ１００ｎｍ以下のＨｆＯ２膜であり、ゲート電極１４がＣｒからなり、フィン１２０ａの厚さが５００ｎｍ以下である。 In the FinFET 1, for example, the donor concentration of the substrate 11 is 5×10 17 cm −3 or more, the donor concentration of the n + region 121 is 1×10 18 cm −3 or more, and the height of the fin 120 is 1 μm or more. be. Further, when the FinFET 1 has normally-off characteristics, for example, the donor concentration of the epitaxial layer 12 is 1×10 16 cm −3 or less, the gate insulating film 13 is an HfO 2 film with a thickness of 100 nm or less, The gate electrode 14 is made of Cr, and the thickness of the fin 120a is 500 nm or less.
　ＦｉｎＦＥＴ１の閾値電圧Ｖｔｈは、次の式（１）により求められる。ここで、φＢはゲート電極１４の材料及びゲート絶縁膜１３の材料により決まる障壁高さであり、ＶＯＸはフィン１２０のドナー濃度、ゲート絶縁膜１３の材料、及びゲート絶縁膜１３の厚さにより決まるゲート絶縁膜１３の電圧であり、ΔＥＣはゲート絶縁膜１３の材料及びフィン１２０の材料により決まる伝導体側のバンド不連続量であり、φＳはフィン１２０のドナー濃度、厚さ、誘電率により決まるフィン１２０の仕事関数であり、ＥＦはフィン１２０のドナー濃度及び温度により決まるフェルミエネルギーである。 The threshold voltage V th of the FinFET 1 is determined by the following equation (1). Here, φB is the barrier height determined by the material of the gate electrode 14 and the gate insulating film 13, and VOX is the donor concentration of the fin 120, the material of the gate insulating film 13, and the thickness of the gate insulating film 13. ΔEC is the amount of band discontinuity on the conductor side determined by the material of the gate insulating film 13 and the material of the fin 120, and φS is the voltage of the gate insulating film 13 determined by the donor concentration, thickness, and dielectric value of the fin 120. is the work function of the fin 120 determined by the rate, and E F is the Fermi energy determined by the donor concentration and temperature of the fin 120.
　なお、フィン１２０ａとフィン１２０ｂの間隔が大きすぎると、フィン１２０ａにもフィン１２０ｂと同様の厚さの増加や表面の荒れが発生する。本発明のフィン１２０ｂをダミーフィンとすることによる効果は、厚さの増加や表面の荒れがほぼフィン１２０ｂにのみ生じる場合に、特に大きくなる。このため、フィン１２０ａとフィン１２０ｂの間隔は、ある程度小さい、例えば、１０μｍ以下であることが好ましい。典型的には、フィン１２０は全て等間隔で形成される。この場合、フィン１２０の間隔が１０μｍ以下であることが好ましい。 Note that if the distance between the fins 120a and 120b is too large, the thickness of the fins 120a will increase and the surface will become rough, similar to that of the fins 120b. The effect of using the fins 120b of the present invention as dummy fins becomes particularly large when an increase in thickness or surface roughness occurs almost only on the fins 120b. Therefore, it is preferable that the distance between the fins 120a and the fins 120b is small to some extent, for example, 10 μm or less. Typically, the fins 120 are all equally spaced. In this case, it is preferable that the interval between the fins 120 is 10 μm or less.
（フィン型電界効果トランジスタの評価）
　フィン１２０ｂがダミーフィンであるＦｉｎＦＥＴ１と、ソース電極１５がフィン１２０ｂの上方を覆い、フィン１２０ｂに接続された、比較例としてのＦｉｎＦＥＴ（以下、比較試料と呼ぶ）の特性を測定し、比較した。比較試料の構成は、フィン１２０ｂがソース電極１５に接続されている点以外は、ＦｉｎＦＥＴ１の構成と同様である。 (Evaluation of fin field effect transistor)
The characteristics of a FinFET 1 in which the fin 120b is a dummy fin and a FinFET as a comparative example (hereinafter referred to as a comparative sample) in which the source electrode 15 covers the upper part of the fin 120b and is connected to the fin 120b were measured and compared. The configuration of the comparative sample is similar to the configuration of FinFET 1 except that the fin 120b is connected to the source electrode 15.
　図３Ａは、比較試料における、ゲート電圧に対するゲート電流Ｉｇとドレイン電流Ｉｄを示すグラフである。図３Ｂは、図１Ｂに示される形状のソース電極１５を備えたＦｉｎＦＥＴ１における、ゲート電圧に対するゲート電流Ｉｇとドレイン電流Ｉｄを示すグラフである。 FIG. 3A is a graph showing gate current Ig and drain current Id versus gate voltage in a comparative sample. FIG. 3B is a graph showing the gate current I g and drain current I d with respect to the gate voltage in the FinFET 1 having the source electrode 15 having the shape shown in FIG. 1B.
　図３Ａによれば、ドレイン電流Ｉｄが増加し始めてから飽和するまでに、フィン１２０ｂの厚さのずれや不均一性によると考えられる大きな段差が存在する。一方、図３Ｂによれば、ドレイン電流Ｉｄが増加し始めてから飽和するまでに段差が存在しない。これは、フィン１２０ｂにソース電極１５が接続されていないため、フィン１２０ｂの厚さのずれや不均一性による影響がないことによると考えられる。 According to FIG. 3A, from when the drain current I d starts to increase until it is saturated, there is a large step that is considered to be due to a deviation or non-uniformity in the thickness of the fin 120b. On the other hand, according to FIG. 3B, there is no step between the time when the drain current I d starts to increase and the time when it is saturated. This is considered to be because the source electrode 15 is not connected to the fin 120b, so there is no influence from deviation or non-uniformity in the thickness of the fin 120b.
（変形例）
　図４は、ＦｉｎＦＥＴ１の変形例におけるフィン１２０とソース電極１５の平面方向の位置関係の例を示す模式図である。図４は、ＦｉｎＦＥＴ１の上方から視たときのフィン１２０とソース電極１５の形状を示している。 (Modified example)
FIG. 4 is a schematic diagram showing an example of the positional relationship in the planar direction between the fin 120 and the source electrode 15 in a modified example of the FinFET 1. FIG. 4 shows the shapes of the fin 120 and the source electrode 15 when viewed from above the FinFET 1.
　図４に示されるように、ＦｉｎＦＥＴ１においては、ダミーフィンであるフィン１２０ｂが、その内側のフィン１２０ａを四方から囲むように配置されていてもよい。フィン１２０ｂがフィン１２０ａを四方から囲むように配置されることにより、フィン１２０ａの平面方向の端部（すなわち図４の右端と左端）における厚さの増加や側面の荒れを抑えることができる。 As shown in FIG. 4, in the FinFET 1, a fin 120b, which is a dummy fin, may be arranged to surround the inner fin 120a from all sides. By arranging the fins 120b so as to surround the fins 120a from all sides, it is possible to suppress an increase in thickness and roughness of the side surfaces at the ends of the fins 120a in the planar direction (that is, the right and left ends in FIG. 4).
　なお、図４に示される例では、フィン１２０ａを四方から囲むフィン１２０ｂが連続した１つのダミーフィンで構成されているが、複数のダミーフィンで構成されていてもよい。 Note that in the example shown in FIG. 4, the fins 120b surrounding the fins 120a from all sides are composed of one continuous dummy fin, but they may be composed of a plurality of dummy fins.
〔第２の実施の形態〕
　本発明の第２の実施の形態は、ソース電極１５とフィン１２０ｂの電気的な接続を避けるための構造において第１の実施の形態と異なる。第１の実施の形態と同様の点については、説明を省略又は簡略化する。 [Second embodiment]
The second embodiment of the present invention differs from the first embodiment in the structure for avoiding electrical connection between the source electrode 15 and the fin 120b. Descriptions of the same points as in the first embodiment will be omitted or simplified.
　図５Ａは、本発明の第２の実施の形態に係るＦｉｎＦＥＴ２の垂直断面図である。ＦｉｎＦＥＴ２は、酸化ガリウム系半導体からなる半導体層を備えた縦型のＦｉｎＦＥＴである。 FIG. 5A is a vertical cross-sectional view of the FinFET 2 according to the second embodiment of the present invention. The FinFET 2 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
　ＦｉｎＦＥＴ２は、ＦｉｎＦＥＴ１と同様に、酸化ガリウム系半導体からなり、複数のフィン１２０を有する半導体層１０と、複数のフィン１２０の各々の側面上にゲート絶縁膜１３を介して形成されたゲート電極１４と、半導体層１０の複数のフィン１２０側に接続されたソース電極１５と、半導体層１０の複数のフィン１２０の反対側に接続されたドレイン電極１６と、を備える。また、複数のフィン１２０の間及び周囲に層間絶縁膜１７が形成される。 FinFET2, like FinFET1, is made of a gallium oxide semiconductor and includes a semiconductor layer 10 having a plurality of fins 120, and a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13. , a source electrode 15 connected to the side of the plurality of fins 120 of the semiconductor layer 10, and a drain electrode 16 connected to the side of the semiconductor layer 10 opposite to the plurality of fins 120. Furthermore, an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
　ＦｉｎＦＥＴ２においては、ソース電極１５がフィン１２０ｂの上方を覆っているが、フィン１２０ｂの上端とソース電極１５との間に絶縁膜２１が形成され、絶縁膜２１によりソース電極１５とフィン１２０ｂが絶縁されている。すなわち、ＦｉｎＦＥＴ２においては、ＦｉｎＦＥＴ１と同様に、最も外側のフィン１２０ｂが、ソース電極１５が電気的に接続されないダミーフィンである。絶縁膜２１は、ＳｉＯ２、ＳｉＮ、ＨｆＯ２、Ａｌ２Ｏ３などの絶縁体からなる。 In the FinFET 2, the source electrode 15 covers the top of the fin 120b, but an insulating film 21 is formed between the upper end of the fin 120b and the source electrode 15, and the insulating film 21 insulates the source electrode 15 and the fin 120b. ing. That is, in FinFET2, like FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. The insulating film 21 is made of an insulator such as SiO 2 , SiN, HfO 2 , Al 2 O 3 or the like.
　ＦｉｎＦＥＴ２においても、ＦｉｎＦＥＴ１と同様に、最も外側のフィン１２０ｂをソース電極１５が電気的に接続されないダミーフィンとすることにより、フィン１２０ｂの厚さのずれや不均一性に起因するＦｉｎＦＥＴ２の閾値電圧のずれなどの不良を防いでいる。 In FinFET2, similarly to FinFET1, by using the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, the threshold voltage of FinFET2 due to deviation or non-uniformity in the thickness of the fin 120b can be reduced. This prevents defects such as misalignment.
　図５Ｂ、図５Ｃは、ＦｉｎＦＥＴ２におけるフィン１２０、ソース電極１５、及び絶縁膜２１の平面方向の位置関係の例を示す模式図である。図５Ｂは、ＦｉｎＦＥＴ２の上方から視たときのフィン１２０、ソース電極１５、及び絶縁膜２１の形状と位置を示している。図５Ｂ、図５Ｃの例で示されるように、ＦｉｎＦＥＴ２においては、ソース電極１５がフィン１２０ｂの上方を覆っているが、ソース電極１５とフィン１２０ｂは絶縁膜２１により絶縁されている。 5B and 5C are schematic diagrams showing an example of the positional relationship in the planar direction of the fin 120, the source electrode 15, and the insulating film 21 in the FinFET 2. FIG. 5B shows the shapes and positions of the fin 120, the source electrode 15, and the insulating film 21 when viewed from above the FinFET 2. As shown in the examples of FIGS. 5B and 5C, in the FinFET 2, the source electrode 15 covers the fin 120b, but the source electrode 15 and the fin 120b are insulated by the insulating film 21.
　また、図５Ｃに示される例では、フィン１２０ａの平面方向の端部（すなわち図５Ｃの右端と左端）の上端とソース電極１５との間にも、これらを絶縁する絶縁膜２１が形成されている。このため、フィン１２０ａの平面方向の端部において厚さの増加や側面の荒れが生じている場合であっても、この部分にソース電極１５が電気的に接続されないため、フィン１２０ａの平面方向の端部の厚さのずれや不均一性に起因するＦｉｎＦＥＴ２の閾値電圧のずれなどの不良を防ぐことができる。したがって、ソース電極１５が、絶縁膜２１により、フィン１２０ａの平面方向の端部の少なくとも一部に電気的に接続されていないことが好ましい。 In the example shown in FIG. 5C, an insulating film 21 is also formed between the upper end of the fin 120a in the planar direction (that is, the right end and left end in FIG. 5C) and the source electrode 15 to insulate them. There is. Therefore, even if the end portion of the fin 120a in the planar direction has an increased thickness or roughened side surface, the source electrode 15 is not electrically connected to this portion, so that the end portion of the fin 120a in the planar direction is It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 2 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the insulating film 21.
　図５Ｃに示されるように、フィン１２０ａの平面方向の端部にソース電極１５が接続されない領域を設ける場合、この領域が小さすぎるとこの領域を設けることによる上記の効果が不十分になり、大きすぎるとＦｉｎＦＥＴ１の動作への影響が生じるおそれがある。このため、このフィン１２０ａの平面方向の端部のソース電極１５が接続されない領域の、平面方向の長さＬ２は、例えば、１～１０μｍの範囲内に設定される。 As shown in FIG. 5C, when a region to which the source electrode 15 is not connected is provided at the end of the fin 120a in the planar direction, if this region is too small, the above effect of providing this region will be insufficient, and If it is too high, the operation of the FinFET 1 may be affected. Therefore, the length L2 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set, for example, within a range of 1 to 10 μm.
　なお、図５Ｂ、図５Ｃに示されるソース電極１５は、上方からコンタクトプラグや引き出し用ワイヤーを接続するための、フィン１２０の上方を覆う領域から外れた位置に設けられる領域１５１を有していてもよい。 Note that the source electrode 15 shown in FIGS. 5B and 5C has a region 151 provided at a position apart from the region covering the upper part of the fin 120 for connecting a contact plug or a lead wire from above. Good too.
（変形例）
　図６は、ＦｉｎＦＥＴ２の変形例の垂直断面図である。ＦｉｎＦＥＴ２においては、図６に示されるように、フィン１２０ｂの高さがフィン１２０ａの高さよりも低くてもよい。この場合、例えば、フィン１２０ｂの上端とその上方を覆うソース電極１５との間に層間絶縁膜１７が形成され、層間絶縁膜１７によりソース電極１５とフィン１２０ｂが絶縁される。 (Modified example)
FIG. 6 is a vertical cross-sectional view of a modification of the FinFET 2. FIG. In the FinFET 2, as shown in FIG. 6, the height of the fin 120b may be lower than the height of the fin 120a. In this case, for example, an interlayer insulating film 17 is formed between the upper end of the fin 120b and the source electrode 15 covering the upper end of the fin 120b, and the interlayer insulating film 17 insulates the source electrode 15 and the fin 120b.
　また、フィン１２０ａの平面方向の端部の少なくとも一部の高さが、フィン１２０ｂと同様に低くなっていてもよい。この場合、フィン１２０ａの平面方向の端部の低くなっている部分の上端とその上方を覆うソース電極１５との間にも層間絶縁膜１７が形成される。このため、フィン１２０ａの平面方向の端部において厚さの増加や側面の荒れが生じている場合であっても、この部分にソース電極１５が電気的に接続されないため、フィン１２０ａの平面方向の端部の厚さのずれや不均一性に起因するＦｉｎＦＥＴ２の閾値電圧のずれなどの不良を防ぐことができる。したがって、ソース電極１５が、層間絶縁膜１７により、フィン１２０ａの平面方向の端部の少なくとも一部に電気的に接続されていないことが好ましい。 Furthermore, the height of at least a portion of the end portion of the fin 120a in the planar direction may be lowered similarly to the height of the fin 120b. In this case, the interlayer insulating film 17 is also formed between the upper end of the lower end of the fin 120a in the planar direction and the source electrode 15 covering the upper end. Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 2 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the interlayer insulating film 17.
〔第３の実施の形態〕
　本発明の第３の実施の形態は、ソース電極１５とフィン１２０ｂの電気的な接続を避けるための構造において第１の実施の形態と異なる。第１の実施の形態と同様の点については、説明を省略又は簡略化する。 [Third embodiment]
The third embodiment of the present invention differs from the first embodiment in the structure for avoiding electrical connection between the source electrode 15 and the fin 120b. Descriptions of the same points as in the first embodiment will be omitted or simplified.
　図７Ａは、本発明の第３の実施の形態に係るＦｉｎＦＥＴ３の垂直断面図である。ＦｉｎＦＥＴ３は、酸化ガリウム系半導体からなる半導体層を備えた縦型のＦｉｎＦＥＴである。 FIG. 7A is a vertical cross-sectional view of the FinFET 3 according to the third embodiment of the present invention. The FinFET 3 is a vertical FinFET including a semiconductor layer made of a gallium oxide semiconductor.
　ＦｉｎＦＥＴ３は、ＦｉｎＦＥＴ１と同様に、酸化ガリウム系半導体からなり、複数のフィン１２０を有する半導体層１０と、複数のフィン１２０の各々の側面上にゲート絶縁膜１３を介して形成されたゲート電極１４と、半導体層１０の複数のフィン１２０側に接続されたソース電極１５と、半導体層１０の複数のフィン１２０の反対側に接続されたドレイン電極１６と、を備える。また、複数のフィン１２０の間及び周囲に層間絶縁膜１７が形成される。 Like the FinFET 1, the FinFET 3 is made of a gallium oxide semiconductor, and includes a semiconductor layer 10 having a plurality of fins 120, and a gate electrode 14 formed on the side surface of each of the plurality of fins 120 via a gate insulating film 13. , a source electrode 15 connected to the side of the plurality of fins 120 of the semiconductor layer 10, and a drain electrode 16 connected to the side of the semiconductor layer 10 opposite to the plurality of fins 120. Furthermore, an interlayer insulating film 17 is formed between and around the plurality of fins 120 .
　ＦｉｎＦＥＴ３においては、フィン１２０ｂの上端にアクセプター不純物を含む高抵抗領域１２３が形成され、高抵抗領域１２３にソース電極１５が接触している。このため、ソース電極１５はフィン１２０ｂに接触しているが、高抵抗領域１２３により絶縁されている。すなわち、ＦｉｎＦＥＴ３においては、ＦｉｎＦＥＴ１と同様に、最も外側のフィン１２０ｂが、ソース電極１５が電気的に接続されないダミーフィンである。高抵抗領域１２３は、例えば、Ｎ、Ｍｇなどのアクセプター不純物をイオン注入することにより形成される。 In the FinFET 3, a high resistance region 123 containing acceptor impurities is formed at the upper end of the fin 120b, and the source electrode 15 is in contact with the high resistance region 123. Therefore, although the source electrode 15 is in contact with the fin 120b, it is insulated by the high resistance region 123. That is, in FinFET3, like FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. The high resistance region 123 is formed, for example, by ion implantation of acceptor impurities such as N and Mg.
　ＦｉｎＦＥＴ３においても、ＦｉｎＦＥＴ１と同様に、最も外側のフィン１２０ｂをソース電極１５が電気的に接続されないダミーフィンとすることにより、フィン１２０ｂの厚さのずれや不均一性に起因するＦｉｎＦＥＴ３の閾値電圧のずれなどの不良を防いでいる。 In FinFET3, similarly to FinFET1, by using the outermost fin 120b as a dummy fin to which the source electrode 15 is not electrically connected, the threshold voltage of FinFET3 due to deviation or non-uniformity in the thickness of the fin 120b can be reduced. This prevents defects such as misalignment.
　図７Ｂ、図７Ｃは、ＦｉｎＦＥＴ３におけるフィン１２０、ソース電極１５、及び高抵抗領域１２３の平面方向の位置関係の例を示す模式図である。図７Ｂ、図７Ｃは、ＦｉｎＦＥＴ３の上方から視たときのフィン１２０、ソース電極１５、及び高抵抗領域１２３の形状と位置を示している。図７Ｂ、図７Ｃの例で示されるように、ＦｉｎＦＥＴ３においては、ソース電極１５がフィン１２０ｂの上方を覆っているが、ソース電極１５とフィン１２０ｂは高抵抗領域１２３により絶縁されている。 7B and 7C are schematic diagrams showing an example of the positional relationship in the planar direction of the fin 120, the source electrode 15, and the high resistance region 123 in the FinFET 3. 7B and 7C show the shapes and positions of the fin 120, the source electrode 15, and the high resistance region 123 when viewed from above the FinFET 3. As shown in the examples of FIGS. 7B and 7C, in the FinFET 3, the source electrode 15 covers the fin 120b, but the source electrode 15 and the fin 120b are insulated by the high resistance region 123.
　また、図７Ｃに示される例では、フィン１２０ａの平面方向の端部（すなわち図７Ｃの右端と左端）の上端にも、フィン１２０ａとソース電極１５を絶縁する高抵抗領域１２３が形成されている。このため、フィン１２０ａの平面方向の端部において厚さの増加や側面の荒れが生じている場合であっても、この部分にソース電極１５が電気的に接続されないため、フィン１２０ａの平面方向の端部の厚さのずれや不均一性に起因するＦｉｎＦＥＴ３の閾値電圧のずれなどの不良を防ぐことができる。したがって、ソース電極１５が、高抵抗領域１２３により、フィン１２０ａの平面方向の端部の少なくとも一部に電気的に接続されていないことが好ましい。 Furthermore, in the example shown in FIG. 7C, high resistance regions 123 that insulate the fin 120a and the source electrode 15 are also formed at the upper ends of the planar ends of the fin 120a (i.e., the right and left ends in FIG. 7C). . Therefore, even if the thickness of the fin 120a is increased or the side surface is rough, the source electrode 15 is not electrically connected to this portion, so that the end of the fin 120a in the planar direction is not electrically connected. It is possible to prevent defects such as a shift in the threshold voltage of the FinFET 3 due to a thickness shift or non-uniformity of the end portion. Therefore, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the end portion of the fin 120a in the planar direction by the high resistance region 123.
　図７Ｃに示されるように、フィン１２０ａの平面方向の端部にソース電極１５が接続されない領域を設ける場合、この領域が小さすぎるとこの領域を設けることによる上記の効果が不十分になり、大きすぎるとＦｉｎＦＥＴ１の動作への影響が生じるおそれがある。このため、このフィン１２０ａの平面方向の端部のソース電極１５が接続されない領域の、平面方向の長さＬ３は、例えば、１～１０μｍの範囲内に設定される。なお、長さＬ３は、フィン１２０ａにおける高抵抗領域１２３の平面方向の長さに等しい。 As shown in FIG. 7C, when providing a region to which the source electrode 15 is not connected at the end of the fin 120a in the planar direction, if this region is too small, the above effect of providing this region will be insufficient, If it is too high, the operation of the FinFET 1 may be affected. Therefore, the length L3 in the planar direction of the region at the end of the fin 120a in the planar direction to which the source electrode 15 is not connected is set within a range of 1 to 10 μm, for example. Note that the length L3 is equal to the length of the high resistance region 123 in the fin 120a in the planar direction.
　なお、図７Ｂ、図７Ｃに示されるソース電極１５は、領域１５１を含まなくてもよい。この場合、ソース電極１５のフィン１２０の上方を覆う領域にコンタクトプラグや引き出し用ワイヤーを接続する。 Note that the source electrode 15 shown in FIGS. 7B and 7C does not need to include the region 151. In this case, a contact plug or a lead wire is connected to a region of the source electrode 15 that covers the upper part of the fin 120.
（実施の形態の効果）
　上記第１～３の実施の形態に係るＦｉｎＦＥＴ１～３によれば、複数のフィン１２０のうちの最も外側のフィン１２０ｂをソース電極１５が電気的に接続されないダミーフィンとすることにより、フィン１２０ｂの厚さのずれや不均一性による閾値電圧への影響を抑えることができる。また、フィン１２０ａの平面方向の端部の少なくとも一部にソース電極１５が接続されないようにすることにより、フィン１２０ａの平面方向の端部の厚さのずれや不均一性よる閾値電圧への影響を抑えることができる。 (Effects of embodiment)
According to the FinFETs 1 to 3 according to the first to third embodiments, the outermost fin 120b of the plurality of fins 120 is used as a dummy fin to which the source electrode 15 is not electrically connected. The influence on the threshold voltage due to thickness deviation or non-uniformity can be suppressed. Furthermore, by preventing the source electrode 15 from being connected to at least a portion of the end portion of the fin 120a in the planar direction, the influence on the threshold voltage due to deviation or non-uniformity in the thickness of the end portion of the fin 120a in the planar direction can be avoided. can be suppressed.
　以上、本発明の実施の形態を説明したが、本発明は、上記実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。また、発明の主旨を逸脱しない範囲内において上記実施の形態の構成要素を任意に組み合わせることができる。また、上記に記載した実施の形態は特許請求の範囲に係る発明を限定するものではない。また、実施の形態の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Moreover, the constituent elements of the embodiments described above can be arbitrarily combined without departing from the spirit of the invention. Furthermore, the embodiments described above do not limit the claimed invention. Furthermore, it should be noted that not all combinations of features described in the embodiments are essential for solving the problems of the invention.
　酸化ガリウム系半導体を半導体層に用いたＦｉｎＦＥＴであって、最も外側のフィンの厚さのずれや不均一性による閾値電圧への影響が抑えられたＦｉｎＦＥＴを提供する。 To provide a FinFET using a gallium oxide-based semiconductor as a semiconductor layer, in which the influence on the threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed.
１、２、３…ＦｉｎＦＥＴ、　１０…半導体層、　１１…基板、　１２…エピタキシャル層、　１２０、１２０ａ、１２０ｂ…フィン、　１２１…ｎ＋領域、　１２３…高抵抗領域、　１３…ゲート絶縁膜、　１４…ゲート電極、　１５…ソース電極、　１６…ドレイン電極、　１７…層間絶縁膜、　２１…絶縁膜
  DESCRIPTION OF SYMBOLS 1, 2, 3...FinFET, 10...Semiconductor layer, 11...Substrate, 12...Epitaxial layer, 120, 120a, 120b...Fin, 121...n + region, 123...High resistance region, 13...Gate insulating film, 14... Gate electrode, 15... Source electrode, 16... Drain electrode, 17... Interlayer insulating film, 21... Insulating film

Claims (7)

  1. 　酸化ガリウム系半導体からなり、複数のフィンを有する半導体層と、
    　前記複数のフィンの各々の側面上にゲート絶縁膜を介して形成されたゲート電極と、
    　前記半導体層の前記複数のフィン側に接続されたソース電極と、
    　前記半導体層の前記複数のフィンの反対側に接続されたドレイン電極と、
    　を備え、
    　前記複数のフィンのうちの最も外側のフィンが、前記ソース電極が電気的に接続されないダミーフィンである、
    　フィン型電界効果トランジスタ。     a semiconductor layer made of a gallium oxide-based semiconductor and having a plurality of fins;
    a gate electrode formed on a side surface of each of the plurality of fins with a gate insulating film interposed therebetween;
    a source electrode connected to a side of the plurality of fins of the semiconductor layer;
    a drain electrode connected to the opposite side of the plurality of fins of the semiconductor layer;
    Equipped with
    The outermost fin of the plurality of fins is a dummy fin to which the source electrode is not electrically connected.
    Fin field effect transistor.
  2. 　前記ソース電極が、前記複数のフィンのうちの前記ダミーフィンの内側のフィンの平面方向の端部の少なくとも一部に電気的に接続されない、
    　請求項１に記載のフィン型電界効果トランジスタ。     the source electrode is not electrically connected to at least a portion of an end in a planar direction of a fin inside the dummy fin of the plurality of fins;
    The fin field effect transistor according to claim 1.
  3. 　前記ソース電極が前記ダミーフィンの上方を覆い、
    　前記ダミーフィンの上端と前記ソース電極との間に絶縁膜が形成された、
    　請求項１又は２に記載のフィン型電界効果トランジスタ。     the source electrode covers above the dummy fin;
    an insulating film is formed between an upper end of the dummy fin and the source electrode;
    The fin field effect transistor according to claim 1 or 2.
  4. 　前記ダミーフィンの高さが、前記複数のフィンのうちのその他のフィンの高さよりも低い、
    　請求項３に記載のフィン型電界効果トランジスタ。     The height of the dummy fin is lower than the height of other fins among the plurality of fins.
    The fin field effect transistor according to claim 3.
  5. 　前記ダミーフィンの上端にアクセプター不純物を含む高抵抗領域が形成され、
    　前記高抵抗領域に前記ソース電極が接触している、
    　請求項１又は２に記載のフィン型電界効果トランジスタ。     a high resistance region containing acceptor impurities is formed at the upper end of the dummy fin;
    the source electrode is in contact with the high resistance region;
    The fin field effect transistor according to claim 1 or 2.
  6. 　前記ソース電極が前記ダミーフィンの上方を覆わない、
    　請求項１又は２に記載のフィン型電界効果トランジスタ。     the source electrode does not cover above the dummy fin;
    The fin field effect transistor according to claim 1 or 2.
  7. 　前記ダミーフィンが、前記複数のフィンのうちの前記ダミーフィンの内側のフィンを四方から囲むように配置された、
    　請求項６に記載のフィン型電界効果トランジスタ。     The dummy fin is arranged to surround an inner fin of the dummy fin from all sides among the plurality of fins,
    The fin field effect transistor according to claim 6.
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