WO2024001036A1 - Corps d'emballage et son procédé de fabrication - Google Patents

Corps d'emballage et son procédé de fabrication Download PDF

Info

Publication number
WO2024001036A1
WO2024001036A1 PCT/CN2022/135574 CN2022135574W WO2024001036A1 WO 2024001036 A1 WO2024001036 A1 WO 2024001036A1 CN 2022135574 W CN2022135574 W CN 2022135574W WO 2024001036 A1 WO2024001036 A1 WO 2024001036A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive
blind hole
conductive layer
chip
Prior art date
Application number
PCT/CN2022/135574
Other languages
English (en)
Chinese (zh)
Inventor
朱凯
黄立湘
缪桦
Original Assignee
深南电路股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深南电路股份有限公司 filed Critical 深南电路股份有限公司
Publication of WO2024001036A1 publication Critical patent/WO2024001036A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29018—Shape in side view comprising protrusions or indentations
    • H01L2224/29019—Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector

Definitions

  • the present application relates to the field of chip packaging technology, and in particular to a package body and a manufacturing method thereof.
  • the chip mounting method includes the following steps: providing a temporary carrier with a metal layer on the temporary carrier, pre-making a chip attachment layer on one side of the chip, and then placing the chip attachment layer on one side It is attached to one side of the metal layer on the temporary carrier so that the chip is relatively fixed. Then the chip is plastic-sealed and the temporary carrier is peeled off. In this way, the chip attach layer is attached to the metal layer by thermosetting molding, and the bonding force between the chip attach layer and the metal layer is poor.
  • the main technical problem solved by this application is to provide a package and a manufacturing method thereof to improve the bonding force between the attachment layer and the conductive layer.
  • the package body includes: a conductive layer, the surface on one side of the conductive layer is a rough surface; a chip, the chip passes through the attachment layer Mounted on the rough surface of the conductive layer; a conductive component, the conductive component is disposed on one side of the rough surface of the conductive layer, wherein the conductive component makes the pad of the chip conductive to the conductive layer Pass.
  • the method of manufacturing the package includes: obtaining a substrate, which includes a carrier and a conductive conductor located on one side of the carrier. layer, the surface of the conductive layer away from the carrier is a rough surface; conductive components are made on the rough surface side of the conductive layer and chips are mounted using an attachment layer, and the carrier is removed from the substrate Lifting, wherein the conductive component conducts the pads of the chip and the conductive layer.
  • the package of this application includes a conductive layer, a chip and a conductive component.
  • the surface on one side of the conductive layer is a rough surface
  • the chip is mounted on the conductive layer through an attachment layer.
  • the conductive component is arranged on the rough surface side of the conductive layer, and the conductive component connects the pad of the chip to the conductive layer.
  • Figure 1 is a schematic flow chart of the first embodiment of the manufacturing method of the package of the present application.
  • FIG. 2 is a schematic flowchart of an embodiment of step S12 in Figure 1;
  • Figure 3 is a schematic flow chart of a second embodiment of the manufacturing method of a printed circuit board according to the present application.
  • Figure 4 is a schematic structural diagram of the production process of each step corresponding to steps S301-S308 in Figure 3 according to an embodiment
  • Figure 5 is a schematic flow chart of the third embodiment of the manufacturing method of the printed circuit board of the present application.
  • Figure 6 is a schematic structural diagram of the production process of each step corresponding to steps S501-S510 in Figure 5 according to an embodiment
  • Figure 7 is a schematic flow chart of the fourth embodiment of the manufacturing method of the printed circuit board of the present application.
  • Figure 8 is a schematic structural diagram of the production process of each step corresponding to steps S701-S707 in Figure 7 according to an embodiment
  • Figure 9 is a schematic flow chart of the fifth embodiment of the manufacturing method of the printed circuit board of the present application.
  • Figure 10 is a schematic structural diagram of the production process of each step corresponding to steps S901-S910 in Figure 9 according to an embodiment
  • FIG 11 is a schematic flow chart of another embodiment of step S12 in Figure 1;
  • Figure 12 is a schematic flowchart of an implementation of step S1221 in Figure 11;
  • Figure 13 is a schematic flow chart of the sixth embodiment of the manufacturing method of the printed circuit board of the present application.
  • Figure 14 is a schematic structural diagram of the production process of each step corresponding to steps S1301-S1308 in Figure 13 according to an embodiment
  • Figure 15 is a schematic flow chart of the seventh embodiment of the printed circuit board manufacturing method of the present application.
  • Figure 16 is a schematic structural diagram of the production process of each step corresponding to steps S1501-S1508 in Figure 15 according to an embodiment
  • Figure 17 is a schematic flow chart of the eighth embodiment of the printed circuit board manufacturing method of the present application.
  • Figure 18 is a schematic structural diagram of the production process of each step corresponding to steps S1701-S1708 in Figure 17 according to an embodiment
  • Figure 19 is a schematic structural diagram of an embodiment of the package of the present application.
  • FIG. 1 is a schematic flowchart of a first embodiment of a method for manufacturing a package according to the present application.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • the substrate which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • the substrate can be a piece of board-level peelable copper foil material.
  • the substrate can be specifically composed of a carrier and a conductive layer.
  • the carrier is a peelable carrier and the conductive layer is a copper foil layer; the peelable carrier is a double-sided copper-clad sheet.
  • the organic resin substrate has smooth copper foil surfaces on both sides; one side of the copper foil layer is a smooth surface and the other side is a rough surface.
  • the rough surface can be a copper tooth structure, and the rough surface is set outwards away from the carrier; the copper foil layer can Mechanically peeled off from the peelable carrier, the peelable carrier can provide mechanical strength support for the entire processing process.
  • S12 Make a conductive component on the rough surface side of the conductive layer and mount the chip using the attachment layer, and peel the carrier from the substrate, where the conductive component makes the pad of the chip contact the
  • the conductive layer is conductive. Specifically, by first obtaining a substrate, the substrate includes a carrier and a conductive layer located on one side of the carrier. The surface of the conductive layer away from the carrier is a rough surface. Then, conductive components are made on the rough surface side of the conductive layer and attached using an attachment layer. To install the chip, the conductive component connects the pad of the chip to the conductive layer, and then the carrier can be peeled off from the substrate to form a package.
  • the surface of the side of the conductive layer away from the carrier is set as a rough surface, so that when the chip is mounted using the attachment layer on the rough side of the conductive layer, during the curing process of the attachment layer, the rough surface and the attachment layer Bite structures can be formed to improve bonding strength.
  • step S12 includes:
  • S1211 Use the attachment layer to mount the chip on the rough surface of the conductive layer. Specifically, an attachment layer is attached to one side of the chip, and then the chip with the attachment layer attached is attached to the rough surface of the conductive layer.
  • the attachment layer may be a chip attachment film. Due to the curing characteristics (heat curing) of the chip attachment film, the mounted chip is firmly fixed on the surface of the conductive layer by the cured chip attachment film.
  • S1212 Make a plastic sealing layer on the rough surface side of the conductive layer, and the plastic sealing layer covers the chip.
  • S1213 Make a conductive component on the rough surface side of the conductive layer, and peel the carrier from the substrate, where the conductive component connects the pad of the chip to the conductive layer.
  • a plastic sealing layer can be made on the rough surface side of the conductive layer to cover the chip, and then a conductive component can be made on the rough surface side of the conductive layer to conduct electricity.
  • the component connects the chip's pad to the conductive layer and peels the carrier off the substrate to achieve plastic packaging of the chip.
  • the above-mentioned step S1213 may specifically include: making a metal layer on the side of the plastic layer away from the conductive layer; making a first blind hole at a first preset position, and making a third blind hole at a second preset position.
  • Two blind holes wherein the first blind hole penetrates the metal layer and the plastic sealing layer, the bottom of the first blind hole reaches the rough surface of the conductive layer, and the second blind hole penetrates the metal layer and the plastic sealing layer, the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer; and the inner walls of the first blind hole and the inner wall of the second blind hole are respectively made.
  • a conductive seed layer electroplating to fill the first blind hole and the second blind hole to form a first conductive part in the first blind hole and a second conductive part in the second blind hole ;
  • the first conductive part conducts the conductive layer and the metal layer
  • the second conductive part conducts the pad on the side of the chip away from the conductive layer and the metal layer;
  • the carrier is peeled off from the substrate to expose the surface of the conductive layer on the side away from the rough surface.
  • the method of manufacturing the package further includes: forming a first conductive line on the metal layer, and forming a second conductive line on the conductive layer.
  • Figure 3 is a schematic flow chart of a second embodiment of the manufacturing method of a printed circuit board of the present application
  • Figure 4 is an embodiment corresponding to steps S301-S308 in Figure 3 Schematic diagram of the production process structure of each step.
  • the surface of the metal layer close to the conductive layer is a rough surface.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • a substrate 10 which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • a substrate 10 is obtained.
  • the substrate 10 is composed of a carrier 100 and a conductive layer 101.
  • the carrier 100 is a peelable carrier, and the peelable carrier is a double-sided copper-clad organic resin.
  • the substrate has smooth copper foil surfaces on both sides.
  • the conductive layer 101 is a copper foil layer.
  • One side of the copper foil layer is a smooth surface and the other side is a rough surface.
  • the rough surface has a copper tooth structure and the rough surface faces outward away from the carrier 100. Setting; the copper foil layer can be mechanically peeled off from the peelable carrier.
  • S302 Use the attachment layer to mount the chip on the rough surface of the conductive layer. Specifically, as shown in FIG. 4b , in one embodiment, before cutting the wafer, an attachment layer 11 is attached to the non-pad surface.
  • the attachment layer 11 is a chip attachment film, and then the chip 12 is obtained by cutting. Therefore, the chip 12 with the attachment layer 11 attached can be mounted on the rough surface of the conductive layer 101 .
  • S304 Create a metal layer on the side of the plastic sealing layer away from the conductive layer.
  • a film-like film may be stacked on one side of the rough surface of the conductive layer 101 .
  • the metal layer 14 is copper foil.
  • the thickness of the metal layer 14 is less than or equal to 12 ⁇ m.
  • the metal layer 14 has a rough surface with the rough surface facing the plastic sealing material.
  • the plastic sealing material is laminated. After curing, the plastic sealing layer 13 covering the chip 12 is formed, so that the conductive layer 101, the plastic sealing layer 13 and the top metal layer 14 on the carrier 100 are all firmly combined, and the plastic sealing of the chip 12 is completed at the same time.
  • S305 Make a first blind hole at a first preset position, and make a second blind hole at a second preset position; wherein the first blind hole penetrates the metal layer and the plastic sealing layer, and the first blind hole penetrates the metal layer and the plastic sealing layer. The bottom of the hole reaches the rough surface of the conductive layer, the second blind hole penetrates the metal layer and the plastic sealing layer, and the bottom of the second blind hole reaches the solder joint on the side of the chip away from the conductive layer. plate.
  • laser drilling is performed at the first preset position and the second preset position corresponding to the surface of the pressed metal layer 14 to form the first blind hole 151 and the second preset position.
  • Two blind holes 152 wherein the first blind hole 151 penetrates the metal layer 14 and the plastic sealing layer 13, the bottom of the first blind hole 151 reaches the rough surface of the conductive layer 101, and the second blind hole 152 penetrates the metal layer 14 and the plastic sealing layer 13, The bottom of the second blind hole 152 reaches the pad 121 on the side of the chip 12 away from the conductive layer 101 .
  • the metal layer 14 at the location that requires laser drilling can be etched away by sequentially applying dry film, exposing, developing, and etching, and then perform laser drilling to obtain the first blind
  • the hole shape of the hole 151 and the second blind hole 152 is better; in another embodiment of the present application, the metal layer 14 can be thinned by micro-etching and browning, and the absorption of the laser by the metal layer 14 can be improved, and then Direct laser drilling, this method has fast processing speed and low cost.
  • S306 Make a conductive seed layer on the inner wall of the first blind hole and the second blind hole respectively, and fill the first blind hole and the second blind hole with electroplating to form a conductive seed layer on the inner wall of the first blind hole and the second blind hole.
  • a first conductive part is formed in the blind hole, and a second conductive part is formed in the second blind hole; wherein the first conductive part conducts the conductive layer and the metal layer, and the second conductive part
  • the pad on the side of the chip away from the conductive layer is electrically connected to the metal layer.
  • a hole can be made on the inner walls of the first blind hole 151 and the second blind hole 152 .
  • a conductive seed layer (not shown).
  • the first blind hole 151 and the second blind hole 152 are then filled with electroplated copper to form a first conductive part 161 in the first blind hole 151 and a second conductive part 162 in the second blind hole 152, wherein the first The conductive part 161 conducts the conductive layer 101 and the metal layer 14 , and the second conductive part 162 conducts the pad 121 on the side of the chip 12 away from the conductive layer 101 and the metal layer 14 .
  • the conductive seed layer can be made by electroless copper plating, titanium/copper sputtering, black holes, black shadows, graphene oxide adsorption, conductive polymer adsorption, silver paste coating, etc.
  • S307 Peel off the carrier from the substrate to expose the surface of the conductive layer on the side away from the rough surface. Specifically, as shown in FIG. 4f and FIG. 4g , in one embodiment, the carrier 100 can then be peeled off to separate the carrier 100 from the conductive layer 101 to expose the surface of the conductive layer 101 away from the rough surface.
  • S308 Make a first conductive line on the metal layer, and make a second conductive line on the conductive layer.
  • the first conductive circuits (not shown), A second conductive circuit (not shown) is formed on the conductive layer 101 .
  • the metal layer 14 can be thinned by grinding, micro-etching, etc., so that the metal layer 14 reaches a required thickness.
  • the above-mentioned step S1213 may specifically include: making a metal layer on the side of the plastic layer away from the conductive layer; making a first blind hole at a first preset position; wherein the first blind hole Penetrating the metal layer and the plastic sealing layer, the bottom of the first blind hole reaches the rough surface of the conductive layer; a conductive seed layer is made on the inner wall of the first blind hole, and electroplating fills the first a blind hole to form a first conductive part in the first blind hole; wherein the first conductive part conducts the conductive layer and the metal layer; peeling off the carrier from the substrate, To expose the surface of the conductive layer on the side away from the rough surface; make a second blind hole at the second preset position, and make a third blind hole at the third preset position; wherein the second blind hole penetrates all The metal layer and the plastic sealing layer, the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer, the third blind hole penetrates the
  • the method of manufacturing the package further includes: forming a first conductive line on the metal layer, and forming a second conductive line on the conductive layer.
  • FIG. 5 is a schematic flow diagram of a third embodiment of the manufacturing method of a printed circuit board of the present application
  • FIG. 6 is an embodiment corresponding to steps S501-S510 in FIG. 5 Schematic diagram of the production process structure of each step.
  • the surface of the metal layer close to the conductive layer is a rough surface.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • S501 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • S504 Create a metal layer on the side of the plastic sealing layer away from the conductive layer.
  • steps S501 to S504 in this embodiment are basically the same as steps S301 to S304 in the above embodiment.
  • Figures 6a to 6d correspond to the same as Figures 4a to 4d.
  • S505 Make a first blind hole at a first preset position; wherein the first blind hole penetrates the metal layer and the plastic sealing layer, and the bottom of the first blind hole reaches the rough surface of the conductive layer.
  • laser drilling is performed at a first preset position corresponding to the surface of the pressed metal layer 14 to form a first blind hole 151 , where the first blind hole 151 Penetrating through the metal layer 14 and the plastic sealing layer 13 , the bottom of the first blind hole 151 reaches the rough surface of the conductive layer 101 .
  • S506 Make a conductive seed layer on the inner wall of the first blind hole, and fill the first blind hole with electroplating to form a first conductive part in the first blind hole; wherein, the first conductive part
  • the conductive layer is electrically connected to the metal layer.
  • a conductive seed layer (not shown) can be made on the inner wall of the first blind hole 151, and then filled with electroplated copper.
  • the first blind hole 151 is used to form a first conductive portion 161 in the first blind hole 151 , wherein the first conductive portion 161 conducts the conductive layer 101 and the metal layer 14 .
  • S507 Peel off the carrier from the substrate to expose the surface of the conductive layer on the side away from the rough surface. Specifically, as shown in FIG. 6f and FIG. 6g, in one embodiment, the carrier 100 can then be peeled off to separate the carrier 100 from the conductive layer 101 to expose the surface of the conductive layer 101 away from the rough surface.
  • S508 Make a second blind hole at the second preset position, and make a third blind hole at the third preset position; wherein the second blind hole penetrates the metal layer and the plastic sealing layer, and the second blind hole penetrates the metal layer and the plastic sealing layer. The bottom of the hole reaches the pad on the side of the chip away from the conductive layer. The third blind hole penetrates the conductive layer and the plastic sealing layer. The bottom of the third blind hole reaches the chip close to the pad on one side of the conductive layer.
  • the chip 12 of the present application has pads 121 on both sides.
  • laser drilling can be performed at the second preset position corresponding to the surface of the pressed metal layer 14.
  • hole to form a second blind hole 152 perform laser drilling at a third preset position corresponding to the conductive layer 101, and form a third blind hole 153, wherein the second blind hole 152 penetrates the metal layer 14 and the plastic sealing layer 13, and the second blind hole 152 penetrates the metal layer 14 and the plastic sealing layer 13.
  • the bottom of the blind hole 152 reaches the pad 121 on the side of the chip 12 away from the conductive layer 101.
  • the third blind hole 153 penetrates the conductive layer 101 and the plastic sealing layer 13.
  • the bottom of the third blind hole 153 reaches the side of the chip 12 close to the conductive layer 101.
  • Pad 121 is a pad 121.
  • S509 Make a conductive seed layer on the inner wall of the second blind hole and the third blind hole respectively, fill the second blind hole and the third blind hole with electroplating, so that the second blind hole and the third blind hole are filled with electroplating.
  • a second conductive part is formed in the blind hole, and a third conductive part is formed in the third blind hole; wherein the second conductive part keeps the chip away from the pad on one side of the conductive layer and the metal layer The third conductive part conducts the pad on the side of the chip close to the conductive layer and the conductive layer.
  • a hole can be made on the inner wall of the second blind hole 152 and the third blind hole 153.
  • layer a conductive seed layer (not shown), and then use electroplated copper to fill the second blind hole 152 and the third blind hole 153 to form a second conductive part 162 in the second blind hole 152 and a second conductive part 162 in the third blind hole 153.
  • the third conductive part 163 wherein the second conductive part 162 connects the pad 121 on the side of the chip 12 away from the conductive layer 101 with the metal layer 14 , and the third conductive part 163 connects the pad on the side of the chip 12 close to the conductive layer 101 121 is electrically connected to the conductive layer 101.
  • S510 Make a first conductive line on the metal layer, and make a second conductive line on the conductive layer.
  • first conductive lines are respectively produced on the metal layer 14 by applying dry film on both sides, exposing, developing, etching, and removing the film. (not shown in the figure), a second conductive circuit (not shown in the figure) is formed on the conductive layer 101.
  • the metal layer 14 and the conductive layer 101 can be thinned by grinding, micro-etching, etc., so that the metal layer 14 and the conductive layer 101 reach the required thickness.
  • the above-mentioned step S1213 may specifically include: making a first blind hole at a first preset position, and making a second blind hole at a second preset position; wherein the first blind hole penetrates the plastic sealing layer. , the bottom of the first blind hole reaches the rough surface of the conductive layer, the second blind hole penetrates the plastic sealing layer, and the bottom of the second blind hole reaches the side of the chip away from the conductive layer Welding pad; make a conductive seed layer on the inner wall of the first blind hole and the second blind hole respectively, fill the first blind hole and the second blind hole with electroplating, so as to form a conductive seed layer on the inner wall of the first blind hole and the second blind hole.
  • a first conductive part is formed in a blind hole, a second conductive part is formed in the second blind hole, and a metal layer is formed on a side of the plastic layer away from the conductive layer; wherein, the first conductive part The conductive layer is connected to the metal layer, and the second conductive part connects the pad on the side of the chip away from the conductive layer to the metal layer; remove the carrier from the substrate Peel off to expose the surface of the conductive layer on the side away from the rough surface.
  • the method of manufacturing the package further includes: forming a first conductive line on the metal layer, and forming a second conductive line on the conductive layer.
  • FIG. 7 is a schematic flow diagram of a fourth embodiment of the manufacturing method of a printed circuit board of the present application
  • FIG. 8 is an implementation corresponding to steps S701-S707 in FIG. 7 Schematic diagram of the production process structure of each step.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • S701 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • steps S701 to S703 in this embodiment are basically the same as steps S301 to S303 in the above embodiment.
  • Figures 8a to 8c correspond to the same as Figures 4a to 4c.
  • S704 Make a first blind hole at the first preset position, and make a second blind hole at the second preset position; wherein the first blind hole penetrates the plastic sealing layer, and the bottom of the first blind hole reaches the The second blind hole penetrates the rough surface of the conductive layer, and the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer.
  • the metal layer 14 in FIG. 4d is not pressed onto the plastic layer 13 , but directly at the first preset position and the second corresponding position on the surface of the plastic layer 13 .
  • Laser drilling is performed at the preset position to form the first blind hole 151 and the second blind hole 152 , wherein the first blind hole 151 and the second blind hole 152 penetrate the plastic sealing layer 13 , and the bottom of the first blind hole 151 reaches the conductive layer 101 On the rough surface, the bottom of the second blind hole 152 reaches the pad 121 on the side of the chip 12 away from the conductive layer 101 .
  • laser drilling can be performed directly in this step.
  • S705 Make a conductive seed layer on the inner wall of the first blind hole, the inner wall of the second blind hole and the side of the plastic sealing layer away from the conductive layer, and fill the first blind hole and the first blind hole with electroplating.
  • the second blind hole is to form a first conductive part in the first blind hole, a second conductive part in the second blind hole, and a side of the plastic sealing layer away from the conductive layer.
  • Metal layer wherein, the first conductive part conducts the conductive layer and the metal layer, and the second conductive part conducts the pad on the side of the chip away from the conductive layer and the metal layer. Pass. Specifically, as shown in FIG.
  • the inner walls of the first blind hole 151 , the second blind hole 152 and the plastic sealing layer 13 can be separated from each other.
  • a conductive seed layer (not shown) is formed on one side of the conductive layer 101, and then electroplated copper is used to fill the first blind hole 151 and the second blind hole 152 to form the first conductive portion 161 and the second blind hole 152 in the first blind hole 151.
  • a second conductive part 162 is formed in the second blind hole 152 , and a metal layer 14 is formed on the side of the plastic layer 13 away from the conductive layer 101 .
  • the first conductive part 161 conducts the conductive layer 101 and the metal layer 14 .
  • the conductive part 162 connects the pad 121 on the side of the chip 12 away from the conductive layer 101 with the metal layer 14 .
  • the metal layer 14 is connected to the first conductive part 161 .
  • the first conductive part 161 connects the conductive layer 101 with the metal layer 14 .
  • S706 Peel off the carrier from the substrate to expose the surface of the conductive layer on the side away from the rough surface.
  • S707 Make a first conductive line on the metal layer, and make a second conductive line on the conductive layer.
  • steps S706 to S707 in this embodiment are basically the same as steps S307 to S308 in the above embodiment, and Figures 8f to 8g correspond to the same as Figures 4g to 4h.
  • the above-mentioned step S1213 may specifically include: making a first blind hole at a first preset position; wherein the first blind hole penetrates the plastic sealing layer, and the bottom of the first blind hole reaches the The rough surface of the conductive layer; make a conductive seed layer on the inner wall of the first blind hole, fill the first blind hole with electroplating to form a first conductive part in the first blind hole, and A metal electroplating layer is formed on the side of the plastic sealing layer away from the conductive layer; the metal electroplating layer is ground until the metal electroplating layer is completely removed; a second blind hole is made at a second preset position; wherein, the third Two blind holes penetrate the plastic sealing layer, and the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer; a conductive seed layer is made on the inner wall of the second blind hole, and Pattern plating, filling the second blind hole to form a second conductive part in the second blind hole, and forming a metal layer as
  • Figure 9 is a schematic flow diagram of a fifth embodiment of the manufacturing method of a printed circuit board of the present application
  • Figure 10 is an implementation corresponding to steps S901-S910 in Figure 9. Schematic diagram of the production process structure of each step.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • S901 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • steps S901 to S903 in this embodiment are basically the same as steps S501 to S503 in the above embodiment.
  • Figures 10a to 10c correspond to the same as Figures 6a to 6c.
  • S904 Make a first blind hole at a first preset position; wherein the first blind hole penetrates the plastic sealing layer, and the bottom of the first blind hole reaches the rough surface of the conductive layer.
  • the metal layer 14 of Figure 6d is not pressed onto the plastic layer 13, but laser drilling is directly performed at the first preset position corresponding to the surface of the plastic layer 13. , forming a first blind hole 151, wherein the first blind hole 151 penetrates the plastic sealing layer 13, and the bottom of the first blind hole 151 reaches the rough surface of the conductive layer 101.
  • laser drilling can be performed directly in this step.
  • S905 Make a conductive seed layer on the inner wall of the first blind hole and the side of the plastic sealing layer away from the conductive layer, and fill the first blind hole with electroplating to form a conductive seed layer in the first blind hole.
  • a first conductive part, and a metal plating layer is formed on the side of the plastic sealing layer away from the conductive layer. Specifically, as shown in FIG.
  • a conductive seed layer can be made on the inner wall of the first blind hole 151 and the side of the plastic layer 13 away from the conductive layer 101 (not shown), then electroplating copper is used to fill the first blind hole 151 to form the first conductive part 161 in the first blind hole 151, and a metal plating layer 164 is formed on the side of the plastic layer 13 away from the conductive layer 101, Among them, the first conductive part 161 conducts the conductive layer 101 and the metal plating layer 164 .
  • S906 Grind the metal electroplating layer until the metal electroplating layer is completely removed.
  • the metal plating layer 164 is polished and removed to expose the plastic sealing layer 13 corresponding to the pad 121 on the side of the chip 12 away from the conductive layer 101 .
  • S907 Make a second blind hole at the second preset position; wherein the second blind hole penetrates the plastic sealing layer, and the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer. .
  • laser drilling can be directly performed on the second preset position corresponding to the surface of the plastic sealing layer 13 to form a second Blind hole 152, wherein the second blind hole 152 penetrates the plastic sealing layer 13, and the bottom of the second blind hole 152 reaches the pad 121 on the side of the chip 12 away from the conductive layer 101.
  • laser drilling can be performed directly in this step.
  • S908 Make a conductive seed layer on the inner wall of the second blind hole and the side of the plastic sealing layer away from the conductive layer, perform pattern plating, and fill the second blind hole to form a layer on the second blind hole.
  • a second conductive part is formed in the blind hole, and a metal layer with a first conductive line is formed on the side of the plastic layer away from the conductive layer; wherein the second conductive part keeps the chip away from the conductive layer.
  • the pad on one side is electrically connected to the metal layer, the metal layer is connected to the first conductive part, and the first conductive part connects the conductive layer to the metal layer.
  • a conductive seed layer can be formed on the inner wall of the second blind hole 152 and the side of the plastic layer 13 away from the conductive layer 101. (not shown), and then by sequentially applying dry film, exposure, development, pattern plating, film removal, and rapid etching to form the second conductive portion 162 in the second blind hole 152 and the plastic sealing layer 13 away from the conductive layer 101.
  • the metal layer 14 is formed on one side of the chip 12 . At this time, the metal layer 14 is a first conductive line.
  • the second conductive portion 162 connects the pad 121 on the side of the chip 12 away from the conductive layer 101 with the metal layer 14 .
  • the metal layer 14 Connected to the first conductive part 161 , the first conductive part 161 conducts the conductive layer 101 and the metal layer 14 .
  • S909 Peel off the carrier from the substrate to expose the surface of the conductive layer away from the rough surface.
  • the carrier 100 is peeled off to separate the carrier 100 from the conductive layer 101 to expose the surface of the conductive layer 101 away from the rough surface.
  • S910 Make a second conductive line on the conductive layer. Specifically, as shown in FIG. 10j , in one embodiment, a second conductive circuit (not shown) is produced on the conductive layer 101 by applying dry film on both sides, exposing, developing, etching, and removing the film. In this embodiment, the manufacturing of a three-dimensional packaging structure of high-definition conductive circuits is achieved.
  • step S12 includes:
  • the first conductive part is a copper pillar.
  • the first conductive part can be directly produced on the rough surface side of the conductive layer, or prefabricated copper pillars can be directly placed on the rough surface of the conductive layer. It can be understood that the conductive layer is used as the conductive seed layer to make the first conductive part before plastic packaging to realize inter-layer interconnection of the plastic packaging layer, which can meet the needs of high-density three-dimensional packaging.
  • S1222 Use the attachment layer to mount the chip on the rough surface of the conductive layer. Specifically, an attachment layer is attached to one side of the chip, and then the chip with the attachment layer attached is attached to the rough surface of the conductive layer.
  • the attachment layer may be a chip attachment film. Due to the curing characteristics (heat curing) of the chip attachment film, the mounted chip is firmly fixed on the surface of the conductive layer by the cured chip attachment film.
  • S1224 Make a conductor on the side of the chip away from the conductive layer, and peel the carrier from the substrate, wherein the first conductive part and the conductor form a conductive component, and the conductive component The pad of the chip is electrically connected to the conductive layer.
  • a plastic sealing layer can be made on the rough surface side of the conductive layer, and then a conductor can be made on the rough surface side of the conductive layer.
  • the conductive component Composed of a first conductive part and a conductive body, the conductive component connects the pad of the chip to the conductive layer, and peels the carrier from the substrate to achieve plastic packaging of the chip.
  • step S1221 includes:
  • S12211 Paste a dry film on the rough surface side of the conductive layer, wherein the height of the surface of the dry film away from the rough surface of the conductive layer is greater than or equal to the soldering height of the chip on the side away from the conductive layer. plate.
  • S12212 Expose, develop, and pattern plating the dry film in sequence, and then remove the film to form the first conductive part.
  • the first conductive part can be produced on the rough surface side of the conductive layer by sequentially applying a thick dry film, exposure, development, pattern plating, and film removal on the rough surface side of the conductive layer.
  • a conductive part can be produced on the rough surface side of the conductive layer by sequentially applying a thick dry film, exposure, development, pattern plating, and film removal on the rough surface side of the conductive layer.
  • the surface of the first conductive part away from the conductive layer is exposed outside the plastic sealing layer; the above step S1224 may specifically include: making a second blind hole at a second preset position; wherein, The second blind hole penetrates the plastic sealing layer, and the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer; the inner wall of the second blind hole is far away from the plastic sealing layer.
  • a conductive seed layer is made on one side of the conductive layer, and the second blind hole is filled with electroplating to form a second conductive part in the second blind hole, and a part of the plastic sealing layer away from the conductive layer is A metal layer is formed on one side; wherein, the first conductive part conducts the conductive layer and the metal layer, and the second conductive part connects the pad on the side of the chip away from the conductive layer and the The metal layer is conductive; the carrier is peeled off from the substrate to expose the surface of the conductive layer on the side away from the rough surface.
  • the method of manufacturing the package further includes: forming a first conductive line on the metal layer, and forming a second conductive line on the conductive layer.
  • FIG. 13 is a flow diagram of the sixth embodiment of the manufacturing method of the printed circuit board of the present application
  • FIG. 14 is an implementation corresponding to steps S1301-S1308 in FIG. 13 Schematic diagram of the production process structure of each step.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • step S1301 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • step S1301 in this embodiment is basically the same as step S301 in the above-mentioned embodiment, and Figure 14a corresponds to the same as Figure 4a.
  • S1302 Create a first conductive part on the rough surface side of the conductive layer.
  • the first conductive part 161 is produced by applying a thick dry film on the rough surface of the conductive layer 101, exposing, developing, pattern plating, and removing the film.
  • S1303 Use the attachment layer to mount the chip on the rough surface of the conductive layer. Specifically, as shown in FIG. 14c , in one embodiment, an attachment layer 11 is attached to one side of the chip 12 , and the attachment layer 11 is a chip attachment film, and then the attachment layer 11 is attached. The chip 12 is mounted on the rough surface of the conductive layer 101 .
  • S1304 Make a plastic sealing layer on the rough surface side of the conductive layer, and the plastic sealing layer covers the chip. Specifically, as shown in FIG. 14d , in one embodiment, after making the first conductive portion 161 on the rough surface of the conductive layer 101 and mounting the chip 12 , a film-like plastic seal can be superimposed on the rough surface side of the conductive layer 101 The plastic sealing material is then solidified by lamination or vacuum lamination to form a plastic sealing layer 13 covering the chip 12 .
  • S1305 Make a second blind hole at the second preset position; wherein the second blind hole penetrates the plastic sealing layer, and the bottom of the second blind hole reaches the pad on the side of the chip away from the conductive layer.
  • the plastic layer 13 can be ground to a target thickness so that the top of the first conductive portion 161 is exposed to the plastic layer 13 ; and then the corresponding third layer on the surface of the plastic layer 13 is directly Laser drilling is performed at two preset positions to form a second blind hole 152 , where the second blind hole 152 penetrates the plastic sealing layer 13 and the bottom of the second blind hole 152 reaches the pad 121 on the side of the chip 12 away from the conductive layer 101 .
  • laser drilling can be performed directly in this step.
  • S1306 Make a conductive seed layer on the inner wall of the second blind hole and the side of the plastic layer away from the conductive layer, and fill the second blind hole with electroplating to form a conductive seed layer in the second blind hole.
  • a second conductive part, and a metal layer is formed on the side of the plastic layer away from the conductive layer; wherein the first conductive part conducts the conductive layer and the metal layer, and the second conductive part
  • the pad on the side of the chip away from the conductive layer is electrically connected to the metal layer. Specifically, as shown in FIG.
  • a conductive seed layer can be formed on the inner wall of the second blind hole 152 and the side of the plastic layer 13 away from the conductive layer 101 (not shown), and then use electroplated copper to fill the second blind hole 152 to form the second conductive part 162 in the second blind hole 152, and form the metal layer 14 on the side of the plastic layer 13 away from the conductive layer 101, where,
  • the second conductive part 162 connects the pad 121 on the side of the chip 12 away from the conductive layer 101 with the metal layer 14.
  • the metal layer 14 is connected to the first conductive part 161.
  • the first conductive part 161 connects the conductive layer 101 with the metal layer 14. Pass.
  • S1308 Make a first conductive line on the metal layer, and make a second conductive line on the conductive layer.
  • steps S1307 to S1308 in this embodiment are basically the same as steps S307 to S308 in the above embodiment.
  • Figures 14g to 14h are basically the same as Figures 4g to 4h.
  • the plastic layer covers the first conductive part; the above step S1224 may specifically include: polishing the plastic layer and the first conductive part until the chip is away from the conductive layer.
  • the pad on one side of the chip is exposed outside the plastic layer, and the surface of the pad on the side of the chip away from the conductive layer is flush with the surface of the first conductive part on the side away from the conductive layer; in the A conductive seed layer is made on the surface of the side of the plastic layer away from the conductive layer and electroplated to form a metal layer on the side of the plastic layer away from the conductive layer; wherein the first conductive part is The conductive layer is electrically connected to the metal layer, and the pad on the side of the chip away from the conductive layer is connected to the metal layer; the carrier is peeled off from the substrate to expose the conductive layer away from the The surface on the rough side.
  • the method of manufacturing the package further includes: forming a first conductive line on the metal layer, and forming a second conductive line on the conductive layer.
  • FIG. 15 is a flow diagram of the seventh embodiment of the manufacturing method of the printed circuit board of the present application
  • FIG. 16 is an implementation corresponding to steps S1501-S1508 in FIG. 15 Schematic diagram of the production process structure of each step.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • S1501 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • S1502 Create a first conductive part on the rough surface side of the conductive layer.
  • steps S1501 to S1504 in this embodiment are basically the same as steps S1301 to S1304 in the above embodiment, and Figures 16a to 16d are correspondingly the same as Figures 14a to 14d.
  • S1505 Polish the plastic layer and the first conductive part until the pad on the side of the chip away from the conductive layer is exposed outside the plastic layer, and the chip is on the side away from the conductive layer.
  • the surface of the soldering pad is flush with the surface of the first conductive part on the side away from the conductive layer.
  • the plastic layer 13 and the first conductive part 161 are polished until the pad 121 of the chip 12 on the side away from the conductive layer 101 is exposed outside the plastic layer 13 .
  • the chip 12 The surface of the pad 121 on the side away from the conductive layer 101 is flush with the surface on the side of the first conductive part 161 away from the conductive layer 101 , and the top of the first conductive part 161 exposes the plastic sealing layer 13 .
  • S1506 Make a conductive seed layer on the surface of the side of the plastic layer away from the conductive layer, and perform electroplating to form a metal layer on the side of the plastic layer away from the conductive layer; wherein, The first conductive part conducts the conductive layer and the metal layer, and the pad on the side of the chip away from the conductive layer is connected to the metal layer.
  • a conductive seed layer (not shown) is directly formed on the surface of the plastic sealing layer 13 away from the conductive layer 101 , and electroplating is performed to form a conductive seed layer on the surface of the plastic sealing layer 13 .
  • a metal layer 14 is formed on the side away from the conductive layer 101 .
  • the first conductive part 161 connects the conductive layer 101 to the metal layer 14 .
  • the pad 121 on the side of the chip 12 away from the conductive layer 101 is directly connected to the metal layer 14 .
  • S1508 Make a first conductive line on the metal layer, and make a second conductive line on the conductive layer.
  • steps S1507 to S1508 in this embodiment are basically the same as steps S307 to S308 in the above embodiment.
  • Figures 16g to 16h are correspondingly the same as Figures 14g to 14h.
  • the plastic layer covers the first conductive part; the above step S1224 may specifically include: polishing the plastic layer and the first conductive part until the chip is away from the conductive layer.
  • the pad on one side of the chip is exposed outside the plastic layer, and the surface of the pad on the side of the chip away from the conductive layer is flush with the surface of the first conductive part on the side away from the conductive layer; in the A conductive seed layer is made on the surface of the side of the plastic layer away from the conductive layer, and pattern plating is performed to form a metal layer as a first conductive line on the side of the plastic layer away from the conductive layer; wherein, The metal layer is respectively connected to the first conductive part and the pad on the side of the chip away from the conductive layer, and the first conductive part conducts the conductive layer and the metal layer;
  • the carrier is peeled off from the substrate to expose the surface of the conductive layer away from the rough surface; a second conductive circuit is produced on the conductive layer.
  • FIG. 17 is a flow diagram of the eighth embodiment of the manufacturing method of a printed circuit board of the present application
  • FIG. 18 is an implementation corresponding to steps S1701-S1708 in FIG. 17 Schematic diagram of the production process structure of each step.
  • the manufacturing method of the package in this embodiment includes the following steps:
  • S1701 Obtain a substrate, which includes a carrier and a conductive layer located on one side of the carrier.
  • the surface of the conductive layer on the side away from the carrier is a rough surface.
  • S1702 Create a first conductive part on the rough surface side of the conductive layer.
  • S1705 Polish the plastic layer and the first conductive part until the pad on the side of the chip away from the conductive layer is exposed outside the plastic layer, and the chip is on the side away from the conductive layer.
  • the surface of the soldering pad is flush with the surface of the first conductive part on the side away from the conductive layer.
  • steps S1701 to S1705 in this embodiment are basically the same as steps S1501 to S1505 in the above embodiment, and Figures 18a to 18e are correspondingly the same as Figures 16a to 16e.
  • S1706 Make a conductive seed layer on the surface of the plastic layer far away from the conductive layer, and perform pattern plating to form a first conductive line on the side of the plastic layer far away from the conductive layer.
  • Metal layer wherein, the metal layer is connected to the first conductive part and the pad on the side of the chip away from the conductive layer, and the first conductive part makes the conductive layer conductive to the metal layer. Pass.
  • a conductive seed layer is directly formed on the surface of the side of the plastic sealing layer 13 away from the conductive layer 101, and then dry film is applied, exposed, developed, pattern plating, and By removing the film and quickly etching, the metal layer 14 is formed on the side of the plastic layer 13 away from the conductive layer 101. At this time, the metal layer 14 is the first conductive line, and the first conductive portion 161 makes the conductive layer 101 and the metal layer 14 conductive. Through, the pad 121 on the side of the chip 12 away from the conductive layer 101 is directly connected to the metal layer 14 .
  • steps S1707 to S1708 in this embodiment are basically the same as steps S1507 to S1508 in the above embodiment.
  • Figures 18g to 18h are basically the same as Figures 16g to 16h.
  • the manufacturing of a three-dimensional packaging structure of high-definition conductive circuits is achieved.
  • the package includes: a conductive layer 101, the surface on one side of the conductive layer 101 is a rough surface; a chip 12, the chip 12 is mounted on the rough surface of the conductive layer 101 through the attachment layer 11 ; Conductive component 16, the conductive component 16 is disposed on the rough surface side of the conductive layer 101, wherein the conductive component 16 connects the pad 121 of the chip 12 to the conductive layer 101.
  • the conductive layer 101 is etched from 1 to 12 ⁇ m copper foil, and the height difference of the rough surface of the conductive layer 101 within an area of 0.1 square millimeters is greater than 1 micron or greater than one-third of the thickness of the conductive layer 101 .
  • the conductive component 16 includes a metal layer 14, a first conductive circuit (not shown) is formed on the metal layer 14, and a second conductive circuit (not shown) is formed on the conductive layer 101.
  • the package body includes a plastic sealing layer 13.
  • the plastic sealing layer 13 is disposed on the rough surface side of the conductive layer 101 and covers the chip 12.
  • the height of the surface of the plastic sealing layer 13 away from the conductive layer 101 is greater than the height of the surface of the plastic sealing layer 13 away from the conductive layer 101.
  • the conductive component 16 specifically includes a first conductive part 161, a second conductive part 162 and a metal layer 14.
  • the metal layer 14 is located on the side of the plastic sealing layer 13 away from the conductive layer 101.
  • the first conductive part 161 is located at the first preset position of the plastic sealing layer 13
  • the second conductive part 162 is located at the second preset position of the plastic sealing layer 13 .
  • the first conductive part 161 conducts the conductive layer 101 and the metal layer 14
  • the second conductive part 162 connects the pad 121 on the side of the chip 12 away from the conductive layer 101 with the metal layer 14 .
  • the chip 12 is also provided with a pad 121 on the side close to the conductive layer 101.
  • the conductive component 16 also includes a third conductive part 163.
  • the second conductive part 162 is located on the third side of the chip 12 close to the conductive layer 101.
  • the third conductive portion 163 connects the pad 121 on the side of the chip 12 close to the conductive layer 101 with the conductive layer 101 .
  • the surface of the metal layer 14 close to the conductive layer 101 is a rough surface.
  • the package includes a plastic sealing layer 13.
  • the plastic sealing layer 13 is disposed on the rough surface side of the conductive layer 101.
  • the height of the surface of the plastic sealing layer 13 away from the conductive layer 101 is the same as the height of the surface away from the conductive layer 12.
  • the height of the pad 121 on the layer 101 side is flush.
  • the conductive component 16 includes a first conductive part 161 and a metal layer 14.
  • the metal layer 14 is located on a side of the plastic layer 13 away from the conductive layer 101.
  • the first conductive part 161 is located at a first preset position of the plastic layer 13.
  • the first The conductive part 161 conducts the conductive layer 101 and the metal layer 14.
  • the second conductive part 162 conducts the pad 121 on the side of the chip 12 away from the conductive layer 101 and the metal layer 14.
  • the pad on the side of the chip 12 away from the conductive layer 101 is connected.
  • 121 is connected to metal layer 14.
  • FIG. 19 is a schematic structural diagram of an embodiment of the package of the present application.
  • the package further includes at least one metal outer layer 17 and/or at least one conductive outer layer 18; at least one metal outer layer 17 is spaced apart from the side of the metal layer 14 away from the conductive layer 101, at least A metal outer layer 17 is electrically connected to the metal layer 14 , and at least a third conductive circuit (not shown) is formed on at least one metal outer layer 17 ; at least one conductive outer layer 18 is spaced apart from the conductive layer 101 away from the metal layer 14 On one side, at least one conductive outer layer 18 is electrically connected to the conductive layer 101, and a fourth conductive circuit (not shown) is formed on at least one conductive outer layer 18.
  • the surface of the conductive layer 101 close to the chip 12 is provided as a rough surface, so that when the chip 12 is mounted on the rough surface side of the conductive layer 101 using the attachment layer 11, the attachment layer 11 solidifies.
  • the rough surface and the adhesion layer 11 can form a bite structure to enhance the bonding force; further, after the chip 12 is molded, the mold seal layer 13 can also form a bite structure with the rough surface of the conductive layer 101 to enhance the bonding force between the mold seal layer 13 and the conductive layer 101 .
  • the bonding force of the layer 101 in addition, when the surface of the metal layer 14 close to the conductive layer 101 is also a rough surface, the bonding force between the metal layer 14 and the plastic sealing layer 13 can be ensured.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne un corps d'emballage et son procédé de fabrication. Le corps d'emballage comprend : une couche électroconductrice, une surface d'un côté de la couche électroconductrice étant une surface rugueuse ; une puce, la puce étant fixée à la surface rugueuse de la couche électroconductrice au moyen d'une couche de fixation ; et un ensemble électroconducteur, l'ensemble électroconducteur étant agencé sur le côté de la surface rugueuse de la couche électroconductrice, et l'ensemble électroconducteur permettant à une pastille de la puce d'être connectée à la couche électroconductrice. De cette manière, la puce dans la présente invention est fixée à la surface rugueuse de la couche électroconductrice au moyen de la couche de fixation, de telle sorte que, pendant la solidification de la couche de fixation, la surface rugueuse et la couche de fixation peuvent former une structure en prise pour améliorer une force de liaison.
PCT/CN2022/135574 2022-06-30 2022-11-30 Corps d'emballage et son procédé de fabrication WO2024001036A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210770218.XA CN115274601A (zh) 2022-06-30 2022-06-30 一种封装体及其制作方法
CN202210770218.X 2022-06-30

Publications (1)

Publication Number Publication Date
WO2024001036A1 true WO2024001036A1 (fr) 2024-01-04

Family

ID=83763596

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/135574 WO2024001036A1 (fr) 2022-06-30 2022-11-30 Corps d'emballage et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN115274601A (fr)
WO (1) WO2024001036A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274601A (zh) * 2022-06-30 2022-11-01 深南电路股份有限公司 一种封装体及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101480116A (zh) * 2006-04-27 2009-07-08 日本电气株式会社 电路基板、电子器件配置及用于电路基板的制造工艺
US20100103634A1 (en) * 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
CN104684254A (zh) * 2013-11-27 2015-06-03 Tdk株式会社 Ic内置基板及其制造方法
CN115274601A (zh) * 2022-06-30 2022-11-01 深南电路股份有限公司 一种封装体及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101480116A (zh) * 2006-04-27 2009-07-08 日本电气株式会社 电路基板、电子器件配置及用于电路基板的制造工艺
US20100103634A1 (en) * 2007-03-30 2010-04-29 Takuo Funaya Functional-device-embedded circuit board, method for manufacturing the same, and electronic equipment
CN104684254A (zh) * 2013-11-27 2015-06-03 Tdk株式会社 Ic内置基板及其制造方法
CN115274601A (zh) * 2022-06-30 2022-11-01 深南电路股份有限公司 一种封装体及其制作方法

Also Published As

Publication number Publication date
CN115274601A (zh) 2022-11-01

Similar Documents

Publication Publication Date Title
US6324067B1 (en) Printed wiring board and assembly of the same
TWI640234B (zh) 具厚銅線路的電路板及其製作方法
WO2024001036A1 (fr) Corps d'emballage et son procédé de fabrication
TW201349957A (zh) 多層電路板及其製作方法
JP4143609B2 (ja) 配線基板の製造方法
JP2017220502A (ja) インダクタ部品、インダクタ部品の製造方法
JP2008016817A (ja) 埋立パターン基板及びその製造方法
JP2002076578A (ja) プリント配線板及びその製造方法
JP2003031950A (ja) 多層配線基板及びその製造方法
JP2000058986A (ja) 配線基板およびその製造方法
TWI633821B (zh) 軟性電路板及其製作方法
JP2009147080A (ja) 半導体装置用パッケージおよびその製造方法
JPS60216573A (ja) フレキシブル印刷配線板の製造方法
JP3624512B2 (ja) 電子部品搭載用基板の製造方法
JPWO2020203724A1 (ja) 樹脂多層基板、および樹脂多層基板の製造方法
JPH0255958B2 (fr)
JP2827472B2 (ja) スルーホールプリント配線基板の製造方法
CN209861253U (zh) 多层柔性线路板内层及外层屏蔽的叠层结构
JPH02266586A (ja) フレキシブルプリント配線板及びその製造方法
JP4106592B2 (ja) 配線基板及びその製造方法
JP2868779B2 (ja) Ｔａｂ用テープ
JP2001144445A (ja) 多層プリント配線板の製造方法
JPS6372192A (ja) 回路板の製造方法
JPH0770834B2 (ja) 内層パターン部が露出したプリント基板、およびその製造方法
JP2007067276A (ja) プリント配線板とその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22949115

Country of ref document: EP

Kind code of ref document: A1