WO2024000431A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2024000431A1
WO2024000431A1 PCT/CN2022/102894 CN2022102894W WO2024000431A1 WO 2024000431 A1 WO2024000431 A1 WO 2024000431A1 CN 2022102894 W CN2022102894 W CN 2022102894W WO 2024000431 A1 WO2024000431 A1 WO 2024000431A1
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region
channel layer
electrode
layer
semiconductor device
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PCT/CN2022/102894
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English (en)
Chinese (zh)
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黎子兰
王乐知
张树昕
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广东致能科技有限公司
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Priority to PCT/CN2022/102894 priority Critical patent/WO2024000431A1/fr
Publication of WO2024000431A1 publication Critical patent/WO2024000431A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • the present disclosure relates to a semiconductor device, and in particular to a normally-off gate structure semiconductor.
  • Group III nitride semiconductor is an important new semiconductor material, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Due to its direct band gap, wide bandgap, high breakdown electric field strength and other advantages, Group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics, radio frequency devices and other fields.
  • HEMT high electron mobility transistor
  • the gate electrode controls the switching of the device.
  • 2DEG near the interface between GaN and AlGaN, and only by applying a larger negative voltage to the gate electrode can the current be turned off.
  • the threshold voltage of HEMT is negative and it is a normally-on device. In many applications, this poses a significant security risk.
  • gate leakage current easily occurs between the gate electrode and 2DEG. Gate leakage current is very detrimental to many applications and can easily lead to reliability issues.
  • a common way to reduce gate leakage current is to add an insulating layer between the gate electrode and the AlGaN barrier. This can significantly reduce leakage current, but it will cause the threshold voltage to go in a more negative direction.
  • One way to increase the threshold voltage is to use P-type GaN or P-type AlGaN. Since P-type GaN has a high work function, the threshold voltage of the device will be significantly increased. Panasonic, TSMC and other companies have demonstrated the use of this method to achieve normally-off devices.
  • the present disclosure proposes a semiconductor device, including: a barrier layer; a channel layer adjacent to the barrier layer, wherein the channel layer is close to the barrier layer.
  • a two-dimensional carrier gas is formed at the interface between the barrier layer and the channel layer; a first electrode, located above the barrier layer, is configured to control the connection or disconnection of the two-dimensional carrier gas.
  • the channel layer includes a first region in a corresponding range below the first electrode, and the carrier acceptor concentration of the first region is such that in the first region below the first electrode
  • the two-dimensional carrier gas is depleted; and a second electrode is located above a second region in the channel layer and is electrically connected to the two-dimensional carrier gas, the second region is located on the first One side of the region is in contact with the barrier layer, and the second region is doped with a carrier donor type.
  • a body electrode electrically connected to the first region of the channel layer through one or more connection regions in the channel layer; wherein the body electrode is located in the channel The upper surface or sides of the layer.
  • connection areas are located at least partially beneath the second area.
  • the second region is ion implanted.
  • the barrier layer above the second region is ion implanted.
  • a portion of the gate insulating layer above the first region is ion implanted.
  • the first electrode serves as a partial mask in the ion implantation.
  • connection regions include a first connection region below the barrier layer, and the carrier acceptor concentration of the first connection region is smaller than the carrier acceptor concentration of the first region. Main concentration.
  • connection regions include a second connection region below the barrier layer
  • the body electrode is in contact with the second connection region, and the carrier acceptor concentration of the second connection region Greater than or equal to the carrier acceptor concentration of the first region.
  • the channel layer includes a third region on the opposite side of the first region and the second region, wherein the third region is not intentionally doped or carrier donor doped.
  • a fourth region is included between the first region and the third region in the channel layer, and the carrier acceptor concentration of the fourth region is greater than the carrier acceptor concentration of the third region.
  • the sub-acceptor concentration is smaller than the carrier acceptor concentration of the first region.
  • a third electrode is further included, which is located on a position corresponding to the third region of the channel.
  • the channel layer further includes a surrounding area surrounding the first electrode, and the carrier acceptor concentration in the surrounding area causes the two-dimensional carrier gas to be depleted in the surrounding area.
  • a nucleation layer between the substrate and the third region is further included.
  • a sapphire or silicon substrate or a template including sapphire or silicon is further included.
  • the present application further includes a method for manufacturing a semiconductor device, including: forming a portion of the channel layer through epitaxial growth; forming a plurality of other portions of the channel layer through lateral epitaxial growth based on the epitaxial growth portion of the channel layer.
  • the plurality of other parts at least include a first region of the channel layer and one or more connection regions of the channel layer; a barrier layer is formed on the channel layer, wherein in the channel forming a two-dimensional carrier gas in the channel layer near the interface between the barrier layer and the channel layer; and forming a first electrode located above and covering the barrier layer and configured to control the The connection or disconnection of the two-dimensional carrier gas; wherein the first electrode covers the position corresponding to the first region of the channel, and the carrier acceptor concentration of the first region makes the third The two-dimensional carrier gas in the first region of an electrode is depleted.
  • the method further includes: removing a plurality of vertically overlapping layers on the channel layer.
  • the method further includes: forming a second region doped with a carrier donor type by ion implantation, wherein the second region is located on one side of the first region and in contact with the barrier layer.
  • the ion implantation is performed before forming the barrier layer.
  • the ion implantation is performed after forming the barrier layer.
  • the ion implantation is performed after forming the first electrode and using the first electrode as a partial mask.
  • the method further includes: forming a body electrode located on a side of the channel layer and electrically connected to the first region of the channel layer.
  • the method further includes: removing part of the barrier layer connected to the body electrode.
  • the one or more connection regions include a first connection region, and the carrier acceptor concentration of the first connection region is less than the carrier acceptor concentration of the first region.
  • connection regions include a second connection region
  • the body electrode is in contact with the second connection region
  • the carrier acceptor concentration of the second connection region is greater than or equal to the The carrier acceptor concentration in the second region.
  • the portion of the channel layer formed by vertical epitaxial growth includes a third region, wherein the third region is undoped or unintentionally doped.
  • the channel layer formed by lateral epitaxial growth includes a fourth region between the first region and the third region, and the carrier acceptor concentration of the first region is greater than that of the third region. Carrier acceptor concentration in four regions.
  • the method further includes: forming a second electrode located on a position corresponding to the second region of the channel.
  • the method further includes: forming a third electrode located on a position corresponding to the third region of the channel.
  • this application also proposes a semiconductor device, including: a barrier layer; a channel layer adjacent to the barrier layer, wherein the channel layer is close to the barrier layer and the A two-dimensional carrier gas is formed at the interface between the channel layers; a first electrode, located above the barrier layer, is configured to control the connection or disconnection of the two-dimensional carrier gas; wherein the The channel layer includes a first region in a corresponding range below the first electrode, and the carrier acceptor concentration of the first region is such that two-dimensional carriers in the first region below the first electrode gas depletion; and a body electrode located in the channel layer or on one side of the channel layer and configured to be electrically connected to the first region of the channel layer.
  • the body electrode and the first region of the channel layer are electrically connected through one or more connection regions in the channel layer.
  • an ohmic contact is formed between the body electrode and the one or more connection regions.
  • the application also includes: a manufacturing method of a semiconductor device, including: forming a part of the channel layer through vertical epitaxial growth; forming a plurality of other parts of the channel layer based on the part of the channel layer through lateral epitaxial growth. portion, the plurality of other portions at least include a first region of the channel layer and one or more connection regions of the channel layer; remove a plurality of vertically overlapping layers on the channel layer; A barrier layer is formed on the channel layer, wherein a two-dimensional carrier gas is formed in the channel layer near the interface between the barrier layer and the channel layer; a first electrode is formed, Located above and covering the barrier layer, and configured to control the connection or disconnection of the two-dimensional carrier gas; wherein the first electrode covers a position corresponding to the first region of the channel, The carrier acceptor concentration in the first region causes the two-dimensional carrier gas in the first region of the first electrode to be depleted; and forming a body electrode located in the channel layer or in the channel On one side of the layer, the body electrode
  • the method further includes: forming a second electrode located at a position corresponding to the connection area of the channel.
  • the method further includes: forming a third electrode located at a position corresponding to the fourth region of the channel.
  • Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure
  • 2A-2J are flow charts of a semiconductor device manufacturing method according to one embodiment of the present disclosure.
  • 3A-3C are schematic diagrams of ion implantation steps in a semiconductor device manufacturing method according to embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a semiconductor device according to another embodiment of the present disclosure.
  • spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature(s) as illustrated in the drawings.
  • the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present.
  • This disclosure proposes a technical solution that can simultaneously solve the threshold voltage and gate leakage, that is, making a P-type buried layer under the gate channel. Since the P-type buried layer is close to the channel, it is very effective in depleting the two-dimensional electron gas. On the other hand, in order to avoid the depletion of the two-dimensional electron gas in the area other than the gate electrode, which will lead to the turn-off of the device or a substantial increase in the on-resistance and the stability of the threshold voltage, the P-type buried layer is electrically connected to the electrode and does not and then in a floating state; the source or drain regions can be doped to improve conductivity.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure.
  • this embodiment is a normally-off gate structure semiconductor device, including a substrate 101, channel layers 103, 104, 106, 108, 109 and 131, 133, a barrier layer 105, and a gate electrode 111 and 113, source electrodes 112 and 116, and drain electrode 114.
  • a two-dimensional carrier gas 2DEG 107 is formed in the channel layer near the interface between the channel layer and the barrier layer 105.
  • the material of the channel layer is GaN or doped GaNg
  • the barrier layer 105 is an AlGaN, InAlGaN, InAlN layer, or the like.
  • Gate electrodes 111 and 113 are located above the barrier layer 105 and are configured to control the 2DEG 107 to be turned on or off. In some embodiments, gate electrodes 111 and 113 form Schottky contacts with barrier layer 105 to reduce off-state leakage current. In some embodiments, a gate insulation layer is included between the gate electrodes 111 and 113 and the barrier layer 105 .
  • the material of the substrate 101 can be selected according to actual needs.
  • the specific form of the substrate 101 is not limited in this embodiment.
  • the material of the substrate 101 may be sapphire, ZnO, SiC, AIN, GaAs, LiAlO, GaAlLiO, GaN, or Si, etc.
  • the substrate 101 may be a heterogeneous substrate, such as a sapphire or silicon substrate.
  • the substrate may be replaced with a template. Templates include substrates of sapphire, silicon, or other materials. Nitride semiconductor materials can be grown on them.
  • insulating layers 121 and 123 are included on the substrate 101 . They isolate the semiconductor device from the substrate to reduce substrate influence.
  • Nucleation layer 102 is included between insulating layers 121 and 123.
  • the material of nucleation layer 102 may be AlN. The nucleation layer 102 can reduce the impact of lattice differences, reduce the impact of differences in lattice constants and thermal expansion coefficients between the substrate and the channel layer, and effectively avoid cracks in the nitride epitaxial layer. Reduce defects in the crystal lattice.
  • the semiconductor further includes a buffer layer.
  • the buffer layer is formed on the nucleation layer on the surface of the substrate, or can be formed directly on the substrate.
  • the channel layer is formed on the buffer layer.
  • the material of the buffer layer may be one or more of AlN, GaN, AlGaN, InGaN, AlInN and AlGaInN.
  • the channel layer includes a first region 108 .
  • the first region 108 of the channel layer is located in a corresponding range below the gate electrode 111, that is, the gate electrode is within the projection range of the channel layer.
  • the gate electrode 111 is above the first region 108 .
  • the carrier acceptor concentration in the first region 108 causes the two-dimensional carrier gas 107 in the first region 108 below the first electrode 111 to be depleted.
  • the two-dimensional carrier gas is 2DEG
  • the first region 108 is strongly P-type doped, so that when no voltage is applied to the gate electrode 111, the 2DEG in the first region 108 is depleted and the device is turned off. state.
  • the semiconductor device of the present disclosure becomes a normally-off type device.
  • the doping concentration of the strongly P-type doped first region 108 is, for example, 1E18-5E19/cm3.
  • a gate insulation layer is included between the first electrode 111 and the barrier layer above the first region 108 .
  • the length of the gate insulating layer is comparable to the length of the gate electrode 111 .
  • Figure 1 shows the structure of two transistors with a shared drain.
  • a first region 109 is also included below the gate electrode 113, which is also strongly P-type doped, and can deplete the 2DEG 107 in the first region 109 when no voltage is applied to the gate electrode 113. Put the device in the off state.
  • only one side of the transistor structure may be included.
  • the channel layer of this embodiment further includes: a second region 131 and a second region 133 .
  • Source electrodes 111 and 113 (which can also be drain electrodes) are located on the second regions 131 and 133 in the channel layer and are electrically connected to the 2DEG 107.
  • the second regions 131 and 133 provide main type doping for carriers, that is, N-type doping.
  • the second regions 131 and 133 are located on one side of the first regions 108 and 109 and are in direct contact with the barrier layer 105 . In this way, 2DEG 107 will be formed in the second area.
  • N-type doping in the second region can increase the 2DEG concentration and conductivity, improve the conductivity of this region, and is conducive to obtaining higher-performance semiconductor devices.
  • second region 131 and second region 133 are formed by ion implantation.
  • elements such as Si are doped in the channel layer through ion implantation.
  • Other methods in the art to form the N-type doped second region in the channel layer can also be applied to this disclosure.
  • the channel layer includes a third region 103 located on the opposite side of the first region 108 and the second region 131 in the channel layer. (As shown in the figure, the area on the opposite side of the first area 109 and the second area 133 is also the third area 103). At least part of the third region 103 is located above the nucleation layer 102 .
  • the material of the third region 103 may be undoped or unintentionally doped.
  • the third region 103 may be N-type doped.
  • the drain electrode (which may also be the source electrode) 114 is disposed above the third region and is electrically connected to the 2DEG 107. In some embodiments, the distance between the drain electrode and the gate electrode is farther than the distance between the source electrode and the gate electrode, so as to help improve the withstand voltage of the device.
  • a fourth area 137 is included between the first area 108 and the third area 103 .
  • the fourth region 137 is also P-type doped, and its carrier acceptor concentration is greater than the carrier acceptor concentration of the third region 103 and less than the carrier acceptor concentration of the strongly P-type doped first region 108 concentration.
  • fourth region 137 is located at least partially beneath gate electrode 111 . The introduction of the fourth region can change the electric field distribution under the gate electrode, reduce the problem of excessive local electric field, and improve the withstand voltage of the device.
  • all or part of the third region 103 adjacent the fourth region 137 is N-type doped.
  • the N-type doped portion of the third region 103 is combined with the P-type doped portion of the fourth region 137 to form a low-doped P-N junction, thereby constructing an internal PN diode.
  • the existence of such a PN diode can enhance the isolation between the gate electrode and the drain electrode, reduce leakage current, and improve device performance.
  • the semiconductor device further includes a body electrode 115 .
  • the strongly P-type doped first region 108 is electrically connected to the body electrode 115, thereby changing from a floating region to a voltage-controllable active region.
  • the off or on resistance and threshold voltage can also remain stable, and the stability of the device is improved.
  • the first region 108 of the channel layer is electrically connected by a first connection region 104 in the channel layer.
  • the first connection area 104 is located outside the first area 108 .
  • first region 108 is strongly P-type doped, while first connection region 104 may be weakly P-type doped.
  • the first connection area 104 is directly connected to the first area 108 .
  • An exemplary doping concentration of the first connection region 104 does not exceed 5E18/cm3, such as 1E18/cm3, 5E17cm3, etc.
  • the strong P-type doping in the first region 108 and the weak P-type doping in the first connection region 104 are opposite and related to
  • the two-dimensional carrier gas 107 formed between the channel layer 103 and the barrier layer 105 is related.
  • concentration of the intrinsic two-dimensional carrier gas 107 at the interface between the channel layer 103 and the barrier layer 105 is higher, the doping concentration corresponding to the strong P-type doping is also higher, and the doping concentration corresponding to the weak P-type doping is also higher.
  • the impurity concentration can also be relatively higher than usual.
  • the doping concentration of strong P-type doping may be, for example, more than 2 times the doping concentration of weak P-type doping.
  • the first region 108 has a lower Fermi level, which can deplete the two-dimensional carrier gas 107 above it, thereby causing the device to have a higher threshold voltage and a normally-off state of the device.
  • the arrangement of the first region 108 such as its thickness, length, width, and P-type doping concentration, device parameters are set to satisfy the shutdown by depleting more than 95% of the two-dimensional charge carriers above it. 2DEG.
  • the device parameters of the first region 108 can be set according to device threshold voltage and other requirements.
  • the first connection region 104 has a lower P-type doping concentration.
  • device parameters such as thickness, length, width, and P-type doping concentration of the first connection region 104 are set so that when in direct contact with the barrier layer, it can only deplete less than 80% of the area above it. 2DEG to protect the conductivity of the first connection area 104.
  • the first connection region 104 is at least partially located below the second region 131 and is at least partially not in contact with the barrier layer 105 . Due to the weak P-type doping of the first connection region, there is a certain depletion effect on 2DEG. Although the doping concentration used in this area still ensures the existence of 2DEG in this area, it will have an adverse effect on the on-resistance. Adding a second region such as ion implantation can completely avoid this, and due to the N-type doping of the second region, not only will the 2DEG not be depleted, but the concentration will increase. As a result, the on-resistance of the device will be further reduced, and the device performance will be greatly improved.
  • the body electrode 115 is located on the upper surface or side surface of the channel layer 103 .
  • the body electrode 115 is located on the side of the first connection region 104, which can significantly increase the point contact area between the body electrode 115 and the weakly P-type doped first connection region 104, and can significantly reduce the contact resistance.
  • being disposed on the side of the first connection region 104 allows the body electrode 115 to occupy only a smaller chip area while still ensuring low contact resistance between the body electrode and the connection region.
  • body electrode 115 may be connected to source electrode 112 . Alternatively, the body electrode 115 may be independently controlled.
  • the body electrode 115 controls the potential of the first region 108 via the first connection region 104 .
  • the sidewalls of the barrier layer may be removed before forming the body electrode.
  • the device of this embodiment also includes a body electrode 117, which is electrically connected to the first region 109 through the connection region 106, so that the potential of the first region 109 can be controlled.
  • a second connection region 151 is further included between the body electrode 115 and the first connection region 104 .
  • the second connection region 151 is also P-type doped to ensure the electrical connection between the body electrode 115 and the first region 108 .
  • the carrier acceptor doping concentration of the second connection region 151 is greater than or equal to the carrier acceptor doping concentration of the first region 104 .
  • the second connection region 151 with a higher P-type doping concentration improves the conductivity of the channel layer in contact with the body electrode 115 and is more conducive to forming an ohmic contact between the body electrode and the channel layer.
  • FIG. 2A-2I illustrate a manufacturing method of a semiconductor device according to an embodiment of the present invention. As shown in the figure, the manufacturing method of the semiconductor device of this embodiment includes the following steps:
  • Step 2001 Form an insulating layer on the substrate, as shown in Figure 2A.
  • the first insulating layer 220 is deposited on the first surface of the substrate 201 .
  • the substrate may be a sapphire substrate or a silicon substrate, and the insulating layer may be a silicon nitride layer formed by a MOCVD process.
  • Step 2002 Pattern the insulating layer and remove the insulating layer in some areas, as shown in Figure 2B.
  • the first insulating layer 220 covers the entire surface of the substrate 201 . At least a portion of the first insulating layer 220 is removed, and the insulating layers 221 and 223 and openings are formed to expose a portion of the substrate 201 .
  • Step 2003 Form a nucleation layer in the opening formed by removing the insulating layer, as shown in Figure 2C.
  • Step 2004 Form a part of the channel layer through epitaxial growth, as shown in Figure 2D.
  • the initial part 203 of the channel layer is formed by epitaxial growth. This part can form the third area or part of the third area in the future.
  • the growth method of the channel layer is not particularly limited, and vertical epitaxial growth, hydride vapor phase epitaxy (HVPE), etc. can be used.
  • the initial portion 203 of the channel layer may be an undoped nitride semiconductor layer or an unintentionally doped nitride semiconductor layer.
  • the initial portion 203 of the channel layer is an N-type nitride-doped semiconductor layer.
  • the position and/or size of the initial portion 203 can be controlled by adjusting the epitaxial growth process or conditions one or more times.
  • Step 2005 Form multiple portions of the channel layer through lateral epitaxial growth, as shown in Figures 2E and 2F.
  • a strongly P-type doped portion 2088 is formed through a lateral growth process based on the initial portion 203 of the channel layer.
  • the doping concentration range of the strongly P-type doped part is exemplarily between 1E18/cm 3 -5E19/cm 3 .
  • the strongly P-type doped portion 2088 ranges from a length of about 3.5 microns and a thickness of about 0.79 microns along the two-dimensional carrier charge flow direction.
  • a first weak P-type doped portion 2044 is grown by lateral epitaxial growth based on the strongly P-type doped portion 2088 .
  • other portions of the channel layer may also be formed by lateral epitaxial growth.
  • a second weak P-type doped portion may be formed by lateral epitaxial growth.
  • a third weak P-type doped portion is formed through lateral epitaxial growth; and the doping concentration of the carrier acceptor in the third weak P-type doped portion is Greater than the doping concentration of the carrier acceptor of the first weak P-type doped portion 2044 .
  • multiple portions of the channel layer with different doping types and doping concentrations or undoped or unintentionally doped can be formed by lateral epitaxial growth, thereby achieving a complex structure of the channel layer; and, As observed, symmetrical channel layer structures can be formed on both sides at the same time through lateral epitaxial growth as needed, reducing process costs.
  • Step 2006 Remove multiple vertically overlapping layers on the channel layer, as shown in Figure 2G. Through etching or other methods, remove multiple overlapping layers on the channel layer, remove the horizontally extending portions formed during the lateral epitaxial growth, leaving only the portions of the channel layer arranged side by side in the vertical direction, and expose the first areas 208 and 209, connecting areas 204 and 206, and the upper surface of the third area 203.
  • Step 2007 Form an N-type doped second region in the connection region by ion implantation, as shown in Figure 2H.
  • a mask layer 232 is formed over the first regions 208 and 209 and the third region 203, and the connection regions 204 and 206 are exposed.
  • N-type doped ions such as Si are implanted into semiconductor devices by ion implantation. Due to the presence of the mask layer 232, the N-type doped second regions 231 and 233 are formed only in the connection regions 204 and 206. For example, the thickness of the N-type doped second region is 30-200nm to increase the concentration of 2DEG 107. Then, the mask layer 232 is removed, exposing the upper surfaces of the first regions 208 and 209, the second regions 231 and 233, and the third region 203.
  • Step 2008 Form a barrier layer on the channel layer, as shown in Figure 2I.
  • the material of the barrier layer 205 is AlGaN, InAlGaN, InAlN layer, etc.
  • 2DEG 207 is formed in the channel layer near the interface between the barrier layer and the channel layer. Since the first regions 208 and 209 are strongly P-type doped, the 2DEG 207 is depleted in the first regions 208 and 209. Therefore, the semiconductor device becomes a normally-off type device.
  • Step 2009 Form the source electrode, gate electrode and drain electrode, as shown in Figure 2J.
  • Gate electrodes 211 and 213 are formed above the first regions 208 and 209, which are located above the barrier layer and configured to control the connection or disconnection of the two-dimensional carrier gas.
  • Source electrodes 212 and 216 are formed over the second regions 231 and 233.
  • Drain electrode 214 is formed over third region 203 .
  • the method of this embodiment further includes: removing the barrier layer extending along the side of the channel layer, and forming body electrodes 215 and 217 in ohmic contact with the connection region on the side of the channel layer. Through connection regions 204 and 206, body electrodes 215 and 217 are electrically connected to the first regions 208 and 209 of the channel layer, respectively.
  • FIGS. 3A-3C are schematic diagrams of ion implantation steps in a semiconductor device manufacturing method according to embodiments of the present disclosure.
  • the ion implantation step may be performed after forming the barrier layer.
  • the barrier layer above them has also undergone ion implantation to become N-type doped regions 234 and 235.
  • the N-type doped barrier layer can provide more carriers, which is beneficial to improving the performance of the device.
  • the ion implantation step can be performed after forming the gate electrode and using the gate electrode as a partial mask, thereby realizing the self-alignment function and reducing process difficulty.
  • FIG. 4 is a schematic structural diagram of a semiconductor device according to another embodiment of the present disclosure.
  • the semiconductor device includes a substrate 401, a nucleation layer 402, a channel layer, a barrier layer 405, and gate electrodes 411 and 413, a drain electrode 412, source electrodes 414 and 416, and body electrodes 415 and 417.
  • the channel layer includes first regions 408 and 409, connection regions 404 and 406, and a third region 403.
  • the semiconductor device in the embodiment of FIG. 4 does not include an N-type doped second region. Since the connection area is weakly P-type doped, 2DEG cannot be completely consumed.
  • it can also be a semiconductor device with a normally-off P-type buried layer controlled by potential. Furthermore, by controlling the doping concentration of carrier acceptors in the connection region, the conductivity of the connection region and the concentration of 2DEG can be controlled, thereby controlling the performance of the element. Parts similar to those in the embodiment of Figure 1 will not be described again.

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Abstract

La présente invention concerne un dispositif à semi-conducteur, comprenant : une couche barrière ; une couche de canal, qui est adjacente à la couche barrière, un gaz porteur bidimensionnel étant formé à la position dans la couche de canal à proximité d'une interface entre la couche barrière et la couche de canal ; une première électrode, qui est située au-dessus de la couche barrière et est conçue pour commander la connexion ou la déconnexion du gaz porteur bidimensionnel, la couche de canal comprenant une première région dans une plage correspondante au-dessous de la première électrode, et la concentration d'accepteur de porteuse de la première région amenant le gaz porteur bidimensionnel dans la première région au-dessous de la première électrode à être appauvri ; et une seconde électrode, qui est située au-dessus d'une seconde région dans la couche de canal et est électriquement connectée au gaz porteur bidimensionnel, la seconde région étant située sur un côté de la première région et étant en contact avec la couche barrière, et la seconde région impliquant un dopage de type donneur-porteur. La présente invention concerne en outre un procédé de fabrication d'un dispositif à semi-conducteur.
PCT/CN2022/102894 2022-06-30 2022-06-30 Dispositif à semi-conducteur et son procédé de fabrication WO2024000431A1 (fr)

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US20050258450A1 (en) * 2004-05-20 2005-11-24 Saxler Adam W Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
JP2011146613A (ja) * 2010-01-18 2011-07-28 Mitsubishi Electric Corp ヘテロ接合電界効果型トランジスタおよびその製造方法
CN112447834A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 半导体器件及其制造方法
CN112447835A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 半导体器件及其制造方法
CN112447837A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 一种高耐压的高电子迁移率晶体管

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050258450A1 (en) * 2004-05-20 2005-11-24 Saxler Adam W Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same
JP2011146613A (ja) * 2010-01-18 2011-07-28 Mitsubishi Electric Corp ヘテロ接合電界効果型トランジスタおよびその製造方法
CN112447834A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 半导体器件及其制造方法
CN112447835A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 半导体器件及其制造方法
CN112447837A (zh) * 2019-08-30 2021-03-05 广东致能科技有限公司 一种高耐压的高电子迁移率晶体管

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