WO2023282955A1 - Methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal - Google Patents

Methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal Download PDF

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Publication number
WO2023282955A1
WO2023282955A1 PCT/US2022/024726 US2022024726W WO2023282955A1 WO 2023282955 A1 WO2023282955 A1 WO 2023282955A1 US 2022024726 W US2022024726 W US 2022024726W WO 2023282955 A1 WO2023282955 A1 WO 2023282955A1
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layer
dielectric layer
aio
aluminum oxide
dielectric
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French (fr)
Inventor
Suketu Parikh
Mihaela A. Balseanu
Bhaskar Jyoti Bhuyan
Ning Li
Mark Joseph Saly
Aaron Michael DANGERFIELD
David Thompson
Abhijit B. Mallick
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Applied Materials Inc
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Applied Materials Inc
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
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    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
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    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
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    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
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    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
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    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H
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    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
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    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Definitions

  • Embodiments of the present disclosure generally relate to methods and apparatus for processing substrates, and more particularly, to methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal.
  • the dual damascene structure is, typically, fabricated using one or more deposition processes for depositing a patterned layer atop an underlying dielectric layer in which one or more metal layers (e.g., interconnects) are disposed.
  • an etch process is used to form one or more vias open to the one or more metal layers.
  • the one or more vias e.g., an unlanded via
  • the one or more vias can sometimes expose the underlying dielectric layer, which, in turn, can lead to shorts occurring.
  • a method of processing a substrate includes a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (Fte) or ammonia (Nhh) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
  • SAM self-assembled monolayer
  • AIO aluminum oxide
  • SiOCN silicon oxycarbonitride
  • SiN silicon nitride
  • an integrated tool includes a plurality of processing chambers configured to a) remove oxide from a metal layer disposed in a dielectric layer on a substrate disposed in a processing chamber, b) selectively deposit a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) deposit a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supply at least one of hydrogen (hte) or ammonia (Nhh) to remove the self-assembled monolayer (SAM), and e) deposit one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
  • SiOCN silicon oxycarbonitride
  • SiN silicon nitride
  • Figure 1 is a method of processing a substrate, in accordance with at least some embodiments of the present disclosure.
  • Figures 2A-2F are diagrams of a substrate, in accordance with at least some embodiments of the present disclosure.
  • Figures 3A-3F are diagrams of a substrate, in accordance with at least some embodiments of the present disclosure.
  • Figure 4 is a diagram of an integrated tool, in accordance with at least one embodiment of the present disclosure.
  • methods can include removing oxide from a metal layer disposed in a dielectric layer.
  • a self-assembled monolayer SAM
  • a precursor can be deposited while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer.
  • AIO aluminum oxide
  • Nhb ammonia
  • one of a silicon oxycarbide (SiOC) layer or a silicon nitride (SiN) layer can be deposited atop the metal layer and the one of an aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
  • SiOC silicon oxycarbide
  • SiN silicon nitride
  • AIO aluminum oxide
  • FIG. 1 is a method of processing a substrate
  • Figures 2A-3F are diagrams of substrates, in accordance with at least some embodiments of the present disclosure.
  • the method 100 may be performed in the tool 400 including any suitable processing chambers configured for one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) and/or atomic layer deposition (ALD), such as plasma enhanced ALD or thermal ALD (e.g., no plasma formation).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Exemplary processing systems that may be used to perform the inventive methods disclosed herein may include the line of processing systems commercially available from Applied Materials, Inc., of Santa Clara, California.
  • Other processing chambers, including those from other manufacturers, may also be suitably used in connection with the teachings provided herein.
  • the tool 400 can be embodied in individual process chambers that may be provided in a standalone configuration or as part of a cluster tool, for example, an integrated tool described below with respect to Figure 4.
  • the integrated tool include the line of integrated tools, available from Applied Materials, Inc., of Santa Clara, California.
  • the methods described herein may be practiced using other cluster tools having suitable process chambers coupled thereto, or in other suitable process chambers.
  • the inventive methods discussed above may be performed in an integrated tool such that there are limited or no vacuum breaks between processing steps.
  • reduced vacuum breaks may limit or prevent contamination (e.g., oxidation) of the tungsten liner layer or other portions of the substrate.
  • the integrated tool includes processing platform 401 (e.g., a vacuum-tight processing platform), a factory interface 404, and a system controller 402.
  • the processing platform 401 comprises multiple processing chambers, such as 414A, 414B, 414C, and 414D operatively coupled to a transfer chamber 403 (a vacuum substrate transfer chamber).
  • the factory interface 404 is operatively coupled to the transfer chamber 403 by one or more load lock chambers (two load lock chambers, such as 406A and 406B shown in Figure 4).
  • the factory interface 404 comprises at least one docking station 407, a factory interface robot 438 to facilitate the transfer of one or more semiconductor substrates (wafers).
  • the at least one docking station 407 is configured to accept one or more front opening unified pod (FOUP).
  • FOUP front opening unified pod
  • Four FOUPS, such as 405A, 405B, 405C, and 405D are shown in the embodiment of Figure 4.
  • the factory interface robot 438 is configured to transfer the substrates from the factory interface 404 to the processing platform 401 through the load lock chambers, such as 406A and 406B.
  • Each of the load lock chambers 406A and 406B have a first port coupled to the factory interface 404 and a second port coupled to the transfer chamber 403.
  • the load lock chamber 406A and 406B are coupled to a pressure control system (not shown) which pumps down and vents the load lock chambers 406A and 406B to facilitate passing the substrates between the vacuum environment of the transfer chamber 403 and the substantially ambient (e.g., atmospheric) environment of the factory interface 404.
  • the transfer chamber 403 has a vacuum robot 442 disposed within the transfer chamber 403. The vacuum robot 442 is capable of transferring the substrates 421 between the load lock chamber 406A and 406B and the processing chambers 414A, 414B, 414C, and 414D.
  • processing chambers 414A, 414B, 414C, and 414D comprise at least an ALD chamber, a CVD chamber, a PVD chamber, an e-beam deposition chamber, and/oran electroplating, electroless (EEP) deposition chamber.
  • one or more optional service chambers may be coupled to the transfer chamber 403.
  • the service chambers 416A and 416B may be configured to perform other substrate processes, such as degassing, bonding, chemical mechanical polishing (CMP), wafer cleaving, etching, plasma dicing, orientation, substrate metrology, cool down and the like.
  • CMP chemical mechanical polishing
  • the system controller 402 controls the operation of the tool 400 using a direct control of the process chambers 414A, 414B, 414C, and 414D or alternatively, by controlling the computers (or controllers) associated with the process chambers 414A, 414B, 414C, and 414D and the tool 400. In operation, the system controller 402 enables data collection and feedback from the respective chambers and systems to optimize performance of the tool 400.
  • the system controller 402 generally includes a central processing unit 430, a memory 434, and a support circuit 432.
  • the central processing unit 430 may be any form of a general-purpose computer processor that can be used in an industrial setting.
  • the support circuit 432 is conventionally coupled to the central processing unit 430 and may comprise a cache, clock circuits, input/output subsystems, power supplies, and the like.
  • Software routines, such as processing methods as described above may be stored in the memory 434 ⁇ e.g., non-transitory computer readable storage medium) and, when executed by the central processing unit 430, transform the central processing unit 430 into a specific purpose computer.
  • the software routines may also be stored and/or executed by a second controller (not shown) that is located remotely from the tool 400.
  • the substrate 200 can comprise a dielectric layer 202.
  • the dielectric layer 202 can comprise low-k dielectric material (e.g., silicon oxycarbonitride (SiOC), oxide, silicon nitride (SiN), etc.
  • the substrate 200 can also comprise a metal layer 204.
  • the metal layer can be made from at least one of cobalt (Co), copper (Cu), or other suitable metal (e.g., titanium (Ti), tungsten (W), etc.).
  • the metal layer 204 can be made from copper (Cu).
  • a capping layer 206 can, optionally, be deposited on the metal layer.
  • the capping layer 206 can be made from copper (Cu), cobalt (Co) or other suitable metal (e.g., titanium (Ti), tungsten (W), etc.).
  • the capping layer 206 can be made from cobalt (Co).
  • the capping layer functions to improve EM.
  • the substrate 200 is shown with the capping layer 206 deposited on the metal layer 204.
  • the method 100 comprises removing oxide from a metal layer disposed in a dielectric layer on a substrate disposed in a processing chamber.
  • the factory interface robot 438 can transfer the substrate 200 from the factory interface 404 to the processing platform 401 through, for example, the load lock chamber 406A.
  • the vacuum robot 442 can transfer the substrate 200 from the load lock chamber 406A to and from one or more of the processing chambers 414A- 414D and/or the service chambers 416A and 416B to process the substrate.
  • the substrate 200 can be transferred to the processing chamber 414A to perform one or more processes to remove the oxide (e.g., metal oxide) from the metal layer 204, a top surface of the dielectric layer 202, and/or the capping layer 206, if used.
  • the oxide is shown removed from the metal layer 204, the top surface of the dielectric layer 202, and the capping layer 206.
  • the removal process e.g., to remove/reduce Co and/or Cu oxide
  • the method 100 comprises selectively depositing a self- assembled monolayer (SAM) on the metal layer using atomic layer deposition.
  • SAM self-assembled monolayer
  • 104 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 104 (e.g., without vacuum break).
  • the self-assembled monolayer (SAM) 208 can be deposited over the metal layer 204 or the capping layer 206 using CVD (e.g., vapor or liquid phase).
  • a self-assembled monolayer (SAM) 308 can be deposited over a metal layer 304 or a capping layer 306 of a substrate 300 ( Figures 3A-3C) using CVD (e.g., vapor or liquid phase)
  • the self-assembled monolayer (SAM) 208 blocks deposition of the relatively large molecules (e.g., on the metal layer 204 and/or the capping layer 206) present during deposition of a precursor at 106.
  • one or more process parameters can be controlled for depositing the self-assembled monolayer (SAM) 208 over the metal layer 204 or the capping layer 206.
  • vapor pressure and/or temperature can be controlled to selectively deposit the self- assembled monolayer (SAM) 208 over the metal layer 204 or the capping layer 206.
  • the method 100 comprises depositing a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer.
  • the precursor can comprise aluminum (Al) (e.g., trimethylaluminum (TMA), neo pentene Al, etc.).
  • Al aluminum
  • TMA trimethylaluminum
  • Nhh can be supplied during 106.
  • one or more additional oxides e.g., hafnium oxide, zirconium oxide, and/or zinc oxide
  • 106 can be performed using CVD or ALD.
  • 106 can be performed using ALD in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 106 (e.g., the processing chamber 414B, without vacuum break).
  • a temperature of the substrate can be maintained at about 200° C to about 400° C.
  • an aluminum oxide (AIO) layer 210 can be deposited on the dielectric layer 202 ( Figure 2C).
  • a low-k dielectric layer 310 e.g., trimethylsilane or DM DM
  • a dielectric layer 302 of the substrate 300 Figure 3C.
  • the method 100 comprises supplying at least one of hydrogen (Fte) or ammonia (NF ) to remove the self-assembled monolayer (SAM).
  • 108 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 108 (e.g., without vacuum break).
  • the capping layer can also be treated (e.g., for reduction of the capping layer).
  • 102 can be performed again to remove any metal oxide present on the metal layer 204 or the capping layer 206.
  • the method 100 comprises purging the at least one of hydrogen (H2) or ammonia (NFb) from a processing volume of the processing chamber. Additionally, prior to proceeding to 110 of the method 100, in at least some embodiments, 102 to 108 can be repeated (cyclically) for a predetermined amount of times. For example, in at least some embodiments, the predetermined amount of time is 1- to about 10 times.
  • a nitridation process can be performed on the aluminum oxide (AIO) layer 210 and the low-k dielectric layer 310 (e.g., to form a dual film) prior to proceeding to 110 of the method 100.
  • AIO aluminum oxide
  • the low-k dielectric layer 310 e.g., to form a dual film
  • the method 100 comprises depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of an aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
  • 110 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 110 using CVD and/or ALD (e.g., the processing chamber 414C, without vacuum break).
  • silicon oxycarbonitride (SiOCN) layer 212 (or a silicon nitride (SiN) layer) can be deposited atop the metal layer 204 or the capping layer 206 and the aluminum oxide (AIO) layer 210 on the dielectric layer 202 ( Figure 2D).
  • a silicon oxycarbonitride (SiOCN) layer 312 (or a silicon nitride (SiN) layer) can be deposited atop the metal layer 304 or the capping layer 306 and the low-k dielectric layer 310 on the dielectric layer 302 ( Figure 3D).
  • the method 100 comprises optionally depositing an aluminum oxide (AIO) layer 214 atop the silicon oxycarbonitride (SiOCN) layer 212 (or the silicon nitride (SiN) layer).
  • an aluminum oxide (AIO) layer 314 can be deposited atop the silicon oxycarbonitride (SiOCN) layer 312 (or the silicon nitride (SiN) layer).
  • the aluminum oxide (AIO) layer 314 can be silicon carbon nitride (SiCN).
  • the method 100 comprises forming a patterned layer 216 (or a patterned layer 316) comprising dielectric material atop one of the aluminum oxide (AIO) layer 214 or the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer) to form a dual damascene on the patterned layer 216 (or a patterned layer 316).
  • a patterned layer 216 or a patterned layer 316
  • the method 100 comprises forming a patterned layer 216 (or a patterned layer 316) comprising dielectric material atop one of the aluminum oxide (AIO) layer 214 or the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer) to form a dual damascene on the patterned layer 216 (or a patterned layer 316).
  • the method 100 comprises selectively etching the patterned layer 216 to expose the aluminum oxide (AIO) layer 210 on the dielectric layer 202 or the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer), e.g., to land a via 218 to an etch stop layer, as shown in Figure 2E.
  • the method comprises selectively etching the patterned layer 316 to expose the low-k dielectric layer 310 on the dielectric layer 302, the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer), or the aluminum oxide (AIO) layer 314.
  • the patterned layer 316 is etched to expose the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer), e.g., to land a via 318 to an etch stop layer, as shown in Figure 3E.
  • the method 100 comprises selectively etching the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer or the one of silicon oxycarbonitride (SiOCN) layer or silicon nitride (SiN) layer to expose one of the aluminum oxide (AIO) layer on the substrate or the metal layer.
  • the method 100 comprises selectively etching the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer) with respect to the aluminum oxide (AIO) layer 210, e.g., to land a via 218 onto the metal layer, the capping layer, and/or the aluminum oxide (AIO) layer, as shown in Figure 2F.
  • SiOCN silicon oxycarbonitride
  • SiN silicon nitride
  • the method comprises selectively etching the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer with respect to the low-k dielectric layer 310, e.g., to land a via 318 onto the metal layer, the capping layer, and/or the aluminum oxide (AIO) layer, as shown in Figure 3F.
  • SiOCN silicon oxycarbonitride
  • SiN silicon nitride
  • the respective aluminum oxide (AIO) layer 210 and low-k dielectric layer 310 function as pillars allowing the via 218 and the via 318 to land on the underlaying metal.
  • the selectively etching the silicon oxycarbonitride (SiOCN) layer 212 or the silicon oxycarbonitride (SiOCN) layer 312 allows for vias to land on/expose metal, without shorting (e.g., without landing on/exposing the dielectric layer) and allows enlargement (e.g., about 25%) of the via without shorting, thus increasing cross sectional area of contact and providing lower via resistance (e.g., about 25% to about 50%).

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Abstract

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H2) or ammonia (NH3) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.

Description

METHODS AND APPARATUS FOR SELECTIVE ETCH STOP CAPPING AND SELECTIVE VIA OPEN FOR FULLY LANDED VIA ON UNDERLYING METAL
FIELD
[0001] Embodiments of the present disclosure generally relate to methods and apparatus for processing substrates, and more particularly, to methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal.
BACKGROUND
[0002] Methods and apparatus for fabricating dual damascene structure (e.g., copper (Cu)) are known. For example, the dual damascene structure is, typically, fabricated using one or more deposition processes for depositing a patterned layer atop an underlying dielectric layer in which one or more metal layers (e.g., interconnects) are disposed. Next, an etch process is used to form one or more vias open to the one or more metal layers. During the etch process, however, the one or more vias (e.g., an unlanded via) can sometimes expose the underlying dielectric layer, which, in turn, can lead to shorts occurring.
SUMMARY
[0003] Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (Fte) or ammonia (Nhh) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
[0004] In accordance with at least some embodiments, an apparatus configured for fabricating dual damascene on a substrate includes a dielectric layer, a metal layer disposed in the dielectric layer, one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer, and a via landed to expose at least one of the metal layer or the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer, without exposing the dielectric layer.
[0005] In accordance with at least some embodiments, an integrated tool includes a plurality of processing chambers configured to a) remove oxide from a metal layer disposed in a dielectric layer on a substrate disposed in a processing chamber, b) selectively deposit a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) deposit a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supply at least one of hydrogen (hte) or ammonia (Nhh) to remove the self-assembled monolayer (SAM), and e) deposit one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
[0006] Other and further embodiments of the present disclosure are described below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Embodiments of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the disclosure depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of scope, for the disclosure may admit to other equally effective embodiments.
[0008] Figure 1 is a method of processing a substrate, in accordance with at least some embodiments of the present disclosure. [0009] Figures 2A-2F are diagrams of a substrate, in accordance with at least some embodiments of the present disclosure.
[0010] Figures 3A-3F are diagrams of a substrate, in accordance with at least some embodiments of the present disclosure.
[0011] Figure 4 is a diagram of an integrated tool, in accordance with at least one embodiment of the present disclosure.
[0012] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
DETAILED DESCRIPTION
[0013] Embodiments of a processing a substrate are provided herein. For example, in at least some embodiments, methods can include removing oxide from a metal layer disposed in a dielectric layer. Next, a self-assembled monolayer (SAM) can be deposited on the metal layer. Next, a precursor can be deposited while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer. Thereafter, at least one of hydrogen (hte) or ammonia (Nhb) can be supplied to remove the self-assembled monolayer (SAM). Subsequently, one of a silicon oxycarbide (SiOC) layer or a silicon nitride (SiN) layer can be deposited atop the metal layer and the one of an aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer. The methods and apparatus described herein allows for vias to land on/expose metal, without shorting (e.g., without landing on/exposing the dielectric layer) and allows enlargement (e.g., about 25%) of the via without shorting, thus increasing cross sectional area of contact and providing lower via resistance (e.g., about 25% to about 50%).
[0014] Figure 1 is a method of processing a substrate, and Figures 2A-3F are diagrams of substrates, in accordance with at least some embodiments of the present disclosure. [0015] The method 100 may be performed in the tool 400 including any suitable processing chambers configured for one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) and/or atomic layer deposition (ALD), such as plasma enhanced ALD or thermal ALD (e.g., no plasma formation). Exemplary processing systems that may be used to perform the inventive methods disclosed herein may include the line of processing systems commercially available from Applied Materials, Inc., of Santa Clara, California. Other processing chambers, including those from other manufacturers, may also be suitably used in connection with the teachings provided herein.
[0016] The tool 400 can be embodied in individual process chambers that may be provided in a standalone configuration or as part of a cluster tool, for example, an integrated tool described below with respect to Figure 4. Examples of the integrated tool include the line of integrated tools, available from Applied Materials, Inc., of Santa Clara, California. The methods described herein may be practiced using other cluster tools having suitable process chambers coupled thereto, or in other suitable process chambers. For example, in some embodiments, the inventive methods discussed above may be performed in an integrated tool such that there are limited or no vacuum breaks between processing steps. For example, reduced vacuum breaks may limit or prevent contamination (e.g., oxidation) of the tungsten liner layer or other portions of the substrate.
[0017] The integrated tool includes processing platform 401 (e.g., a vacuum-tight processing platform), a factory interface 404, and a system controller 402. The processing platform 401 comprises multiple processing chambers, such as 414A, 414B, 414C, and 414D operatively coupled to a transfer chamber 403 (a vacuum substrate transfer chamber). The factory interface 404 is operatively coupled to the transfer chamber 403 by one or more load lock chambers (two load lock chambers, such as 406A and 406B shown in Figure 4).
[0018] In some embodiments, the factory interface 404 comprises at least one docking station 407, a factory interface robot 438 to facilitate the transfer of one or more semiconductor substrates (wafers). The at least one docking station 407 is configured to accept one or more front opening unified pod (FOUP). Four FOUPS, such as 405A, 405B, 405C, and 405D are shown in the embodiment of Figure 4. The factory interface robot 438 is configured to transfer the substrates from the factory interface 404 to the processing platform 401 through the load lock chambers, such as 406A and 406B.
[0019] Each of the load lock chambers 406A and 406B have a first port coupled to the factory interface 404 and a second port coupled to the transfer chamber 403. The load lock chamber 406A and 406B are coupled to a pressure control system (not shown) which pumps down and vents the load lock chambers 406A and 406B to facilitate passing the substrates between the vacuum environment of the transfer chamber 403 and the substantially ambient (e.g., atmospheric) environment of the factory interface 404. The transfer chamber 403 has a vacuum robot 442 disposed within the transfer chamber 403. The vacuum robot 442 is capable of transferring the substrates 421 between the load lock chamber 406A and 406B and the processing chambers 414A, 414B, 414C, and 414D.
[0020] In some embodiments, processing chambers 414A, 414B, 414C, and 414D comprise at least an ALD chamber, a CVD chamber, a PVD chamber, an e-beam deposition chamber, and/oran electroplating, electroless (EEP) deposition chamber.
[0021] In some embodiments, one or more optional service chambers (shown as 416A and 416B) may be coupled to the transfer chamber 403. The service chambers 416A and 416B may be configured to perform other substrate processes, such as degassing, bonding, chemical mechanical polishing (CMP), wafer cleaving, etching, plasma dicing, orientation, substrate metrology, cool down and the like.
[0022] The system controller 402 controls the operation of the tool 400 using a direct control of the process chambers 414A, 414B, 414C, and 414D or alternatively, by controlling the computers (or controllers) associated with the process chambers 414A, 414B, 414C, and 414D and the tool 400. In operation, the system controller 402 enables data collection and feedback from the respective chambers and systems to optimize performance of the tool 400. The system controller 402 generally includes a central processing unit 430, a memory 434, and a support circuit 432. The central processing unit 430 may be any form of a general-purpose computer processor that can be used in an industrial setting. The support circuit 432 is conventionally coupled to the central processing unit 430 and may comprise a cache, clock circuits, input/output subsystems, power supplies, and the like. Software routines, such as processing methods as described above may be stored in the memory 434 {e.g., non-transitory computer readable storage medium) and, when executed by the central processing unit 430, transform the central processing unit 430 into a specific purpose computer. The software routines may also be stored and/or executed by a second controller (not shown) that is located remotely from the tool 400.
[0023] With reference again to Figure 1 , initially one or more substrates, e.g., a semiconductor wafer, flat panel, solar panel, polymer substrate, or the like may be loaded into one or more of the Four FOUPS, such as FOUPS 405A, 405B, 405C, and 405D (Figure 2A). In at least some embodiments, the substrate 200 can comprise a dielectric layer 202. The dielectric layer 202 can comprise low-k dielectric material (e.g., silicon oxycarbonitride (SiOC), oxide, silicon nitride (SiN), etc. The substrate 200 can also comprise a metal layer 204. For example, the metal layer can be made from at least one of cobalt (Co), copper (Cu), or other suitable metal (e.g., titanium (Ti), tungsten (W), etc.). In at least some embodiments, the metal layer 204 can be made from copper (Cu). Additionally, a capping layer 206 can, optionally, be deposited on the metal layer. For example, the capping layer 206 can be made from copper (Cu), cobalt (Co) or other suitable metal (e.g., titanium (Ti), tungsten (W), etc.). In at least some embodiments, the capping layer 206 can be made from cobalt (Co). The capping layer functions to improve EM. For illustrative purposes, the substrate 200 is shown with the capping layer 206 deposited on the metal layer 204.
[0024] At 102, the method 100 comprises removing oxide from a metal layer disposed in a dielectric layer on a substrate disposed in a processing chamber. For example, the factory interface robot 438 can transfer the substrate 200 from the factory interface 404 to the processing platform 401 through, for example, the load lock chamber 406A. The vacuum robot 442 can transfer the substrate 200 from the load lock chamber 406A to and from one or more of the processing chambers 414A- 414D and/or the service chambers 416A and 416B to process the substrate. [0025] For example, at 102, the substrate 200 can be transferred to the processing chamber 414A to perform one or more processes to remove the oxide (e.g., metal oxide) from the metal layer 204, a top surface of the dielectric layer 202, and/or the capping layer 206, if used. In the illustrated embodiment, the oxide is shown removed from the metal layer 204, the top surface of the dielectric layer 202, and the capping layer 206. At 102, the removal process (e.g., to remove/reduce Co and/or Cu oxide) can comprise treating the substrate with hydrogen (H2) plasma, ammonia (NH3) plasma, or N2/H2 plasma, or soaking the substrate using a thermal process (e.g., at about 200° C to about 400° C).
[0026] Next, at 104 the method 100 comprises selectively depositing a self- assembled monolayer (SAM) on the metal layer using atomic layer deposition. For example, 104 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 104 (e.g., without vacuum break). For example, the self-assembled monolayer (SAM) 208 can be deposited over the metal layer 204 or the capping layer 206 using CVD (e.g., vapor or liquid phase). Similarly, a self-assembled monolayer (SAM) 308 can be deposited over a metal layer 304 or a capping layer 306 of a substrate 300 (Figures 3A-3C) using CVD (e.g., vapor or liquid phase) The self-assembled monolayer (SAM) 208 blocks deposition of the relatively large molecules (e.g., on the metal layer 204 and/or the capping layer 206) present during deposition of a precursor at 106. In at least some embodiments, one or more process parameters can be controlled for depositing the self-assembled monolayer (SAM) 208 over the metal layer 204 or the capping layer 206. For example, in at least some embodiments, vapor pressure and/or temperature can be controlled to selectively deposit the self- assembled monolayer (SAM) 208 over the metal layer 204 or the capping layer 206.
[0027] For example, at 106, the method 100 comprises depositing a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer. For example, the precursor can comprise aluminum (Al) (e.g., trimethylaluminum (TMA), neo pentene Al, etc.). In at least some embodiments, Nhh can be supplied during 106. In at least some embodiments, one or more additional oxides (e.g., hafnium oxide, zirconium oxide, and/or zinc oxide) can be used to selectively deposit on the dielectric layer for application of selective etch stop, which can prevent next layer via to open only on metal, as described in greater detail below. 106 can be performed using CVD or ALD. For example, in at least some embodiments, 106 can be performed using ALD in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 106 (e.g., the processing chamber 414B, without vacuum break). At 106, a temperature of the substrate can be maintained at about 200° C to about 400° C. In at least some embodiments, at 106, an aluminum oxide (AIO) layer 210 can be deposited on the dielectric layer 202 (Figure 2C). Similarly, in at least some embodiments, a low-k dielectric layer 310 (e.g., trimethylsilane or DM DM) can be selectively deposited on a dielectric layer 302 of the substrate 300 (Figure 3C).
[0028] Next, at 108, the method 100 comprises supplying at least one of hydrogen (Fte) or ammonia (NF ) to remove the self-assembled monolayer (SAM). For example, 108 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 108 (e.g., without vacuum break). In at least some embodiments, at 108 the capping layer can also be treated (e.g., for reduction of the capping layer). In at least some embodiments, after 108, 102 can be performed again to remove any metal oxide present on the metal layer 204 or the capping layer 206. In at least some embodiments, the method 100 comprises purging the at least one of hydrogen (H2) or ammonia (NFb) from a processing volume of the processing chamber. Additionally, prior to proceeding to 110 of the method 100, in at least some embodiments, 102 to 108 can be repeated (cyclically) for a predetermined amount of times. For example, in at least some embodiments, the predetermined amount of time is 1- to about 10 times.
[0029] In at least some embodiments, a nitridation process can be performed on the aluminum oxide (AIO) layer 210 and the low-k dielectric layer 310 (e.g., to form a dual film) prior to proceeding to 110 of the method 100.
[0030] Next, at 110, the method 100 comprises depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of an aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer. 110 can be performed in the processing chamber 414A or can be transferred to one of the other processing chambers to perform 110 using CVD and/or ALD (e.g., the processing chamber 414C, without vacuum break). For example, at 110 silicon oxycarbonitride (SiOCN) layer 212 (or a silicon nitride (SiN) layer) can be deposited atop the metal layer 204 or the capping layer 206 and the aluminum oxide (AIO) layer 210 on the dielectric layer 202 (Figure 2D). Similarly, a silicon oxycarbonitride (SiOCN) layer 312 (or a silicon nitride (SiN) layer) can be deposited atop the metal layer 304 or the capping layer 306 and the low-k dielectric layer 310 on the dielectric layer 302 (Figure 3D).
[0031] In at least some embodiments, after 110, the method 100 comprises optionally depositing an aluminum oxide (AIO) layer 214 atop the silicon oxycarbonitride (SiOCN) layer 212 (or the silicon nitride (SiN) layer). Similarly, an aluminum oxide (AIO) layer 314 can be deposited atop the silicon oxycarbonitride (SiOCN) layer 312 (or the silicon nitride (SiN) layer). In at least some embodiments, the aluminum oxide (AIO) layer 314 can be silicon carbon nitride (SiCN).
[0032] In at least some embodiments, after 110, the method 100 comprises forming a patterned layer 216 (or a patterned layer 316) comprising dielectric material atop one of the aluminum oxide (AIO) layer 214 or the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer) to form a dual damascene on the patterned layer 216 (or a patterned layer 316). For example, in at least some embodiments, the method 100 comprises selectively etching the patterned layer 216 to expose the aluminum oxide (AIO) layer 210 on the dielectric layer 202 or the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer), e.g., to land a via 218 to an etch stop layer, as shown in Figure 2E. Similarly, in at least some embodiments, the method comprises selectively etching the patterned layer 316 to expose the low-k dielectric layer 310 on the dielectric layer 302, the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer), or the aluminum oxide (AIO) layer 314. For illustrative purposes, the patterned layer 316 is etched to expose the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer), e.g., to land a via 318 to an etch stop layer, as shown in Figure 3E. Next, the method 100 comprises selectively etching the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer or the one of silicon oxycarbonitride (SiOCN) layer or silicon nitride (SiN) layer to expose one of the aluminum oxide (AIO) layer on the substrate or the metal layer. For example, in at least some embodiments, the method 100 comprises selectively etching the silicon oxycarbonitride (SiOCN) layer 212 (or silicon nitride (SiN) layer) with respect to the aluminum oxide (AIO) layer 210, e.g., to land a via 218 onto the metal layer, the capping layer, and/or the aluminum oxide (AIO) layer, as shown in Figure 2F. Similarly, in at least some embodiments, the method comprises selectively etching the silicon oxycarbonitride (SiOCN) layer 312 (or silicon nitride (SiN) layer with respect to the low-k dielectric layer 310, e.g., to land a via 318 onto the metal layer, the capping layer, and/or the aluminum oxide (AIO) layer, as shown in Figure 3F.
[0033] After the selectively etching the silicon oxycarbonitride (SiOCN) layer 212 or the silicon oxycarbonitride (SiOCN) layer 312, the respective aluminum oxide (AIO) layer 210 and low-k dielectric layer 310 function as pillars allowing the via 218 and the via 318 to land on the underlaying metal. For example, the selectively etching the silicon oxycarbonitride (SiOCN) layer 212 or the silicon oxycarbonitride (SiOCN) layer 312 allows for vias to land on/expose metal, without shorting (e.g., without landing on/exposing the dielectric layer) and allows enlargement (e.g., about 25%) of the via without shorting, thus increasing cross sectional area of contact and providing lower via resistance (e.g., about 25% to about 50%).
[0034] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

Claims:
1. A method of processing a substrate, comprising: a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber; b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition; c) depositing a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer; d) supplying at least one of hydrogen (H2) or ammonia (IMH3) to remove the self-assembled monolayer (SAM); and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
2. The method of claim 1 , wherein the metal layer is at least one of cobalt (Co) or copper (Cu).
3. The method of claim 1 , wherein the oxide is metal oxide.
4. The method of claim 1, wherein removing the oxide comprises one of treating the substrate with hydrogen (H2) plasma or soaking the substrate using a thermal process.
5. The method of claim 1 , wherein the precursor comprises aluminum (Al).
6. The method of claim 1 , wherein the precursor comprises trimethylaluminum (TMA).
7. The method of claim 1 , further comprising purging the at least one of hydrogen (H2) or ammonia (NH3) from a processing volume of the processing chamber.
8. The method of claim 1, further comprising depositing an aluminum oxide (AIO) layer atop the one of the silicon oxycarbonitride (SiOCN) layer or the silicon nitride (SiN) layer.
9. The method of claim 8, further comprising forming a patterned layer comprising dielectric material atop one of the aluminum oxide (AIO) layer or the one of the silicon oxycarbonitride (SiOCN) layer or the silicon nitride (SiN) layer to form a dual damascene on the patterned layer.
10. The method of claim 9, further comprising selectively etching the patterned layer to expose one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer or the one of the silicon oxycarbonitride (SiOCN) layer or the silicon nitride (SiN) layer.
11. The method as in any of claims 1 to 10, further comprising selectively etching the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer or the one of the silicon oxycarbonitride (SiOCN) layer or the silicon nitride (SiN) layer to expose one of the aluminum oxide (AIO) layer on the substrate or the metal layer.
12. The method of claim 1, further comprising prior to performing e), repeating a) to d) for a predetermined amount of times.
13. The method as in any of claims 1 to 10, or 12, wherein the predetermined amount of times is 1 to about 10 times.
14. An apparatus configured for fabricating dual damascene on a substrate, comprising: a dielectric layer; a metal layer disposed in the dielectric layer; one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer; one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer; and a via landed to expose at least one of the metal layer or the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer, without exposing the dielectric layer.
15. An integrated tool, comprising: a plurality of processing chambers configured to: a) remove oxide from a metal layer disposed in a dielectric layer on a substrate disposed in a processing chamber; b) selectively deposit a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition; c) deposit a precursor while supplying water to form one of an aluminum oxide (AIO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer; d) supply at least one of hydrogen (hte) or ammonia (Nhb) to remove the self-assembled monolayer (SAM); and e) deposit one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AIO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.
16. The integrated tool of claim 15, wherein the metal layer is at least one of cobalt (Co) or copper (Cu).
17. The integrated tool of claim 15, wherein the oxide is metal oxide.
18. The integrated tool of claim 15, wherein the plurality of processing chambers are further configured to one of treat the substrate with hydrogen (H2) plasma or soak the substrate using a thermal process.
19. The integrated tool of claim 15, wherein the precursor comprises aluminum (Al).
20. The integrated tool as in any of claims 15 to 19, wherein the precursor comprises trimethylaluminum (TMA).
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