WO2023214608A1 - Matériel de simulation de circuit quantique - Google Patents

Matériel de simulation de circuit quantique Download PDF

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Publication number
WO2023214608A1
WO2023214608A1 PCT/KR2022/007270 KR2022007270W WO2023214608A1 WO 2023214608 A1 WO2023214608 A1 WO 2023214608A1 KR 2022007270 W KR2022007270 W KR 2022007270W WO 2023214608 A1 WO2023214608 A1 WO 2023214608A1
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WIPO (PCT)
Prior art keywords
gate
quantum circuit
quantum
state
states
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PCT/KR2022/007270
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English (en)
Korean (ko)
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홍윤표
전석훈
김병수
최규현
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한국전자기술연구원
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Publication of WO2023214608A1 publication Critical patent/WO2023214608A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms

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  • the present invention relates to a simulator of a quantum circuit model, and more specifically, to a technology related to quantum circuit simulation hardware for efficiently calculating state vectors in quantum circuit operations on a classical computer.
  • a quantum computer is a computer that can solve existing NP-complete problems within polynomial time using several new algorithms such as the Shor algorithm and Groover algorithm, and is a technology that can collapse the RSA encryption system that currently utilizes the characteristics of prime numbers.
  • Shor algorithm and Groover algorithm
  • simulations on classical computers are essential for algorithmic research using quantum circuits.
  • a quantum circuit can be expressed as a two-dimensional matrix composed of complex numbers, and a quantum circuit using N qubits is expressed as a 2 N ⁇ 2 N matrix. Therefore, in a 50-qubit system that enjoys quantum supremacy, a complex matrix of 2 50
  • the present invention was created to solve the above problems, and the purpose of the present invention is to simulate the quantum circuit model on a classical computer, and to use the state vector generated at the quantum output, which is the result of the calculation of the quantum circuit.
  • the goal is to provide quantum circuit simulation hardware that can operate with small complexity and memory.
  • a quantum circuit simulator for achieving the above object groups the states constituting the state vector into a plurality of sets based on the target qubit of the gate constituting the quantum circuit simulated on the computer.
  • Grouping Department a decision unit that determines a set to perform a gate operation; and an operation unit that performs a gate operation on the determined set.
  • the grouping unit may group states in which the target qubit is the same and the remaining qubits are different into the same set.
  • the decision unit may decide to perform a gate operation on a set in which all grouped states are not 0.
  • the decision unit may decide not to perform the gate operation on a set in which all grouped states are 0.
  • the decision unit may determine whether to perform a gate operation based on non-zero states and gates for a set in which some of the grouped states are 0.
  • the decision unit may determine not to perform the gate operation if the gate is a control gate and the 0 state is a control qubit.
  • the calculation unit can perform calculations by sequentially updating the quantum state vector on a gate-by-gate basis for the gates constituting the quantum circuit.
  • the decision unit can check whether the state is 0 with low delay by using internal memory instead of using external memory.
  • the decision unit may determine not to access the internal memory and not perform the gate operation if the gate is a control gate and the 0 state is a control qubit.
  • a quantum circuit simulation method includes grouping states constituting a state vector into a plurality of sets based on the target qubit of a gate constituting a quantum circuit simulated on a computer; determining a set to perform a gate operation on; and performing a gate operation on the determined set.
  • the state vector generated at the quantum output which is the result of the calculation of the quantum circuit, can be calculated with less complexity and memory. It becomes possible. As a result , the 2 N
  • FIG. 1 is a diagram showing the configuration of a quantum circuit simulation system according to an embodiment of the present invention
  • Figure 2 is a diagram showing the detailed structure of a quantum circuit simulation accelerator
  • 3 is a diagram showing the detailed structure of a quantum circuit simulator
  • FIG. 4 is a diagram illustrating a gate of a quantum circuit
  • FIG. 6 is a diagram illustrating a 2-qubit single gate
  • FIG. 7 is a diagram illustrating a 2-qubit control gate
  • FIGS 8 and 9 are drawings provided to explain the existing quantum circuit calculation method
  • FIGS 10 and 11 are diagrams provided to explain the quantum circuit calculation method according to an embodiment of the present invention.
  • An embodiment of the present invention presents simulation hardware for a quantum circuit simulator running on a classical computer to efficiently calculate state vectors in quantum circuit operations using limited memory.
  • a classical computer is a currently commonly used computer that performs bit (0 or 1)-based operations, and is a concept corresponding to a quantum computer that performs qubit-based operations.
  • the determinant that combines the matrices of the quantum gates constituting the quantum circuit into one by Kronecker product is not calculated, but the quantum circuit is Quantum state vectors are sequentially calculated for each gate unit.
  • the part consisting of a number of gates in the quantum circuit is divided into gate units and the state vector is updated each time it passes through each gate, thereby requiring a large amount of calculation and memory usage.
  • the Kerr product operation By excluding the Kerr product operation, the amount of computation and memory usage are dramatically reduced.
  • Figure 1 is a diagram showing the configuration of a quantum circuit simulation system according to an embodiment of the present invention.
  • the quantum circuit simulation system according to an embodiment of the present invention includes a host system 100 and a quantum circuit simulation accelerator 200.
  • the quantum circuit simulation accelerator 200 is simulation hardware that simulates a quantum circuit and can be implemented using an FPGA (Field Programmable Gate Array).
  • the host system 100 is a system for developing a quantum circuit simulator of the quantum circuit simulation accelerator 200.
  • FIG. 2 shows the detailed structure of the quantum circuit simulation accelerator 200.
  • the quantum circuit simulation accelerator 200 includes a Micro Controller Unit (MCU) 210, a memory 220, a BUS 230, and a quantum circuit simulator 240.
  • MCU Micro Controller Unit
  • the MCU 210 is equipped with firmware developed and compiled in the host system 100.
  • the MCU 210 equipped with firmware receives quantum circuit data and initial quantum state data to be simulated by the quantum circuit simulator 240 from the host system 100 and stores them in the memory 220.
  • Gates include single-qubit gates such as identity gates, Pauli gates, and Clifford gates, controlled Pauli gates, controlled Hadamard gates, controlled rotation gates, and Toffoli gates. There are multi-qubit gates, etc.
  • Gates that make up a quantum circuit are expressed as matrices.
  • the MCU 210 stores the matrices in the memory 220.
  • the quantum circuit simulator 240 performs quantum operations using matrices stored in the memory 220 under the control of the MCU 210.
  • the quantum operation results and final quantum state by the quantum circuit simulator 240 are transmitted to the host system 100 through the MCU 210.
  • BUS 240 provides a communication interface between components of quantum circuit simulation accelerator 200.
  • FIG. 3 shows the detailed structure of the quantum circuit simulator 240.
  • the quantum circuit simulator 240 includes a state grouping unit 241, an operation skip decision unit 242, an operation unit 243, and a Zero Flag (ZF) SRAM 244.
  • ZF Zero Flag
  • the state grouping unit 241 groups and outputs the states constituting the state vector based on the target qubit of the gate constituting the quantum circuit. Specifically, the state grouping unit 242 groups two states in which the target qubit is the same and the remaining qubits are different into one set.
  • the state vector can be expressed as a 2 N ⁇ 1 matrix, and each item of the matrix represents the probability of measuring the corresponding state (
  • the target qubit refers to the qubit to which the gate is applied.
  • the set grouped and output from the state grouping unit 241 consists of two states (s1, s2) as shown in FIG. 5, and is named using two indices (v1, v2).
  • the states (s1, s2) in the same set are related to each other, but are independent from the states in other sets.
  • the operation skip decision unit 242 determines sets to be skipped without performing the gate operation and sets to perform the gate operation among the sets grouped and output from the state grouping unit 241.
  • Figure 6 shows a 2-qubit single gate. If the set input through the gate is (s1, s2), the output of the gate (s1', s2') can be expressed by the following matrix operation.
  • the operation skip decision unit 242 determines to perform the gate operation on the set in which all grouped states are not 0, and does not perform the gate operation on the set in which all grouped states are 0. You can decide to skip it.
  • the operation skip decision unit 242 determines whether to perform a gate operation based on non-zero states and gates for a set in which some of the grouped states are 0.
  • the operation skip decision unit 242 determines to perform the operation even if some of the states are set to 0.
  • the gate is a control gate as illustrated in FIG. 7, which is a multi-qubit gate that can be bypassed according to the input qubit, and the 0 state is the control qubit (q0), it is skipped without accessing the ZF SRAM 244 and performing the gate operation. Decide to do it.
  • the operation unit 243 sequentially reads the set of states determined to perform the gate operation by the operation skip decision unit 242 from the memory 220 and uses them as inputs to the gate to perform the operation, and the state updated by the operation. These are recorded in the memory 220.
  • the calculation by the calculation unit 243 is repeated for each of all gates constituting the quantum circuit simulated by the quantum circuit simulator 240 until the calculation is completed. As a result, the finally updated final quantum state vector remains in the memory 120.
  • FIG. 8 is a diagram showing the concept of an existing quantum circuit calculation method for an arbitrary quantum circuit
  • FIG. 9 is a flowchart showing the existing quantum circuit calculation method.
  • FIG. 10 is a diagram showing the concept of a quantum circuit calculation method according to an embodiment of the present invention for an arbitrary quantum circuit
  • FIG. 11 is a flowchart showing a quantum circuit calculation method according to an embodiment of the present invention.
  • calculation is performed on a quantum gate basis, that is, calculation is performed on only one quantum gate at a time. Accordingly, instead of Kronecker multiplying (x) the three H gates, they are separated by Hani and operated individually.
  • the final state vector is not calculated using an intermediate unitary matrix with a size of 2 N ⁇ 2 N in a quantum circuit composed of several quantum gates, but is repeatedly divided into 2 ⁇ 2 unitary operations of a single quantum gate. Memory consumption was reduced by using intermediate results in units of state vectors with a size of 2N +1 .
  • states that are related to each other are grouped into a set based on the target qubit of the gate, and if the gate operation can be bypassed depending on the state value and type of gate, the operation is skipped to increase latency and power. Consumption was reduced.
  • a computer-readable recording medium can be any data storage device that can be read by a computer and store data.
  • computer-readable recording media can be ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical disk, hard disk drive, etc.
  • computer-readable codes or programs stored on a computer-readable recording medium may be transmitted through a network connected between computers.

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Abstract

L'invention concerne un matériel de simulation de circuit quantique. Un simulateur de circuit quantique, selon un mode de réalisation de la présente invention, comprend : une unité de groupement qui regroupe, en une pluralité d'ensembles, des états constituant un vecteur d'état sur la base de bits quantiques cibles de portes constituant des circuits quantiques simulés sur un ordinateur ; une unité de détermination pour déterminer un ensemble sur lequel une opération de porte doit être effectuée ; et une unité d'opération pour effectuer l'opération de porte sur l'ensemble déterminé. Ainsi, lors de la simulation d'un modèle de circuit quantique sur un ordinateur classique, non sur un ordinateur quantique, un vecteur d'état généré pendant une sortie quantique, qui est un résultat d'opération de circuits quantiques, peut être calculé avec une faible complexité et une petite capacité de mémoire.
PCT/KR2022/007270 2022-05-04 2022-05-23 Matériel de simulation de circuit quantique WO2023214608A1 (fr)

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KR10-2022-0055340 2022-05-04
KR1020220055340A KR20230155760A (ko) 2022-05-04 2022-05-04 양자 회로 시뮬레이션 하드웨어

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020515999A (ja) * 2017-03-24 2020-05-28 ビュル エスアエス 古典的なコンピュータ上で量子回路をシミュレートする方法
US20210232961A1 (en) * 2020-01-24 2021-07-29 United States Of America As Represented By Secretary Of The Navy Quantum Computer Based Method for Analyzing Cyber Data and Spectra while Performing Optimization Based on the Analysis
US20210342730A1 (en) * 2020-05-01 2021-11-04 equal1.labs Inc. System and method of quantum enhanced accelerated neural network training
KR20210144846A (ko) * 2020-04-15 2021-11-30 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 양자 회로를 위한 결함 허용 및 에러 정정 디코딩 방법 및 장치, 그리고 칩
US20220101165A1 (en) * 2020-09-28 2022-03-31 Beit Inc. Controllable quantum logic gates with measurement and methods for use therewith

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020515999A (ja) * 2017-03-24 2020-05-28 ビュル エスアエス 古典的なコンピュータ上で量子回路をシミュレートする方法
US20210232961A1 (en) * 2020-01-24 2021-07-29 United States Of America As Represented By Secretary Of The Navy Quantum Computer Based Method for Analyzing Cyber Data and Spectra while Performing Optimization Based on the Analysis
KR20210144846A (ko) * 2020-04-15 2021-11-30 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 양자 회로를 위한 결함 허용 및 에러 정정 디코딩 방법 및 장치, 그리고 칩
US20210342730A1 (en) * 2020-05-01 2021-11-04 equal1.labs Inc. System and method of quantum enhanced accelerated neural network training
US20220101165A1 (en) * 2020-09-28 2022-03-31 Beit Inc. Controllable quantum logic gates with measurement and methods for use therewith

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