WO2023206130A1 - 像素电路、驱动方法和显示装置 - Google Patents

像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2023206130A1
WO2023206130A1 PCT/CN2022/089515 CN2022089515W WO2023206130A1 WO 2023206130 A1 WO2023206130 A1 WO 2023206130A1 CN 2022089515 W CN2022089515 W CN 2022089515W WO 2023206130 A1 WO2023206130 A1 WO 2023206130A1
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Prior art keywords
control
circuit
terminal
transistor
electrically connected
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PCT/CN2022/089515
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English (en)
French (fr)
Inventor
羊振中
詹裕程
景阳钟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/089515 priority Critical patent/WO2023206130A1/zh
Priority to US18/026,637 priority patent/US20240290258A1/en
Priority to CN202280000937.1A priority patent/CN117501338A/zh
Publication of WO2023206130A1 publication Critical patent/WO2023206130A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method and a display device.
  • insufficient brightness and short-term afterimages in the first frame are mainly related to the hysteresis effect of transistors.
  • the display cycle includes refresh frames and multiple hold frames set successively.
  • the gate-source voltage reset, data voltage writing and threshold voltage compensation of the drive transistor are only performed during the refresh frame. Since the gate-source voltage reset and threshold voltage compensation of the drive transistor are reduced in the hold frame, it is easy to cause charge trap accumulation. Due to the driving transistor, the brightness of the first frame is insufficient and the afterimage problem occurs when the screen is switched.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, an energy storage circuit, a switch control circuit, a first initialization circuit and a compensation control circuit;
  • the display cycle of the pixel circuit includes a refresh frame and a Hold frame, the hold frame includes a first reset stage, a second reset stage and a first light-emitting stage set successively;
  • the first end of the energy storage circuit is electrically connected to the control end of the drive circuit, the Energy storage circuits are used to store electrical energy;
  • the switch control circuit is electrically connected to the switch control terminal, the first voltage terminal and the second terminal of the energy storage circuit respectively, and is used to control the refresh frame in the refresh frame under the control of the switch control signal provided by the switch control terminal.
  • the connection between the first voltage terminal and the second terminal of the energy storage circuit is controlled, and in the first resetting stage and the second resetting stage, the third resetting stage is controlled.
  • a voltage terminal is disconnected from the second terminal of the energy storage circuit;
  • the first initialization circuit is electrically connected to the initialization control terminal, the first initial voltage terminal and the control terminal of the drive circuit respectively, for use in the first reset phase and the second reset phase. Under the control of the initialization control signal provided by the initialization control terminal, write the first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit;
  • the compensation control circuit is electrically connected to the compensation control terminal, the control terminal of the drive circuit and the second terminal of the drive circuit respectively, and is used to provide compensation at the compensation control terminal during the second reset phase. Under the control of the control signal, the control end of the drive circuit is controlled to be connected to the second end of the drive circuit;
  • the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control terminal.
  • the refresh frame includes an initialization phase and a compensation phase set successively;
  • the first initialization circuit is used to write the first initial voltage to the control end of the drive circuit under the control of the initialization control signal during the initialization phase;
  • the compensation control circuit is used to control the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal during the compensation stage.
  • the pixel circuit also includes a data writing circuit
  • the data writing circuit is electrically connected to the writing control terminal, the data line and the first terminal of the driving circuit respectively, and is used for controlling the writing control signal provided at the writing control terminal during the compensation phase. Next, the data voltage provided by the data line is written into the first end of the driving circuit.
  • the pixel circuit further includes a first light emission control circuit and a second light emission control circuit;
  • the refresh frame further includes a second light emission stage set after the compensation stage;
  • the first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, for use in the first light-emitting phase and the second light-emitting phase. Under the control of the lighting control signal provided by the control terminal, the connection between the first voltage terminal and the first terminal of the driving circuit is controlled;
  • the second light-emitting control circuit is electrically connected to the light-emitting control end, the second end of the driving circuit and the first pole of the light-emitting element respectively, for use in the first light-emitting stage and the second light-emitting phase. stage, under the control of the light-emitting control signal, control the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the second pole of the light-emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the initialization control terminal, the second initial voltage terminal and the first pole of the light-emitting element respectively, and is used to change the second initial voltage under the control of the initialization control signal.
  • the second initial voltage provided by the terminal is written into the first pole of the light-emitting element.
  • the first initialization circuit includes a first transistor
  • the compensation control circuit includes a second transistor
  • the switch control circuit includes a third transistor
  • the control electrode of the first transistor is electrically connected to the initialization control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the driving The control terminal of the circuit is electrically connected;
  • the control electrode of the second transistor is electrically connected to the compensation control terminal, the first electrode of the second transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the second transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the energy storage terminal.
  • the second end of the circuit is electrically connected.
  • the energy storage circuit includes a storage capacitor
  • the driving circuit includes a driving transistor
  • the first end of the storage capacitor is the first end of the energy storage circuit, and the second end of the storage capacitor is the second end of the energy storage circuit;
  • the control pole of the drive transistor is the control end of the drive circuit
  • the first pole of the drive transistor is the first end of the drive circuit
  • the second pole of the drive transistor is the second end of the drive circuit.
  • the data writing circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the write control terminal, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the drive circuit. The first end is electrically connected.
  • the first lighting control circuit includes a fifth transistor, and the second lighting control circuit includes a sixth transistor;
  • the control electrode of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit.
  • the first end is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the The first electrode of the light-emitting element is electrically connected.
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the initialization control terminal, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the light emitting terminal.
  • the first pole of the component is electrically connected.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit.
  • the display cycle includes a refresh frame and a hold frame; the hold frame includes a first reset stage, a second reset stage, and a second reset stage. setting stage and first lighting stage; the driving method includes:
  • the switch control circuit controls the connection between the first voltage terminal and the second terminal of the energy storage circuit under the control of the switch control signal
  • the switch control circuit controls the connection between the first voltage terminal and the second terminal of the energy storage circuit under the control of the switch control signal.
  • the first initialization circuit writes the first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit under the control of the initialization control signal;
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the holding frame further includes a holding phase provided between the second reset phase and the first lighting phase;
  • the driving method further includes:
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the refresh frame includes an initialization phase and a compensation phase set successively; the driving method further includes:
  • the first initialization circuit writes the first initial voltage into the control end of the drive circuit under the control of the initialization control signal
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the pixel circuit further includes a data writing circuit, a first lighting control circuit and a second lighting control circuit; the refresh frame further includes a second lighting stage set after the compensation stage; the driving method Also includes:
  • the data writing circuit writes the data voltage provided by the data line into the first end of the driving circuit under the control of the writing control signal provided by the writing control terminal;
  • the first lighting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the lighting control signal provided by the lighting control terminal.
  • the second light-emitting control circuit controls the connection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit converts the second initial voltage provided by the second initial voltage terminal under the control of the initialization control signal. Write to the first pole of the light-emitting element.
  • an embodiment of the present disclosure provides a display device including the above-mentioned pixel circuit.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 4 of the present disclosure
  • FIG. 6A is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the initialization stage of the present disclosure
  • FIG. 6B is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the compensation stage of the present disclosure
  • FIG. 6C is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the second light-emitting stage of the present disclosure
  • Figure 7 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 4 of the present disclosure.
  • Figure 8A is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in Figure 4 in the first reset stage of the present disclosure
  • FIG. 8B is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the second reset stage of the present disclosure
  • FIG. 8C is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the holding phase of the present disclosure
  • FIG. 8D is a schematic diagram of the working state of at least one embodiment of the pixel circuit shown in FIG. 4 in the first light-emitting stage of the present disclosure
  • FIG. 9 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure.
  • the pixel circuit includes a light-emitting element E0, a driving circuit 10, an energy storage circuit 11, a switch control circuit 12, a first initialization circuit 13 and a compensation control circuit 14;
  • the display cycle includes a refresh frame and a hold frame, and the hold frame includes a first reset phase, a second reset phase, and a first lighting phase that are set successively;
  • the first end of the energy storage circuit 11 is electrically connected to the control end of the drive circuit 10, and the energy storage circuit 11 is used to store electrical energy;
  • the switch control circuit 12 is electrically connected to the switch control terminal PG2, the first voltage terminal V1 and the second terminal of the energy storage circuit 11 respectively, and is used to control the switch control signal provided by the switch control terminal PG2.
  • the first voltage terminal V1 is controlled to be connected to the second terminal of the energy storage circuit 11.
  • the connection between the first voltage terminal V1 and the second terminal of the energy storage circuit 11 is controlled.
  • the first voltage terminal V1 is controlled to be disconnected from the second terminal of the energy storage circuit 11;
  • the first initialization circuit 13 is electrically connected to the initialization control terminal NR, the first initial voltage terminal I1 and the control terminal of the drive circuit 10 respectively, for use in the first reset phase and the second reset phase. , under the control of the initialization control signal provided by the initialization control terminal NR, write the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the control terminal of the driving circuit 10;
  • the compensation control circuit 14 is electrically connected to the compensation control terminal NG, the control terminal of the drive circuit 10 and the second terminal of the drive circuit 10 respectively, and is used to control the compensation control during the second reset phase. Under the control of the compensation control signal provided by terminal NG, the control terminal of the driving circuit 10 is controlled to be connected to the second terminal of the driving circuit 10;
  • the driving circuit 10 is electrically connected to the light-emitting element E0 and is used to generate a driving current for driving the light-emitting element E0 under the control of the potential of its control terminal.
  • the display cycle includes a refresh frame and a hold frame;
  • the hold frame includes a first reset stage, a second reset stage, and a second reset stage. Setup stage and first lighting stage;
  • the switch control circuit 12 controls the connection between the first voltage terminal V1 and the second terminal of the energy storage circuit 11 under the control of the switch control signal;
  • the switch control circuit 12 controls the first voltage terminal V1 and the third voltage terminal of the energy storage circuit 11 under the control of the switch control signal.
  • the two terminals are disconnected, and the first initialization circuit 13 writes the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the initialization control signal;
  • the compensation control circuit 14 controls the connection between the control terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the compensation control signal.
  • the first initialization circuit 13 is used to initialize the control signal.
  • the first initial voltage Vint1 is written into the control terminal of the driving circuit 10, so that the gate-source voltage of the driving transistor in the driving circuit 10 is reset during part of each holding frame, so that the The drive transistor is in the OFF-Bias (cut-off bias) state.
  • the pixel circuit described in at least one embodiment of the present disclosure can also compensate for the threshold voltage of the driving transistor, and can also compensate for the picture caused by the uneven threshold voltage of the driving transistor. Quality/Mura (uneven brightness) and other issues.
  • the refresh frame includes an initialization phase and a compensation phase set successively;
  • the first initialization circuit is used to write the first initial voltage to the control end of the drive circuit under the control of the initialization control signal during the initialization phase, so that at the beginning of the compensation phase, the The drive circuit can be turned on for threshold voltage compensation;
  • the compensation control circuit is used to control the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal during the compensation stage.
  • the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit
  • the data writing circuit is electrically connected to the writing control terminal, the data line and the first terminal of the driving circuit respectively, and is used for controlling the writing control signal provided at the writing control terminal during the compensation phase. Next, the data voltage provided by the data line is written into the first end of the driving circuit to perform data voltage writing.
  • the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit;
  • the refresh frame further includes a second light-emitting stage set after the compensation stage;
  • the first light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, for use in the first light-emitting phase and the second light-emitting phase. Under the control of the lighting control signal provided by the control terminal, the connection between the first voltage terminal and the first terminal of the driving circuit is controlled;
  • the second light-emitting control circuit is electrically connected to the light-emitting control end, the second end of the driving circuit and the first pole of the light-emitting element respectively, for use in the first light-emitting stage and the second light-emitting phase. stage, under the control of the light-emitting control signal, control the connection between the second end of the driving circuit and the first pole of the light-emitting element;
  • the second pole of the light-emitting element is electrically connected to the second voltage terminal.
  • the pixel circuit may further include a first light-emitting control circuit and a second light-emitting control circuit.
  • the first light-emitting control circuit Under the control of the signal, the first voltage terminal is controlled to be connected to the first terminal of the driving circuit.
  • the second lighting control circuit is controlled by the lighting control signal to control the second terminal of the driving circuit to be connected to the first terminal of the driving circuit.
  • the first poles of the light-emitting elements are connected to each other, and the driving circuit controls the light-emitting elements to emit light.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 21 , a first light emitting control circuit 22 and a third 2. Lighting control circuit 23;
  • the data writing circuit 21 is electrically connected to the writing control terminal PG1, the data line D1 and the first end of the driving circuit 10 respectively, and is used to provide the data at the writing control terminal PG1 during the compensation phase. Under the control of the write control signal, write the data voltage provided by the data line D1 into the first end of the drive circuit 10;
  • the first lighting control circuit 22 is electrically connected to the lighting control terminal E1, the first voltage terminal V1 and the first terminal of the driving circuit 10, respectively, for controlling the lighting control signal provided by the lighting control terminal E1. , controlling the connection between the first voltage terminal V1 and the first terminal of the driving circuit 10;
  • the second lighting control circuit 23 is electrically connected to the lighting control terminal E1, the second terminal of the driving circuit 10 and the first pole of the lighting element E0, respectively, for controlling the lighting control signal. , controlling the communication between the second terminal of the driving circuit 10 and the first pole of the light-emitting element E0;
  • the second pole of the light-emitting element E0 is electrically connected to the second voltage terminal V2.
  • the first node A is electrically connected to the control terminal of the driving circuit 10
  • the second node B is electrically connected to the second terminal of the energy storage circuit 11
  • the The third node C is electrically connected to the first terminal of the driving circuit 10 .
  • the first voltage terminal V1 may be a high voltage terminal
  • the second voltage terminal V2 may be a low voltage terminal, but is not limited thereto.
  • the display cycle of the pixel circuit includes a refresh frame and a hold frame that are set successively, and the refresh frame includes an initialization setting. stage, a compensation stage and a second lighting stage;
  • the holding frame includes a first reset stage, a second reset stage, a holding stage and a first lighting stage that are set successively;
  • the switch control circuit 12 controls the connection between the first voltage terminal V1 and the second terminal of the energy storage circuit 11 under the control of the switch control signal provided by the switch control terminal PG2. ;
  • the first initialization circuit 13 writes the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the driver under the control of the initialization control signal provided by the initialization control terminal NR.
  • the control end of the circuit 10 so that when the compensation phase starts, the drive circuit 10 can control the first end of the drive circuit 10 and the second end of the drive circuit 10 under the control of the potential of its control end. connected between;
  • the data writing circuit writes the data voltage Vdata provided by the data line D1 into the first terminal of the driving circuit 10 under the control of the writing control signal provided by the writing control terminal PG1. terminal; the compensation control circuit 14 controls the connection between the control terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the compensation control signal provided by the compensation control terminal NG;
  • the driving circuit 10 controls the connection between the first end of the driving circuit 10 and the second end of the driving circuit 10 under the control of the potential of its control end, and passes the data voltage Vdata Charge the energy storage circuit 11 to change the potential of the control terminal of the drive circuit 10 until the drive circuit 10 controls the first terminal of the drive circuit 10 to be connected to the driver under the control of the potential of its control terminal. The second terminals of the circuit 10 are disconnected. At this time, the potential of the control terminal of the driving circuit 10 is Vdata+Vth, where Vth is the threshold voltage of the driving transistor in the driving circuit 10;
  • the first lighting control circuit 22 controls the first voltage terminal V1 and the first terminal of the driving circuit 10 under the control of the lighting control signal provided by the lighting control terminal E1
  • the second light-emitting control circuit 23 controls the connection between the second end of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the driving circuit 10 drives The light-emitting element E0 emits light; in the light-emitting stage, the driving current of the driving circuit 10 that drives the light-emitting element E0 has nothing to do with Vth, and can compensate for the threshold voltage shift;
  • the switch control circuit 12 controls the first voltage terminal V1 and the energy storage circuit 11 under the control of the switch control signal provided by the switch control terminal PG2 disconnected between the second terminals; the first initialization circuit 13 writes the first initial voltage Vint1 provided by the first initial voltage terminal I1 into the initialization control signal provided by the initialization control terminal NR.
  • the second node B since the second node B is in a floating state, the first node A is connected to the first initial voltage Vint1.
  • the second node B The potential also changes as the potential of the first node A changes, and Vdata+Vth is still stored in the storage capacitor;
  • the switch control circuit 12 controls the switching between the first voltage terminal V1 and the energy storage circuit 11 under the control of the switch control signal provided by the switch control terminal PG2.
  • the data writing circuit 21 controls the disconnection between the data line D1 and the first end of the driving circuit 10 under the control of the writing control signal provided by the writing control terminal PG1. , no data voltage writing is performed; the first initialization circuit 13 writes the first initial voltage Vint1 provided by the first initial voltage terminal I1 under the control of the initialization control signal provided by the initialization control terminal NR.
  • the control terminal of the driving circuit 10 is controlled by the compensation control circuit 14 under the control of the compensation control signal provided by the compensation control terminal NG. connected; the third node C is in a floating state;
  • the driving circuit 10 controls the connection between the first end of the driving circuit 10 and the second end of the driving circuit 10 under the control of the potential of its control end; by The drive circuit 10, the compensation control circuit 14 and the first initialization circuit 13 discharge to the first initial voltage terminal I1, and the potential of the third node C gradually decreases until the drive circuit 10 controls the The first end of the drive circuit 10 is disconnected from the second end of the drive circuit 10, and the drive transistor is placed in the OFF-Bias state. At this time, the potential of the first node A is Vint1, and the potential of the third node C is Vint1. is Vint1-Vth, the energy storage circuit 11 still maintains Vdata+Vth;
  • the compensation control circuit 14 controls the connection between the control terminal of the driving circuit 10 and the second terminal of the driving circuit 10 under the control of the compensation control signal provided by the compensation control terminal NG. Connected, at this time, the driving transistor is still in the OFF-Bias state, and the potential of each node is consistent with the second reset stage;
  • the switch control circuit 12 controls the first voltage terminal V1 and the second terminal of the energy storage circuit 11 under the control of the switch control signal provided by the switch control terminal PG2. are connected; the compensation control circuit 14 controls the segment between the control end of the drive circuit 10 and the second end of the drive circuit 10 to be disconnected under the control of the compensation control signal provided by the compensation control end NG. , the first lighting control circuit 22 controls the connection between the first voltage terminal V1 and the first end of the driving circuit 10 under the control of the lighting control signal provided by the lighting control terminal E1.
  • the two light-emitting control circuits 23 control the communication between the second end of the driving circuit 10 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the driving circuit 10 drives the light-emitting element E0 to emit light; In the light-emitting stage, the driving current of the driving circuit 10 that drives the light-emitting element E0 has nothing to do with Vth, and can compensate for the threshold voltage shift.
  • a reset sequence is added in the holding frame.
  • the data voltage is not refreshed and written, by changing the gate source of the driving transistor in each holding frame.
  • the voltage is reset so that the drive transistor is in the OFF-Bias state.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the initialization control terminal, the second initial voltage terminal and the first pole of the light-emitting element respectively, and is used to change the second initial voltage under the control of the initialization control signal.
  • the second initial voltage provided by the terminal is written into the first pole of the light-emitting element to control the light-emitting element not to emit light, ensure that the dark state brightness of the light-emitting element is dark enough, and clear the first pole residue of the light-emitting element of charge.
  • the pixel circuit described in at least one embodiment of the present disclosure also includes a second initialization circuit 31;
  • the second initialization circuit 31 is electrically connected to the initialization control terminal NR, the second initial voltage terminal I2 and the first pole of the light-emitting element E0, respectively, for controlling the initialization control signal.
  • the second initial voltage Vint2 provided by the second initial voltage terminal I2 is written into the first pole of the light-emitting element E0 to control the light-emitting element E0 not to emit light, ensure that the dark state brightness of the light-emitting element is dark enough, and clear all The charge remaining on the first electrode of the light-emitting element E0.
  • the first initial voltage terminal I1 and the second initial voltage terminal I2 may be the same initial voltage terminal.
  • the initial voltage terminal is used to provide the initial voltage Vint, but is not used for this purpose. is limited.
  • the second initialization circuit 31 is controlled by the initialization control signal. , write the second initial voltage Vint2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E0,
  • the first initialization circuit includes a first transistor
  • the compensation control circuit includes a second transistor
  • the switch control circuit includes a third transistor
  • the control electrode of the first transistor is electrically connected to the initialization control terminal, the first electrode of the first transistor is electrically connected to the first initial voltage terminal, and the second electrode of the first transistor is electrically connected to the driving The control terminal of the circuit is electrically connected;
  • the control electrode of the second transistor is electrically connected to the compensation control terminal, the first electrode of the second transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the second transistor is electrically connected to the drive circuit.
  • the second end of the circuit is electrically connected;
  • the control electrode of the third transistor is electrically connected to the switch control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the energy storage terminal.
  • the second end of the circuit is electrically connected.
  • the energy storage circuit includes a storage capacitor
  • the driving circuit includes a driving transistor
  • the first end of the storage capacitor is the first end of the energy storage circuit, and the second end of the storage capacitor is the second end of the energy storage circuit;
  • the control pole of the drive transistor is the control end of the drive circuit
  • the first pole of the drive transistor is the first end of the drive circuit
  • the second pole of the drive transistor is the second end of the drive circuit.
  • the data writing circuit includes a fourth transistor
  • the control electrode of the fourth transistor is electrically connected to the write control terminal, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the drive circuit. The first end is electrically connected.
  • the first lighting control circuit includes a fifth transistor, and the second lighting control circuit includes a sixth transistor;
  • the control electrode of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit.
  • the first end is electrically connected;
  • the control electrode of the sixth transistor is electrically connected to the light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the The first electrode of the light-emitting element is electrically connected.
  • the second initialization circuit includes a seventh transistor
  • the control electrode of the seventh transistor is electrically connected to the initialization control terminal, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the light emitting terminal.
  • the first pole of the component is electrically connected.
  • the light-emitting element is an organic light-emitting diode
  • the first electrode of the light-emitting element is an anode
  • the second electrode of the light-emitting element is a cathode, but it is not limited to this.
  • the first initialization circuit 13 includes a first transistor M1
  • the compensation control circuit 14 includes a second transistor M2
  • the The switch control circuit 12 includes a third transistor M3
  • the drive circuit 10 includes a drive transistor DTFT
  • the energy storage circuit 11 includes a storage capacitor C1
  • the light-emitting element is an organic light-emitting diode O1;
  • the gate of the first transistor M1 is electrically connected to the initialization control terminal NR, the source of the first transistor M1 is electrically connected to the initial voltage terminal I0, and the drain of the first transistor M1 is connected to the driving transistor.
  • the gate of the DTFT is electrically connected; the initial voltage terminal I0 is used to provide the initial voltage Vint;
  • the gate of the second transistor M2 is electrically connected to the compensation control terminal NG, the source of the second transistor M2 is electrically connected to the gate of the driving transistor DTFT, and the drain of the second transistor M2 is electrically connected to the compensation control terminal NG.
  • the drain of the driving transistor M0 is electrically connected;
  • the gate of the third transistor M3 is electrically connected to the switch control terminal PG2, the source of the third transistor M3 is electrically connected to the high voltage terminal, and the drain of the third transistor M3 is connected to the storage capacitor C1
  • the second end is electrically connected; the high voltage end is used to provide high voltage ELVDD;
  • the first end of the storage capacitor C1 is electrically connected to the gate of the driving transistor DTFT;
  • the data writing circuit 21 includes a fourth transistor M4;
  • the gate of the fourth transistor M4 is electrically connected to the write control terminal PG1, the source of the fourth transistor M4 is electrically connected to the data line D1, and the drain of the fourth transistor M4 is electrically connected to the write control terminal PG1.
  • the source of the driving transistor DTFT is electrically connected;
  • the first lighting control circuit 22 includes a fifth transistor M5, and the second lighting control circuit 23 includes a sixth transistor M6;
  • the gate of the fifth transistor M5 is electrically connected to the light-emitting control terminal E1, the source of the fifth transistor M5 is electrically connected to the high voltage terminal, and the drain of the fifth transistor M5 is electrically connected to the driving terminal.
  • the source of the transistor DTFT is electrically connected;
  • the gate of the sixth transistor M6 is electrically connected to the light-emitting control terminal E1
  • the source of the sixth transistor M6 is electrically connected to the drain of the driving transistor DTFT
  • the drain of the sixth transistor M6 is electrically connected to the light-emitting control terminal E1.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the second initialization circuit 31 includes a seventh transistor M7;
  • the gate of the seventh transistor M7 is electrically connected to the initialization control terminal NR, the source of the seventh transistor M7 is electrically connected to the initial voltage terminal I0, and the drain of the seventh transistor M7 is electrically connected to the initialization control terminal NR.
  • the anode of the organic light-emitting diode O1 is electrically connected;
  • the cathode of the organic light emitting diode O1 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage ELVSS.
  • both the first initial voltage terminal and the second initial voltage terminal are the initial voltage terminal I0, and the initial voltage terminal I0 is used to provide an initial voltage. Vint.
  • the first transistor M1, the second transistor M2 and the seventh transistor M7 are all NMOS (N-type metal-oxide-semiconductor) transistors.
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all PMOS (P-type metal-oxide-semiconductor) transistors.
  • the first transistor M1 and the second transistor M2 are NMOS transistors to reduce leakage current and facilitate maintaining the potential of the gate of the driving transistor DTFT.
  • the first node A is electrically connected to the gate of the driving transistor DTFT
  • the second node B is electrically connected to the second end of C1
  • the third node C is electrically connected to the source of the driving transistor DTFT.
  • the refresh frame includes an initialization phase S51, a compensation phase S52 and a second light-emitting phase S53 that are set successively;
  • the initialization control terminal NR provides a high voltage signal
  • the compensation control terminal NG provides a low voltage signal
  • the writing control terminal PG1 provides a high voltage signal
  • the switch control terminal PG2 provides a low voltage signal
  • E1 provides a high voltage signal
  • the third transistor M3 is turned on
  • the first transistor M1 and the seventh transistor M7 are turned on
  • the second transistor M2 the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the driving transistor DTFT are turned off
  • the initial voltage terminal I0 provides an initial voltage Vint, which is connected between the second node B and the high voltage terminal.
  • the initial voltage Vint is written into the first node A and the anode of the organic light-emitting diode O1 to initialize the potential of the gate of the driving transistor DTFT, so that At the beginning of the compensation phase S52, the driving transistor DTFT can be turned on and ensure that the dark state brightness of the organic light-emitting diode O1 is dark enough;
  • the initialization control terminal NR provides a low voltage signal
  • the compensation control terminal NG provides a high voltage signal
  • the writing control terminal PG1 provides an over-low voltage signal
  • the switching control terminal PG2 provides a low voltage signal
  • E1 provides a high voltage signal, such as As shown in Figure 6B, the second transistor M2 and the third transistor M3 are turned on, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off, and the data line D1 provides data. VoltageVdata;
  • the driving transistor DTFT is turned on, and the data voltage Vdata charges C1 through the fourth transistor M4, the driving transistor DTFT and the second transistor M2 to increase the potential of the first node A until the driving transistor DTFT is turned off.
  • the potential of the first node A is Vdata + Vth, and the voltage is stored in C1, where Vth is the threshold voltage of the driving transistor DTFT;
  • the initialization control terminal NR provides a low voltage signal
  • the compensation control terminal NG provides a low voltage signal
  • the writing control terminal PG1 provides a high voltage signal
  • the switch control terminal PG2 provides a low voltage signal
  • E1 provides a low voltage signal.
  • the third transistor M3 is turned on
  • the fifth transistor M5 the driving transistor DTFT and the sixth transistor M6 are all turned on.
  • the potential of the third node C is ELVDD.
  • the driving transistor DTFT drives the organic light-emitting diode O1 to emit light.
  • the driving current of the transistor DTFT that drives the organic light-emitting diode O1 to emit light is proportional to (Vdata-ELVDD)2. This driving current has nothing to do with Vth, which compensates for the problem of threshold voltage offset of the driving transistor;
  • the potential of the first node A is Vdata+Vth
  • the potential of the second node B and the potential of the third node C are ELVDD.
  • the refresh frame includes a first reset phase S71 , a second reset phase S72 , a holding phase S73 and a first reset phase S73 .
  • the initialization control terminal NR provides a high voltage signal
  • the compensation control terminal NG provides a low voltage signal
  • the writing control terminal PG1 provides a high voltage signal
  • the switching control terminal PG2 provides a high voltage signal
  • E1 provides a high voltage signal.
  • the third transistor M3 is turned off, the first transistor M1 and the seventh transistor M7 are turned on, the initial voltage terminal I0 provides the initial voltage Vint, and Vint is written into the first node A and the anode of the organic light-emitting diode O1 , since the second node B is in a floating state, through the coupling effect of C1, the potential of the second node B changes with the potential of the first node A.
  • the third transistor M3 Since the third transistor M3 is turned off, Vdata+Vth is still stored in In C1; in the first reset phase S71, the potential of the first node A is Vint, the potential of the second node B is ELVDD+(Vint-(Vdata+Vth)), and the potential of the third node C is ELVDD;
  • the initialization control terminal NR provides a high voltage signal
  • the compensation control terminal NG provides a high voltage signal
  • the writing control terminal PG1 provides a high voltage signal
  • the switch control terminal PG2 provides a high voltage signal
  • E1 provides a high voltage signal.
  • the driving transistor DTFT is turned on, and the driving transistor DTFT, the second transistor M2 and the first transistor M1 discharge to the initial voltage terminal I0, so that the potential of the third node C gradually changes from ELVDD to Decreases until the driving transistor DTFT turns off.
  • the potential of the third node C is Vint-Vth, and the driving transistor DTFT is in the OFF-Bias state.
  • the potential of the first node A continues to be Vint, and C1 still maintains Vdata+Vth;
  • the initialization control terminal NR provides a low voltage signal
  • the compensation control terminal NG provides a high voltage signal
  • both the write control terminal PG1 and the switch control terminal PG2 provide high voltage signals
  • E1 provides a high voltage signal
  • the second transistor M2 is turned on
  • the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off, and the driving transistor DTFT still maintains the OFF-Bias state.
  • the voltage of each node is consistent with the second reset stage S72;
  • the initialization control terminal NR provides a low voltage signal
  • the compensation control terminal NG provides a low voltage signal
  • the writing control terminal PG1 and the switch control terminal PG2 provide a low voltage signal
  • E1 provides a low voltage signal
  • the third transistor M3, the fifth transistor M5, the sixth transistor M6 and the driving transistor DTFT are turned on
  • the first transistor M1, the second transistor M2, the fourth transistor M4 and the seventh transistor M7 are all turned off
  • the driving transistor DTFT drives the organic light-emitting diode O1 to emit light
  • the potential of the second node B is ELVDD again.
  • the first node A is in a floating state.
  • the potential of the first node A becomes Vint+(ELVDD-(ELVDD+(Vint -(Vdata+Vth)))), that is, the potential of the first node A is Vdata+Vth
  • the current flowing through the organic light-emitting diode O1 is proportional to Vgs-Vth, that is, the current flowing through the organic light-emitting diode O1 is proportional to (Vdata-ELVDD)2, the current flowing through the organic light-emitting diode O1 has nothing to do with Vth; where Vgs is the gate-source voltage of the driving transistor DTFT.
  • FIGS. 8A, 8B, 8C and 8D circles represent that the corresponding transistors are turned on, and crosses represent that the corresponding transistors are turned off.
  • FIG. 9 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 4 .
  • the one marked F1 is the first refresh frame
  • the one marked F3 is the second refresh frame
  • the one marked F21 is the first first hold frame
  • the one marked F41 is the second first hold frame.
  • the refresh frequency of at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is 60 Hz
  • one display cycle may include refresh frames and 59 hold frames.
  • the first hold frame F21 and the second refresh frame There are also 58 hold frames set between F3.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit.
  • the display cycle includes a refresh frame and a holding frame; the holding frame includes a first reset phase, a second reset phase and a first light-emitting phase that are set successively.
  • the driving method includes:
  • the switch control circuit controls the connection between the first voltage terminal and the second terminal of the energy storage circuit under the control of the switch control signal
  • the switch control circuit controls the connection between the first voltage terminal and the second terminal of the energy storage circuit under the control of the switch control signal.
  • the first initialization circuit writes the first initial voltage provided by the first initial voltage terminal into the control terminal of the driving circuit under the control of the initialization control signal;
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the first initialization circuit is controlled by the initialization control signal.
  • the first initial voltage is written into the control terminal of the driving circuit to reset the gate-source voltage of the driving transistor in the driving circuit 10 during a part of each holding frame, so that the driving transistor is in OFF-Bias. (cutoff bias) state, by resetting the driving transistor in each frame, reducing the accumulation of charges captured in the driving transistor, and improving the problem of insufficient brightness of the first frame and short-term afterimages when switching low-frequency driving pictures.
  • the holding frame further includes a holding phase provided between the second reset phase and the first lighting phase;
  • the driving method further includes:
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the refresh frame includes an initialization phase and a compensation phase set successively; the driving method further includes:
  • the first initialization circuit writes the first initial voltage into the control end of the drive circuit under the control of the initialization control signal to adjust the potential of the control end of the drive circuit. initialization;
  • the compensation control circuit controls the connection between the control end of the drive circuit and the second end of the drive circuit under the control of the compensation control signal.
  • the pixel circuit further includes a data writing circuit, a first lighting control circuit and a second lighting control circuit; the refresh frame further includes a second lighting stage set after the compensation stage; the driving method Also includes:
  • the data writing circuit writes the data voltage provided by the data line into the first terminal of the driving circuit under the control of the writing control signal provided by the writing control terminal to perform data voltage conversion. write;
  • the first lighting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the lighting control signal provided by the lighting control terminal.
  • the second light-emitting control circuit controls the connection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.
  • the pixel circuit further includes a second initialization circuit; the driving method further includes:
  • the second initialization circuit converts the second initial voltage provided by the second initial voltage terminal under the control of the initialization control signal. Write the first pole of the light-emitting element to control the light-emitting element not to emit light.
  • the display device includes the above-mentioned pixel circuit.
  • the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种像素电路、驱动方法和显示装置。像素电路包括发光元件（E0）、驱动电路（10）、储能电路（11）、开关控制电路（12）、第一初始化电路（13）和补偿控制电路（14）；开关控制电路（12）在开关控制信号的控制下，在刷新帧和第一发光阶段，控制第一电压端与储能电路（11）的第二端之间连通，在第一重置阶段和第二重置阶段，控制第一电压端与储能电路（11）的第二端之间断开；第一初始化电路（13）在第一重置阶段和第二重置阶段，在初始化控制信号的控制下，将第一初始电压写入驱动电路（10）的控制端；补偿控制电路（14）在第二重置阶段，在补偿控制信号的控制下，控制驱动电路（10）的控制端与驱动电路（10）的第二端之间连通。

Description

像素电路、驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、驱动方法和显示装置。
背景技术
在相关技术中，第一帧亮度不足及短期残像主要与晶体管的迟滞效应有关，在低频驱动时序下，显示周期包括先后设置的刷新帧和多个保持帧。驱动晶体管的栅源电压重置、数据电压写入和阈值电压补偿只在刷新帧时进行，由于在保持帧，驱动晶体管的栅源电压重置和阈值电压补偿的次数减少，容易造成电荷捕获累积于驱动晶体管，导致画面切换时第一帧亮度不足及残像问题。
发明内容
在一个方面中，本公开实施例提供一种像素电路，包括发光元件、驱动电路、储能电路、开关控制电路、第一初始化电路和补偿控制电路；所述像素电路的显示周期包括刷新帧和保持帧，所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路用于储存电能；
所述开关控制电路分别与开关控制端、第一电压端和所述储能电路的第二端电连接，用于在所述开关控制端提供的开关控制信号的控制下，在所述刷新帧和所述第一发光阶段，控制所述第一电压端与所述储能电路的第二端之间连通，在所述第一重置阶段和所述第二重置阶段，控制所述第一电压端与所述储能电路的第二端之间断开；
所述第一初始化电路分别与初始化控制端、第一初始电压端和所述驱动电路的控制端电连接，用于在所述第一重置阶段和所述第二重置阶段，在所述初始化控制端提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的控制端；
所述补偿控制电路分别与补偿控制端、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述第二重置阶段，在所述补偿控制端提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
所述驱动电路用于在其控制端的电位的控制下，产生驱动所述发光元件的驱动电流。
可选的，所述刷新帧包括先后设置的初始化阶段和补偿阶段；
所述第一初始化电路用于在所述初始化阶段，在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端；
所述补偿控制电路用于在所述补偿阶段，在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路；
所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述补偿阶段，在所述写入控制端的提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段；
所述第一发光控制电路分别与发光控制端、第一电压端与所述驱动电路的第一端电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制端提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
所述第二发光控制电路分别与所述发光控制端、所述驱动电路的第二端与所述发光元件的第一极电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
所述发光元件的第二极与第二电压端电连接。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与所述初始化控制端、第二初始电压端和所述 发光元件的第一极电连接，用于在所述初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
可选的，所述第一初始化电路包括第一晶体管，所述补偿控制电路包括第二晶体管，所述开关控制电路包括第三晶体管；
所述第一晶体管的控制极与所述初始化控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的控制端电连接；
所述第二晶体管的控制极与所述补偿控制端电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
所述第三晶体管的控制极与所述开关控制端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述储能电路的第二端电连接。
可选的，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
所述存储电容的第一端为所述储能电路的第一端，所述存储电容的第二端为所述储能电路的第二端；
所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的控制极与所述写入控制端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
所述第五晶体管的控制极与所述发光控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的控制极与所述发光控制端电连接，所述第六晶体管的 第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述初始化控制端电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的像素电路，显示周期包括刷新帧和保持帧；所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；所述驱动方法包括：
在所述刷新帧和所述第一发光阶段，开关控制电路在开关控制信号的控制下，控制第一电压端与储能电路的第二端之间连通；
在所述第一重置阶段和所述第二重置阶段，所述开关控制电路在所述开关控制信号的控制下，控制所述第一电压端与所述储能电路的第二端之间断开，第一初始化电路在初始化控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的控制端；
在所述第二重置阶段，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，所述保持帧还包括设置于所述第二重置阶段和所述第一发光阶段之间的保持阶段；所述驱动方法还包括：
在所述保持阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，所述刷新帧包括先后设置的初始化阶段和补偿阶段；所述驱动方法还包括：
在所述初始化阶段，所述第一初始化电路在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端；
在所述补偿阶段，所述补偿控制电路在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，所述像素电路还包括数据写入电路、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段； 所述驱动方法还包括：
在所述补偿阶段，所述数据写入电路分在写入控制端的提供的写入控制信号的控制下，将数据线提供的数据电压写入所述驱动电路的第一端；
在所述第一发光阶段和所述第二发光阶段，所述第一发光控制电路在发光控制端提供的发光控制信号的控制下，控制第一电压端与所述驱动电路的第一端之间连通，所述第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
可选的，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
在所述初始化阶段、所述第一重置阶段和所述第二重置阶段，所述第二初始化电路在所述初始化控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的电路图；
图5是本公开如图4所示的像素电路的至少一实施例的工作时序图；
图6A是本公开如图4所示的像素电路的至少一实施例在初始化阶段的工作状态示意图；
图6B是本公开如图4所示的像素电路的至少一实施例在补偿阶段的工作状态示意图；
图6C是本公开如图4所示的像素电路的至少一实施例在第二发光阶段的工作状态示意图；
图7是本公开如图4所示的像素电路的至少一实施例的工作时序图；
图8A是本公开如图4所示的像素电路的至少一实施例在第一重置阶段 的工作状态示意图；
图8B是本公开如图4所示的像素电路的至少一实施例在第二重置阶段的工作状态示意图；
图8C是本公开如图4所示的像素电路的至少一实施例在保持阶段的工作状态示意图；
图8D是本公开如图4所示的像素电路的至少一实施例在第一发光阶段的工作状态示意图；
图9是本公开如图4所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1所示，本公开实施例所述的像素电路包括发光元件E0、驱动电路10、储能电路11、开关控制电路12、第一初始化电路13和补偿控制电路14；所述像素电路的显示周期包括刷新帧和保持帧，所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；
所述储能电路11的第一端与所述驱动电路10的控制端电连接，所述储能电路11用于储存电能；
所述开关控制电路12分别与开关控制端PG2、第一电压端V1和所述储能电路11的第二端电连接，用于在所述开关控制端PG2提供的开关控制信号的控制下，在所述刷新帧和所述第一发光阶段，控制所述第一电压端V1与所述储能电路11的第二端之间连通，在所述第一重置阶段和所述第二重置阶段，控制所述第一电压端V1与所述储能电路11的第二端之间断开；
所述第一初始化电路13分别与初始化控制端NR、第一初始电压端I1和所述驱动电路10的控制端电连接，用于在所述第一重置阶段和所述第二重置阶段，在所述初始化控制端NR提供的初始化控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vint1写入所述驱动电路10的控制端；
所述补偿控制电路14分别与补偿控制端NG、所述驱动电路10的控制端和所述驱动电路10的第二端电连接，用于在所述第二重置阶段，在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间连通；
所述驱动电路10与所述发光元件E0电连接，用于在其控制端的电位的控制下，产生驱动所述发光元件E0的驱动电流。
本公开如图1所示的像素电路的至少一实施例在工作时，在低频显示时，显示周期包括刷新帧和保持帧；所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；
在所述刷新帧和所述第一发光阶段，开关控制电路12在开关控制信号的控制下，控制第一电压端V1与储能电路11的第二端之间连通；
在所述第一重置阶段和所述第二重置阶段，所述开关控制电路12在所述开关控制信号的控制下，控制所述第一电压端V1与所述储能电路11的第二端之间断开，第一初始化电路13在初始化控制信号的控制下，将第一初始电压端I1提供的第一初始电压Vint1写入驱动电路10的控制端；
在所述第二重置阶段，补偿控制电路14在补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间连通。
本公开至少一实施例所述的像素电路在工作时，在低频显示时，在每个保持帧，在第一重置阶段和第二重置阶段，通过第一初始化电路13在初始化控制信号的控制下，将第一初始电压Vint1写入驱动电路10的控制端，以在每个保持帧的部分时间段，都对驱动电路10中的驱动晶体管的栅源电压进行复位重置，使得所述驱动晶体管处于OFF-Bias(截止偏置)状态，通过在每一帧对所述驱动晶体管进行复位，来减少驱动晶体管内捕获的电荷累积，改善低频驱动时画面切换时，第一帧亮度不足及短期残像。本公开至少一实施例所述的像素电路在工作时，在低频显示时，在每个保持帧，也能够对驱动晶体管的阈值电压进行补偿，也能补偿驱动晶体管的阈值电压不均一造成的画质/Mura(亮度不均匀)等问题。
在本公开至少一实施例中，所述刷新帧包括先后设置的初始化阶段和补偿阶段；
所述第一初始化电路用于在所述初始化阶段，在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端，以在补偿阶段开始时，所述驱动电路能够导通，以便进行阈值电压补偿；
所述补偿控制电路用于在所述补偿阶段，在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
本公开至少一实施例所述的像素电路还可以包括数据写入电路；
所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述补偿阶段，在所述写入控制端的提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端，以进行数据电压写入。
在本公开至少一实施例中，所述的像素电路还包括第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段；
所述第一发光控制电路分别与发光控制端、第一电压端与所述驱动电路的第一端电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制端提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
所述第二发光控制电路分别与所述发光控制端、所述驱动电路的第二端与所述发光元件的第一极电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
所述发光元件的第二极与第二电压端电连接。
在具体实施时，本公开至少一实施例所述的像素电路还可以包括第一发光控制电路和第二发光控制电路，在第一发光阶段和第二发光阶段，第一发光控制电路在发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通，第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通，驱动电路控制发光元件发光。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开 至少一实施例所述的像素电路还包括数据写入电路21、第一发光控制电路22和第二发光控制电路23；
所述数据写入电路21分别与写入控制端PG1、数据线D1和所述驱动电路10的第一端电连接，用于在所述补偿阶段，在所述写入控制端PG1的提供的写入控制信号的控制下，将所述数据线D1提供的数据电压写入所述驱动电路10的第一端；
所述第一发光控制电路22分别与发光控制端E1、第一电压端V1与所述驱动电路10的第一端电连接，用于在所述发光控制端E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路10的第一端之间连通；
所述第二发光控制电路23分别与所述发光控制端E1、所述驱动电路10的第二端与所述发光元件E0的第一极电连接，用于在所述发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E0的第一极之间连通；
所述发光元件E0的第二极与第二电压端V2电连接。
在图2所示的像素电路的至少一实施例中，第一节点A与所述驱动电路10的控制端电连接，第二节点B与所述储能电路11的第二端电连接，第三节点C与所述驱动电路10的第一端电连接。
在本公开至少一实施例中，所述第一电压端V1可以为高电压端，所述第二电压端V2可以为低电压端，但不以此为限。
本公开如图2所示的像素电路的至少一实施例在工作时，在低频显示时，所述像素电路的显示周期包括先后设置的刷新帧和保持帧，所述刷新帧包括享有设置的初始化阶段、补偿阶段和第二发光阶段；所述保持帧包括先后设置的第一重置阶段、第二重置阶段、保持阶段和第一发光阶段；
在所述刷新帧，所述开关控制电路12在所述开关控制端PG2提供的开关控制信号的控制下，控制所述第一电压端V1与所述储能电路11的第二端之间连通；
在所述初始化阶段，所述第一初始化电路13在所述初始化控制端NR提供的初始化控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vint1写入所述驱动电路10的控制端，以使得所述补偿阶段开始时，所述驱动电路10能够在其控制端的电位的控制下，控制所述驱动电路10的第一 端与所述驱动电路10的第二端之间连通；
在所述补偿阶段，数据写入电路在所述写入控制端PG1的提供的写入控制信号的控制下，将所述数据线D1提供的数据电压Vdata写入所述驱动电路10的第一端；所述补偿控制电路14在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间连通；
在所述补偿阶段开始时，所述驱动电路10在其控制端的电位的控制下，控制所述驱动电路10的第一端与所述驱动电路10的第二端之间连通，通过数据电压Vdata为所述储能电路11充电，以改变所述驱动电路10的控制端的电位，直至所述驱动电路10在其控制端的电位的控制下，控制所述驱动电路10的第一端与所述驱动电路10的第二端之间断开，此时，所述驱动电路10的控制端的电位为Vdata+Vth，其中，Vth为所述驱动电路10中的驱动晶体管的阈值电压；
在所述第二发光阶段，所述第一发光控制电路22在所述发光控制端E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路10的第一端之间连通，所述第二发光控制电路23在所述发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E0的第一极之间连通；驱动电路10驱动所述发光元件E0发光；在发光阶段，所述驱动电路10驱动所述发光元件E0的驱动的电流与Vth无关，能够补偿阈值电压偏移；
在所述保持帧中的第一重置阶段，所述开关控制电路12在所述开关控制端PG2提供的开关控制信号的控制下，控制所述第一电压端V1与所述储能电路11的第二端之间断开；所述第一初始化电路13在所述初始化控制端NR提供的初始化控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vint1写入所述驱动电路10的控制端，由于第二节点B处于浮空状态，第一节点A接入第一初始电压Vint1，通过所述储能电路11中的存储电容的耦合作用，第二节点B的电位也随着第一节点A的电位的改变而改变，Vdata+Vth仍然存储于所述存储电容中；
在所述保持帧的第二重置阶段，所述开关控制电路12在所述开关控制端PG2提供的开关控制信号的控制下，控制所述第一电压端V1与所述储能电 路11的第二端之间断开；数据写入电路21在所述写入控制端PG1的提供的写入控制信号的控制下，控制所述数据线D1与所述驱动电路10的第一端之间断开，不进行数据电压写入；所述第一初始化电路13在所述初始化控制端NR提供的初始化控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vint1写入所述驱动电路10的控制端，所述补偿控制电路14在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间连通；所述第三节点C处于浮空状态；
在所述第二重置阶段开始时，所述驱动电路10在其控制端的电位的控制下，控制所述驱动电路10的第一端与所述驱动电路10的第二端之间连通；通过驱动电路10、补偿控制电路14和第一初始化电路13向第一初始电压端I1放电，第三节点C的电位逐渐下降，直至所述驱动电路10在其控制端的电位的控制下，控制所述驱动电路10的第一端与所述驱动电路10的第二端之间断开，将所述驱动晶体管置于OFF-Bias状态，此时第一节点A的电位为Vint1，第三节点C的电位为Vint1-Vth，所述储能电路11依然保持Vdata+Vth；
在保持帧的保持阶段，所述补偿控制电路14在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间连通，此时所述驱动晶体管依然处于OFF-Bias状态，各节点的电位与第二重置阶段一致；
在保持帧的第一发光阶段，所述开关控制电路12在所述开关控制端PG2提供的开关控制信号的控制下，控制所述第一电压端V1与所述储能电路11的第二端之间连通；所述补偿控制电路14在所述补偿控制端NG提供的补偿控制信号的控制下，控制所述驱动电路10的控制端与所述驱动电路10的第二端之间段断开，所述第一发光控制电路22在所述发光控制端E1提供的发光控制信号的控制下，控制所述第一电压端V1与所述驱动电路10的第一端之间连通，所述第二发光控制电路23在所述发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E0的第一极之间连通；驱动电路10驱动所述发光元件E0发光；在发光阶段，所述驱动电路10驱动所述发光元件E0的驱动的电流与Vth无关，能够补偿阈值电压偏移。
本公开至少一实施例所述的像素电路在进行低频驱动时，在保持帧增加 重置时序，此时数据电压不进行刷新写入，通过在每一保持帧都对所述驱动晶体管的栅源电压进行复位重置，使得所述驱动晶体管处于OFF-Bias状态，通过在每一帧对所述驱动晶体管进行复位，来减少驱动晶体管内捕获的电荷累积，改善低频驱动画面切换时，第一帧亮度不足及短期残像的问题。
本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与所述初始化控制端、第二初始电压端和所述发光元件的第一极电连接，用于在所述初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光，确保所述发光元件的暗态亮度够暗，并清除所述发光元件的第一极残留的电荷。
如图3所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二初始化电路31；
所述第二初始化电路31分别与所述初始化控制端NR、第二初始电压端I2和所述发光元件E0的第一极电连接，用于在所述初始化控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vint2写入所述发光元件E0的第一极，以控制所述发光元件E0不发光，确保所述发光元件的暗态亮度够暗，并清除所述发光元件E0的第一极残留的电荷。
在本公开至少一实施例中，所述第一初始电压端I1和所述第二初始电压端I2可以为相同的初始电压端，所述初始电压端用于提供初始电压Vint，但不以此为限。
本公开如图3所示的像素电路的至少一实施例在工作时，在初始化阶段、第一重置阶段和第二重置阶段，所述第二初始化电路31在所述初始化控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vint2写入所述发光元件E0的第一极，
可选的，所述第一初始化电路包括第一晶体管，所述补偿控制电路包括第二晶体管，所述开关控制电路包括第三晶体管；
所述第一晶体管的控制极与所述初始化控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的控制端电连接；
所述第二晶体管的控制极与所述补偿控制端电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
所述第三晶体管的控制极与所述开关控制端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述储能电路的第二端电连接。
可选的，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
所述存储电容的第一端为所述储能电路的第一端，所述存储电容的第二端为所述储能电路的第二端；
所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
可选的，所述数据写入电路包括第四晶体管；
所述第四晶体管的控制极与所述写入控制端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
所述第五晶体管的控制极与所述发光控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
所述第六晶体管的控制极与所述发光控制端电连接，所述第六晶体管的第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
可选的，所述第二初始化电路包括第七晶体管；
所述第七晶体管的控制极与所述初始化控制端电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
在本公开至少一实施例中，所述发光元件为有机发光二极管，所述发光 元件的第一极为阳极，所述发光元件的第二极为阴极，但不以此为限。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，所述第一初始化电路13包括第一晶体管M1，所述补偿控制电路14包括第二晶体管M2，所述开关控制电路12包括第三晶体管M3；所述驱动电路10包括驱动晶体管DTFT；所述储能电路11包括存储电容C1；所述发光元件为有机发光二极管O1；
所述第一晶体管M1的栅极与所述初始化控制端NR电连接，所述第一晶体管M1的源极与初始电压端I0电连接，所述第一晶体管M1的漏极与所述驱动晶体管DTFT的栅极电连接；所述初始电压端I0用于提供初始电压Vint；
所述第二晶体管M2的栅极与所述补偿控制端NG电连接，所述第二晶体管M2的源极与所述驱动晶体管DTFT的栅极电连接，所述第二晶体管M2的漏极与所述驱动晶体管M0的漏极电连接；
所述第三晶体管M3的栅极与所述开关控制端PG2电连接，所述第三晶体管M3的源极与高电压端电连接，所述第三晶体管M3的漏极与所述存储电容C1的第二端电连接；所述高电压端用于提供高电压ELVDD；
所述存储电容C1的第一端与所述驱动晶体管DTFT的栅极电连接；
所述数据写入电路21包括第四晶体管M4；
所述第四晶体管M4的栅极与所述写入控制端PG1电连接，所述第四晶体管M4的源极与所述数据线D1电连接，所述第四晶体管M4的漏极与所述驱动晶体管DTFT的源极电连接；
所述第一发光控制电路22包括第五晶体管M5，所述第二发光控制电路23包括第六晶体管M6；
所述第五晶体管M5的栅极与所述发光控制端E1电连接，所述第五晶体管M5的源极与所述高电压端电连接，所述第五晶体管M5的漏极与所述驱动晶体管DTFT的源极电连接；
所述第六晶体管M6的栅极与所述发光控制端E1电连接，所述第六晶体管M6的源极与所述驱动晶体管DTFT的漏极电连接，所述第六晶体管M6的漏极与所述有机发光二极管O1的阳极电连接；
所述第二初始化电路31包括第七晶体管M7；
所述第七晶体管M7的栅极与所述初始化控制端NR电连接，所述第七晶体管M7的源极与所述初始电压端I0电连接，所述第七晶体管M7的漏极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电压端电连接；所述低电压端用于提供低电压ELVSS。
在图4所示的像素电路的至少一实施例中，所述第一初始电压端和所述第二初始电压端都为所述初始电压端I0，所述初始电压端I0用于提供初始电压Vint。
在图4所示的像素电路的至少一实施例为8T1C的LTPO像素电路，第一晶体管M1、第二晶体管M2和第七晶体管M7都为NMOS(N型金属-氧化物-半导体)晶体管，第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6都为PMOS(P型金属-氧化物-半导体)晶体管。
在图4所示的至少一实施例中，第一晶体管M1和第二晶体管M2为NMOS晶体管，以减小漏电流，利于保持驱动晶体管DTFT的栅极的电位。
在图4中，第一节点A与驱动晶体管DTFT的栅极电连接，第二节点B与C1的第二端电连接，第三节点C与驱动晶体管DTFT的源极电连接。
如图5所示，本公开如图4所示的像素电路的至少一实施例在工作时，刷新帧包括先后设置的初始化阶段S51、补偿阶段S52和第二发光阶段S53；
在初始化阶段S51，初始化控制端NR提供高电压信号，补偿控制端NG提供低电压信号，写入控制端PG1提供高电压信号，开关控制端PG2提供低电压信号，E1提供高电压信号，如图6A所示，第三晶体管M3打开，第一晶体管M1和第七晶体管M7打开，第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6和驱动晶体管DTFT关断，初始电压端I0提供初始电压Vint，第二节点B与高电压端之间连通，所述初始电压Vint写入第一节点A和有机发光二极管O1的阳极，对驱动晶体管DTFT的栅极的电位进行初始化，使得在所述补偿阶段S52开始时，驱动晶体管DTFT能够导通，并确保有机发光二极管O1的暗态亮度够暗；
在补偿阶段S52，初始化控制端NR提供低电压信号，补偿控制端NG提 供高电压信号，写入控制端PG1提供过低电压信号，开关控制端PG2提供低电压信号，E1提供高电压信号，如图6B所示，第二晶体管M2和第三晶体管M3导通，第一晶体管M1、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7都关断，数据线D1提供数据电压Vdata；
在补偿阶段S52开始时，驱动晶体管DTFT导通，数据电压Vdata通过第四晶体管M4、驱动晶体管DTFT和第二晶体管M2为C1充电，以提升第一节点A的电位，直至驱动晶体管DTFT关断，此时第一节点A的电位为Vdata+Vth，电压存储于C1中，其中，Vth为驱动晶体管DTFT的阈值电压；
在第二发光阶段S53，初始化控制端NR提供低电压信号，补偿控制端NG提供低电压信号，写入控制端PG1提供高电压信号，开关控制端PG2提供低电压信号，E1提供低电压信号，如图6C所示，第三晶体管M3导通，第五晶体管M5、驱动晶体管DTFT和第六晶体管M6都导通，第三节点C的电位为ELVDD，驱动晶体管DTFT驱动有机发光二极管O1发光，驱动晶体管DTFT驱动有机发光二极管O1发光的驱动电流与(Vdata-ELVDD)2成正比，该驱动电流与Vth无关，补偿了驱动晶体管的阈值电压偏移的问题；
在第二发光阶段S53，所述第一节点A的电位为Vdata+Vth，所述第二节点B的电位和所述第三节点C的电位为ELVDD。
在图6A、图6B和图6C中，圆圈代表相应的晶体管导通，叉号代表相应的晶体管关断。
如图7所示，本公开如图4所示的像素电路的至少一实施例在工作时，刷新帧包括先后设置的第一重置阶段S71、第二重置阶段S72、保持阶段S73和第一发光阶段S74；
在第一重置阶段S71，初始化控制端NR提供高电压信号，补偿控制端NG提供低电压信号，写入控制端PG1提供高电压信号，开关控制端PG2提供高电压信号，E1提供高电压信号，如图8A所示，第三晶体管M3关断，第一晶体管M1和第七晶体管M7导通，初始电压端I0提供初始电压Vint，将Vint写入第一节点A和有机发光二极管O1的阳极，由于第二节点B处于浮空状态，通过C1的耦合作用，第二节点B的电位随着所述第一节点A的电位改变，由于第三晶体管M3关断，则Vdata+Vth依然存储于C1中；在所 述第一重置阶段S71，第一节点A的电位为Vint，第二节点B的电位为ELVDD+(Vint-(Vdata+Vth))，第三节点C的电位为ELVDD；
在第二重置阶段S72，初始化控制端NR提供高电压信号，补偿控制端NG提供高电压信号，写入控制端PG1提供高电压信号，开关控制端PG2提供高电压信号，E1提供高电压信号，如图8B所示，第一晶体管M1和第七晶体管M7导通，第二晶体管M2导通，第三晶体管M3、第五晶体管M5、第六晶体管M6和第四晶体管M4关断，第三节点C处于浮空状态；
在所述第二重置阶段S72开始时，驱动晶体管DTFT导通，通过驱动晶体管DTFT、第二晶体管M2和第一晶体管M1向初始电压端I0放电，以使得第三节点C的电位由ELVDD逐渐下降，直至驱动晶体管DTFT关断，此时第三节点C的电位为Vint-Vth，驱动晶体管DTFT处于OFF-Bias状态，此时第一节点A的电位持续为Vint，C1依然保持Vdata+Vth；
在保持阶段S73，初始化控制端NR提供低电压信号，补偿控制端NG提供高电压信号，写入控制端PG1和开关控制端PG2都提供高电压信号，E1提供高电压信号，如图8C所示，第二晶体管M2导通，第一晶体管M1、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7都关断，驱动晶体管DTFT仍保持OFF-Bias状态，各节点的电压与第二重置阶段S72一致；
在所述第一发光阶段S74，初始化控制端NR提供低电压信号,补偿控制端NG提供低电压信号，写入控制端PG1和开关控制端PG2提供低电压信号，E1提供低电压信号，如图8D所示，第三晶体管M3、第五晶体管M5、第六晶体管M6和驱动晶体管DTFT导通，第一晶体管M1、第二晶体管M2、第四晶体管M4和第七晶体管M7都关断，驱动晶体管DTFT驱动有机发光二极管O1发光；
在第一发光阶段S74，第二节点B的电位重新为ELVDD，此时第一节点A处于浮空状态，通过C1的耦合作用，第一节点A的电位变为Vint+(ELVDD-(ELVDD+(Vint-(Vdata+Vth))))，也即第一节点A的电位为Vdata+Vth，流过有机发光二极管O1的电流正比于Vgs-Vth，也即，流过有机发光二极管O1的电流正比于(Vdata-ELVDD)2，流过有机发光二极管O1的电流与Vth 无关；其中，Vgs为驱动晶体管DTFT的栅源电压。
在图8A、图8B、图8C和图8D中，圆圈代表相应的晶体管导通，叉号代表相应的晶体管关断。
图9是图4所示的像素电路的至少一实施例的工作时序图。在图9中，标号为F1的为第一刷新帧，标号为F3的为第二刷新帧，标号为F21的为第一个第一保持帧，标号为F41的为第二个第一保持帧。当本公开如图4所示的像素电路的至少一实施例的刷新频率为60Hz时，一个显示周期可以包括刷新帧和59个保持帧，在第一个第一保持帧F21和第二刷新帧F3之间还设置有58个保持帧。
本公开实施例所述的驱动方法，应用于上述的像素电路，显示周期包括刷新帧和保持帧；所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；所述驱动方法包括：
在所述刷新帧和所述第一发光阶段，开关控制电路在开关控制信号的控制下，控制第一电压端与储能电路的第二端之间连通；
在所述第一重置阶段和所述第二重置阶段，所述开关控制电路在所述开关控制信号的控制下，控制所述第一电压端与所述储能电路的第二端之间断开，第一初始化电路在初始化控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的控制端；
在所述第二重置阶段，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
在本公开实施例所述的驱动方法中，在低频显示时，在所述保持帧，在第一重置阶段和第二重置阶段，通过第一初始化电路在初始化控制信号的控制下，将第一初始电压写入驱动电路的控制端，以在每个保持帧的部分时间段，都对驱动电路10中的驱动晶体管的栅源电压进行复位重置，使得所述驱动晶体管处于OFF-Bias(截止偏置)状态，通过在每一帧对所述驱动晶体管进行复位，来减少驱动晶体管内捕获的电荷累积，改善低频驱动画面切换时第一帧亮度不足及短期残像的问题。
可选的，所述保持帧还包括设置于所述第二重置阶段和所述第一发光阶段之间的保持阶段；所述驱动方法还包括：
在所述保持阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
在本公开至少一实施例中，所述刷新帧包括先后设置的初始化阶段和补偿阶段；所述驱动方法还包括：
在所述初始化阶段，所述第一初始化电路在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端，以对所述驱动电路的控制端的电位进行初始化；
在所述补偿阶段，所述补偿控制电路在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
可选的，所述像素电路还包括数据写入电路、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段；所述驱动方法还包括：
在所述补偿阶段，所述数据写入电路分在写入控制端的提供的写入控制信号的控制下，将数据线提供的数据电压写入所述驱动电路的第一端，以进行数据电压写入；
在所述第一发光阶段和所述第二发光阶段，所述第一发光控制电路在发光控制端提供的发光控制信号的控制下，控制第一电压端与所述驱动电路的第一端之间连通，所述第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光元件发光。
在本公开至少一实施例中，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
在所述初始化阶段、所述第一重置阶段和所述第二重置阶段，所述第二初始化电路在所述初始化控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极，以控制所述发光元件不发光。
本公开实施例所述的显示装置包括上述的像素电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通 技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种像素电路，包括发光元件、驱动电路、储能电路、开关控制电路、第一初始化电路和补偿控制电路；所述像素电路的显示周期包括刷新帧和保持帧，所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；所述储能电路的第一端与所述驱动电路的控制端电连接，所述储能电路用于储存电能；
    所述开关控制电路分别与开关控制端、第一电压端和所述储能电路的第二端电连接，用于在所述开关控制端提供的开关控制信号的控制下，在所述刷新帧和所述第一发光阶段，控制所述第一电压端与所述储能电路的第二端之间连通，在所述第一重置阶段和所述第二重置阶段，控制所述第一电压端与所述储能电路的第二端之间断开；
    所述第一初始化电路分别与初始化控制端、第一初始电压端和所述驱动电路的控制端电连接，用于在所述第一重置阶段和所述第二重置阶段，在所述初始化控制端提供的初始化控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述驱动电路的控制端；
    所述补偿控制电路分别与补偿控制端、所述驱动电路的控制端和所述驱动电路的第二端电连接，用于在所述第二重置阶段，在所述补偿控制端提供的补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通；
    所述驱动电路用于在其控制端的电位的控制下，产生驱动所述发光元件的驱动电流。
  2. 如权利要求1所述的像素电路，其中，所述刷新帧包括先后设置的初始化阶段和补偿阶段；
    所述第一初始化电路用于在所述初始化阶段，在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端；
    所述补偿控制电路用于在所述补偿阶段，在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
  3. 如权利要求2所述的像素电路，其中，还包括数据写入电路；
    所述数据写入电路分别与写入控制端、数据线和所述驱动电路的第一端电连接，用于在所述补偿阶段，在所述写入控制端的提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述驱动电路的第一端。
  4. 如权利要求3所述的像素电路，其中，还包括第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段；
    所述第一发光控制电路分别与发光控制端、第一电压端与所述驱动电路的第一端电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制端提供的发光控制信号的控制下，控制所述第一电压端与所述驱动电路的第一端之间连通；
    所述第二发光控制电路分别与所述发光控制端、所述驱动电路的第二端与所述发光元件的第一极电连接，用于在所述第一发光阶段和所述第二发光阶段，在所述发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通；
    所述发光元件的第二极与第二电压端电连接。
  5. 如权利要求1至4中任一权利要求所述的像素电路，其中，还包括第二初始化电路；
    所述第二初始化电路分别与所述初始化控制端、第二初始电压端和所述发光元件的第一极电连接，用于在所述初始化控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
  6. 如权利要求1所述的像素电路，其中，所述第一初始化电路包括第一晶体管，所述补偿控制电路包括第二晶体管，所述开关控制电路包括第三晶体管；
    所述第一晶体管的控制极与所述初始化控制端电连接，所述第一晶体管的第一极与所述第一初始电压端电连接，所述第一晶体管的第二极与所述驱动电路的控制端电连接；
    所述第二晶体管的控制极与所述补偿控制端电连接，所述第二晶体管的第一极与所述驱动电路的控制端电连接，所述第二晶体管的第二极与所述驱动电路的第二端电连接；
    所述第三晶体管的控制极与所述开关控制端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述储能电路的第二端电连接。
  7. 如权利要求1所述的像素电路，其中，所述储能电路包括存储电容，所述驱动电路包括驱动晶体管；
    所述存储电容的第一端为所述储能电路的第一端，所述存储电容的第二端为所述储能电路的第二端；
    所述驱动晶体管的控制极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
  8. 如权利要求3所述的像素电路，其中，所述数据写入电路包括第四晶体管；
    所述第四晶体管的控制极与所述写入控制端电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述驱动电路的第一端电连接。
  9. 如权利要求4所述的像素电路，其中，所述第一发光控制电路包括第五晶体管，所述第二发光控制电路包括第六晶体管；
    所述第五晶体管的控制极与所述发光控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述驱动电路的第一端电连接；
    所述第六晶体管的控制极与所述发光控制端电连接，所述第六晶体管的第一极与所述驱动电路的第二端电连接，所述第六晶体管的第二极与所述发光元件的第一极电连接。
  10. 如权利要求5所述的像素电路，其中，所述第二初始化电路包括第七晶体管；
    所述第七晶体管的控制极与所述初始化控制端电连接，所述第七晶体管的第一极与所述第二初始电压端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
  11. 一种驱动方法，应用于如权利要求1至10中任一权利要求所述的像 素电路，显示周期包括刷新帧和保持帧；所述保持帧包括先后设置的第一重置阶段、第二重置阶段和第一发光阶段；所述驱动方法包括：
    在所述刷新帧和所述第一发光阶段，开关控制电路在开关控制信号的控制下，控制第一电压端与储能电路的第二端之间连通；
    在所述第一重置阶段和所述第二重置阶段，所述开关控制电路在所述开关控制信号的控制下，控制所述第一电压端与所述储能电路的第二端之间断开，第一初始化电路在初始化控制信号的控制下，将第一初始电压端提供的第一初始电压写入驱动电路的控制端；
    在所述第二重置阶段，补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
  12. 如权利要求11所述的驱动方法，其中，所述保持帧还包括设置于所述第二重置阶段和所述第一发光阶段之间的保持阶段；所述驱动方法还包括：
    在所述保持阶段，所述补偿控制电路在补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
  13. 如权利要求11或12所述的驱动方法，其中，所述刷新帧包括先后设置的初始化阶段和补偿阶段；所述驱动方法还包括：
    在所述初始化阶段，所述第一初始化电路在所述初始化控制信号的控制下，将所述第一初始电压写入所述驱动电路的控制端；
    在所述补偿阶段，所述补偿控制电路在所述补偿控制信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第二端之间连通。
  14. 如权利要求13所述的驱动方法，其中，所述像素电路还包括数据写入电路、第一发光控制电路和第二发光控制电路；所述刷新帧还包括设置于所述补偿阶段之后的第二发光阶段；所述驱动方法还包括：
    在所述补偿阶段，所述数据写入电路分在写入控制端的提供的写入控制信号的控制下，将数据线提供的数据电压写入所述驱动电路的第一端；
    在所述第一发光阶段和所述第二发光阶段，所述第一发光控制电路在发光控制端提供的发光控制信号的控制下，控制第一电压端与所述驱动电路的第一端之间连通，所述第二发光控制电路在所述发光控制信号的控制下，控制所述驱动电路的第二端与发光元件的第一极之间连通，驱动电路驱动发光 元件发光。
  15. 如权利要求14所述的驱动方法，其中，所述像素电路还包括第二初始化电路；所述驱动方法还包括：
    在所述初始化阶段、所述第一重置阶段和所述第二重置阶段，所述第二初始化电路在所述初始化控制信号的控制下，将第二初始电压端提供的第二初始电压写入所述发光元件的第一极。
  16. 一种显示装置，包括如权利要求1至10中任一权利要求所述的像素电路。
PCT/CN2022/089515 2022-04-27 2022-04-27 像素电路、驱动方法和显示装置 WO2023206130A1 (zh)

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