WO2023185035A1 - 内存直接访问架构、系统、方法、电子设备和介质 - Google Patents

内存直接访问架构、系统、方法、电子设备和介质 Download PDF

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Publication number
WO2023185035A1
WO2023185035A1 PCT/CN2022/134792 CN2022134792W WO2023185035A1 WO 2023185035 A1 WO2023185035 A1 WO 2023185035A1 CN 2022134792 W CN2022134792 W CN 2022134792W WO 2023185035 A1 WO2023185035 A1 WO 2023185035A1
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Prior art keywords
descriptor
component
read
write
direct access
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PCT/CN2022/134792
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English (en)
French (fr)
Inventor
王洪良
牟奇
张德闪
刘伟
李仁刚
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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Priority to US18/724,096 priority Critical patent/US12277079B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of computer technology, and in particular to a memory direct access architecture, system, method, electronic device and medium.
  • PCI-Express peripheral component interconnect express
  • PCIE has two data transmission methods: 1. DMA (Direct Memory Access). In this mode, data transmission is not performed by The CPU (Central Processing Unit, central processing unit) is responsible for processing, which is completed by a special processor DMA controller, so it takes up very little CPU resources; 2. PIO (Programmed Input-Output, programmable input and output), In this mode, data transfer is processed by the CPU by executing I/O port instructions in byte or larger data units, which takes up a lot of CPU resources and the data transfer speed is much lower than that in DMA mode. Therefore, DMA mode is better than PIO mode.
  • DMA Direct Memory Access
  • the purpose of this application is to provide a memory direct access architecture, system, method, electronic device and medium, which improves the transmission efficiency of DMA.
  • this application provides a memory direct access architecture, which is applied to digital circuits and includes a memory direct access control component, a read data moving component, a write data moving component and a data storage component;
  • the memory direct access control component It includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transmission component, and a write command transmission component;
  • the control register is set to be set by the host to obtain descriptor address information;
  • the read descriptor storage component is set to Store the read descriptor obtained using the control register;
  • the write descriptor storage component is configured to store the write descriptor obtained using the control register;
  • the read command transmission component is configured to send the read descriptor based on the read descriptor or the read command obtained from the descriptor address information;
  • the write command transmission component is configured to send the write command obtained based on the read descriptor to the write data moving component;
  • the read data moving component is configured to execute the read command,
  • the write data moving component is
  • This application also provides an electronic device, which applies the above-mentioned memory direct access architecture.
  • This application also provides a memory direct access system, including a host and the above-mentioned electronic device, and the host and the electronic device are connected through a target bus.
  • This application also provides a memory direct access method, which is applied to the above-mentioned electronic device.
  • the method includes: if it is detected that the control register of the memory direct access control component is triggered, obtaining the descriptor address information; using the memory to directly access the memory.
  • the access control component generates a descriptor read command based on the descriptor address information; uses the read data moving component to execute the descriptor read command to obtain a descriptor, and writes the descriptor into the memory direct access control component.
  • a descriptor storage component using the memory direct access control component to generate an access command based on the descriptor; based on the type of the access command, using a read data moving component or a write data moving component to execute the access command.
  • This application also provides a computer-readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the above-mentioned direct memory access method is implemented.
  • the memory direct access architecture is applied to digital circuits and includes a memory direct access control component, a read data moving component, a write data moving component, and a data storage component;
  • the memory direct access control component includes a control register, a read descriptor storage component, Write descriptor storage component, read command transmission component, write command transmission component;
  • the control register is set to be set by the host to obtain descriptor address information;
  • the read descriptor storage component is set to store the read descriptor obtained by using the control register; write descriptor storage The component is configured to store the write descriptor obtained using the control register;
  • the read command transmission component is configured to send a read command based on the read descriptor or descriptor address information to the read data moving component;
  • the write command transmission component is configured to send the write data moving component Send the write command obtained based on the read descriptor;
  • the read data moving component is set to execute the read command, the write data moving component is set to execute the write command, and the data storage component is set to store the
  • the read data moving component and the writing data moving component are set up in this architecture, which are set up to execute read commands and write commands respectively.
  • the read descriptor storage component and the write descriptor storage component are also set up correspondingly, so that the digital circuit can read Write parallel processing.
  • the read data moving component can also execute the read command obtained from the descriptor address information, and can realize the moving of the descriptor. The same set of components can be used to complete the moving of the descriptor and data, saving hardware resources.
  • this application also provides a system, method, electronic device and medium, which also have the above beneficial effects.
  • Figure 1 is a schematic structural diagram of a memory direct access architecture provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a host memory provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a specific host memory provided by an embodiment of the present application.
  • Figure 4 is a schematic diagram of a data migration process provided by an embodiment of the present application.
  • Figure 5 is a flow chart of a memory direct access method provided by an embodiment of the present application.
  • Figure 6 is a host memory writing flow chart provided by an embodiment of the present application.
  • Figure 7 is a host memory reading flow chart provided by an embodiment of the present application.
  • chain DMA has problems with low transmission efficiency, including the inability to support out-of-order data reception when reading data, the inability to interconnect with a standard bus, the inability to perform parallel processing of reading and writing, and low bandwidth utilization.
  • this application proposes a new memory direct access architecture, which is applied to digital circuits.
  • it can be a field programmable logic gate array (Field Programmable Gate Array, FPGA) circuit, or it can be a digital integrated ( digital integrated circuit, digital IC) circuit.
  • the entire architecture includes a memory direct access control component, a read data moving component, a write data moving component and a data storage component.
  • the memory direct access control component further includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transmission component, Write command transfer component.
  • Figure 1 is a specific implementation, which shows the memory direct access control component DMA Descriptor Controller, the read data moving component PCIe Read DMA Data Mover, the write data moving component PCIe Write DMA Data Mover, and the data storage Components DDR&RAM.
  • the memory direct access control component further includes the control register Control Register, the read descriptor storage component Read Descriptor Table Slave, the write descriptor storage component Write Descriptor Table Slave, the read command transmission component Read DMA Control Source, and the write command transmission component Write DMA Control Source.
  • the control register is set to be set by the host to obtain the descriptor address information.
  • the host can set the register value of the control register so that the control register can locate the descriptor according to the written register value, that is, obtain the descriptor address, and then obtain the descriptor address from the host Read the descriptor from the memory to further perform DMA reading and writing based on the descriptor.
  • the control register (or can be called the DMA descriptor control register) is accessed through the BAR (Base Address register, base address register) space, for example, it can correspond to BAR0 of the PCIe bus.
  • the control register The address offset corresponding to the register can be 0x0000. It should be noted that the address offset can be set as needed, and there is no specific limit.
  • the structure of the control register can be as follows:
  • MSI Message Signal Interrupt
  • RC Root Complex
  • ED End Point
  • terminal device that is, the digital circuit in this application, for example, it can refer to the FPGA circuit.
  • R stands for Read and W stands for Write.
  • the read descriptor storage component and the write descriptor storage component are first-in-first-out memories, and the read descriptor storage component and the write descriptor storage component have predefined storage addresses.
  • FIFO is First Input First Output, first in first out queue, or first in first out memory.
  • the descriptor is stored in the FIFO in the digital circuit, and the FIFO is given an address so that it can be identified by the address. , so that the digital circuit can be interconnected with a standard bus to facilitate development.
  • the control register includes a source address register, a destination address register, a descriptor size register, and a trigger register, where the destination address register is set to store any storage address.
  • control register structure is:
  • the starting address offset of the DMA descriptor control register is set to 0x0100.
  • the address offset can also be set as needed, and there is no specific limit.
  • RC Write Status and Descriptor Base (Low) and RC Write Status and Descriptor Base (High), or RC Read Status and Descriptor Base (Low) and RC Read Status and Descriptor Base (High), constitute the descriptor address information, according to The descriptor address information can locate the read descriptor or write descriptor and then read it.
  • the memory direct access control component can generate the corresponding read command or write command based on the descriptor or descriptor address information.
  • the read data movement component and the write data movement component also have controllers, such as the Read DMA Data Master and Write DMA in Figure 1 Data Master, set to control instruction execution.
  • this application is provided with a read descriptor storage component and a write descriptor storage component, wherein the read descriptor storage component is configured to store the read descriptor obtained using the control register, and the write descriptor storage component is configured to Stores the write descriptor obtained using the control register.
  • the read descriptor is a descriptor that instructs the digital circuit to read data from the host to itself
  • the write descriptor is a descriptor that instructs the digital circuit to write its own data to the host.
  • Working in conjunction with the two are the read command transmission component and the write command transmission component.
  • the read command transmission component is configured to send the read command based on the read descriptor or the read command based on the descriptor address information to the read data moving component. It can be understood that the read command obtained based on the descriptor address information is set as a command to read the descriptor. In this way, the same set of components can be used to complete the movement of the descriptor and data, saving hardware resources.
  • the write command transmission component is configured to send the write command obtained based on the read descriptor to the write data moving component.
  • it also includes a read data moving component and a write data moving component.
  • the read data moving component is configured to execute the read command
  • the write data moving component is configured to execute the write command
  • the data storage component is configured to store the read data obtained after the read command is executed.
  • the descriptors are stored in the host in advance.
  • the host has a descriptor table in the memory.
  • the descriptor table has space to store a certain number of descriptors. The specific number is not limited. For example, it can be 128, each descriptor.
  • the space size corresponding to the symbol is not limited, for example, it can be 8 words, or it can be 32 bytes.
  • the descriptor table may also include a state table corresponding to each descriptor.
  • the data in the state table can be updated according to the execution status of the descriptor. When the host needs it, it can Read the data in the status table to determine the execution status of each descriptor. If necessary, you can update the descriptors that have been executed so that the digital circuit can continuously read and write data to improve efficiency.
  • Figure 2 shows a host memory structure.
  • the host memory adopts a state table + descriptor table.
  • the form is preceded by a status table and followed by a descriptor table.
  • the address of the status table can be RC Write Status and Descriptor Base or RC Read Status and Descriptor Base address.
  • the address of the descriptor table is the base address + offset address
  • the offset address is the overall size of the status table.
  • the offset address is 0x200.
  • There are 31 bits in each status table as reserved operation bits (reserved), and the other is an identification operation bit (done).
  • the identification operation bit is used to indicate the execution status of the corresponding descriptor.
  • the structure of the read descriptor is not limited and can be set as needed.
  • the structure of the read descriptor may be:
  • the structure of the write descriptor can be:
  • Figure 4 is a schematic diagram of a data moving process provided by an embodiment of the present application, specifically moving three data blocks from the host memory to the FPGA bus address space.
  • each entry in the state table is 4 bytes, and 128 entries requires 512 bytes of memory; each The size of the descriptor is 32 bytes. Taking Figure 2 and Figure 3 as an example, three descriptors require 96 bytes of memory, so the total memory allocation for the status table and descriptor table is 608 bytes.
  • the host allocates 608 bytes of memory in the PCI Express address space.
  • the starting address of the allocated memory can be 0xf000_0000, and this address is written into the Root Complex Read Status and Descriptor register.
  • the base address is 0xf000_0000
  • the address of the first descriptor is the base address + offset address, that is, 0xf000_0000+0x200. Therefore, the high 32bit source address 0 is written in 0xf000_0204 of the host memory space, and the low 32bit is written in 0xf000_0200.
  • Source address 0x1000_0000 write the high 32bit destination address 0 in 0xf000_0200c, write the low 32bit destination address 0x5000_0000 in 0xf000_0208, write 0x0000_4000 in 0xf000_0210, send 16Kdwords (64KB), the descriptor ID is 0, complete the first description specific settings of the symbol. Repeat this step twice to complete the settings of the remaining two descriptors. The completed rendering is shown in Figure 3.
  • the host configures the control register through bar0 so that the control register reads the read status descriptor base address.
  • a 64-bit address can be used. That is, the host writes 0x0000_0000-high 32bit read status descriptor base address in 0x0000_0004, and writes 0xF000_0000-low 32bit read status descriptor base address in 0x0000_0000.
  • the digital circuit can get the descriptor address based on +0x200.
  • the host configures the FIFO address of the control register through bar0. Since the FIFO itself has no concept of address, in order to adapt it to the standard bus, when using the FIFO of the bus interface, the address of the FIFO needs to be defined. Specifically, you can write 0x0000_0000-high 32bitFIFO address in 0x0000_000C, and write 0x0100_0000-low 32bitFIFO address in 0x0000_0008. At this time, the corresponding address of the FIFO on the FPGA internal bus is 0x0100_0000.
  • the host writes the register RD_DMA_LAST_PTR, that is, writes 0x2 at 0x0000_0010, indicating that there are 3 descriptors in total.
  • the host writes an arbitrary value at 0x0000_001c in order to start the DMA operation of the digital circuit.
  • the memory direct access control component is configured to receive the move completion notification sent by the read data moving component and the write data moving component.
  • the DMA Descriptor Controller includes Read DMA Status Sink (which can be called the read status acquisition component) and Write DMA Status Sink (which can be called the write status acquisition component), which are respectively related to the Read DMA Status Source (read status Generate component) and Write DMA Status Source (write status generation component) are connected.
  • the memory direct access control component includes a status update component, such as the Status&MSI component in Figure 1.
  • the status update component is set to update the target status bit data corresponding to the target descriptor in the host's system memory after detecting that the target descriptor has been executed. Specifically, it can update the target status bit data in the target status table corresponding to the target descriptor in the host through the TX Slave (can be called the status and interrupt reporting part) in the Reg&Status&MSI Manager (which can be called the status and interrupt management component) .
  • the MWr write data packet can be generated through the TX Slave and sent to the host through the PCIe bus.
  • two independent memory spaces can be divided at the host, which are used to store read descriptors and corresponding state tables, and write descriptors and The corresponding status table.
  • the digital circuit can send an interrupt signal, and the host can determine whether the reading or writing is completed by judging which state table in the memory space is in the completion state.
  • the memory direct access control component includes an interrupt reporting component, and the interrupt reporting component is configured to send an interrupt message to the host after detecting that the target descriptor has been executed.
  • the TX Slave in the Reg&Status&MSI Manage can be called the status and interrupt management component
  • the Status&MSI component in the DMA Descriptor Controller can be used as an interrupt reporting component and is generated in conjunction with the TX Slave.
  • MWr writes the data packet and sends it to the host through the PCIe bus, which has the effect of interrupt reporting. It can be understood that the contents of the MWr write data packets corresponding to interrupt reporting and status bit data update are different.
  • each read data packet may be obtained in another order that does not follow the reading order. In order to avoid data errors, it is usually only read at a time. A data packet, which will prevent the bandwidth from being fully utilized.
  • the memory direct access architecture in this application also includes a first-in first-out buffer, and the first-in first-out buffer is set to cache the read data packets obtained after the read command is executed.
  • each read data packet includes a data packet tag corresponding to the read command, and the read data packets are arranged in sequence according to the data packet tags to obtain the read data.
  • each data packet By caching multiple data packets in the first-in first-out buffer, and using the data packet tags obtained according to the read command when reading the data packets, each data packet can be sorted and stored, so that multiple data packets can be read at the same time. Data packets, making full use of the bandwidth effect.
  • the direct memory access architecture can include Communication component of the target bus connection.
  • the communication component is configured to send the first data packet to the target bus, or is configured to obtain the second data packet from the target bus, and send the second data packet to the corresponding component based on the data packet type of the second data packet.
  • the first data packet refers to any kind of data packet that the digital circuit can generate, such as a write data packet, or it can be a terminal data packet.
  • the second data packet refers to any type of data packet obtained from the host, such as a read data packet. Please refer to Figure 1.
  • the Schedule in Figure 1 ie AXI-ST Schedule, indicating the communication component based on the AXI bus
  • AXI-ST Schedule indicating the communication component based on the AXI bus
  • the above-mentioned digital circuit can work alone as a device, or can be integrated into other electronic devices, that is, the electronic device can apply the above-mentioned direct memory access architecture.
  • the electronic device can be connected to the host through a target bus, such as a PCIe bus, and together form a memory direct access system.
  • Figure 5 is a flow chart of a direct memory access method provided by an embodiment of the present application.
  • the method includes:
  • S102 Utilize the memory direct access control component to generate a descriptor read command based on the descriptor address information.
  • S103 Use the read data moving component to execute the descriptor read command to obtain the descriptor, and write the descriptor into the descriptor storage component of the memory direct access control component. It should be noted that the number of descriptors is not limited, and the type can be read descriptor and/or write descriptor.
  • S104 Utilize the memory to directly access the control component and generate access commands based on the descriptor.
  • S105 Based on the type of the access command, use the read data moving component or the writing data moving component to execute the access command.
  • the access command may be a read command or a write command.
  • Figure 6 is a host memory writing flow chart provided by an embodiment of the present application, which includes the following steps:
  • the host CPU sets the DMA descriptor control register and starts the DMA process.
  • the control register commands the read data mover to obtain the descriptors in the descriptor table in the host computer (i.e. host).
  • the control register commands the write data mover to transfer data.
  • the write data mover fetches data from the FPGA's DDR (Double Data Rate, double rate synchronous dynamic random access memory) or ram (Random Access Memory, random access memory) to form a MWr (storage write) TLP package. Move the data to the Host system memory.
  • DDR Double Data Rate, double rate synchronous dynamic random access memory
  • ram Random Access Memory, random access memory
  • the control register sends an MSI interrupt to the host.
  • Figure 7 is a host memory reading flow chart provided by an embodiment of the present application, which includes the following steps:
  • the host CPU sets the DMA descriptor control register and starts the DMA process.
  • the control register commands the read data mover to obtain the descriptors in the descriptor table in the host computer.
  • the control register commands the read data mover to send an MRd (memory read) TLP packet.
  • Each TLP packet has a tag (that is, a packet tag), and the tag is generated based on message management.
  • the read data mover moves the data from the Host system memory to the FPGA, and uses 16 FIFOs (i.e. first-in, first-out buffers) to receive CplD (read data packets). Each read data packet has a corresponding tag, and is processed based on the tag. Data sequencing processing, writing data to the corresponding bus.
  • the read data mover uses a done bit notification to send it to the control register to notify the control register to complete the data transfer.
  • the control register sends an MSI interrupt to the host.
  • a read data moving component and a writing data moving component are set up to execute read commands and write commands respectively.
  • a read descriptor storage component and a write descriptor storage component are respectively set up. components that enable digital circuits to read and write in parallel.
  • the read data moving component can also execute the read command obtained from the descriptor address information, and can realize the moving of the descriptor. The same set of components can be used to complete the moving of the descriptor and data, saving hardware resources.
  • the electronic device provided by the embodiment of the present application is introduced below.
  • the electronic device described below and the memory direct access method described above can be mutually referenced.
  • the electronic device 100 applies the above-mentioned direct memory access architecture.
  • the electronic device 100 may specifically include a processor 101 and a memory 102, and may further include a multimedia component 103, an information input/output (I/O) interface 104 and a communication component.
  • a multimedia component 103 may further include a multimedia component 103, an information input/output (I/O) interface 104 and a communication component.
  • I/O information input/output
  • 105 One or more of 105.
  • the processor 101 is configured to control the overall operation of the electronic device 100 to complete all or part of the steps in the above-mentioned direct memory access method;
  • the memory 102 is configured to store various types of data to support operations on the electronic device 100.
  • the data may include, for example, instructions for any application or method operating on the electronic device 100, as well as application-related data.
  • the memory 102 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (Read- Only Memory (ROM), magnetic memory, flash memory, one or more of magnetic disks or optical disks.
  • SRAM static random access memory
  • EEPROM Electrically erasable programmable read-only memory
  • EPROM Erasable Programmable Read-Only Memory
  • PROM Programmable Read-Only Memory
  • ROM Read-Only Memory
  • magnetic memory flash memory, one or more of magnetic disks or optical disks.
  • Multimedia components 103 may include screen and audio components.
  • the screen may be a touch screen, for example, and the audio component is configured to output and/or input audio signals.
  • the audio component may include a microphone configured to receive external audio signals.
  • the received audio signals may be further stored in memory 102 or sent via communication component 105 .
  • the audio component also includes at least one speaker configured to output audio signals.
  • the I/O interface 104 provides an interface between the processor 101 and other interface modules.
  • the other interface modules may be keyboards, mice, buttons, etc. These buttons can be virtual buttons or physical buttons.
  • the communication component 105 is configured to perform wired or wireless communication between the electronic device 100 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G or 4G, or one or a combination of them, so the corresponding communication component 105 may include: Wi-Fi parts, Bluetooth parts, NFC parts.
  • the electronic device 100 may be configured by one or more application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), digital signal processor (Digital Signal Processor, DSP for short), digital signal processing device (Digital Signal Processing Device, DSPD for short), Programmable Logic Device (PLD for short), Field Programmable Gate Array (FPGA for short), controller, microcontroller, microprocessor or other electronic components are implemented for executing the above embodiments Direct memory access method given.
  • ASIC Application Specific Integrated Circuit
  • DSP Digital Signal Processor
  • DSPD Digital Signal Processing Device
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • the computer-readable storage medium provided by the embodiment of the present application is introduced below.
  • the computer-readable storage medium described below and the memory direct access method described above can be mutually referenced.
  • This application also provides a computer-readable storage medium.
  • a computer program is stored on the computer-readable storage medium.
  • the steps of the above-mentioned direct memory access method are implemented.
  • the computer-readable storage medium can include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, etc., which can store program code medium.
  • RAM random access memory
  • ROM read-only memory
  • electrically programmable ROM electrically erasable programmable ROM
  • registers hard disks, removable disks, CD-ROMs, or anywhere in the field of technology. any other known form of storage media.

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Abstract

本申请公开了内存直接访问架构，包括内存直接访问控制部件、读数据搬移部件、写数据搬移部件和数据存储部件；内存直接访问控制部件包括控制寄存器、读描述符存储部件、写描述符存储部件、读命令传输部件、写命令传输部件；控制寄存器设置为被主机设置得到描述符地址信息；读描述符存储部件设置为存储利用控制寄存器得到的读描述符；写描述符存储部件设置为存储利用控制寄存器得到的写描述符；读命令传输部件设置为向读数据搬移部件发送基于读描述符或描述符地址信息得到的读命令；写命令传输部件设置为向写数据搬移部件发送基于读描述符得到的写命令；读数据搬移部件设置为执行读命令，写数据搬移部件设置为执行写命令；该架构能够读写并行处理，效率高。

Description

内存直接访问架构、系统、方法、电子设备和介质
相关申请的交叉引用
本申请要求于2022年4月2日提交中国专利局，申请号为202210340235.X，申请名称为“内存直接访问架构、系统、方法、电子设备和介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种内存直接访问架构、系统、方法、电子设备和介质。
背景技术
PCI-Express(peripheral component interconnect express)是一种高速串行计算机扩展总线标准，PCIE具有两种数据传输方式：1、DMA(Direct Memory Access，直接内存访问)，在该模式下，数据传送不是由CPU(Central Processing Unit，中央处理器)负责处理，而是由一个特殊的处理器DMA控制器来完成，因此占用极少的CPU资源；2、PIO(Programmed Input-Output，可编程输入输出)，在该模式下，数据传送由CPU执行I/O端口指令来按照字节或更大的数据单位来处理，占用大量的CPU资源，数据传输速度也大大低于DMA模式。故此，DMA模式优于PIO模式。
目前实现DMA的方式是有两种，链式DMA与块DMA方式。在DMA传输数据的过程中，要求源物理地址和目标物理地址必须是连续的。但是在某些计算机体系中，连续的存储器地址在物理上不一定是连续的，所以DMA传输要分成多次完成。如果在传输完一块物理上连续的数据后引起一次中断，然后再由主机进行下一块物理上连续的数据传输，则为块DMA方式。链式DMA方式则不同，它使用一个链表描述物理上不连续的存储空间，然后把链表首地址告诉DMA控制器。DMA控制器在传输完一块物理连续的数据后，不用发起中断，而是根据链表来传输下一块物理上连续的数据，直到传输完毕后再发起一次中断。然而，当前链式DMA的传输效率仍较低。
因此，相关技术存在的链式DMA的传输效率仍较低的问题，尚未提出有效的解决方案。
发明内容
有鉴于此，本申请的目的在于提供一种内存直接访问架构、系统、方法、电子设备和介质，提高了DMA的传输效率。
为解决上述技术问题，本申请提供了一种内存直接访问架构，应用于数字电路，包括内存直接访问控制部件、读数据搬移部件、写数据搬移部件和数据存储部件；所述内存直接访问控制部件包括控制寄存器、读描述符存储部件、写描述符存储部件、读命令传输部件、写命令传输部件；所述控制寄存器设置为被主机设置得到描述符地址信息；所述读描述符存储部件设置为存储利用控制寄存器得到的读描述符；所述写描述符存储部件设置为存储利用控制寄存器得到的写描述符；所述读命令传输部件设置为向所述读数据搬移部件发送基于读描述符或所述描述符地址信息得到的读命令；所述写命令传输部件设置为向所述写数据搬移部件发送基于读描述符得到的写命令；所述读数据搬移部件设置为执行所述读命令，所述写数据搬移部件设置为执行所述写命令，所述数据存储部件设置为存储所述读命令执行后得到的读数据。
本申请还提供了一种电子设备，所述电子设备应用了上述的内存直接访问架构。
本申请还提供了一种内存直接访问系统，包括主机和上述的电子设备，所述主机和所述电子设备通过目标总线连接。
本申请还提供了一种内存直接访问方法，应用于上述的电子设备，所述方法包括：若检测到内存直接访问控制部件的控制寄存器被触发，则获取描述符地址信息；利用所述内存直接访问控制部件，基于所述描述符地址信息生成描述符读命令；利用读数据搬移部件执行所述描述符读命令，得到描述符，并将所述描述符写入所述内存直接访问控制部件的描述符存储部件；利用所述内存直接访问控制部件，基于所述描述符生成访问命令；基于所述访问命令的种类，利用读数据搬移部件或写数据搬移部件执行所述访问命令。
本申请还提供了一种计算机可读存储介质，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现上述的内存直接访问方法。
本申请提供的内存直接访问架构，应用于数字电路，包括内存直接访问控制部件、读数据搬移部件、写数据搬移部件和数据存储部件；内存直接访问控制部件包括控制寄存器、读描述符存储部件、写描述符存储部件、读命令传输部件、写命令传输部件；控制寄存器设置为被主机设置得到描述符地址信息；读描述符存储部件设置为存储利用控制寄存器得到的读描述符；写描述符存储部件设置为存储利用控制寄存器得到的写描述符；读命令传输部件设 置为向读数据搬移部件发送基于读描述符或描述符地址信息得到的读命令；写命令传输部件设置为向写数据搬移部件发送基于读描述符得到的写命令；读数据搬移部件设置为执行读命令，写数据搬移部件设置为执行写命令，数据存储部件设置为存储读命令执行后得到的读数据。
可见，该架构中设置了读数据搬移部件和写数据搬移部件，分别设置为执行读命令和写命令，此外还分别对应设置了读描述符存储部件和写描述符存储部件，使得数字电路能够读写并行处理。此外，读数据搬移部件还能够执行描述符地址信息得到的读命令，能够实现对描述符的搬移，利用同一套部件完成对描述符以及数据的搬移，节省硬件资源。
此外，本申请还提供了一种系统、方法、电子设备和介质，同样具有上述有益效果。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请实施例提供的一种内存直接访问架构的结构示意图；
图2为本申请实施例提供的一种主机内存的结构示意图；
图3为本申请实施例提供的一种具体的主机内存的机构示意图；
图4为本申请实施例提供的一种数据搬移的过程示意图；
图5为本申请实施例提供的一种内存直接访问方法的流程图；
图6为本申请实施例提供的一种主机内存写入流程图；
图7为本申请实施例提供的一种主机内存读取流程图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
当前，链式DMA存在传输效率较低的问题，具体包括在读取数据时不支持数据乱序接 收、无法与标准总线互连、无法进行读写并行处理、带宽利用率较低等问题。
为了解决上述问题，本申请提出了一种新的内存直接访问架构，该架构应用于数字电路，具体可以为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)电路，或者可以为数字集成(digital integrated circuit，数字IC)电路。整个架构包括内存直接访问控制部件、读数据搬移部件、写数据搬移部件和数据存储部件，内存直接访问控制部件进一步包括控制寄存器、读描述符存储部件、写描述符存储部件、读命令传输部件、写命令传输部件。
请参考图1，图1为一种具体的实施方式，其中示出了内存直接访问控制部件DMA Descriptor Controller，读数据搬移部件PCIe Read DMA Data Mover，写数据搬移部件PCIe Write DMA Data Mover，数据存储部件DDR&RAM。内存直接访问控制部件进一步包括控制寄存器Control Register、读描述符存储部件Read Descriptor Table Slave、写描述符存储部件Write Descriptor Table Slave、读命令传输部件Read DMA Control Source、写命令传输部件Write DMA Control Source。
其中，控制寄存器设置为被主机设置得到描述符地址信息，具体的，主机能够设置控制寄存器的寄存器值，使得控制寄存器能够根据写入的寄存器值定位描述符，即得到描述符地址，进而从主机内存中读出描述符，以便进一步根据描述符执行DMA读写。在一种实施方式中，控制寄存器(或者可以称为DMA描述符控制寄存器)通过BAR(Base Address register，基地址寄存器)空间访问，例如可以对应于PCIe总线的BAR0，在这种情况下，控制寄存器对应的地址偏移量可以为0x0000，需要注意的是，该地址偏移量可以根据需要进行设置，具体不做限定。
在一种实施方式中，控制寄存器的结构可以如下所示：
表1读状态控制寄存器的结构示意图
Figure PCTCN2022134792-appb-000001
其中，MSI为Message Signal Interrupt，是PCIe设备通过写一个特定消息到特定地址，从而触发一个处理器中断的机制。RC，Root Complex，根组件，通常指主机，ED，End Point，终端设备，即本申请中的数字电路，例如可以指FPGA电路。R表示读(Read)，W表示写(Write)。
在一种实施方式中，读描述符存储部件和写描述符存储部件为先入先出存储器，读描述符存储部件和写描述符存储部件被预先定义了存储地址。FIFO为First Input First Output，先入先出队列，或称为先入先出存储器，在该实施方式中，描述符在数字电路中被存放于FIFO中，并为FIFO赋予地址，使得其能够被地址标识，以便使得该数字电路能够与标准总线互连，便于开发。相应的，控制寄存器包括源地址寄存器、目的地址寄存器、描述符大小寄存器、触发寄存器，其中，目的地址寄存器设置为存储任一存储地址。
需要说明的是，上述的示例为读取读描述符时的配置，在读取写描述符时，该控制寄存器结构为：
表2写状态控制寄存器结构示意图
Figure PCTCN2022134792-appb-000002
二者区别在于，在该状态下，DMA描述符控制寄存器的起始地址偏移量被设置为0x0100，当然，该地址偏移量同样可以根据需要进行设置，具体不做限定。
其中，RC Write Status and Descriptor Base(Low)和RC Write Status and Descriptor Base(High)，或者RC Read Status and Descriptor Base(Low)和RC Read Status and Descriptor Base(High)，构成描述符地址信息，根据该描述符地址信息，能够定位读描述符或写描述符，进而进行读取。
内存直接访问控制部件能够根据描述符或者描述符地址信息生成对应的读命令或写命令，读数据搬移部件和写数据搬移部件中同样具有控制器，例如图1中的Read DMA Data Master和Write DMA Data Master，设置为控制指令执行。为了能够实现读写并行处理，本申请设置有读描述符存储部件和写描述符存储部件，其中，读描述符存储部件设置为存储利用控制寄存器得到的读描述符，写描述符存储部件设置为存储利用控制寄存器得到的写描述符。读描述符为指示数字电路从主机中读取数据到自身的描述符，写描述符为指示数字电路将自身的数据写入到主机中的描述符。与二者相配合工作的是读命令传输部件和写命令传输部件，读命令传输部件设置为向读数据搬移部件发送基于读描述符得到的读命令，或者基于描述符地址信息得到的读命令，可以理解的是，基于描述符地址信息得到的读命令即设置为读取描述符的命令，通过该方式，可以利用同一套部件完成对描述符以及数据的搬移，节省 硬件资源。写命令传输部件设置为向写数据搬移部件发送基于读描述符得到的写命令。此外，还包括读数据搬移部件和写数据搬移部件，读数据搬移部件设置为执行读命令，写数据搬移部件设置为执行写命令，数据存储部件设置为存储读命令执行后得到的读数据。
具体的，描述符预先存储在主机中，具体的，主机内存中具有描述符表，描述符表具有存储若干数量的描述符的空间，具体数量不做限定，例如可以为128个，每个描述符对应的空间大小不做限定，例如可以为8个word，或者可以为32个字节。此外，在另一种实施方式中，描述符表中还可以存在与各个描述符分别一一对应的状态表，状态表中的数据能够根据描述符的执行情况进行更新，在主机需要时，能够读取状态表中的数据，确定各个描述符的执行情况，在必要时，可以更新已经被执行完毕的描述符，以便数字电路能够连续不断地进行数据读写，提高效率。
本实施例并不限定状态表和描述符表的具体形式，在一种实施方式中，请参考图2，图2示出了一种主机内存结构，主机内存中采用状态表+描述符表的形式，前面是状态表，后面是描述符表。状态表的地址可以为RC Write Status and Descriptor Base或者RC Read Status and Descriptor Base地址，在这种情况下，描述符表的地址即为基地址+偏移地址，偏移地址与状态表的总体大小相关，例如图2所示，当有128个状态表，每个状态表32个比特位时，偏移地址为0x200。每个状态表中有31个比特位为预留操作位(reserved)，另一个为标识操作位(done)，标识操作位用于表示对应的描述符的执行状态。
描述符的具体结构不做限定，可以根据需要进行设置。具体的，在一种实施方式中，读描述符的结构可以为：
表3读描述符结构示意图
Figure PCTCN2022134792-appb-000003
相应的，写描述符的结构可以为：
表4写描述符结构示意图
Figure PCTCN2022134792-appb-000004
描述符的具体内容不做限定，可以根据实际需要进行设置，例如请参考图3，图3中示出了三个描述符的具体内容，即descriptor 0、descriptor 1和descriptor 2。请参考图4，图4为本申请实施例提供的一种数据搬移的过程示意图，具体为将三个数据块从主机内存移动到FPGA总线地址空间。
为了完成该操作，主机首先需要计算需要分配所需的内存空间大小，在一种实施方式中，每个状态表中的条目为4字节，128个条目即需要512字节的内存；每个描述符的大小为32个字节，以图2和图3为例，三个描述符需要96字节的内存，因此状态表和描述符表的总内存分配为608字节。
然后，主机在PCI Express地址空间中分配608字节的内存，具体的，分配内存的起始地址可以是0xf000_0000，将此地址写入Root Complex Read Status and Descriptor寄存器中。基地址为0xf000_0000，那么第一个描述符的地址即为基地址+偏移地址，即0xf000_0000+0x200，因此在主机内存空间的0xf000_0204中写入高32bit源地址0，在0xf000_0200中写入低32bit源地址0x1000_0000，在0xf000_0200c中写入高32bit目的地址0，在0xf000_0208中写入低32bit目的地址0x5000_0000，在0xf000_0210中写入0x0000_4000发送16Kdwords(64KB)，描述符ID为0，完成对第一个描述符的具体设置。重复该步骤两次，完成剩余两个描述符的设置，完成后的效果图即为图3。
主机通过bar0配置控制寄存器，以便控制寄存器读取读状态描述符基地址，具体可以使用64位地址。即主机在0x0000_0004中写入0x0000_0000-高32bit读状态描述符基地址，并在0x0000_0000中写入0xF000_0000-低32bit读状态描述符基地址。数字电路能够在此基础上+0x200得到描述符地址。
进一步的，主机通过bar0配置控制寄存器的FIFO地址，由于FIFO本身没有地址的概念，为了使其能够适配标准总线，在使用总线接口的FIFO时，需要定义该FIFO的地址。具体的，可以在0x0000_000C中写入0x0000_0000-高32bitFIFO地址，并在0x0000_0008中写入0x0100_0000-低32bitFIFO地址。此时，该FIFO在FPGA内部总线上对应的地址为0x0100_0000。
然后，主机写寄存器RD_DMA_LAST_PTR，即在0x0000_0010写入0x2，表示共有3个描述符。
最后，主机在0x0000_001c写入任意值，以便启动数字电路的DMA操作。
在上述的内存直接访问架构的基础上，该架构内还可以进一步增加其他部件，以便提高其性能。具体的，在一种实施方式中，内存直接访问控制部件设置为接收读数据搬移部件和写数据搬移部件发送的搬移完毕通知。具体的，请参考图1，DMA Descriptor Controller中包括Read DMA Status Sink(可称为读状态获取部件)和Write DMA Status Sink(可称为写状态获取部件)，分别与Read DMA Status Source(读状态生成部件)和Write DMA Status Source(写状态生成部件)相连，Read DMA Status Source和Write DMA Status Source分别 在执行完描述符、或读命令/写命令后生成搬移完毕通知并发送至Read DMA Status Sink和Write DMA Status Sink，使得控制寄存器得知其状态。内存直接访问控制部件包括状态更新部件，例如图1中的Status&MSI部件，状态更新部件设置为在检测到目标描述符执行完毕后，更新主机的系统内存中目标描述符对应的目标状态位数据。具体的，其可以通过Reg&Status&MSI Manager(可称为状态和中断管理部件)中的TX Slave(可称为状态和中断上报部件)更新主机内的目标描述符对应的目标状态表中的目标状态位数据。具体的，可以通过TX Slave生成MWr写数据包，并将其通过PCIe总线发送给主机。
需要说明的是，为了能够实现读写并行的效果，在本申请中，在主机处可以分别划分两个独立的内存空间，分别用于存储读描述符和对应的状态表，以及写描述符和对应的状态表。在完成后，数字电路可以发送中断信号，主机可以通过判断哪一个内存空间中的状态表均为完成状态，来确定是读完成还是写完成。
进一步的，内存直接访问控制部件包括中断上报部件，中断上报部件设置为在检测到目标描述符执行完毕后，向主机发送中断消息。继续参考图1，图1中Reg&Status&MSI Manage(可称为状态和中断管理部件)中的TX Slave同样可以承担中断上报的功能，DMA Descriptor Controller中的Status&MSI部件可以作为中断上报部件，与TX Slave配合生成MWr写数据包，并将其通过PCIe总线发送给主机，起到中断上报的效果。可以理解的是，中断上报和状态位数据更新对应的MWr写数据包的内容不同。
此外，在读数据的场景下，若同时读取多个数据包，读取的各个数据包可能会出现不按照读取顺序的其他顺序被获取，为了避免数据错误，通常会在一个时刻仅读取一个数据包，这样会使得带宽无法被充分利用。为了解决该问题，本申请中内存直接访问架构中还包括先入先出缓存器，先入先出缓存器设置为缓存读命令执行后得到的读数据包。此外，各个读数据包包括与读命令对应的数据包标签，读数据包按照数据包标签进行先后顺序排列得到读数据。通过在先入先出缓存器中对多个数据包进行缓存，配合数据包读取时根据读命令得到的数据包标签，可以对各个数据包进行排序后存储，实现在一个时刻同时读取多个数据包，充分利用带宽的效果。
可以理解的是，在读写并行，以及同时进行状态表更新或中断上报时，数字电路需要与主机进行多类型且高频的交互，为了保证数据交互的正常，内存直接访问架构中可以包括与目标总线连接的通讯部件。通讯部件设置为向目标总线发送第一数据包，或者设置为从目标总线上获取第二数据包，并基于第二数据包的数据包类型，将第二数据包发送至对应的部件。第一数据包，是指数字电路能够生成的任意一种数据包，例如写数据包，或者可以为终 端数据包。第二数据包，是指从主机获取的任意一种类型的数据包，例如读数据包。请参考图1，图1中的Schedule(即AXI-ST Schedule，表示基于AXI总线的通讯部件)即为通信部件。
上述的数字电路可以单独作为一个设备工作，或者可以集成至其他的电子设备中，即电子设备可以应用上述的内存直接访问架构。该电子设备可以通过目标总线，例如PCIe总线，与主机相连，共同组成内存直接访问系统。
请参考图5，图5为本申请实施例提供的一种内存直接访问方法的流程图。该方法包括：
S101：若检测到内存直接访问控制部件的控制寄存器被触发，则获取描述符地址信息。
S102：利用内存直接访问控制部件，基于描述符地址信息生成描述符读命令。
S103：利用读数据搬移部件执行描述符读命令，得到描述符，并将描述符写入内存直接访问控制部件的描述符存储部件。需要说明的是，描述符的数量不做限定，类型可以为读描述符和/或写描述符。
S104：利用内存直接访问控制部件，基于描述符生成访问命令。
S105：基于访问命令的种类，利用读数据搬移部件或写数据搬移部件执行访问命令。
可以理解的是，访问命令可以读命令或者为写命令。
具体的，请参考图6，图6为本申请实施例提供的一种主机内存写入流程图，其中包括如下步骤：
1、主机CPU设置DMA描述符控制寄存器，启动DMA流程。
2、控制寄存器命令读数据搬移器获取上位机(即主机，host)内的描述符表内描述符。
3、将获取的描述符存入FPGA内部写描述符FIFO(即Read Descriptor Table Slave)中。
4、控制寄存器命令写数据搬移器传输数据。
5、写数据搬移器将数据从FPGA的DDR(Double Data Rate，双倍速率同步动态随机存储器)或者ram(Random Access Memory，随机存取存储器)中取数据，组成MWr(存储写)TLP包，将数据搬移到Host系统内存中。
6、写数据搬移器生成done bit通知(即搬移完毕通知)，发送至控制寄存器，以便通知控制寄存器完成数据传输。
7、更新Host系统内存中对应ID的描述符状态位。
8、控制寄存器向主机发送MSI中断。
请参考图7，图7为本申请实施例提供的一种主机内存读取流程图，其中包括如下步骤：
1、主机CPU设置DMA描述符控制寄存器，启动DMA流程。
2、控制寄存器命令读数据搬移器获取上位机内的描述符表内描述符。
3、将获取的描述符存入FPGA内部读描述符FIFO中。
4、控制寄存器命令读数据搬移器发送MRd(内存读)TLP包，每个TLP数据包具有tag(即数据包标签)，tag基于报文管理生成。
5、读数据搬移器将数据从Host系统内存搬移到FPGA，利用16个FIFO(即先入先出缓存器)接收CplD(读数据包)，每个读数据包中具有对应的tag，依据tag进行数据定序处理，将数据写到相应的总线上。
6、读数据搬移器使用done bit通知发送至控制寄存器，以便通知控制寄存器完成数据传输。
7、更新Host系统内存中对应ID的描述符状态位。
8、控制寄存器向主机发送MSI中断。
应用本申请实施例提供的内存直接访问架构，设置了读数据搬移部件和写数据搬移部件，分别设置为执行读命令和写命令，此外还分别对应设置了读描述符存储部件和写描述符存储部件，使得数字电路能够读写并行处理。此外，读数据搬移部件还能够执行描述符地址信息得到的读命令，能够实现对描述符的搬移，利用同一套部件完成对描述符以及数据的搬移，节省硬件资源。
下面对本申请实施例提供的电子设备进行介绍，下文描述的电子设备与上文描述的内存直接访问方法可相互对应参照。
其中电子设备100应用了上述的内存直接访问架构，该电子设备100具体可以包括处理器101和存储器102，还可以进一步包括多媒体组件103、信息输入/信息输出(I/O)接口104以及通信组件105中的一种或多种。
其中，处理器101设置为控制电子设备100的整体操作，以完成上述的内存直接访问方法中的全部或部分步骤；存储器102设置为存储各种类型的数据以支持在电子设备100的操作，这些数据例如可以包括用于在该电子设备100上操作的任何应用程序或方法的指令，以 及应用程序相关的数据。该存储器102可以由任何类型的易失性或非易失性存储设备或者它们的组合实现，例如静态随机存取存储器(Static Random Access Memory，SRAM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、可擦除可编程只读存储器(Erasable Programmable Read-Only Memory，EPROM)、可编程只读存储器(Programmable Read-Only Memory，PROM)、只读存储器(Read-Only Memory，ROM)、磁存储器、快闪存储器、磁盘或光盘中的一种或多种。
多媒体组件103可以包括屏幕和音频组件。其中屏幕例如可以是触摸屏，音频组件设置为输出和/或输入音频信号。例如，音频组件可以包括一个麦克风，麦克风设置为接收外部音频信号。所接收的音频信号可以被进一步存储在存储器102或通过通信组件105发送。音频组件还包括至少一个扬声器，设置为输出音频信号。I/O接口104为处理器101和其他接口模块之间提供接口，上述其他接口模块可以是键盘，鼠标，按钮等。这些按钮可以是虚拟按钮或者实体按钮。通信组件105设置为电子设备100与其他设备之间进行有线或无线通信。无线通信，例如Wi-Fi，蓝牙，近场通信(Near Field Communication，简称NFC)，2G、3G或4G，或它们中的一种或几种的组合，因此相应的该通信组件105可以包括：Wi-Fi部件，蓝牙部件，NFC部件。
电子设备100可以被一个或多个应用专用集成电路(Application Specific Integrated Circuit，简称ASIC)、数字信号处理器(Digital Signal Processor，简称DSP)、数字信号处理设备(Digital Signal Processing Device，简称DSPD)、可编程逻辑器件(Programmable Logic Device，简称PLD)、现场可编程门阵列(Field Programmable Gate Array，简称FPGA)、控制器、微控制器、微处理器或其他电子元件实现，用于执行上述实施例给出的内存直接访问方法。
下面对本申请实施例提供的计算机可读存储介质进行介绍，下文描述的计算机可读存储介质与上文描述的内存直接访问方法可相互对应参照。
本申请还提供一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述的内存直接访问方法的步骤。
该计算机可读存储介质可以包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例 的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
本领域技术人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应该认为超出本申请的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系属于仅仅用来将一个实体或者操作与另一个实体或者操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语包括、包含或者其他任何变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种内存直接访问架构，应用于数字电路，包括内存直接访问控制部件、读数据搬移部件、写数据搬移部件和数据存储部件；
    所述内存直接访问控制部件包括控制寄存器、读描述符存储部件、写描述符存储部件、读命令传输部件、写命令传输部件；
    所述控制寄存器设置为被主机设置得到描述符地址信息；
    所述读描述符存储部件设置为存储利用控制寄存器得到的读描述符；
    所述写描述符存储部件设置为存储利用控制寄存器得到的写描述符；
    所述读命令传输部件设置为向所述读数据搬移部件发送基于读描述符或所述描述符地址信息得到的读命令；
    所述写命令传输部件设置为向所述写数据搬移部件发送基于读描述符得到的写命令；
    所述读数据搬移部件设置为执行所述读命令，所述写数据搬移部件设置为执行所述写命令，所述数据存储部件设置为存储所述读命令执行后得到的读数据。
  2. 根据权利要求1所述的内存直接访问架构，其中，所述数字电路为现场可编程逻辑门阵列电路，或者为数字集成电路。
  3. 根据权利要求1所述的内存直接访问架构，其中，所述内存直接访问控制部件设置为接收所述读数据搬移部件和所述写数据搬移部件发送的搬移完毕通知；
    所述内存直接访问控制部件包括状态更新部件，所述状态更新部件设置为在检测到目标描述符执行完毕后，更新所述主机的系统内存中所述目标描述符对应的目标状态位数据。
  4. 根据权利要求1所述的内存直接访问架构，其中，还包括先入先出缓存器，所述先入先出缓存器设置为缓存所述读命令执行后得到的读数据包；
    所述读数据包包括与所述读命令对应的数据包标签，所述读数据包按照所述数据包标签先后顺序排列得到所述读数据。
  5. 根据权利要求3所述的内存直接访问架构，其中，所述内存直接访问控制部件包括中断上报部件，所述中断上报部件设置为在检测到所述目标描述符执行完毕后，向所述主机发送中断消息。
  6. 根据权利要求1所述的内存直接访问架构，其中，还包括与目标总线连接的通讯部件；
    所述通讯部件设置为向所述目标总线发送第一数据包，或者设置为从所述目标总线上获取第二数据包，并基于所述第二数据包的数据包类型，将所述第二数据包发送至对应的部件。
  7. 根据权利要求1所述的内存直接访问架构，其中，所述读描述符存储部件和写描述符存储部件为先入先出存储器，所述读描述符存储部件和写描述符存储部件被预先定义了存储地址；
    所述控制寄存器包括源地址寄存器、目的地址寄存器、描述符大小寄存器、触发寄存器，其中，所述目的地址寄存器设置为存储任一所述存储地址。
  8. 根据权利要求1所述的内存直接访问架构，其中，所述控制寄存器设置为通过基地址寄存器进行空间访问。
  9. 根据权利要求1所述的内存直接访问架构，其中，所述主机的系统内存中包括描述符表，其中，所述描述符表具有存储若干数量的描述符的空间。
  10. 根据权利要求9所述的内存直接访问架构，其中，所述描述符表包括与各个描述符一一对应的状态表，其中，所述状态表中的数据允许根据描述符的执行情况进行更新。
  11. 根据权利要求9所述的内存直接访问架构，其中，所述主机，设置为划分两个独立的内存空间，其中，所述两个独立的内存空间分别用于存储读描述符和读描述符对应的状态表，以及写描述符和写描述符对应的状态表。
  12. 根据权利要求1所述的内存直接访问架构，其中，所述主机，设置为配置所述控制寄存器，以使所述控制寄存器读取读描述符的基地址。
  13. 根据权利要求1所述的内存直接访问架构，其中，所述状态更新部件包括：读状态获取部件，与所述读数据搬移部件中的读状态生成部件连接，其中，所述读状态生成部件用于在读命令生成所述搬移完毕通知后，将所述搬移完毕通知发送至所述读状态读取部件。
  14. 根据权利要求1所述的内存直接访问架构，其中，所述状态更新部件包括：写状态获取部件，与所述写数据搬移部件中的写状态生成部件连接，其中，所述写状态生成部件用于在写命令生成所述搬移完毕通知后，将所述搬移完毕通知发送至所述写状态读取部件。
  15. 根据权利要求6所述的内存直接访问架构，其中，所述第一数据包包括以下至少之一：写数据包，终端数据包；所述第二数据包包括：读数据包。
  16. 一种电子设备，所述电子设备应用了如权利要求1至15任一项所述的内存直接 访问架构。
  17. 一种内存直接访问系统，包括主机和如权利要求16所述的电子设备，所述主机和所述电子设备通过目标总线连接。
  18. 一种内存直接访问方法，应用于如权利要求16所述的电子设备，所述方法包括：
    若检测到内存直接访问控制部件的控制寄存器被触发，则获取描述符地址信息；
    利用所述内存直接访问控制部件，基于所述描述符地址信息生成描述符读命令；
    利用读数据搬移部件执行所述描述符读命令，得到描述符，并将所述描述符写入所述内存直接访问控制部件的描述符存储部件；
    利用所述内存直接访问控制部件，基于所述描述符生成访问命令；
    基于所述访问命令的种类，利用读数据搬移部件或写数据搬移部件执行所述访问命令。
  19. 根据权利要求18所述的内存直接访问方法，其中，所述方法还包括：在检测到所述目标描述符执行完毕后，向所述主机发送中断消息。
  20. 一种计算机可读存储介质，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求10所述的内存直接访问方法。
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