WO2023153188A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2023153188A1
WO2023153188A1 PCT/JP2023/001892 JP2023001892W WO2023153188A1 WO 2023153188 A1 WO2023153188 A1 WO 2023153188A1 JP 2023001892 W JP2023001892 W JP 2023001892W WO 2023153188 A1 WO2023153188 A1 WO 2023153188A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
semiconductor device
terminals
sealing resin
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/001892
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
文悟 田中
敏行 金谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2023580152A priority Critical patent/JPWO2023153188A1/ja
Priority to DE112023000869.8T priority patent/DE112023000869T5/de
Priority to CN202380020374.7A priority patent/CN118648104A/zh
Publication of WO2023153188A1 publication Critical patent/WO2023153188A1/ja
Priority to US18/789,087 priority patent/US20240395681A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/498—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/755—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent insulating package substrate, interpose or RDL

Definitions

  • the present disclosure relates to semiconductor devices.
  • Patent Document 1 discloses an example of a circuit for monitoring the voltage of a battery mounted on an electric vehicle and controlling an inverter. This circuit can prevent overvoltage from being supplied to the inverter for driving the motor.
  • the circuits necessary for monitoring the voltage of the battery mounted on the electric vehicle are the resistance voltage detection circuit and the high voltage battery detection circuit. These two circuits are composed of multiple ICs. Here, if these two circuits are integrated with as few ICs as possible and a single semiconductor device having a plurality of terminals electrically connected to the ICs is used, the circuit disclosed in Patent Document 1 is more compact. become something. However, a high voltage is applied to a plurality of terminals connected to the battery among the plurality of terminals of the semiconductor device. Therefore, if an attempt is made to further reduce the size of the semiconductor device, the intervals between the terminals become shorter, and discharge may occur between the terminals to which a high voltage is applied.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device capable of suppressing discharge between a plurality of terminals while miniaturizing the device.
  • a semiconductor device provided by a first aspect of the present disclosure includes: a first semiconductor element; a first terminal electrically connected to the first semiconductor element; electrically connected to the first semiconductor element; A second terminal located away from one terminal, and a sealing resin covering a part of each of the first terminal and the second terminal and the first semiconductor element.
  • the sealing resin has a first side surface facing a second direction orthogonal to the first direction and located closest to the first terminal and the second terminal in the second direction. The first terminal and the second terminal are spaced from the first side.
  • FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a plan view corresponding to FIG. 1, showing the encapsulating resin through.
  • 3 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 4 is a left side view of the semiconductor device shown in FIG. 1.
  • FIG. 5 is a right side view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a cross-sectional view taken along line VI-VI of FIG.
  • FIG. 7 is a cross-sectional view along line VII-VII of FIG.
  • FIG. 10 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, showing through a sealing resin.
  • 11 is a bottom view of the semiconductor device shown in FIG. 10.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 10.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 10.
  • FIG. 14 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, showing through a sealing resin.
  • 15 is a bottom view of the semiconductor device shown in FIG. 14.
  • FIG. 16 is a cross-sectional view taken along line XVI--XVI of FIG. 14.
  • FIG. 17 is a cross-sectional view along line XVII-XVII of FIG. 14.
  • FIG. 18 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure
  • FIG. 19 is a bottom view of the semiconductor device shown in FIG. 18.
  • FIG. 20 is a left side view of the semiconductor device shown in FIG. 18.
  • FIG. 21 is a cross-sectional view taken along line XXI-XXI of FIG. 18.
  • FIG. 22 is a cross-sectional view along line XXII-XXII of FIG. 18.
  • FIG. 23 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure;
  • FIG. FIG. 24 is a plan view corresponding to FIG. 23, showing the sealing resin through.
  • 25 is a cross-sectional view taken along line XXV--XXV of FIG. 24.
  • FIG. 26 is a cross-sectional view taken along line XXVI--XXVI of FIG. 24.
  • FIG. 27 is a cross-sectional view along line XXVII-XXVII of FIG
  • FIG. 1 A semiconductor device A10 according to the first embodiment of the present disclosure will be described based on FIGS. 1 to 8.
  • the semiconductor device A10 is used, for example, for monitoring the voltage of a battery mounted on an electric vehicle.
  • the package format of the semiconductor device A10 is a QFN (Quad Flat Non-leaded package).
  • the semiconductor device A10 includes a die pad 10, a first terminal 21, a second terminal 22, a plurality of third terminals 23, two fourth terminals 24, a first semiconductor element 31, a second semiconductor element 32, and a sealing resin 50.
  • FIG. 2 shows the encapsulation resin 50 in a transparent manner for convenience of understanding.
  • an imaginary line indicates the outline of the encapsulating resin 50 that is transmitted through.
  • the VI-VI line is indicated by a one-dot chain line.
  • first direction x A direction in which the first terminal 21 and the second terminal 22 are separated is called "first direction x”.
  • second direction y A direction perpendicular to the first direction x is called a “second direction y”.
  • third direction z A direction orthogonal to the first direction x and the second direction y is called a “third direction z”.
  • the third direction z corresponds to the normal direction of the top surface 51 of the sealing resin 50, which will be described later.
  • the sealing resin 50 includes the die pad 10, the first semiconductor element 31, the second semiconductor element 32, the first terminal 21, the second terminal 22, the plurality of third terminals 23, and the It partially covers each of the two fourth terminals 24 .
  • the sealing resin 50 has electrical insulation.
  • Sealing resin 50 includes, for example, black epoxy resin.
  • the sealing resin 50 has a top surface 51 , a bottom surface 52 , a first side surface 531 , a second side surface 532 , a third side surface 533 and a fourth side surface 534 .
  • the bottom surface 52 faces one side in the third direction z.
  • the top surface 51 faces the side opposite to the bottom surface 52 in the third direction z.
  • the first side surface 531 faces one side in the second direction y.
  • the first side surface 531 is located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the second side surface 532 faces one side in the first direction x.
  • the second side surface 532 is located closest to the first terminal 21 in the first direction x.
  • the third side surface 533 faces the side opposite to the second side surface 532 in the first direction x.
  • the fourth side surface 534 faces the side opposite to the first side surface 531 in the second direction y.
  • a first side surface 531 , a second side surface 532 , a third side surface 533 and a fourth side surface 534 are connected to the bottom surface 52 .
  • the first side surface 531 , the second side surface 532 , the third side surface 533 and the fourth side surface 534 are also connected to the top surface 51 .
  • the die pad 10 is located between the first terminal 21 and the second terminal 22 in the first direction x, as shown in FIG.
  • Die pad 10 contains a metal element.
  • the metal element is, for example, copper (Cu).
  • the die pad 10, the first terminal 21, the second terminal 22, the plurality of third terminals 23 and the two fourth terminals 24 are obtained from the same terminal frame.
  • die pad 10 has mounting surface 11 and first edge 12 .
  • the mounting surface 11 faces the same side as the top surface 51 of the sealing resin 50 in the third direction z.
  • the first edge 12 extends in the first direction x and is located closest to the first side surface 531 of the sealing resin 50 .
  • the dimension of the die pad 10 in the first direction x increases toward the side opposite to the side on which the first side surface 531 of the sealing resin 50 is located with respect to the first semiconductor element 31 in the second direction y. expands. Furthermore, the portion of the die pad 10 located on the opposite side of the first edge 12 with respect to the first semiconductor element 31 in the second direction y protrudes on both sides of the first edge 12 with respect to the first direction x. As shown in FIGS. 6 and 7 , the die pad 10 is positioned away from the bottom surface 52 of the sealing resin 50 .
  • the first terminal 21 is positioned away from the first side surface 531 of the sealing resin 50, as shown in FIG. As shown in FIGS. 2 and 3, the first terminal 21 is positioned on one side of the first edge 12 of the die pad 10 in the first direction x. In the semiconductor device A10, the first terminal 21 is located on the side opposite to the fourth side surface 534 of the sealing resin 50 with respect to the first edge 12 in the second direction y. Further, the first terminal 21 is located apart from a first extension line L1 extending from one end of the first edge 12 in the first direction x.
  • the first terminal 21 has a first main surface 211, a first back surface 212 and a first end surface 213.
  • the first main surface 211 faces the same side as the top surface 51 of the sealing resin 50 in the third direction z.
  • the first main surface 211 is covered with the sealing resin 50.
  • the first rear surface 212 faces the side opposite to the first main surface 211 in the third direction z.
  • the first rear surface 212 is exposed to the outside from the bottom surface 52 of the sealing resin 50 .
  • the first end surface 213 faces the same side as the second side surface 532 of the sealing resin 50 in the first direction x.
  • the first end surface 213 is exposed to the outside from the second side surface 532 .
  • the second terminal 22 is positioned away from the first side surface 531 of the sealing resin 50, as shown in FIG.
  • the second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the second terminal 22 is located on the opposite side of the first terminal 21 with respect to the first edge 12 of the die pad 10 in the first direction x. Therefore, the first terminal 21 and the second terminal 22 are positioned on both sides of the first edge 12 in the first direction x.
  • the second terminal 22 is located on the side opposite to the fourth side surface 534 of the sealing resin 50 with respect to the first edge 12 in the second direction y. Further, the second terminal 22 is located apart from a second extension line L2 extending from the other end of the first edge 12 in the first direction x.
  • the second terminal 22 has a second main surface 221, a second rear surface 222 and a second end surface 223.
  • the second main surface 221 faces the same side as the top surface 51 of the sealing resin 50 in the third direction z.
  • the second main surface 221 is covered with the sealing resin 50.
  • the second rear surface 222 faces the side opposite to the second main surface 221 in the third direction z.
  • the second rear surface 222 is exposed to the outside from the bottom surface 52 of the sealing resin 50 .
  • the second end surface 223 faces the same side as the third side surface 533 of the sealing resin 50 in the second direction y.
  • the second end surface 223 is exposed outside from the third side surface 533 .
  • the plurality of third terminals 23 are located on the side opposite to the first side surface 531 of the sealing resin 50 with the die pad 10 as a reference in the second direction y.
  • the multiple third terminals 23 are arranged along the first direction x.
  • the interval between two third terminals 23 adjacent in the first direction x is shorter than the interval between the first terminal 21 and the second terminal 22 .
  • the multiple third terminals 23 include an A terminal 23A, a B terminal 23B, two C terminals 23C, and multiple D terminals 23D.
  • the plurality of third terminals 23 have a third main surface 231, a third rear surface 232 and a third end surface 233.
  • the third main surface 231 faces the same side as the top surface 51 of the sealing resin 50 in the third direction z.
  • the third main surface 231 is covered with the sealing resin 50.
  • the third rear surface 232 faces the side opposite to the third main surface 231 in the third direction z.
  • the third back surface 232 is exposed to the outside from the bottom surface 52 of the sealing resin 50 .
  • the third end surface 233 faces the same side as the fourth side surface 534 of the sealing resin 50 in the second direction y. As shown in FIG. 5 , the third end face 233 is exposed outside from the fourth side face 534 .
  • the two fourth terminals 24 are positioned apart from each other in the first direction x and support the die pad 10, as shown in FIG.
  • a plurality of third terminals 23 are positioned between two fourth terminals 24 in the first direction x.
  • the two fourth terminals 24 have a fourth main surface 241, a fourth rear surface 242, a fourth end surface 243 and a connecting surface 244.
  • the fourth main surface 241 faces the same side as the top surface 51 of the sealing resin 50 in the third direction z.
  • the fourth main surface 241 is covered with the sealing resin 50.
  • the fourth rear surface 242 faces the side opposite to the third main surface 231 in the third direction z.
  • the fourth rear surface 242 is exposed to the outside from the bottom surface 52 of the sealing resin 50 .
  • the fourth end surface 243 faces the same side as the fourth side surface 534 of the sealing resin 50 in the second direction y. As shown in FIG.
  • the fourth end surface 243 is exposed to the outside from the fourth side surface 534 .
  • the connecting surface 244 connects the fourth main surface 241 and the mounting surface 11 of the die pad 10 .
  • the connecting surface 244 is inclined with respect to the fourth principal surface 241 and the mounting surface 11 .
  • the connecting surface 244 is covered with the sealing resin 50 .
  • the first semiconductor element 31 and the second semiconductor element 32 are mounted on the mounting surface 11 of the die pad 10, as shown in FIGS. Both the first semiconductor element 31 and the second semiconductor element 32 are integrated circuits (ICs).
  • the second semiconductor element 32 is positioned between the first semiconductor element 31 and the plurality of third terminals 23 in the second direction y. As shown in FIG. 7, the first semiconductor element 31 and the second semiconductor element 32 are bonded to the mounting surface 11 via the bonding layer 39 .
  • the bonding layer 39 is made of, for example, a paste containing silver-containing epoxy resin as a main component (so-called Ag paste).
  • the first semiconductor element 31 has multiple first electrodes 311 .
  • the multiple first electrodes 311 are electrically connected to the circuit configured in the first semiconductor element 31 .
  • the second semiconductor element 32 has a plurality of second electrodes 321 .
  • the multiple second electrodes 321 are electrically connected to the circuit configured in the second semiconductor element 32 .
  • the semiconductor device A10 further includes two first wires 41, a plurality of second wires 42, a plurality of third wires 43, and a plurality of fourth wires 44.
  • the composition of these wires includes gold (Au), for example. These wires are covered with a sealing resin 50 .
  • the two first wires 41 are connected to the two first electrodes 311 of the first semiconductor element 31, the first main surface 211 of the first terminal 21, and the second main surface of the second terminal 22. 221 separately. Thereby, the first terminal 21 and the second terminal 22 are electrically connected to the first semiconductor element 31 .
  • the plurality of second wires 42 are connected to the two first electrodes 311 of the first semiconductor element 31, the third main surface 231 of the A terminal 23A, and the third main surface 231 of the B terminal 23B. are individually bonded to the Thereby, the first semiconductor element 31 is electrically connected to the A terminal 23A and the B terminal 23B.
  • the multiple third wires 43 are individually joined to the multiple first electrodes 311 of the first semiconductor element 31 and the multiple second electrodes 321 of the second semiconductor element 32 .
  • the second semiconductor element 32 is electrically connected to the first semiconductor element 31 .
  • the plurality of fourth wires 44 are connected to the plurality of second electrodes 321 of the second semiconductor element 32, the third main surfaces 231 of the two C terminals 23C, and the third main surfaces 231 of the plurality of D terminals 23D. It is individually bonded to the main surface 231 . Thereby, the second semiconductor element 32 is electrically connected to the two C terminals 23C and the plurality of D terminals 23D.
  • the sealing resin 50 is provided with a plurality of recesses 55.
  • the plurality of recesses 55 are positioned between the first terminal 21 and the second terminal 22 in the first direction x. As shown in FIGS. 6 and 7, the recesses 55 overlap the first terminals 21 and the second terminals 22 when viewed in the first direction x.
  • a plurality of recesses 55 are recessed from the bottom surface 52 and connected to the first side surface 531 .
  • the multiple recesses 55 extend in the second direction y. In the semiconductor device A10, the recesses 55 are located away from the die pad 10 when viewed in the third direction z.
  • the dimension H of each of the plurality of recesses 55 in the third direction z is greater than the dimensions H1 and H2 of each of the first terminal 21 and the second terminal 22 in the third direction z. .
  • a step-down circuit is configured in the first semiconductor element 31 .
  • the step-down circuit includes a plurality of resistive elements.
  • the first terminal 21 and the second terminal 22 are connected to a battery (not shown) to be monitored.
  • the first terminal 21 is a positive electrode.
  • the second terminal 22 is the negative electrode.
  • the voltage of the battery applied to the first terminal 21 and the second terminal 22 is converted into a weak electrical signal by the step-down circuit of the first semiconductor element 31 .
  • the second semiconductor element 32 includes two operational amplifiers OP1 and OP2. However, the second semiconductor element 32 may be configured without the operational amplifier OP2.
  • the operational amplifier OP1 amplifies the weak electric signal converted by the first semiconductor element 31 and outputs the amplified signal to the A terminal 23A through the first semiconductor element 31. FIG. This allows the voltage of the battery to be monitored.
  • the B terminal 23B is for grounding the first semiconductor element 31 .
  • a power supply for driving the second semiconductor element 32 is connected to the two C terminals 23C.
  • a plurality of D terminals 23D are electrically connected to the operational amplifier OP2.
  • An electrical signal generated by another control circuit (not shown) based on the electrical signal output from the A terminal 23A is input to the operational amplifier OP2.
  • high-frequency noise contained in the electrical signal output from the A terminal 23A is removed by the operational amplifier OP2, and monitoring can be performed with higher accuracy.
  • the semiconductor device A10 includes a sealing resin 50 that partially covers each of the first terminals 21 and the second terminals 22, and a second terminal that is electrically connected to the first terminals 21 and the second terminals 22 and covered with the sealing resin 50.
  • 1 semiconductor element 31 The second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the sealing resin 50 has a first side surface 531 facing the second direction y and located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the first terminal 21 and the second terminal 22 are located away from the first side surface 531 .
  • the semiconductor device A10 further includes a die pad 10 on which the first semiconductor element 31 is mounted. As viewed in the third direction z, the die pad 10 has a first edge 12 extending in the first direction x. The first edge 12 is positioned closest to the first side surface 531 of the sealing resin 50 . The first terminal 21 and the second terminal 22 are positioned on both sides of the first edge 12 in the first direction x. By adopting this configuration, the distances between the plurality of third terminals 23 and the first terminals 21 and the second terminals 22 are sufficiently secured. It is possible to suppress the discharge between the plurality of third terminals 23 and the first terminals 21 and the second terminals 22 are sufficiently secured. It is possible to suppress the discharge between
  • the sealing resin 50 is provided with a concave portion 55 located between the first terminal 21 and the second terminal 22 in the first direction x.
  • the recess 55 is recessed from the bottom surface 52 of the sealing resin 50 .
  • the concave portion 55 overlaps the first terminal 21 and the second terminal 22 when viewed in the first direction x.
  • the recess 55 extends in the second direction y. Furthermore, the dimension H of the recess 55 in the third direction z is larger than the dimensions H1 and H2 of the first terminal 21 and the second terminal 22 in the third direction z (see FIG. 8). As a result, when viewed in the first direction x, the entirety of each of the first terminal 21 and the second terminal 22 overlaps with the recess 55 (see FIGS. 6 and 7). Therefore, discharge between the first terminal 21 and the second terminal 22 can be suppressed more effectively.
  • the semiconductor device A10 further includes two fourth terminals 24 positioned apart from each other in the first direction x and supporting the die pad 10 .
  • the two fourth terminals 24 are located apart from the second side surface 532 and the third side surface 533 of the sealing resin 50 .
  • a plurality of third terminals 23 are positioned between two fourth terminals 24 in the first direction x.
  • the dimension of the die pad 10 in the first direction x increases toward the side opposite to the side where the first side surface 531 of the sealing resin 50 is located with respect to the first semiconductor element 31 in the second direction y. Furthermore, the portion of the die pad 10 located on the opposite side of the first edge 12 with respect to the first semiconductor element 31 in the second direction y protrudes on both sides of the first edge 12 with respect to the first direction x.
  • the interval between the two fourth terminals 24 can be made longer, so the interval between the two adjacent third terminals 23 can be set longer. This makes it possible to reduce mutual interference of noise in the plurality of third terminals 23 .
  • the first terminal 21 is exposed outside from the second side surface 532 of the sealing resin 50 .
  • the second terminal 22 is exposed outside from the third side surface 533 of the sealing resin 50 .
  • FIG. 10 shows the encapsulation resin 50 in a transparent manner for convenience of understanding.
  • the outline of the encapsulating resin 50 that is transmitted through is indicated by imaginary lines.
  • the semiconductor device A20 differs from the semiconductor device A10 in the configuration of the first terminals 21 and the second terminals 22 and the configuration of the plurality of concave portions 55 provided in the sealing resin 50 .
  • the first terminal 21 when viewed in the third direction z, overlaps the first extension line L1 extending from one end of the first edge 12 of the die pad 10 in the first direction x.
  • the second terminal 22 overlaps the second extension line L2 extending from the other end of the first edge 12 of the die pad 10 when viewed in the third direction z.
  • the recesses 55 overlap the die pad 10 when viewed in the third direction z. As a result, the recesses 55 overlap the first terminals 21 and the second terminals 22 when viewed in the first direction x.
  • the dimension H of each of the plurality of recesses 55 in the third direction z is smaller than the dimensions H1 and H2 of each of the first terminal 21 and the second terminal 22 in the third direction z.
  • the semiconductor device A20 includes a sealing resin 50 that partially covers each of the first terminals 21 and the second terminals 22, and a second terminal that is electrically connected to the first terminals 21 and the second terminals 22 and covered with the sealing resin 50.
  • 1 semiconductor element 31 The second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the sealing resin 50 has a first side surface 531 facing the second direction y and located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the first terminal 21 and the second terminal 22 are located away from the first side surface 531 . Therefore, according to this configuration, even in the semiconductor device A20, it is possible to reduce the size of the device while suppressing the discharge between the plurality of terminals. Furthermore, since the semiconductor device A20 has the same configuration as the semiconductor device A10, the semiconductor device A20 also exhibits the effects of the configuration.
  • the first terminal 21 when viewed in the third direction z, overlaps the first extension line L1 extending from one end of the first edge 12 of the die pad 10 in the first direction x.
  • the second terminal 22 overlaps the second extension line L2 extending from the other end of the first edge 12 of the die pad 10 when viewed in the third direction z.
  • the recess 55 overlaps the die pad 10 when viewed in the third direction z.
  • the concave portion 55 overlaps the first terminal 21 and the second terminal 22 when viewed in the first direction x. Therefore, the creeping distance of the sealing resin 50 from the first terminal 21 to the second terminal 22 via the bottom surface 52 is equivalent to the distance of the semiconductor device A10. Discharge between the two terminals 22 can be effectively suppressed.
  • FIG. 14 shows the encapsulation resin 50 in a transparent manner for convenience of understanding.
  • the outline of the encapsulating resin 50 that is transmitted through is indicated by imaginary lines.
  • the XVII-XVII line is indicated by a dashed line.
  • the semiconductor device A30 differs from the semiconductor device A10 in the configuration of the first terminals 21 and the second terminals 22 and the configuration of the plurality of concave portions 55 provided in the sealing resin 50 .
  • the first terminal 21 and the second terminal 22 are located in the second direction y with the first edge 12 of the die pad 10 as a reference. 1 side 531 is located on the opposite side. Therefore, the first terminal 21 is located away from the first extension line L1 extending from one end of the first edge 12 of the die pad 10 in the first direction x.
  • the second terminal 22 is positioned away from the second extension line L2 extending from the other end of the first edge 12 of the die pad 10 .
  • the recesses 55 overlap the die pad 10 when viewed in the third direction z. As a result, the recesses 55 overlap the first terminals 21 and the second terminals 22 when viewed in the first direction x.
  • the dimension H of each of the plurality of recesses 55 in the third direction z is smaller than the dimensions H1 and H2 of each of the first terminal 21 and the second terminal 22 in the third direction z.
  • the semiconductor device A30 includes a sealing resin 50 that partially covers each of the first terminals 21 and the second terminals 22, and a second terminal that is electrically connected to the first terminals 21 and the second terminals 22 and covered with the sealing resin 50.
  • 1 semiconductor element 31 The second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the sealing resin 50 has a first side surface 531 facing the second direction y and located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the first terminal 21 and the second terminal 22 are located away from the first side surface 531 . Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce the size of the device while suppressing discharge between a plurality of terminals. Further, since the semiconductor device A30 has the same configuration as the semiconductor device A10, the semiconductor device A30 also exhibits the effects of the configuration.
  • the first terminal 21 and the second terminal 22 are aligned with the first side surface 531 of the sealing resin 50 with the first edge 12 of the die pad 10 as a reference in the second direction y. are located on the opposite side.
  • the creepage distance of the sealing resin 50 from the first terminal 21 to the second terminal 22 via the first side surface 531 becomes longer than the configuration of the semiconductor device A20 described above. Therefore, the effect of suppressing discharge between a plurality of terminals becomes even higher than in the case of the semiconductor device A10.
  • FIG. 18 A semiconductor device A40 according to the fourth embodiment of the present disclosure will be described with reference to FIGS. 18 to 22.
  • FIG. 18 the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the XXI-XXI line is indicated by a dashed line.
  • the semiconductor device A40 differs from the semiconductor device A10 in the configuration of the plurality of concave portions 55 provided in the sealing resin 50 .
  • the multiple recesses 55 are recessed from the first side surface 531 of the sealing resin 50. As shown in FIGS. The plurality of recesses 55 are connected to the top surface 51 of the sealing resin 50 and the bottom surface 52 of the sealing resin 50 . The recesses 55 overlap the first terminal 21 and the second terminal 22 when viewed in the first direction x.
  • the dimension H of the recesses 55 in the third direction z is greater than the dimensions H1 and H2 of the first terminal 21 and the second terminal 22 in the third direction z.
  • dimension H is equal to the distance between top surface 51 and bottom surface 52 .
  • the semiconductor device A40 includes a sealing resin 50 that partially covers each of the first terminals 21 and the second terminals 22, and a second terminal that is electrically connected to the first terminals 21 and the second terminals 22 and covered with the sealing resin 50.
  • 1 semiconductor element 31 The second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the sealing resin 50 has a first side surface 531 facing the second direction y and located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the first terminal 21 and the second terminal 22 are located away from the first side surface 531 . Therefore, according to this configuration, even in the semiconductor device A40, it is possible to reduce the size of the device while suppressing discharge between a plurality of terminals. Further, since the semiconductor device A40 has the same configuration as the semiconductor device A10, the semiconductor device A40 also has the effect of the configuration.
  • FIG. 24 shows the encapsulation resin 50 in a transparent manner for convenience of understanding.
  • the outline of the encapsulation resin 50 seen through is shown by imaginary lines.
  • the XXVI-XXVI line and the XXVII-XXVII line are each indicated by a dashed line.
  • the semiconductor device A50 differs from the semiconductor device A10 in the configuration of the die pad 10, the first terminal 21, the second terminal 22, the plurality of third terminals 23, and the two fourth terminals 24.
  • the package format of the semiconductor device A50 is SOP (Small Outline Package).
  • the plurality of concave portions 55 are not provided in the sealing resin 50. As shown in FIG.
  • the die pad 10 includes a first pad 10A and a second pad 10B.
  • the second pads 10B are positioned between the first pads 10A and the plurality of third terminals 23 in the second direction y.
  • the first semiconductor element 31 is mounted on the mounting surface 11 of the first pad 10A.
  • the second semiconductor element 32 is mounted on the mounting surface 11 of the second pad 10B.
  • the second terminal 22 is connected to the first pad 10A.
  • the two fourth terminals 24 are connected to the second pads 10B.
  • a first edge 12 is included in the first pad 10A.
  • the first terminal 21 protrudes from the second side surface 532 of the sealing resin 50.
  • the second terminal 22 protrudes from the third side surface 533 of the sealing resin 50 .
  • a portion of each of the first terminal 21 and the second terminal 22 protruding from the sealing resin 50 is bent toward the side where the bottom surface 52 of the sealing resin 50 is located in the third direction z.
  • a part of each of the first main surface 211 of the first terminal 21 and the second main surface 221 of the second terminal 22 is covered with the sealing resin 50 .
  • the plurality of third terminals 23 and the two fourth terminals 24 protrude from the fourth side surface 534 of the sealing resin 50. As shown in FIG. Portions of each of the plurality of third terminals 23 and the two fourth terminals 24 protruding from the sealing resin 50 are bent toward the side where the bottom surface 52 of the sealing resin 50 is located in the third direction z.
  • the first terminals 21 and the second terminals 22 are located apart from the first side surface 531 of the sealing resin 50 . Also in the semiconductor device A50, the first terminal 21 and the second terminal 22 are positioned on both sides of the first edge 12 of the first pad 10A in the first direction x. Further, in the semiconductor device A50, the first terminal 21 and the second terminal 22 are located on the opposite side of the first side surface 531 with the first edge 12 as a reference in the second direction y.
  • the semiconductor device A50 includes a sealing resin 50 that partially covers each of the first terminals 21 and the second terminals 22, and a second terminal that is electrically connected to the first terminals 21 and the second terminals 22 and covered with the sealing resin 50.
  • 1 semiconductor element 31 The second terminal 22 is positioned apart from the first terminal 21 in the first direction x.
  • the sealing resin 50 has a first side surface 531 facing the second direction y and located closest to the first terminal 21 and the second terminal 22 in the second direction y.
  • the first terminal 21 and the second terminal 22 are located away from the first side surface 531 . Therefore, according to this configuration, even in the semiconductor device A50, it is possible to reduce the size of the device while suppressing the discharge between the plurality of terminals. Furthermore, since the semiconductor device A50 has the same configuration as the semiconductor device A10, the semiconductor device A50 also exhibits the effects of the configuration.
  • Appendix 1 a first semiconductor element; a first terminal electrically connected to the first semiconductor element; a second terminal electrically connected to the first semiconductor element and positioned away from the first terminal in a first direction; a part of each of the first terminal and the second terminal, the first semiconductor element, and a sealing resin covering the terminal; the sealing resin has a first side surface facing a second direction orthogonal to the first direction and positioned closest to the first terminal and the second terminal in the second direction; The semiconductor device, wherein the first terminal and the second terminal are located away from the first side surface.
  • the die pad When viewed in a third direction orthogonal to the first direction and the second direction, the die pad extends in the first direction and is located closest to the first side surface in the second direction. having an edge,
  • the semiconductor device according to appendix 1 wherein the first terminal and the second terminal are positioned on both sides of the first edge in the first direction.
  • Appendix 3. The semiconductor device according to appendix 2, wherein the first terminal and the second terminal are positioned on the opposite side of the first side surface with respect to the first edge in the second direction.
  • Appendix 4. The semiconductor device according to appendix 2, wherein the first terminal overlaps a first extension line extending in the first direction from one end of the first edge when viewed in the third direction.
  • the sealing resin has a bottom surface facing the side opposite to the side on which the first semiconductor element is positioned with respect to the die pad, 8.
  • the sealing resin is provided with a recess positioned between the first terminal and the second terminal in the first direction, The semiconductor device according to appendix 8, wherein the recess overlaps the first terminal and the second terminal when viewed in the first direction.
  • Appendix 10 The semiconductor device according to appendix 9, wherein the recess is recessed from the bottom surface and extends in the second direction. Appendix 11.
  • the sealing resin has a second side surface and a third side surface facing opposite to each other in the first direction, The first terminal is exposed to the outside from the second side surface, 4.
  • Appendix 13 The first terminal protrudes from the second side surface, 13.
  • the semiconductor device according to any one of appendices 2 to 13, wherein the first semiconductor element includes a step-down circuit including a plurality of resistance elements.
  • Appendix 15. a second semiconductor device including an operational amplifier; further comprising a plurality of third terminals electrically connected to the second semiconductor element; the second semiconductor element is electrically connected to the first semiconductor element; a part of each of the plurality of third terminals and the second semiconductor element are covered with the sealing resin; 15.
  • Appendix 16. 16 The semiconductor device according to appendix 15, wherein the second semiconductor element is mounted on the die pad. Appendix 17.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
PCT/JP2023/001892 2022-02-08 2023-01-23 半導体装置 Ceased WO2023153188A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2023580152A JPWO2023153188A1 (https=) 2022-02-08 2023-01-23
DE112023000869.8T DE112023000869T5 (de) 2022-02-08 2023-01-23 Halbleitervorrichtung
CN202380020374.7A CN118648104A (zh) 2022-02-08 2023-01-23 半导体装置
US18/789,087 US20240395681A1 (en) 2022-02-08 2024-07-30 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022017651 2022-02-08
JP2022-017651 2022-02-08

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/789,087 Continuation US20240395681A1 (en) 2022-02-08 2024-07-30 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2023153188A1 true WO2023153188A1 (ja) 2023-08-17

Family

ID=87564114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/001892 Ceased WO2023153188A1 (ja) 2022-02-08 2023-01-23 半導体装置

Country Status (5)

Country Link
US (1) US20240395681A1 (https=)
JP (1) JPWO2023153188A1 (https=)
CN (1) CN118648104A (https=)
DE (1) DE112023000869T5 (https=)
WO (1) WO2023153188A1 (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082759B2 (en) * 2012-11-27 2015-07-14 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
JP2016136608A (ja) * 2015-01-16 2016-07-28 新日本無線株式会社 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5510746B2 (ja) 2010-10-26 2014-06-04 株式会社デンソー 電子装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082759B2 (en) * 2012-11-27 2015-07-14 Infineon Technologies Ag Semiconductor packages and methods of formation thereof
JP2016136608A (ja) * 2015-01-16 2016-07-28 新日本無線株式会社 半導体装置

Also Published As

Publication number Publication date
US20240395681A1 (en) 2024-11-28
DE112023000869T5 (de) 2024-12-05
CN118648104A (zh) 2024-09-13
JPWO2023153188A1 (https=) 2023-08-17

Similar Documents

Publication Publication Date Title
CN114175234B (zh) 半导体装置及电子装置
JP7649171B2 (ja) 半導体装置
JPH09260550A (ja) 半導体装置
US7298034B2 (en) Multi-chip semiconductor connector assemblies
CN114026685A (zh) 电子装置以及电子装置的安装结构
JP7594950B2 (ja) 半導体装置
JP2005142189A (ja) 半導体装置
JP3450803B2 (ja) 樹脂封止型半導体装置
WO2023112677A1 (ja) 半導体装置および半導体装置の製造方法
WO2023153188A1 (ja) 半導体装置
US7535087B2 (en) Semiconductor device with lead frames
US12582016B2 (en) Semiconductor device
WO2023090059A1 (ja) 半導体装置
JPH10275887A (ja) 半導体装置
WO2023189650A1 (ja) 半導体装置
JP3150560B2 (ja) 半導体装置
JP2019050297A (ja) 半導体装置
JP2007184475A (ja) 半導体装置
US20030234434A1 (en) Semiconductor device
US7492038B2 (en) Semiconductor device
WO2023112743A1 (ja) 電子装置
JP3001399B2 (ja) 半導体装置
WO2025069992A1 (ja) 半導体装置
JP2000269376A (ja) 半導体装置
WO2023140046A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23752656

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2023580152

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 202380020374.7

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 112023000869

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23752656

Country of ref document: EP

Kind code of ref document: A1