WO2023149382A1 - 信号処理回路、及び、光検出装置 - Google Patents

信号処理回路、及び、光検出装置 Download PDF

Info

Publication number
WO2023149382A1
WO2023149382A1 PCT/JP2023/002700 JP2023002700W WO2023149382A1 WO 2023149382 A1 WO2023149382 A1 WO 2023149382A1 JP 2023002700 W JP2023002700 W JP 2023002700W WO 2023149382 A1 WO2023149382 A1 WO 2023149382A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
terminal
comparison circuit
signal
comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/002700
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
陸 島田
卓也 藤田
隆 馬場
俊介 足立
進也 岩科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hamamatsu Photonics KK
Original Assignee
Hamamatsu Photonics KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hamamatsu Photonics KK filed Critical Hamamatsu Photonics KK
Priority to CN202380019711.0A priority Critical patent/CN118647844A/zh
Priority to DE112023000750.0T priority patent/DE112023000750T5/de
Priority to US18/834,338 priority patent/US20250116551A1/en
Priority to JP2023578538A priority patent/JPWO2023149382A1/ja
Publication of WO2023149382A1 publication Critical patent/WO2023149382A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H04N25/773—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J1/46—Electric circuits using a capacitor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/444—Compensating; Calibrating, e.g. dark current, temperature drift, noise reduction or baseline correction; Adjusting
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/446—Photodiode
    • G01J2001/4466—Avalanche

Definitions

  • the present invention relates to signal processing circuits and photodetectors.
  • the signal processing circuit includes a front-stage circuit that receives light by an avalanche photodiode and a rear-stage circuit that processes the signal output from the front-stage circuit.
  • the pre-stage circuit includes an AC coupling.
  • the AC coupling section is provided between the avalanche photodiode and the subsequent circuit, and the avalanche photodiode and the subsequent circuit are AC-coupled.
  • a comparison circuit that removes the noise component of the signal from the avalanche photodiode between the AC coupling section and the subsequent circuit.
  • a comparison circuit is, for example, a circuit element such as a comparator and an inverter, and outputs a signal based on a component exceeding a threshold among components included in an input signal. As a result, noise components are removed.
  • a comparison circuit in order to improve the accuracy of light detection by the avalanche photodiode, it is required to further improve the transmission speed of the signal to the subsequent circuit.
  • An object of each aspect of the present invention is to provide a signal processing circuit and a photodetector that can ensure the accuracy of noise removal while improving the transmission speed of signals to subsequent circuits.
  • the inventor of the present application has come up with a configuration in which an AC coupling section and a level shifter section are provided in order to further improve the transmission speed of signals to the subsequent circuit.
  • the AC coupling section the parasitic capacitance between the avalanche photodiode and the comparison circuit is reduced, and the speed of change in the signal output from the avalanche photodiode is increased. In other words, quenching is speeded up.
  • the level shifter section adjusts the voltage of the signal input to the comparison circuit between the AC coupling section and the comparison circuit to a value lower than the voltage applied to the avalanche photodiode.
  • the voltage can be set lower on the post-stage circuit side than the AC coupling portion while a relatively higher voltage is ensured on the avalanche photodiode side than the AC coupling portion.
  • a relatively higher voltage is secured on the avalanche photodiode side than the AC coupling part, photon detection efficiency in the avalanche photodiode can be secured.
  • the voltage is set lower on the post-stage circuit side than the AC coupling section, circuit elements that can operate with a relatively low power supply voltage can be used in the post-stage circuit. If the power supply voltage used for the operation of the circuit elements is suppressed, the power consumption in the subsequent circuit can be greatly suppressed. The smaller the power supply voltage used to operate the circuit element, the smaller the size of the circuit element and the less parasitic capacitance in the circuit element. If the size of the circuit elements in the subsequent circuit is reduced, the overall size of the signal processing circuit can also be reduced.
  • the parasitic capacitance in the circuit element is reduced, the power consumption in the subsequent circuit can be further suppressed and the input/output response speed in the subsequent circuit can be further improved.
  • MOSFET metal oxide semiconductor FET
  • the gate length of the MOSFET can be reduced as the power supply voltage of the MOSFET is reduced. If the gate length of the MOSFET is reduced, the parasitic capacitance in the subsequent circuit can be reduced.
  • the threshold in the comparison circuit may vary.
  • the resistance values in each of the level shifter section and the comparison circuit may also vary. The above variations in threshold and resistance values may occur, for example, in the manufacturing process. If the level shifter section and the comparator circuit have different resistance values, the reference values of the signals input to the comparator circuit are also different. Therefore, both the threshold value of the comparison circuit and the reference value of the signal input to the comparison circuit may vary. Therefore, it is difficult to remove noise, and it is difficult to ensure the accuracy of noise removal.
  • the adjustment circuit includes an AC coupling section, a level shifter section, and a reference value adjustment section.
  • the reference value adjuster adjusts the reference value of the signal input to the comparison circuit. If the reference value of the signal input to the comparison circuit is adjusted according to the variation in the threshold value of the comparison circuit, noise removal accuracy can be ensured.
  • a signal processing circuit includes an input terminal, a comparison circuit, an adjustment circuit, and a post-stage circuit.
  • the input terminal is configured to receive an analog signal output from an avalanche photodiode operating in Geiger mode.
  • the comparison circuit removes noise components related to the signal input to the input terminal by comparing information related to the signal input to the input terminal with a threshold.
  • the adjustment circuit adjusts the signal input to the comparison circuit.
  • the post-stage circuit processes the signal output from the comparison circuit.
  • the comparison circuit outputs a signal based on a component exceeding a threshold among the components included in the signal input to the comparison circuit.
  • the adjustment circuit includes an AC coupling section, a level shifter section, and a reference value adjustment section.
  • the AC coupling unit AC-couples the input terminal and the comparison circuit.
  • the level shifter section adjusts the voltage of the signal input to the comparison circuit between the AC coupling section and the comparison circuit to a value lower than the reverse bias voltage applied to the avalanche photodiode.
  • the reference value adjuster adjusts the reference value of the signal input to the comparison circuit.
  • the signal processing circuit includes an adjustment circuit that adjusts the signal input to the comparison circuit.
  • the adjustment circuit includes an AC coupling section, a level shifter section, and a reference value adjustment section. According to this configuration, the transmission speed of the signal to the subsequent circuit is significantly improved, and the accuracy of noise removal can be ensured by adjusting the reference value according to the threshold value of the comparison circuit.
  • the reference value adjusting section may include a circuit element and a terminal electrically connected to the comparison circuit through the circuit element.
  • a circuit element has a resistance component.
  • the circuit element may include a variable resistance section configured to change the resistance value of the resistance component of the circuit element. In this case, the reference value of the signal input to the comparison circuit can be easily adjusted by changing the resistance value of the variable resistance section.
  • the signal processing circuit may further include a control unit.
  • the control section may be electrically connected to the variable resistance section.
  • the control section may control a resistance value between the terminal and the comparison circuit. In this case, the reference value of the signal input to the comparison circuit can be easily controlled.
  • variable resistance section may include an FET or an IGBT.
  • the control unit may include a bandgap reference circuit and control the voltage applied to the gate of the FET or IGBT based on the bandgap reference circuit.
  • the bandgap reference circuit can output a voltage independent of temperature, the reference value of the signal input to the comparison circuit can be controlled more accurately.
  • variable resistance section may include a MOSFET.
  • a MOSFET may connect the terminal and the comparison circuit.
  • the source of the MOSFET may be coupled to a comparator circuit. In this case, the reference value of the signal input to the comparison circuit can be adjusted more easily.
  • the reference value adjusting section may include first and second circuit elements, a first terminal, and a second terminal.
  • the first and second circuit elements each have a resistive component.
  • a first potential may be applied to the first terminal.
  • the first terminal may be electrically connected to the comparison circuit through the first circuit element.
  • a second potential lower than the first potential may be applied to the second terminal.
  • the second terminal may be electrically connected to the comparison circuit through the second circuit element.
  • At least one of the first circuit element and the second circuit element corresponds to the above circuit element, and may include a variable resistance section configured to change the resistance value of the resistance component of at least one of the circuit elements. In this case, the adjustment range of the reference value of the signal input to the comparison circuit can be improved by changing the resistance value of the variable resistance section.
  • the first circuit element may include an N-channel first MOSFET as the variable resistance section.
  • the second circuit element may include a second P-channel MOSFET as a variable resistance section.
  • the sources of both the first MOSFET and the second MOSFET may be connected to the comparison circuit. In this case, the reference value of the signal input to the comparison circuit can be easily and accurately controlled.
  • the AC coupling section may include a capacitor.
  • the level shifter section may include a circuit element having a resistance component and a terminal to which a voltage lower than the reverse bias voltage is applied.
  • the terminals of the level shifter section may be electrically connected to the capacitor and the comparison circuit through circuit elements of the level shifter section. In this case, the voltage of the signal input to the comparison circuit can be easily adjusted to a value lower than the reverse bias voltage applied to the avalanche photodiode.
  • the comparison circuit may include an inverter.
  • the transmission speed of signals to subsequent circuits can be further improved.
  • the signal processing circuit may further include at least one of an active quenching circuit and an active recharging circuit.
  • the active quenching circuit performs active quenching on the avalanche photodiode based on the signal from the subsequent circuit.
  • the active recharge circuit actively recharges the avalanche photodiode based on the signal from the subsequent circuit.
  • the synergistic effect of at least one of the active quenching circuit and the active recharging circuit and the adjustment circuit further shortens the time required for quenching and recharging.
  • circuit elements having a relatively low withstand voltage can be used in the subsequent circuit.
  • a photodetector comprises the signal processing circuit described above, an avalanche photodiode, and a quenching resistor electrically connected to the avalanche photodiode.
  • the AC coupling unit AC-couples the avalanche photodiode and quenching resistor and the comparison circuit.
  • the accuracy of noise removal can be ensured by adjusting the reference value according to the threshold value of the comparison circuit. As a result, the detection accuracy of light incident on the avalanche photodiode can be further improved.
  • Each aspect of the present invention can provide a signal processing circuit and a photodetector that can ensure the accuracy of noise removal while improving the transmission speed of signals to subsequent circuits.
  • FIG. 1 is a schematic perspective view showing an example of a photodetector according to one embodiment; FIG. It is an exploded perspective view showing an example of a photodetector.
  • 1 is a schematic circuit diagram of part of a photodetector;
  • FIG. 1 is a schematic circuit diagram of part of a photodetector;
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment;
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment;
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment;
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment;
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment;
  • FIG. 1 is a schematic perspective view
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment
  • FIG. 5 is a diagram for explaining signal conversion in a comparative example; It is a figure for demonstrating conversion of the signal in this embodiment.
  • FIG. 4 is a diagram for explaining noise removal
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment
  • FIG. 11 is a schematic circuit diagram of part of a photodetector in a modified example of the present embodiment
  • FIG. 11 is a diagram for explaining signals input to a comparison circuit in a modified example;
  • FIG. 1 is a schematic perspective view showing an example of a photodetector according to this embodiment.
  • FIG. 2 is an exploded perspective view of an example of the photodetector shown in FIG.
  • the photodetector 1 detects light incident on the avalanche photodiode.
  • the avalanche photodiode is hereinafter referred to as "APD".
  • APD avalanche photodiode
  • the photodetector 1 may be a front-illuminated photodetector.
  • the photodetector 1 includes a light receiving substrate 10, a circuit board 20, and a glass substrate 30, as shown in FIGS.
  • the circuit board 20 faces the light receiving board 10 .
  • the glass substrate 30 faces the light receiving substrate 10 .
  • the light receiving substrate 10 is arranged between the circuit board 20 and the glass substrate 30 .
  • the plane parallel to the main surfaces of the light receiving substrate 10, the circuit board 20, and the glass substrate 30 is the XY-axis plane, and the direction perpendicular to the main surfaces is the Z-axis direction.
  • the light receiving substrate 10 and the circuit board 20 are laminated in the Z-axis direction.
  • the light receiving substrate 10 is, for example, a semiconductor substrate having a rectangular shape in plan view.
  • the light receiving substrate 10 has a principal surface 1Na and a principal surface 1Nb facing each other.
  • the main surface 1Na corresponds to the light incident surface of the light receiving substrate 10.
  • the light receiving substrate 10 has at least one pixel U as shown in FIG.
  • the photodetector 1 detects light incident on the pixels U.
  • the light receiving substrate 10 has a plurality of pixels U.
  • the plurality of pixels U are arranged two-dimensionally in a matrix on the light receiving substrate 10, for example.
  • the light receiving substrate 10 outputs a signal from each pixel U.
  • FIG. The photodetector 1 detects light incident on each pixel U based on the signal output from each pixel U.
  • FIG. A plurality of pixels U are arranged in the X-axis direction and the Y-axis direction.
  • the glass substrate 30 has a main surface 30a and a main surface 30b facing each other.
  • the glass substrate 30 has a rectangular shape in plan view.
  • the principal surface 30 b faces the principal surface 1 Na of the light receiving substrate 10 .
  • the principal surface 30a and the principal surface 30b are flat.
  • the glass substrate 30 and the light receiving substrate 10 are optically connected by an optical adhesive OA.
  • the glass substrate 30 may be directly formed on the light receiving substrate 10 .
  • the circuit board 20 has a main surface 20a and a main surface 20b facing each other.
  • the circuit board 20 has a rectangular shape in plan view.
  • the light receiving substrate 10 is connected to the circuit board 20 .
  • the main surface 20a and the main surface 1Nb face each other.
  • the circuit board 20 has at least one signal processing circuit 21, as shown in FIG.
  • the signal processing circuit 21 reads the signal output from the pixel U.
  • the signal processing circuit 21 is electrically connected to the pixels U of the light receiving substrate 10 .
  • the signal processing circuit 21 is electrically connected to the pixels U, for example, through bump electrodes BE.
  • the circuit board 20 has multiple signal processing circuits 21 .
  • the plurality of signal processing circuits 21 are two-dimensionally arranged on the main surface 20a side of the circuit board 20 .
  • the signal processing circuit 21 and the pixels U are electrically connected by the bump electrodes BE in a one-to-one relationship.
  • the signal processing circuit 21 and the pixels U are electrically connected to each other through pad electrodes provided on the light receiving substrate 10 and the circuit board 20 without passing through the bump electrodes BE. good too.
  • electrically connected includes the case of being electrically connected via another element.
  • FIG. 3 is a schematic circuit diagram of part of the photodetector.
  • the photodetector 1 includes an APD 11 , a quenching resistor 12 , a bump electrode BE, and a signal processing circuit 21 .
  • the light receiving substrate 10 has an APD 11 and a quenching resistor 12 .
  • the pixel U described above is composed of an APD 11 and a quenching resistor 12 .
  • Each pixel U is composed of one APD 11 and one quenching resistor 12 .
  • the APD 11 and the signal processing circuit 21 are electrically connected to each other in a one-to-one relationship.
  • the APD 11 is configured to operate in Geiger mode.
  • the APD 11 forms a light receiving area for detecting light for each pixel U.
  • the quenching resistor 12 is electrically connected in series with the APD 11 .
  • the quenching resistor 12 is composed of, for example, passive elements. In the configuration shown in FIG. 3, quenching resistor 12 is coupled to the cathode of APD 11 .
  • connection does not include cases where the elements described in this specification are connected through elements other than wiring, but connection via elements not described in this specification is not included. do not exclude cases where
  • the photodetector 1 further includes terminals 13 , 14 and 15 .
  • terminal 13 is connected to the anode of APD 11 .
  • terminal 14 is coupled to the cathode of APD 11 and quenching resistor 12 .
  • Terminal 15 is coupled to quenching resistor 12 and is electrically connected to terminal 14 through quenching resistor 12 .
  • terminal 15 is given a higher voltage than terminal 13 .
  • the APD 11 is provided with a reverse bias voltage that breaks down the APD 11 .
  • terminal 13 is tied to ground and terminal 15 is provided with a voltage above the breakdown voltage.
  • the voltage applied to the terminal 15 corresponds to the reverse bias voltage.
  • the voltage applied to terminal 15 is 40V or higher.
  • the breakdown voltage of APD 11 is 40V
  • the excess bias is 10V
  • the voltage applied to terminal 15 is 50V.
  • the quenching resistor 12 may be connected to the anode of the APD 11.
  • terminal 13 is connected to the cathode of APD 11 .
  • terminal 14 is connected to the anode of APD 11 and quenching resistor 12 .
  • terminal 15 is given a lower voltage than terminal 13 .
  • the APD 11 is provided with a reverse bias voltage that breaks down the APD 11 .
  • terminal 13 is tied to ground and the voltage applied to terminal 15 is -40 V or less.
  • the breakdown voltage of APD 11 is 40V
  • the excess bias is 10V
  • the voltage applied to terminal 15 is -50V.
  • the signal processing circuit 21 is electrically connected in series with each of the APD 11 and the quenching resistor 12 . In the configuration shown in FIG. 3, the signal processing circuit 21 is electrically connected to the terminals 14 through the bump electrodes BE.
  • the signal processing circuit 21 includes an input terminal 22 , a comparison circuit 23 , an adjustment circuit 25 and a control section 26 .
  • the input terminal 22, the comparison circuit 23, and the adjustment circuit 25 constitute a front-stage circuit.
  • the signal processing circuit 21 further includes a post-stage circuit 24 that processes the signal output from the pre-stage circuit.
  • the input terminal 22 is electrically connected to the corresponding pixel U among the plurality of pixels U.
  • Input terminal 22 is coupled to terminal 14 and is electrically connected to APD 11 and quenching resistor 12 through terminal 14 .
  • the input terminal 22 is a pad electrode connected to the bump electrode BE.
  • a signal output from the APD 11 is input to the input terminal 22 in response to incidence of light on the APD 11 .
  • the APD 11 outputs an analog signal according to incident light.
  • An analog signal output from the APD 11 is input to the input terminal 22 .
  • the comparison circuit 23 removes the noise component contained in the signal by comparing the information about the input signal with the threshold.
  • the comparison circuit 23 compares information about the signal input to the input terminal 22 with a threshold value, and removes noise components about the signal input to the input terminal 22 by the comparison.
  • the comparison circuit 23 outputs a signal based on the component exceeding the threshold among the components included in the signal input to the comparison circuit 23 .
  • the comparison circuit 23 outputs only the components included in the signal input to the comparison circuit 23 that exceed the threshold.
  • the threshold value of the comparison circuit 23 is set so as to remove components other than the component indicating the incidence of light on the APD 11 .
  • the threshold of comparison circuit 23 is a predetermined value.
  • the threshold value of the comparison circuit 23 is a value determined in the manufacturing process and a unique value of the comparison circuit 23 .
  • “exceeding the threshold” includes not only transitioning to a value greater than the threshold, but also transitioning to a value smaller than the threshold.
  • the comparison circuit 23 outputs a signal based on the component that transitions to a value smaller than the threshold among the components included in the signal that is input to the comparison circuit 23 .
  • An analog signal based on the signal output from the APD 11 is input to the comparison circuit 23 via the input terminal 22 .
  • a signal indicating the variation of the voltage applied to the terminal 14 is input to the comparison circuit 23 .
  • a voltage corresponding to the voltage applied to the terminal 14 is applied to the input of the comparison circuit 23 .
  • the comparison circuit 23 is configured, for example, to output a digital signal corresponding to the value of the input analog signal.
  • a comparison circuit 23 outputs a digital signal based on the signal output from the APD 11 .
  • a digital signal output from the comparison circuit 23 is, for example, a HighLow signal indicating the timing at which light enters the APD 11 .
  • the comparison circuit 23 includes an inverter 41, for example.
  • the inverter 41 is a so-called NOT gate.
  • the input of the inverter 41 is applied with a voltage corresponding to the voltage applied to the electrode 51b of the capacitor 51, which will be described later. In other words, a voltage corresponding to the voltage applied to the terminal 57 is applied to the input of the inverter 41 .
  • the inverter 41 outputs a predetermined voltage when a voltage exceeding the threshold is input.
  • the output of the inverter 41 is, for example, Low when a voltage greater than the threshold is input, and High when a voltage less than the threshold is input.
  • a threshold value of the inverter 41 is determined inside the inverter 41 .
  • the threshold of the inverter 41 is determined by circuit elements provided inside the inverter 41 .
  • the threshold value of inverter 41 is determined by, for example, a transistor configured inside inverter 41 .
  • Comparator circuit 23 may not include, for example, a comparator whose threshold value is determined by a voltage applied from the outside of comparator circuit 23 , and comparator circuit 23 may be configured only with inverter 41 .
  • the comparator is composed of an analog circuit including an amplifier inside, and the inverter 41 is composed of an analog circuit without an amplifier.
  • the inverter 41 is configured by a switch circuit including transistors such as MOSFETs.
  • the inverter 41 may be configured by CMOS (Complementary MOS), for example.
  • the post-stage circuit 24 processes the signal output from the comparison circuit 23 .
  • the post-stage circuit 24 processes the digital signal output from the comparison circuit 23, for example.
  • the post-stage circuit 24 performs, for example, at least one of reading the signal output from the comparison circuit 23 , controlling other circuits in the signal processing circuit 21 , and detecting light incident on the APD 11 .
  • the post-stage circuit 24 controls other circuits in the signal processing circuit 21 based on the signal output from the comparison circuit 23, for example.
  • the post-stage circuit 24 detects light incident on the APD 11 based on the signal output from the comparison circuit 23, for example.
  • the comparison circuit 23 and the post-stage circuit 24 are configured by, for example, an ASIC (Application Specific Integrated Circuit).
  • the comparison circuit 23 and the post-stage circuit 24 may be configured by an FPGA (Field Programmable Gate Array).
  • the adjustment circuit 25 adjusts the signal input to the comparison circuit 23 .
  • the adjustment circuit 25 is arranged between the input terminal 22 and the comparison circuit 23 .
  • a signal input to the input terminal 22 is input to the comparison circuit 23 via the adjustment circuit 25 .
  • the adjustment circuit 25 includes an AC coupling section 42 , a level shifter section 43 and a reference value adjustment section 44 .
  • the AC coupling unit 42 AC-couples the input terminal 22 and the comparison circuit 23 .
  • the AC coupling section 42 AC-couples the terminal 14 and the comparison circuit 23 .
  • the AC coupling unit 42 AC-couples the APD 11 and the quenching resistor 12 and the comparison circuit 23 .
  • AC coupling section 42 includes a capacitor 51 .
  • the capacitor 51 includes an electrode 51a and an electrode 51b that are insulated from each other.
  • the electrode 51 a is connected to the input terminal 22 .
  • the electrode 51a is electrically connected to the terminal 14 through the input terminal 22 and the bump electrode BE.
  • the electrode 51 a is electrically connected to the input of the comparison circuit 23 .
  • the capacitor 51 is electrically connected in series with the APD 11 and the quenching resistor 12 and is electrically connected in series with the inverter 41 of the comparator circuit 23 .
  • the level shifter section 43 sets the voltage of the signal input to the comparison circuit 23 to a predetermined value.
  • the level shifter section 43 adjusts the voltage of the signal input to the comparison circuit 23 between the AC coupling section 42 and the comparison circuit 23 to a value lower than the reverse bias voltage applied to the APD 11 .
  • the level shifter section 43 includes a circuit element 52 and terminals 53 and 54 .
  • circuit element 52 has a resistance component.
  • circuit element 52 includes resistive element 61 .
  • the resistive element 61 is a passive element.
  • Resistive element 61 includes, for example, a polysilicon resistor.
  • Terminal 53 is connected to electrode 51 b of capacitor 51 and resistor element 61 .
  • Resistive element 61 is electrically connected in series with capacitor 51 of AC coupling section 42 through terminal 53 .
  • the resistance element 61 is electrically connected in series to the inverter 41 of the comparison circuit 23 through the terminal 53 .
  • Terminal 54 is electrically connected to terminal 53 through resistive element 61 .
  • Terminal 54 is electrically connected to electrode 51 a of capacitor 51 and inverter 41 of comparator circuit 23 through circuit element 52 .
  • a voltage lower than the reverse bias voltage is applied to the terminal 54 .
  • a voltage higher than the threshold of the comparison circuit 23 is applied to the terminal 54 .
  • the terminal 54 is configured so that the voltage of the output of the comparator circuit 23 is equal to the voltage applied to the terminal 54 when the output of the comparator circuit 23 is High.
  • the voltage applied to terminal 54 is, for example, 1.8V.
  • the reference value adjuster 44 adjusts the reference value of the signal input to the comparison circuit 23 .
  • a signal input to the comparison circuit 23 is an analog signal.
  • a “reference value” is a reference amplitude value in an analog signal. For example, the reference value is the center value or lower limit of amplitude.
  • the signal input to the comparison circuit 23 fluctuates with reference to the reference value set by the reference value adjuster 44 .
  • the reference value adjuster 44 includes at least one of circuit elements 55 and 56 . In this embodiment, the reference value adjuster 44 includes both circuit elements 55 and 56 . A case where the reference value adjuster 44 includes both the circuit element 55 and the circuit element 56 will be described below. In this embodiment, the reference value adjuster 44 further includes terminals 57 , 58 and 59 . When the circuit element 55 corresponds to the first circuit element, the circuit element 56 corresponds to the second circuit element. When the terminal 58 corresponds to the first terminal, the terminal 59 corresponds to the second terminal.
  • the circuit element 55 and the circuit element 56 each have a resistance component. At least one of the circuit element 55 and the circuit element 56 includes a variable resistor configured to change the resistance value of the resistance component of at least one of them.
  • a terminal 57 connects the circuit element 55, the circuit element 56, and the comparison circuit 23 to each other.
  • Terminal 58 is electrically connected to the input of comparison circuit 23 through circuit element 55 and terminal 57 .
  • Terminal 59 is electrically connected to the input of comparator circuit 23 through circuit element 56 and terminal 57 .
  • a first potential is applied to the terminal 58 .
  • a second potential lower than the first potential is applied to the terminal 59 .
  • the voltage applied to terminal 58 is, for example, 1.8V.
  • Terminal 59 is, for example, connected to ground.
  • circuit element 55 and the circuit element 56 includes a transistor 62 or a transistor 63 as a variable resistance section.
  • Circuit element 55 includes transistor 62 and circuit element 56 includes transistor 63 .
  • the transistor 62 connects the terminal 58 and the comparison circuit 23 .
  • the transistor 63 connects the terminal 59 and the comparison circuit 23 .
  • transistors 62 and 63 are field effect transistors (FETs). In the configuration shown in FIG. 3, transistor 62 is an N-channel FET and transistor 63 is a P-channel FET.
  • the transistors 62 and 63 may be bipolar transistors (BJT: Bipolar Junction Transistor) or insulated gate transistors (IGBT: Insulated Gate Bipolar Transistor).
  • BJT Bipolar Junction Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • the transistors 62, 63 are metal oxide semiconductor FETs (MOSFETs).
  • MOSFETs metal oxide semiconductor FETs
  • the transistors 62 and 63 may be Junction FETs (JFETs).
  • the control section 26 controls the reference value of the signal input to the comparison circuit 23 under the control of the reference value adjustment section 44 .
  • the controller 26 is electrically connected to the reference value adjuster 44 and controls at least one of the circuit elements 55 and 56, as shown in FIG.
  • the light-receiving substrate 10 has a plurality of pixels U, and the control section 26 controls the reference value of the signal input to the comparison circuit 23 connected to each pixel U.
  • the control unit 26 is electrically connected to each of the plurality of reference value adjustment units 44 connected to the plurality of pixels U, for example.
  • the control unit 26, controls a plurality of reference value adjustment units 44 connected to a plurality of pixels U at once.
  • the control unit 26 may be included in the post-stage circuit 24.
  • the control section 26 is electrically connected to the variable resistance section of the reference value adjustment section 44 and controls the resistance value between the terminal 58 or the terminal 59 and the comparison circuit 23 .
  • the control section 26 is electrically connected to gates of the transistors 62 and 63 of the reference value adjustment section 44 .
  • the control section 26 is electrically connected to the bases of the transistors 62 and 63 of the reference value adjusting section 44 .
  • An example in which the transistors 62 and 63 are MOSFETs will be mainly described below.
  • the sources of both MOSFETs of transistors 62 and 63 are coupled to comparator circuit 23 .
  • a terminal 57 connects the source of the MOSFET of the transistor 62, the source of the MOSFET of the transistor 63, and the input of the comparison circuit 23 to each other.
  • Terminal 58 is coupled to the drain of the MOSFET of transistor 62 .
  • Terminal 59 is coupled to the drain of the MOSFET of transistor 63 .
  • the control unit 26 controls the voltage applied to the gates of the MOSFETs of the transistors 62 and 63 . For example, if the MOSFET of transistor 62 corresponds to the first MOSFET, the MOSFET of transistor 63 corresponds to the second MOSFET.
  • the transistor 62 may be a P-channel FET and the transistor 63 may be an N-channel FET, as shown in FIG.
  • terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of comparator circuit 23 together.
  • Terminal 58 is coupled to the source of the MOSFET of transistor 62 .
  • Terminal 59 is coupled to the source of the MOSFET of transistor 63 .
  • the control unit 26 is composed of, for example, one or more ASICs. As a modified example of this embodiment, the control unit 26 may be configured by an FPGA.
  • the control section 26 includes a bandgap reference circuit 65 and a terminal 66 in the configuration shown in FIG.
  • the bandgap reference circuit 65 outputs a constant voltage independent of temperature based on the voltage applied to the terminal 66 .
  • the control section 26 controls the voltage applied to the gates of the FETs or IGBTs based on the bandgap reference circuit 65 .
  • the control unit 26 uses the output of the bandgap reference circuit 65 to adjust the gates of the FETs or IGBTs of the transistors 62 and 63 so as to correct changes in the input to the comparison circuit 23 in response to changes in the ambient temperature. Adjust the applied voltage.
  • FIG. 6 to 8 are schematic circuit diagrams of part of the photodetector according to modifications of the present embodiment. These variations are generally similar or the same as the embodiments described above.
  • a photodetector 1A shown in FIG. 6 differs from the photodetector 1 in the above-described embodiment in terms of the configuration of the level shifter section 43.
  • the level shifter section 43 includes a circuit element 52A instead of the circuit element 52.
  • the circuit element 52A of the level shifter section 43 includes, instead of the resistance element 61, a variable resistance section capable of changing the resistance value of the resistance component.
  • the circuit element 52A includes a transistor 71 as a variable resistance section.
  • the transistor 71 is, for example, an FET. In the configuration shown in FIG. 6, transistor 71 is an N-channel FET. Transistor 71 is a MOSFET. As a further modification of this modification, the transistor 71 may be a BJT or an IGBT. Transistor 71 may be a JFET.
  • the resistance value of the circuit element 52A is controlled by the controller 26, for example.
  • the resistance value of the circuit element 52A may be controlled by a controller other than the controller 26, or may be preset by a person.
  • the control section 26 is electrically connected to the gate of the transistor 71 of the reference value adjusting section 44 .
  • the control section 26 is electrically connected to the bases of the transistors 62 and 63 of the reference value adjusting section 44 .
  • An example in which the transistors 62 and 63 are MOSFETs will be mainly described below.
  • the MOSFET source of transistor 71 is coupled to terminal 53 .
  • Terminal 53 is connected to electrode 51 b of capacitor 51 and the source of the MOSFET of transistor 71 .
  • the drain of the MOSFET of transistor 71 is coupled to terminal 54 .
  • the control unit 26 is electrically connected to the gate of the MOSFET of the transistor 71 and controls the voltage applied to the gate.
  • transistors 62 and 71 are P-channel FETs and transistor 63 is an N-channel FET, as shown in FIG. good.
  • terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of comparator circuit 23 together.
  • Terminal 58 is coupled to the source of the MOSFET of transistor 62 .
  • Terminal 59 is coupled to the source of the MOSFET of transistor 63 .
  • Terminal 53 is connected to electrode 51 b of capacitor 51 and the drain of the MOSFET of transistor 71 .
  • Terminal 54 is coupled to the source of the MOSFET of transistor 71 .
  • a photodetector 1B and a photodetector 1C shown in FIGS. 8 and 9 differ from the photodetector 1 in the above-described embodiment with respect to the configuration of the reference value adjusting section 44.
  • FIG. 8 A photodetector 1B and a photodetector 1C shown in FIGS. 8 and 9 differ from the photodetector 1 in the above-described embodiment with respect to the configuration of the reference value adjusting section 44.
  • the reference value adjusting section 44 includes a circuit element 56B instead of the circuit element 56.
  • the circuit element 56B includes a resistive element 73 instead of the transistor 63.
  • the resistive element 73 is a passive element.
  • Resistive element 73 includes, for example, a polysilicon resistor.
  • Terminal 57 is electrically connected to terminal 59 through resistive element 73 .
  • transistor 62 is an N-channel FET. In the configuration shown in FIG. 8, transistor 62 may be a P-channel FET.
  • the reference value adjusting section 44 includes a circuit element 55C instead of the circuit element 55.
  • the circuit element 55C includes a resistive element 75 instead of the transistor 62.
  • FIG. Resistive element 75 is a passive element. Resistive element 75 includes, for example, a polysilicon resistor. Terminal 58 is electrically connected to terminal 57 through resistive element 75 .
  • transistor 63 is a P-channel FET. In the configuration shown in FIG. 9, transistor 62 may be an N-channel FET.
  • FIG. 10 is a diagram for explaining signal conversion in a comparative example.
  • FIG. 11 is a diagram for explaining signal conversion in the signal processing circuit 21 of the photodetector 1.
  • FIG. 12 is a diagram for explaining noise removal in the signal processing circuit 21 of the photodetector 1.
  • the comparison circuit 23 outputs a signal based on the component exceeding the threshold among the components included in the signal input to the comparison circuit 23 .
  • the output voltage of the comparison circuit 23 rises when the voltage input to the comparison circuit 23 falls below the threshold Vth , and falls when the voltage input to the comparison circuit 23 exceeds the threshold Vth .
  • data D101 indicates the voltage of the input terminal 22 in the comparative example
  • data D102 indicates the voltage output from the comparison circuit 23 in the comparative example.
  • the voltage indicated by the data D101 corresponds to the voltage input to the comparison circuit 23.
  • data D101 begins to drop at time T101 in response to light incident on APD 11 and falls below threshold Vth at time T102 .
  • the data D102 starts rising at time T102 when the data D101 falls below the threshold Vth , and starts falling at time T103 when the data D101 exceeds the threshold Vth .
  • the time from when the data D101 starts to fall until the value of the data D101 falls below the threshold Vth is the difference between the time T102 and the time T101 .
  • the adjustment circuit 25 is removed from the signal processing circuit 21, and the input terminal 22 and the comparison circuit 23 are electrically connected without the adjustment circuit 25 intervening.
  • the time required for quenching the APD 11 depends on the product of the resistance value of the quenching resistor 12 and the parasitic capacitance in the signal processing circuit 21 .
  • the parasitic capacitance between the input terminal 22 and the comparison circuit 23 has an effect, and the time required for quenching is relatively long.
  • the time required for quenching corresponds to the time required for the voltage of the input terminal 22 to fall in response to the incidence of light on the APD 11 . Therefore, in this modified example, when light enters the APD 11, the voltage of the input terminal 22 drops relatively gently.
  • the time from when the data D101 starts to fall until the value of the data D101 falls below the threshold value Vth is relatively long.
  • the transmission time from when light enters the APD 11 to when the signal indicating the incidence of light on the APD 11 is transmitted to the post-stage circuit 24 is relatively long.
  • the voltage output from the comparison circuit 23 rises to the excess voltage value required for the APD 11 to operate in the Geiger mode.
  • the post-stage circuit 24 positioned after the comparison circuit 23 needs to use a circuit element having a relatively high withstand voltage.
  • the larger the size of the circuit element the higher the withstand voltage of the circuit element. Therefore, in this comparison, the size of the post-stage circuit 24 is relatively large.
  • the signal processing circuit 21 includes an adjustment circuit 25 that adjusts the signal input to the comparison circuit 23.
  • the adjustment circuit 25 includes an AC coupling section 42, level shifter sections 43 and 43A, and reference value adjustment sections 44, 44B and 44C. According to this configuration, the parasitic capacitance between the APD 11 and the comparison circuit 23 is reduced in the AC coupling section 42, and quenching is also speeded up. Therefore, when light is incident on the APD 11, the voltage of the input terminal 22 drops more sharply than in the comparative example.
  • the level shifter section 43 adjusts the voltage of the signal input to the comparison circuit 23 between the AC coupling section 42 and the comparison circuit 23 to a value lower than the reverse bias voltage applied to the APD 11 .
  • data D1 indicates the voltage of the input terminal 22 of the photodetector 1
  • data D2 indicates the voltage input to the comparison circuit 23 of the photodetector 1
  • data D3 indicates the voltage of the photodetector 1. shows the voltage output from the comparison circuit 23 of .
  • data D1 begins to drop at time T1 in response to the incidence of light on APD11.
  • Data D2 begins to fall as data D1 changes.
  • Data D2 falls below the threshold V th at time T2 .
  • the data D3 starts to rise at time T2 when the data D2 falls below the threshold Vth , and starts to fall at time T3 when the data D2 exceeds the threshold Vth .
  • the time from when the data D1 starts to fall until the value of the data D2 falls below the threshold value Vth is the difference between the time T2 and the time T1 .
  • the difference between time T2 and time T1 in FIG. 11 is smaller than the difference between time T101 and time T102 in FIG. Therefore, the time from when the data D1 starts to fall until the data D1 falls below the threshold Vth is shorter than the time from when the data D101 starts to fall until the data D101 falls below the threshold Vth .
  • the quenching speed is increased by the AC coupling section 42 and the voltage of the signal input to the comparison circuit 23 is reduced by the level shifter section 43. Together with the reduction, the transmission speed of the signal to the post-stage circuit 24 can be remarkably improved.
  • the AC coupling section 42 and the level shifter sections 43 and 43A of the photodetecting devices 1, 1A, 1B, and 1C a relatively higher voltage is ensured on the APD 11 side than the AC coupling section 42, while the voltage at the stage after the AC coupling section 42 is ensured.
  • the voltage can be set low on the circuit 24 side.
  • the maximum value of data D1 is V over and the maximum value of data D2 is V ini which is lower than V over .
  • the maximum value of the output of comparator circuit 23 is also reduced.
  • the maximum value of data D3 is V DD which is lower than V over .
  • circuit elements having a lower withstand voltage than the comparative example of FIG. 10 can be used in the post-stage circuit 24 .
  • the lower the withstand voltage of a circuit element the smaller the size of the circuit element.
  • the smaller the size of the circuit element the lower the power consumption of the circuit element.
  • the smaller the size of the circuit element the smaller the parasitic capacitance of the circuit element and the faster the signal input/output response.
  • the overall size of the post-stage circuit 24 can be reduced, the power consumption of the post-stage circuit 24 can be reduced, and the signal input in the post-stage circuit 24 can be reduced.
  • the speed of output response may also be improved.
  • a signal component S1 is a component input to the comparison circuit 23 in response to light incident on the APD 11, and signal components S2, S3 and S4 are noise components input to the comparison circuit 23.
  • the signal components S1, S2, S3, and S4 input to the comparison circuit 23 are components that fluctuate with reference to the reference value Vbase .
  • the comparison circuit 23 outputs a signal based on the component exceeding the threshold value Vth among the signal components S1, S2, S3, and S4.
  • the signal output from the comparison circuit 23 does not contain information indicating the input of the signal components S2, S3 and S4, but contains information indicating the input of the signal component S1.
  • the post-stage circuit 24 can accurately detect the incidence of light on the APD 11 .
  • the threshold value V th and the reference value V base are set so that the signal components S2, S3, and S4 also exceed the threshold value V th , the signal output from the comparison circuit 23 also contains noise components. In this case, the accuracy of detection of light incident on the APD 11 in the subsequent circuit 24 is also lowered.
  • the threshold Vth in the comparison circuit 23 may vary.
  • the resistance values of the level shifter section 43 and the comparison circuit 23 may also vary.
  • the resistance value may vary by about 20%.
  • the threshold V th in the comparison circuit 23 and the reference value of the signal input to the comparison circuit 23 are There is a possibility that both Vbase and Vbase may vary. Therefore, it is difficult to remove noise, and it is difficult to ensure the accuracy of noise removal.
  • the signal processing circuits 21 of the photodetectors 1, 1A, 1B and 1C include reference value adjusters 44, 44B and 44C in addition to the AC coupling section 42 and level shifter sections 43 and 43A.
  • the reference value adjusters 44 , 44 B and 44 C adjust the reference value V base of the signal input to the comparison circuit 23 . If the reference value V_base of the signal input to the comparison circuit 23 is adjusted according to variations in the threshold value Vth of the comparison circuit 23, noise removal accuracy can be ensured. Therefore, according to the signal processing circuit 21 of the photodetector 1, 1A, 1B, 1C, the transmission speed of the signal to the post-stage circuit 24 is remarkably improved, while the reference value V base corresponding to the threshold value of the comparison circuit 23 is reduced. Adjustments may also ensure the accuracy of noise removal.
  • the circuit elements 52, 52A of the level shifter sections 43, 43 are polysilicon resistors or MOSFETs. In this case, resistance values similar to those of the circuit elements 55 and 56 of the reference value adjusters 44, 44B and 44C can be easily realized, and the easiness of manufacturing the signal processing circuit 21 is ensured.
  • the reference value adjusting units 44, 44B, 44C include circuit elements 55, 56 and terminals 58, 59. Circuit elements 55 and 56 each have a resistance component. The circuit elements 55 and 56 each include a variable resistance section configured to change the resistance value of the resistance component. In this case, the reference value of the signal input to the comparison circuit 23 can be easily adjusted by changing the resistance value of the variable resistance section.
  • the first potential is applied to the terminals 58 in the reference value adjusting units 44, 44B, and 44C.
  • Terminal 58 is electrically connected to comparison circuit 23 through circuit element 55 .
  • a second potential lower than the first potential is applied to the terminal 59 .
  • Terminal 59 is electrically connected to comparison circuit 23 through circuit element 56 .
  • At least one of the circuit element 55 and the circuit element 56 includes a variable resistor configured to change the resistance value of the resistance component of at least one of them.
  • the adjustment range of the reference value of the signal input to the comparison circuit 23 can be improved. If both the circuit element 55 and the circuit element 56 include variable resistors, the adjustment range of the reference value of the signal input to the comparison circuit 23 can be further improved.
  • the control section 26 is electrically connected to the variable resistance sections of the reference value adjusting sections 44, 44B, and 44C.
  • the control unit 26 controls the resistance value between the terminal 58 or 59 and the comparison circuit 23 . In this case, the reference value of the signal input to the comparison circuit 23 can be easily controlled.
  • At least one of the circuit element 55 and the circuit element 56 includes an FET or IGBT as a variable resistance section.
  • the control unit 26 includes a bandgap reference circuit 65 and controls the voltage applied to the gate of the FET or IGBT based on the bandgap reference circuit 65 .
  • the bandgap reference circuit 65 can output a voltage independent of temperature, the reference value of the signal input to the comparison circuit 23 can be controlled more accurately.
  • FETs or IGBTs are used for the circuit element 55 or the circuit element 56, the circuit elements 55 and 56 are controlled by voltage, so external adjustment is easier than control by current.
  • At least one of the circuit element 55 and the circuit element 56 includes a MOSFET as a variable resistance section.
  • the MOSFET connects the terminal 58 or 59 and the comparison circuit 23 .
  • the source of the MOSFET is connected to comparator circuit 23 .
  • the reference value of the signal input to the comparison circuit 23 can be adjusted more easily.
  • the circuit element 55 includes an N-channel MOSFET.
  • Circuit element 56 includes a P-channel MOSFET.
  • the sources of both the MOSFET of the circuit element 55 and the MOSFET of the circuit element 56 are connected to the comparison circuit 23 . In this case, the reference value of the signal input to the comparison circuit 23 can be easily and accurately controlled.
  • the AC coupling unit 42 includes a capacitor 51.
  • the level shifter sections 43, 43A include circuit elements 52, 52A having resistance components, and a terminal 54 to which a voltage lower than the reverse bias voltage is applied.
  • a terminal 54 of the level shifter section 43, 43A is electrically connected to the capacitor 51 and the comparison circuit 23 through the circuit elements 52, 52A of the level shifter section 43, 43A. In this case, the voltage of the signal input to the comparison circuit 23 can be easily adjusted to a value lower than the reverse bias voltage applied to the APD 11 .
  • the threshold of the comparator is determined by the voltage applied from the outside of the comparison circuit 23, and the threshold Vth of the inverter 41 is determined inside the inverter 41.
  • FIG. The threshold V th of the inverter 41 varies due to manufacturing processes. Since the threshold value of the comparator is determined by the voltage applied from the outside of the comparison circuit 23, even if the resistance values of the comparison circuit 23 and the level shifter section 43 vary, noise can be removed by adjusting the threshold value. Therefore, the signal output from the comparator is more accurate than the signal output from inverter 41 . On the other hand, since the number of circuit elements forming the inverter 41 is smaller than the number of circuit elements forming the comparator, the signal transmission speed in the inverter 41 is faster than the signal transmission speed in the comparator.
  • the comparison circuit 23 includes an inverter 41. As shown in FIG. In this case, the transmission speed of signals to the post-stage circuit 24 can be further improved as compared with the case where a comparator having a more complicated structure is used. Further, the photodetectors 1, 1A, 1B, 1C include reference value adjusters 44, 44B, 44C. Therefore, by adjusting the reference value Vbase by the reference value adjusters 44, 44B, and 44C, noise caused by the threshold value Vth of the inverter 41 can also be removed.
  • FIG. 13 is a schematic circuit diagram of part of a photodetector in a modification of this embodiment. This variation is generally similar or the same as the embodiment described above.
  • a photodetector 1D in this modification differs from the photodetector 1 in the above-described embodiment in that the signal processing circuit 21 is configured to perform active recharging and active quenching. Differences between the above-described embodiment and modifications will be mainly described below.
  • the photodetector 1D further comprises at least one of an active quenching circuit 27 and an active recharging circuit 28.
  • the photodetector 1D includes both an active quenching circuit 27 and an active recharging circuit 28.
  • the active quenching circuit 27 and the active recharge circuit 28 are electrically connected to the post-stage circuit 24 and controlled based on signals from the post-stage circuit 24 .
  • the post-stage circuit 24 controls at least one of the active quenching circuit 27 and the active recharging circuit 28 .
  • the active quenching circuit 27 quenches the APD 11 based on the signal from the post-stage circuit 24 .
  • the active recharge circuit 28 recharges the APD 11 based on the signal from the post-stage circuit 24 .
  • the active quenching circuit 27 and the active recharging circuit 28 are provided on the circuit board 20, for example.
  • the active quenching circuit 27 includes a circuit element 81, a terminal 82, and a terminal 83.
  • the circuit element 81 switches the conductive state between the terminals 82 and 83 based on the signal from the subsequent circuit 24 .
  • Terminal 83 is connected to input terminal 22 and AC coupling portion 42 .
  • Terminal 83 is connected to input terminal 22 and electrode 51 a of capacitor 51 .
  • the input terminal 22 is electrically connected through the terminal 83 to the electrode 51a.
  • the circuit element 81 includes a transistor 91.
  • the transistor 91 connects the terminals 82 and 83 .
  • the transistor 91 is an FET.
  • transistor 91 is an N-channel FET.
  • the transistor 91 is a MOSFET.
  • the transistor 91 may be a BJT or an IGBT.
  • Transistor 91 may be a JFET. An example in which the transistor 91 is a MOSFET will be mainly described below.
  • the source of the MOSFET of transistor 91 is connected to terminal 82 .
  • the drain of the MOSFET of transistor 91 is coupled to terminal 83 .
  • the MOSFET gate of the transistor 91 is electrically connected to the post-stage circuit 24 without passing through the delay circuit 86 .
  • a voltage lower than the voltage applied to terminal 15 is applied to terminal 82 .
  • a voltage equivalent to the voltage applied to terminal 13 is applied to terminal 82 , for example.
  • Terminal 82 is, for example, connected to ground.
  • the active recharge circuit 28 includes a circuit element 84, a terminal 85, a terminal 83, and a delay circuit 86.
  • the circuit element 84 switches the conductive state between the terminals 85 and 83 based on the signal from the subsequent circuit 24 .
  • the circuit element 84 includes a transistor 92 .
  • Transistor 92 connects terminals 85 and 83 .
  • the transistor 92 is an FET.
  • transistor 92 is a P-channel FET.
  • the transistor 91 is a MOSFET.
  • transistor 92 may be a BJT or an IGBT.
  • Transistor 92 may be a JFET. An example in which the transistor 92 is a MOSFET will be mainly described below.
  • the source of the MOSFET of transistor 92 is coupled to terminal 85 .
  • the drain of the MOSFET of transistor 92 is coupled to terminal 83 .
  • the MOSFET gate of transistor 92 is electrically connected to post-stage circuit 24 through delay circuit 86 .
  • a voltage higher than the voltage applied to terminal 82 is applied to terminal 85 .
  • a voltage higher than the voltage applied to terminal 13 is applied to terminal 85 .
  • a voltage equivalent to the excess bias is applied to the terminal 85, for example.
  • terminals 13 and 82 are tied to ground and a voltage above the breakdown voltage is applied to terminal 15 .
  • APD 11 has a breakdown voltage of 40V and an excess bias of 10V.
  • the voltage applied to terminal 15 is 50V and the voltage applied to terminal 85 is 10V.
  • the delay circuit 86 is a circuit that delays the input signal by a predetermined time and outputs it. A signal output from the post-stage circuit 24 is input to the delay circuit 86 . The delay circuit 86 delays the transmission of the signal output from the post-stage circuit 24 to the circuit element 84 .
  • the transistor 62 is an N-channel FET and the transistor 63 is a P-channel FET.
  • transistor 62 may be a P-channel FET and transistor 63 may be an N-channel FET, as shown in FIG.
  • terminal 57 connects the drain of the MOSFET of transistor 62, the drain of the MOSFET of transistor 63, and the input of comparator circuit 23 together.
  • Terminal 58 is coupled to the source of the MOSFET of transistor 62 .
  • Terminal 59 is coupled to the source of the MOSFET of transistor 63 .
  • FIG. 15 is a diagram for explaining signals input to the comparison circuit in this modification.
  • data D4 indicates the voltage input to the comparison circuit 23 of the photodetector 1D.
  • the maximum value of data D4 is V ini like data D2.
  • the signal processing circuit 21 of the photodetector 1D further includes at least one of an active quenching circuit 27 and an active recharging circuit 28 .
  • the data D4 indicating the voltage input to the comparison circuit 23 of the photodetector 1D begins to drop due to quenching by the quenching resistor 12 at time T6 .
  • the post-stage circuit 24 outputs a signal to the active quenching circuit 27 and the active recharge circuit 28 when the signal output from the comparison circuit 23 is input.
  • the active quenching circuit 27 performs active quenching on the APD 11 based on the signal from the post-stage circuit 24 .
  • a voltage is applied to the gate of the MOSFET of the transistor 91 by the signal output from the post-stage circuit 24 .
  • the resistance between the drain and the source of the MOSFET of transistor 91 decreases and the voltage at terminal 83 approaches the voltage at terminal 82 .
  • active quenching occurs. Due to this active quenching, data D4 drops more sharply between time T7 and time T8 than the quenching between time T6 and time T7 .
  • the active recharge circuit 28 actively recharges the APD 11 based on the signal from the post-stage circuit 24 .
  • a signal input from the post-stage circuit 24 to the active recharge circuit 28 is delayed in the delay circuit 86 . Therefore, the signal output from the post-stage circuit 24 reaches the transistor 92 of the active recharge circuit 28 at time T9 after a predetermined time has passed since reaching the transistor 91 of the active quenching circuit 27 .
  • a voltage is applied to the gate of the MOSFET of the transistor 92 by the signal output from the post-stage circuit 24 .
  • the resistance between the drain and the source of the MOSFET of transistor 92 decreases and the voltage at terminal 83 approaches the voltage at terminal 85 .
  • active recharge occurs.
  • the data D4 rises more sharply between time T9 and time T10 than when active recharge is not performed. Since the signal processing circuit 21 of the photodetector 1 ⁇ /b>D includes the AC coupling section 42 , a voltage equivalent to the voltage applied to the terminal 15 can be applied to the terminal 85 .
  • the synergistic effect of at least one of the active quenching circuit 27 and the active recharging circuit 28 and the adjustment circuit 25 further shortens the time required for quenching and recharging. Furthermore, while the photon detection efficiency of the APD 11 is ensured, circuit elements having a relatively low withstand voltage can be used in the post-stage circuit 24 . Improving the speed of recharging can reduce the time during which no light can be detected.
  • the light-receiving substrate 10 and the circuit board 20 facing each other in the Z-axis direction has been described.
  • the light-receiving substrate 10 and the circuit substrate 20 may be arranged in the XY-axis directions.
  • the light receiving substrate 10 and the circuit board 20 may be integrally formed.
  • the signal processing circuit 21 and the pixels U are electrically connected to each other through the bump electrodes BE has been described as the configuration of the photodetector 1 in the above-described embodiment.
  • the signal processing circuit 21 and the pixels U may be electrically connected to each other without the bump electrodes BE.
  • the signal processing circuit 21 and the pixels U may be electrically connected to each other by bonding pad electrodes.
  • the signal processing circuit 21 and the pixels U may be electrically connected to each other by wire bonding.
  • the signal processing circuit 21 and the pixels U may be electrically connected to each other by metal wiring provided in or on the substrate.
  • the input terminal 22 may be a wire or a connection portion of a wire.
  • the light receiving substrate 10 may have a plurality of pixels U arranged in one row.
  • the light receiving substrate 10 may include only one pixel U.
  • the light receiving substrate 10 may contain only one APD 11 .
  • the circuit board 20 may include only one signal processing circuit 21 .
  • the control section 26 may control the reference value of the signal input to the comparison circuit 23 for each pixel U.
  • the control unit 26 may control the plurality of reference value adjustment units 44 connected to the plurality of pixels U for each reference value adjustment unit 44 .
  • the control section 26 may generate a control signal for each comparison circuit 23 connected to the pixel U and control the reference value adjustment section 44 corresponding to each comparison circuit 23 .
  • the control section 26 controls all the pixels U included in the light-receiving substrate 10 so that the signal input to the comparison circuit 23 connected to each pixel U is can be controlled at once.
  • the control unit 26 may control all the reference value adjustment units 44 connected to the pixels U included in the light receiving substrate 10 at once.
  • the control unit 26 may control the reference value of the signal input to the comparison circuit 23 connected to the pixels U included in each group for each predetermined group.
  • the control section 26 may generate a control signal for each group and control the plurality of reference value adjustment sections 44 for each predetermined group.
  • each group may be composed of, for example, a plurality of pixels U arranged in the same column or the same row, and a plurality of adjustment circuits 25 connected to these pixels U, respectively.
  • Each group may be composed of a plurality of pixels U adjacent to each other and a plurality of adjustment circuits 25 connected to these pixels U, respectively.
  • Each group may be composed of a plurality of pixels U arranged in a plurality of columns adjacent to each other, and a plurality of adjustment circuits 25 connected to these pixels U, respectively.
  • Each group may be composed of pixels U arranged in a plurality of rows adjacent to each other, and a plurality of adjustment circuits 25 connected to these pixels U, respectively.
  • Each group may be composed of a plurality of pixels U spaced apart from each other and a plurality of adjustment circuits 25 connected to these pixels U, respectively.
  • control unit 26 and the post-stage circuit 24 may be formed integrally.
  • the reference value adjusting section 44 may be controlled based on the signal output from the post-stage circuit 24 .
  • the glass substrate 30 has been described as the configuration of the photodetector 1 in the above-described embodiment.
  • the photodetector 1 may not include the glass substrate 30 .
  • main surface 1Na of light receiving substrate 10 is exposed.
  • the active quenching circuit 27 and the active recharging circuit 28 may be provided in the signal processing circuit 21 of the photodetectors 1A, 1B, 1C.
  • the level shifter section 43A of the photodetector 1A may be provided in the signal processing circuit 21 of the photodetector 1B or the photodetector 1C.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Light Receiving Elements (AREA)
PCT/JP2023/002700 2022-02-01 2023-01-27 信号処理回路、及び、光検出装置 Ceased WO2023149382A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202380019711.0A CN118647844A (zh) 2022-02-01 2023-01-27 信号处理电路和光检测装置
DE112023000750.0T DE112023000750T5 (de) 2022-02-01 2023-01-27 Signalverarbeitungsschaltung und lichtdetektionsvorrichtung
US18/834,338 US20250116551A1 (en) 2022-02-01 2023-01-27 Signal processing circuit, and light detecting device
JP2023578538A JPWO2023149382A1 (https=) 2022-02-01 2023-01-27

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-014282 2022-02-01
JP2022014282 2022-02-01

Publications (1)

Publication Number Publication Date
WO2023149382A1 true WO2023149382A1 (ja) 2023-08-10

Family

ID=87552375

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/002700 Ceased WO2023149382A1 (ja) 2022-02-01 2023-01-27 信号処理回路、及び、光検出装置

Country Status (5)

Country Link
US (1) US20250116551A1 (https=)
JP (1) JPWO2023149382A1 (https=)
CN (1) CN118647844A (https=)
DE (1) DE112023000750T5 (https=)
WO (1) WO2023149382A1 (https=)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07306133A (ja) * 1994-03-14 1995-11-21 Hitachi Electron Eng Co Ltd 微粒子検出器
JP2008538606A (ja) * 2005-04-22 2008-10-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｔｏｆ−ｐｅｔ用のディジタルシリコン光電子増倍管
JP2019197833A (ja) * 2018-05-10 2019-11-14 浜松ホトニクス株式会社 裏面入射型半導体光検出装置
JP2020017861A (ja) * 2018-07-25 2020-01-30 キヤノン株式会社 撮像素子、撮像装置及び信号処理方法
US20200370955A1 (en) * 2019-05-24 2020-11-26 Infineon Technologies Ag Array of single-photon avalanche diode (spad) microcells and operating the same
CN112945379A (zh) * 2021-02-03 2021-06-11 中国科学院长春光学精密机械与物理研究所 一种单光子探测器死时间设置与噪声滤除的系统
JP2021524794A (ja) * 2018-05-17 2021-09-16 エイチアイ エルエルシーＨｉ Ｌｌｃ 非侵襲で装着可能な脳インターフェースシステム

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9568620B2 (en) 2014-09-22 2017-02-14 General Electric Company Solid state photomultiplier

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07306133A (ja) * 1994-03-14 1995-11-21 Hitachi Electron Eng Co Ltd 微粒子検出器
JP2008538606A (ja) * 2005-04-22 2008-10-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｔｏｆ−ｐｅｔ用のディジタルシリコン光電子増倍管
JP2019197833A (ja) * 2018-05-10 2019-11-14 浜松ホトニクス株式会社 裏面入射型半導体光検出装置
JP2021524794A (ja) * 2018-05-17 2021-09-16 エイチアイ エルエルシーＨｉ Ｌｌｃ 非侵襲で装着可能な脳インターフェースシステム
JP2020017861A (ja) * 2018-07-25 2020-01-30 キヤノン株式会社 撮像素子、撮像装置及び信号処理方法
US20200370955A1 (en) * 2019-05-24 2020-11-26 Infineon Technologies Ag Array of single-photon avalanche diode (spad) microcells and operating the same
CN112945379A (zh) * 2021-02-03 2021-06-11 中国科学院长春光学精密机械与物理研究所 一种单光子探测器死时间设置与噪声滤除的系统

Also Published As

Publication number Publication date
JPWO2023149382A1 (https=) 2023-08-10
DE112023000750T5 (de) 2024-11-21
CN118647844A (zh) 2024-09-13
US20250116551A1 (en) 2025-04-10

Similar Documents

Publication Publication Date Title
KR100283351B1 (ko) 반도체집적회로
US10542230B2 (en) Imaging device
JPH10313236A (ja) 遅延回路
KR101609960B1 (ko) 광전 변환기, 광전 변환 어레이 및 촬상 장치
US9666505B1 (en) Power MOS transistor die with temperature sensing function and integrated circuit
US4352092A (en) Digital to analog converter
US8035070B2 (en) Imaging apparatus and device
US20130119240A1 (en) Photoelectric conversion cell and array, reading method therefor, and circuit thereof
US20150062762A1 (en) Semiconductor device
WO2023149382A1 (ja) 信号処理回路、及び、光検出装置
US6411133B1 (en) Semiconductor device
US8063689B2 (en) Output stage system
US9000351B2 (en) Semiconductor integrated circuit and optical sensor device using the same
CN106921387B (zh) 读取电路
JP2009117528A (ja) 光半導体リレー装置
JP2000299624A (ja) スイッチングデバイス
US5654673A (en) Amplifier having field effect or bipolar transistors and a power supply voltage supplied by a source or emitter following respectively
KR20000074289A (ko) 레벨 쉬프터 회로
JP4326638B2 (ja) 半導体双方向スイッチ用信号伝送回路
US8063422B2 (en) Image detection apparatus and methods
JP4797600B2 (ja) 固体撮像素子の出力バッファ回路およびこれを用いた固体撮像装置
JP2001157114A (ja) イメージセンサおよびイメージセンサユニット
US20060181347A1 (en) Delay circuit and method therefor
JPH0666608B2 (ja) 半導体相互接続回路に使用する非反転中継増幅器
JPH0792482B2 (ja) 半導体センサ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23749698

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023578538

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 18834338

Country of ref document: US

Ref document number: 112024000130309

Country of ref document: IT

WWE Wipo information: entry into national phase

Ref document number: 202380019711.0

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 112023000750

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23749698

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 18834338

Country of ref document: US