WO2023138466A1 - 图形生成方法、装置、设备及存储介质 - Google Patents

图形生成方法、装置、设备及存储介质 Download PDF

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Publication number
WO2023138466A1
WO2023138466A1 PCT/CN2023/071873 CN2023071873W WO2023138466A1 WO 2023138466 A1 WO2023138466 A1 WO 2023138466A1 CN 2023071873 W CN2023071873 W CN 2023071873W WO 2023138466 A1 WO2023138466 A1 WO 2023138466A1
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Prior art keywords
node
tree
logic
logical
graph
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PCT/CN2023/071873
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English (en)
French (fr)
Inventor
徐远
马锐锋
黄晓波
黄伟锋
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北京字跳网络技术有限公司
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Publication of WO2023138466A1 publication Critical patent/WO2023138466A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/901—Indexing; Data structures therefor; Storage structures
    • G06F16/9027—Trees
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F40/00—Handling natural language data
    • G06F40/20—Natural language analysis
    • G06F40/205—Parsing
    • G06F40/211—Syntactic parsing, e.g. based on context-free grammar [CFG] or unification grammars
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/34—Graphical or visual programming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/42—Syntactic analysis
    • G06F8/427—Parsing

Definitions

  • Embodiments of the present disclosure relate to the field of computer technology, for example, to a method, device, device, and storage medium for generating graphics.
  • Embodiments of the present disclosure provide a graphics generation method, device, device, and storage medium, which can convert logic information into a logic diagram, so that users can configure calculation logic through the logic diagram, and improve configuration efficiency.
  • an embodiment of the present disclosure provides a graph generation method, including:
  • the syntax tree includes multi-level tree nodes, and the tree nodes between levels have affiliation;
  • the embodiment of the present disclosure also provides a graphics generation device, including:
  • the logical element acquisition module is configured to analyze the target logical information to obtain multiple logical elements
  • the syntax tree acquisition module is configured to convert the plurality of logical elements into a syntax tree according to the logic of the target logic information; wherein, the syntax tree includes multi-layer tree nodes, and the tree nodes between layers have affiliation;
  • a graphic node conversion module configured to convert the multi-layer tree node into a plurality of graphic nodes
  • the logic graph acquisition module is configured to connect the plurality of graph nodes according to the affiliation relationship, and obtain the logic graph corresponding to the target logic information, so that the user can edit special effects based on the logic graph.
  • an embodiment of the present disclosure further provides an electronic device, and the electronic device includes:
  • a storage device configured to store one or more programs
  • the one or more processing devices are made to implement the graphic generation method according to the embodiments of the present disclosure.
  • the embodiments of the present disclosure further provide a computer-readable medium on which a computer program is stored, and when the program is executed by a processing device, the method for generating graphics as described in the embodiments of the present disclosure is implemented.
  • Fig. 1 is a flow chart of a graph generating method in an embodiment of the present disclosure
  • Fig. 2a is an example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 2b is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 3 is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4a is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4b is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4c is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4d is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4e is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4f is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4g is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • FIG. 4h is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure.
  • Fig. 4i is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 4j is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • FIG. 4k is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure.
  • Fig. 5a is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 5b is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 5c is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 5d is another example diagram of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure
  • Fig. 5e is another method of inserting or transforming the read logical elements as tree nodes in the embodiment of the present disclosure.
  • FIG. 6 is an example diagram of a logic diagram generated in an embodiment of the present disclosure.
  • Fig. 7 is an example diagram of parsing multi-level nested expressions in an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a graphics generating device in an embodiment of the present disclosure.
  • Fig. 9 is a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
  • the term “comprise” and its variations are open-ended, ie “including but not limited to”.
  • the term “based on” is “based at least in part on”.
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one further embodiment”; the term “some embodiments” means “at least some embodiments.” Relevant definitions of other terms will be given in the description below.
  • Fig. 1 is a flow chart of a graphics generation method provided by Embodiment 1 of the present disclosure. This embodiment is applicable to the situation of converting logical information into a logic diagram.
  • the method can be executed by a graphics generation device, which can be composed of hardware and/or software, and can generally be integrated into a device with a graphics generation function.
  • the device can be an electronic device such as a server, a mobile terminal, or a server cluster.
  • the formula graphical interface provided by this embodiment can analyze the logic information edited by the user to generate a logic graph, which contains multiple graph nodes corresponding to logical elements, and multiple graph nodes are connected according to logic to form numerical calculation logic.
  • the edit box for users to input logical information.
  • the edit box provides formula input and output ports. Users input logical elements through the input port to edit the formula, and the output port outputs the calculation result of the formula.
  • the edit box supports the input of functions, values, variables, mathematical operators and logical operators, etc.
  • it is necessary to register the mathematical atomic nodes supported by the graphical interface of the formula, such as: Cos (cosine calculation), Abs (absolute value calculation), Sqrt (square root calculation), etc.
  • the mathematical atom node only has the function of atomic mathematical calculation, and can perform some function processing on the value, and does not have the function of compound operation.
  • the method includes the following steps:
  • Step 110 analyzing the target logic information to obtain multiple logic elements.
  • the logical information may be a logical expression, for example, a mathematical formula and the like.
  • Logical elements can include values, variables, operators, and multi-level nested expressions.
  • a multi-level nested expression is composed of multi-level sub-expressions, and the sub-expressions include start symbols and end symbols.
  • the start character can be the first half parenthesis (such as: parentheses, square brackets or curly brackets), and the end character can be the last half parenthesis.
  • Operators can include pre-operators, mid-operators, and post-operators.
  • the prefix operator can be It can be understood that the operator is in front of the variable or value, for example: negative; the middle operator can be understood as the operator is in the middle of the variable or value, such as: addition, subtraction, multiplication, division, etc.; the post operator can be understood as the operator is behind the variable or value, for example: find a percentage (%).
  • regular expressions may be used to parse the target logic information into multiple logic elements.
  • Step 120 converting multiple logical elements into a syntax tree according to the logic of the target logical information.
  • the syntax tree includes multi-level tree nodes, and the tree nodes between levels have subordinate relationships.
  • the affiliation relationship can be understood as the relationship between the parent node and the child node, and the syntax tree can be an unbalanced ordinary multi-fork tree, including root nodes, intermediate nodes and leaf nodes.
  • the process of converting multiple logic elements into a syntax tree according to the logic of the target logic information may be: sequentially reading multiple logic elements according to the editing order of the target logic information; inserting or transforming the read logic elements as tree nodes according to the set rules to obtain a syntax tree.
  • the editing order can be from left to right or from top to bottom.
  • the setting rule may be a rule for inserting the logical element into the syntax tree according to the type of the logical element.
  • the way of inserting or transforming the read logical element as a tree node into the tree can be: when the read current logical element is any of the following types: value, variable or pre-operator; if the current logical element is a vertex element, then insert the current logical element into the tree as a root node; if the current logical element is a non-vertex element, then insert the current logical element into the tree as a child node of its adjacent operator.
  • the vertex element can be the first logical element in the formula.
  • the value can be a specific value, for example: 1; the variable can be understood as an indeterminate quantity represented by a letter, for example: represented by a; the pre-operator can be understood as the operator in front of the variable or value.
  • FIG. 2a-FIG. 2b is an example diagram of inserting or transforming the read logical elements as tree nodes in this embodiment, assuming that the logical information is "1+a", "1" is the first logical element of the formula, as shown in FIG. 2a, when “1" is read, "1" is directly inserted into the tree as the root node. As shown in Figure 2b, when “a” is read, since "a” is a non-vertex element, "a” is inserted into the tree as a child node of "+".
  • the method of inserting or transforming the read logical element as a tree node into the tree according to the set rules may be: when the current logical element is read as an intermediate operator or a post-operator, if the forward adjacent logical element of the current logical element is a vertex element, the current logical element is inserted into the tree as a new root node, and the forward adjacent logical element is transformed into a child node of the new root node.
  • the process of inserting the current logical element into the tree as a new root node and transforming the forward adjacent logical element into a child node of the new root node may be as follows: first inserting the current logical element into the tree as a child node of its forward adjacent logical element, and then exchanging positions of the current logical element and its forward adjacent logical element.
  • FIG. 3 is an example diagram of inserting or transforming the read logical element as a tree node in this embodiment. As shown in FIG.
  • the way of inserting or transforming the read logical element as a tree node into the tree may be: when the read current logical element is an intermediate operator or post operator, if the forward adjacent logical element of the current logical element is a non-vertex element, the operator is searched upwards in the constructed tree; if an operator with a priority less than or equal to the current logical element is found, the current logical element is inserted into the tree as a child node of the found operator, and the forward adjacent logical element of the current logical element is transformed into a child node of the current logical element ; If no operator with priority less than or equal to the current logical element is found, the current logical element is inserted into the tree as the root node.
  • Figures 4a-4k generate example diagrams of logic diagrams corresponding to the formulas.
  • Figure 4a when “1" is read, "1" is inserted into the tree as the root node.
  • Figure 4b when “-" is read, "-" is used as a new root node, and "1” is transformed into a child node of "-”.
  • FIG. 4c when continuing to read "2", directly use "2" as a child node of "-”.
  • the way to insert or transform the read logical element as a tree node according to the set rules is: if the read current logical element is a multi-level nested expression, for each level of sub-expression in the multi-level nested expression, start to read the logical elements in the sub-expression from the start symbol, perform tree insertion or transformation for the logical elements in the sub-expression according to the set rules, obtain a sub-tree, and use the sub-tree as the child node of the adjacent operator of the sub-expression; Tree insertions and transformations until multi-level nested expressions complete tree insertions or transformations.
  • a multi-level nested expression can be understood as including at least one level of sub-expression, wherein the sub-expression is surrounded by parentheses, for example, it can be a function expression.
  • Rolling back to the parent node of the initiator can be understood as taking the parent node of the initiator as the current node.
  • a start symbol such as (, then continue to read the logical elements after the start symbol, and insert and transform the logical elements read according to the above rules, if it is a terminator, such as )
  • roll back to the parent node of the corresponding start symbol to continue the tree insertion and transformation.
  • FIGS. 5 a - 5 e are example diagrams for generating a logic diagram corresponding to a formula, taking the formula 2-abs(a-b)+3 as an example.
  • FIG. 5a when “2" is read first, “2" is inserted into the tree as a root node.
  • Figure 5b when “-" is read, "-" is used as a new root node, and "2" is transformed into a child node of "-”.
  • Figure 5c when "abs” is read, a subtree corresponding to "abs" is first generated.
  • Step 130 converting the multi-level tree nodes into multiple graph nodes.
  • different types of logic elements are transformed into different types of graph nodes.
  • the syntax tree is traversed layer-orderly from the root node, and the obtained tree nodes of each layer are stored in a two-dimensional array, and the tree nodes of each layer are converted into graph nodes. Then connect the graph nodes according to the subordination relationship (parent-child relationship) between the tree nodes to obtain the logical graph.
  • one of the dimensions in the two-dimensional array stores the serial number of the level, and the other dimension stores the tree nodes contained in multiple levels.
  • the process of transforming a multi-layer tree node into a plurality of graph nodes may be: perform hierarchical traversal on the syntax tree, and if the traversed tree node is an operator or a function, convert the tree node into an operation graph node; if the traversed tree node is a numerical value, convert the tree node into a numerical graph node; if the traversed tree node is a variable, convert the tree node into a placeholder graph node.
  • the operator may be a logic symbol such as addition, subtraction, multiplication and division
  • the function may be a function such as abs or cos. Numeric and Placeholder Graph Nodes or as input to Operational Graph Nodes.
  • Step 140 connect multiple graphic nodes according to the affiliation relationship, and obtain a logic diagram corresponding to the target logic information, so that the user can edit special effects based on the logic diagram.
  • affiliation relationship can be understood as the parent-child relationship in the syntax tree.
  • Connecting the plurality of graph nodes according to the affiliation relationship includes:
  • the manner of connecting multiple graph nodes according to the affiliation relationship may be: connecting the output port of the graph node corresponding to the child node in the syntax tree to the input port of the graph node corresponding to the parent node. That is, in this embodiment, the graph node converted from the child node in the syntax tree will be used as the input of the graph node converted from its parent node.
  • the process of connecting the output port of the graphics node corresponding to the child node in the syntax tree to the input port of the graphics node corresponding to the parent node may be: connecting the output port of the numerical graphics node or the placeholder graphics node to the input port of the operation graphics node corresponding to the parent node; connecting the output port of the operation graphics node of the non-root node to the input port of the operation graphics node corresponding to the parent node.
  • FIG. 6 is an example diagram of a logic diagram generated in this embodiment.
  • the syntax tree generated by the formula is transformed from the root node into a graph node, "+” into a “summation node”, “-” into a “difference node”, “3” into a numerical graph node, "2” into a numerical graph node, "abs” into an "absolute value node", "-” into a “difference node", and "a” and "b” into placeholder graph nodes in turn.
  • the target logic information includes a multi-level nested expression
  • the target logic information includes a multi-level nested expression
  • the target logic information includes a multi-level nested expression
  • the target logic information includes a multi-level nested expression
  • the target logic information includes a multi-level nested expression
  • the logic elements contained in the multi-level nested expression into the setting stack sequentially from the start character, when the end character is pressed, pop up the logic elements in the setting stack in turn, until the start character matching the end character is popped up, and generate sub-expressions according to the pop-up logical elements
  • the terminator is reached, the logical elements in the setting stack are popped up one by one until the start character matching the terminator is popped up, and the operation of generating subexpressions according to the popped logical elements
  • the multi-level nested expression is parsed, it is judged whether there are logical elements in the setting stack, and if so, an error reminder is given.
  • FIG. 7 is an example diagram of parsing multi-level nested expressions in this embodiment.
  • the logic diagram corresponding to the target logic information is obtained, the logic diagram is combined with other special effect nodes to realize editing of image special effects or audio special effects.
  • the logic graph corresponding to the deformation formula can be called to perform the operation, and the operation result of the logic graph can be input into the deformation effect node to generate the image deformation effect.
  • the logic is to use the average volume of the two audio segments as the volume of the third audio segment, and it is necessary to call the logic diagram corresponding to the formula (a+b)/2 for processing.
  • the target logical information is analyzed to obtain multiple logical elements; according to the logic of the target logical information, the multiple logical elements are converted into a syntax tree; wherein, the syntax tree includes multi-layer tree nodes, and the tree nodes between levels have affiliation; the multi-layer tree nodes are converted into multiple graphic nodes; multiple graphic nodes are connected according to the affiliation, and the logic diagram corresponding to the target logic information is obtained, so that users can edit special effects based on the logic diagram.
  • the graphics generation method provided by the embodiments of the present disclosure can convert logic information into a logic diagram, so that users can configure calculation logic through the logic diagram, so as to realize editing of audio special effects and image special effects, and improve configuration efficiency.
  • Fig. 8 is a schematic structural diagram of a graphics generation device provided by an embodiment of the present disclosure. As shown in Fig. 8, the device includes:
  • the logical element obtaining module 210 is configured to analyze the target logical information to obtain multiple logical elements
  • the syntax tree acquisition module 220 is configured to convert a plurality of logical elements into a syntax tree according to the logic of the target logic information; wherein, the syntax tree includes multi-layer tree nodes, and the tree nodes between levels have affiliation;
  • Graphic node conversion module 230 configured to convert multi-layer tree nodes into multiple graphic nodes
  • the logic graph obtaining module 240 is configured to connect multiple graph nodes according to the affiliation relationship, and obtain a logic graph corresponding to the target logic information, so that the user can edit special effects based on the logic graph.
  • logical elements include values, variables, operators, and multi-level nested expressions; wherein, the multi-level nested expressions are composed of multi-level sub-expressions, and the sub-expressions include start symbols and end symbols.
  • syntax tree acquisition module 220 is also set to:
  • the read logical elements are used as tree nodes to perform tree insertion or transformation to obtain a syntax tree.
  • the current logical element read is any of the following types: value, variable or pre-operator, and the syntax tree acquisition module 220 is also set to:
  • the current logical element In response to determining that the current logical element is a non-vertex element, the current logical element is inserted into the tree as a child node of its adjacent operator.
  • the read current logical element is an intermediate operator or a post operator
  • the syntax tree acquisition module 220 is also set as:
  • the current logical element In response to determining that a forward-adjacent logical element of the current logical element is a vertex element, the current logical element is inserted into the tree as a new root node, and the forward-adjacent logical element is transformed into a child node of the new root node.
  • the read current logical element is an intermediate operator or a post operator
  • the syntax tree acquisition module 220 is also set as:
  • the current logical element is treated as The root node is inserted into the tree.
  • syntax tree acquisition module 220 is also set to:
  • the sub-expression In response to determining that the terminator has been read, the sub-expression is read, and the parent node of the start character is rolled back to continue the tree insertion and transformation until the multi-level nested expression completes the tree insertion or transformation.
  • the graph node conversion module 230 is also set to:
  • the tree node In response to determining that the traversed tree node is a variable, the tree node is converted into a placeholder graph node.
  • the logical diagram acquisition module 240 is also set to:
  • the logical diagram acquisition module 240 is also set to:
  • the output port of the numerical graph node is connected to the input port of the operation graph node corresponding to the parent node of the child node in the syntax tree corresponding to the numerical graph node, or the output port of the placeholder graph node is connected to the input port of the operation graph node corresponding to the parent node of the child node in the syntax tree corresponding to the numerical graph node;
  • the graphics generation device further includes: a multi-level nested expression analysis module configured to generate a setting stack in response to determining that the target logic information includes a multi-level nested expression;
  • the above-mentioned device can execute the methods provided by all the foregoing embodiments of the present disclosure, and has corresponding functional modules and advantageous effects for executing the above-mentioned methods.
  • the above-mentioned device can execute the methods provided by all the foregoing embodiments of the present disclosure, and has corresponding functional modules and advantageous effects for executing the above-mentioned methods.
  • FIG. 9 it shows a schematic structural diagram of an electronic device 300 suitable for implementing the embodiments of the present disclosure.
  • Electronic devices in embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc., or various forms of servers, such as independent servers or server clusters.
  • the electronic device shown in Figure 9 is only an example and should not be used for this No limitations are imposed on the scope of function and use of the disclosed embodiments.
  • an electronic device 300 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 301, which may perform various appropriate actions and processes according to a program stored in a read-only storage device (ROM) 302 or a program loaded from a storage device 305 into a random access storage device (RAM) 303.
  • ROM read-only storage
  • RAM random access storage device
  • various programs and data necessary for the operation of the electronic device 300 are also stored.
  • the processing device 301, ROM 302, and RAM 303 are connected to each other through a bus 304.
  • An input/output (I/O) interface 305 is also connected to the bus 304 .
  • the following devices may be connected to the I/O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309.
  • the communication means 309 may allow the electronic device 300 to perform wireless or wired communication with other devices to exchange data. While FIG. 9 shows electronic device 300 having various means, it should be understood that implementing or possessing all of the means shown is not a requirement. More or fewer means may alternatively be implemented or provided.
  • embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program comprising program code for performing a word recommendation method.
  • the computer program may be downloaded and installed from the network via the communication means 309, or from the storage means 305, or from the ROM 302.
  • the processing device 301 When the computer program is executed by the processing device 301, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.
  • the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the two.
  • a computer readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples of computer readable storage media may include, but are not limited to, electrical connections having one or more wires, portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a computer readable medium may be transmitted by any appropriate medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
  • the computer readable storage medium may be a non-transitory computer readable storage medium.
  • the client and the server can communicate using any currently known or future-developed network protocols such as HTTP (HyperText Transfer Protocol, Hypertext Transfer Protocol), and can be interconnected with any form or medium of digital data communication (for example, a communication network).
  • HTTP HyperText Transfer Protocol
  • Examples of communication networks include local area networks ("LANs”), wide area networks ("WANs”), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.
  • the above-mentioned computer-readable medium may be contained in the above-mentioned electronic device; it may also exist independently without being assembled into in this electronic device.
  • the computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device: parses the target logic information to obtain multiple logic elements; converts the multiple logic elements into a syntax tree according to the logic of the target logic information; wherein, the syntax tree includes multi-layer tree nodes, and the tree nodes between layers have affiliation; converts the multi-layer tree nodes into multiple graph nodes; Editing of special effects.
  • Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, or combinations thereof, including but not limited to object-oriented programming languages—such as Java, Smalltalk, C++, and conventional procedural programming languages—such as the “C” language or similar programming languages.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., through the Internet using an Internet service provider).
  • LAN local area network
  • WAN wide area network
  • Internet service provider e.g., AT&T, MCI, Sprint, EarthLink, MSN, GTE, etc.
  • each block in the flowchart or block diagram may represent a module, program segment, or portion of code that includes one or more executable instructions for implementing specified logical functions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved.
  • the units involved in the embodiments described in the present disclosure may be implemented by software or by hardware. Wherein, the name of a unit does not constitute a limitation of the unit itself under certain circumstances.
  • FPGAs Field Programmable Gate Arrays
  • ASICs Application Specific Integrated Circuits
  • ASSPs Application Specific Standard Products
  • SOCs System on Chips
  • CPLDs Complex Programmable Logic Devices
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • a machine-readable storage medium would include one or more wire-based electrical connections, a portable computer disk, a hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage devices or any suitable combination of the foregoing.
  • the embodiments of the present disclosure disclose a graph generation method, including:
  • the syntax tree includes multi-level tree nodes, and the tree nodes between levels have affiliation;
  • the logical elements include values, variables, operators, and multi-level nested expressions; wherein, the multi-level nested expressions are composed of multi-level sub-expressions, and the sub-expressions include start symbols and end symbols.
  • converting the plurality of logic elements into a syntax tree according to the logic of the target logic information includes:
  • the read logical elements are used as tree nodes to perform tree insertion or transformation to obtain a syntax tree.
  • the read current logical element is any of the following types: value, variable or pre-operator, and the read logical element is used as a tree node for tree insertion or transformation according to the set rules, including:
  • the current logical element is a vertex element, inserting the current logical element into the tree as a root node;
  • the current logical element is a non-vertex element, insert the current logical element into the tree as a child node of its adjacent operator.
  • the read current logical element is an intermediate operator or a post operator, and inserting or transforming the read logical element as a tree node according to the set rules includes:
  • forward adjacent logical element of the current logical element is a vertex element
  • insert the current logical element into the tree as a new root node and transform the forward adjacent logical element into a child node of the new root node.
  • the read current logical element is an intermediate operator or a post operator, and inserting or transforming the read logical element as a tree node according to the set rules includes:
  • the current logical element is inserted into the tree as a child node of the found operator, and the forward adjacent logical elements of the current logical element are transformed into child nodes of the current logical element;
  • the current logical element is inserted into the tree as a root node.
  • the read current logical element is a multi-level nested expression
  • the read current logical element is a multi-level nested expression
  • the read current logical element is a multi-level nested expression
  • the terminator When the terminator is read, the sub-expression is read, and the parent node of the start character is rolled back to continue the tree insertion and transformation until the multi-level nested expression completes the tree insertion or transformation.
  • converting the multi-layer tree node into multiple graph nodes includes:
  • traversed tree node is a numerical value, converting the tree node into a numerical graphic node
  • the traversed tree node is a variable, the tree node is converted into a placeholder graphic node.
  • connecting the plurality of graph nodes according to the affiliation relationship includes:
  • connecting the output port of the graph node corresponding to the child node in the syntax tree to the input port of the graph node corresponding to the parent node includes:
  • this method after analyzing the target logic information and obtaining a plurality of logic elements, it further includes:
  • the target logic information includes multi-level nested expressions, then generate a setting stack
  • the logical elements contained in the multi-level nested expression are sequentially pushed into the setting stack from the start character, and when the end character is pressed, the logical elements in the setting stack are popped up in sequence until the start character matching the end character is popped up, and sub-expressions are generated according to the pop-up logical elements;
  • the parsing of the multi-level nested expression is not completed, return and execute the remaining logical elements and push them into the setting stack in turn, and when the terminator is pressed, the logical elements in the setting stack are popped up in sequence until the start character matching the terminator is popped up, and the operation of generating a sub-expression according to the popped logical elements;

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Abstract

本公开公开了一种图形生成方法、装置、设备及存储介质。对目标逻辑信息进行解析，获得多个逻辑元素；按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；将所述多层树节点转化为多个图形节点；将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图获得目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。

Description

图形生成方法、装置、设备及存储介质
本申请要求在2022年1月20日提交中国专利局、申请号为202210067041.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及计算机技术领域，例如涉及一种图形生成方法、装置、设备及存储介质。
背景技术
图形化编程(Graph)过程中，往往需要编辑一些逻辑信息(如：数学表达式)来实现例如数值计算、运动轨迹计算等功能。目前，图形化编程提供的数学运算模块的功能比较单一，这样使得用户配置较为复杂，配置效率较低。
发明内容
本公开实施例提供一种图形生成方法、装置、设备及存储介质，可以将逻辑信息转化为逻辑图，使得用户通过逻辑图来配置计算逻辑，提高配置效率。
第一方面，本公开实施例提供了一种图形生成方法，包括：
对目标逻辑信息进行解析，获得多个逻辑元素；
按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；
将所述多层树节点转化为多个图形节点；
将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
第二方面，本公开实施例还提供了一种图形生成装置，包括：
逻辑元素获取模块，设置为对目标逻辑信息进行解析，获得多个逻辑元素；
语法树获取模块，设置为按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；
图形节点转化模块，设置为将所述多层树节点转化为多个图形节点；
逻辑图获取模块，设置为将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
第三方面，本公开实施例还提供了一种电子设备，所述电子设备包括：
一个或多个处理装置；
存储装置，设置为存储一个或多个程序；
当所述一个或多个程序被所述一个或多个处理装置执行，使得所述一个或多个处理装置实现如本公开实施例所述的图形生成方法。
第四方面，本公开实施例还提供了一种计算机可读介质，其上存储有计算机程序，该程序被处理装置执行时实现如本公开实施例所述的图形生成方法。
附图说明
图1是本公开实施例中的一种图形生成方法的流程图；
图2a是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的一种示例图；
图2b是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图3是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4a是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4b是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4c是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4d是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4e是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4f是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4g是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4h是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4i是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4j是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图4k是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图5a是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图5b是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图5c是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图5d是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另一种示例图；
图5e是本公开实施例中的将读取到的逻辑元素作为树节点进行树的插入或者变换的另 一种示例图；
图6是本公开实施例中的生成的逻辑图的示例图；
图7是本公开实施例中的解析多级嵌套表达式的示例图；
图8是本公开实施例中的一种图形生成装置的结构示意图；
图9是本公开实施例中的一种电子设备的结构示意图。
具体实施方式
应当理解，本公开的方法实施方式中记载的多个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本公开的范围在此方面不受限制。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。
需要注意，本公开中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本公开中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
本公开实施方式中的多个装置之间所交互的消息或者信息的名称仅用于说明性的目的，而并不是用于对这些消息或信息的范围进行限制。
图1为本公开实施例一提供的一种图形生成方法的流程图，本实施例可适用于将逻辑信息转化为逻辑图的情况，该方法可以由图形生成装置来执行，该装置可由硬件和/或软件组成，并一般可集成在具有图形生成功能的设备中，该设备可以是服务器、移动终端或服务器集群等电子设备。
本实施例提供的公式图形化界面可以将用户编辑的逻辑信息解析生成一个逻辑图，该逻辑图中包含多个逻辑元素对应的图形节点，多个图像节点根据逻辑相连，从而构成数值计算逻辑。
在公式图形化界面中具有一个用户可以输入逻辑信息的编辑框，该编辑框提供公式输入输出端口，用户通过输入端口输入逻辑元素以编辑公式，输出端口输出公式的计算结果。该编辑框支持输入函数、数值、变量、数学运算符及逻辑运算符等。在开发该公式图形化界面时，需要注册该公式图形化界面支持的数学原子节点，如：Cos(余弦计算)，Abs(绝对值计算)，Sqrt(平方根计算)等。数学原子节点只具有原子化的数学计算功能，可以对数值进行某种函数处理，不具备复合运算功能。
如图1所示，该方法包括如下步骤：
步骤110，对目标逻辑信息进行解析，获得多个逻辑元素。
其中，逻辑信息可以是逻辑表达式，例如：数学公式等。逻辑元素可以包括数值、变量、运算符、多级嵌套表达式。多级嵌套表达式由多级子表达式构成，且所述子表达式包括起始符和结束符。起始符可以是前半个括号(如：圆括号、中括号或者大括号)，结束符可以是后半个括号。运算符可以包括前置运算符、中置运算符及后置运算符。其中，前置运算符可 以理解为运算符在变量或者数值的前面，例如：取负；中置运算符可以是理解为运算符在变量或者数值的中间，例如：加、减、乘、除等；后置运算符可以理解为运算符在变量或者数值后面，例如：求取百分比(％)。本实施例中，可以采用正则表达式将目标逻辑信息解析为多个逻辑元素。
步骤120，按照目标逻辑信息的逻辑将多个逻辑元素转化为语法树。
其中，语法树包括多层树节点，且层级间树节点具有从属关系。从属关系可以理解为父节点与子节点的关系，语法树可以是非平衡普通多叉树，包含根节点、中间节点及叶子节点。
本实施例中，按照目标逻辑信息的逻辑将多个逻辑元素转化为语法树的过程可以是：按照目标逻辑信息的编辑顺序依次读取多个逻辑元素；按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，获得语法树。
其中，编辑顺序可以是从左到右或者从上到下。设定规则可以是根据逻辑元素的类型将逻辑元素插入语法树的规则。
例如，按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换的方式可以是：当读取到的当前逻辑元素为如下任一类型时：数值、变量或者前置运算符；若当前逻辑元素为顶点元素，则将当前逻辑元素作为根节点插入树中：若当前逻辑元素为非顶点元素，则将当前逻辑元素作为其相邻运算符的子节点插入树中。
其中，顶点元素可以是公式中的第一个逻辑元素。数值可以是具体的数值，例如：1；变量可以理解为由字母表征的不确定的量，例如：由a表示；前置运算符可以理解为运算符在变量或者数值的前面。示例性的，图2a-图2b是本实施例中将读取到的逻辑元素作为树节点进行树的插入或者变换的示例图，假设逻辑信息为“1+a”，“1”为该公式的第一个逻辑元素，如图2a所示，当读取到“1”时，则直接将“1”作为根节点插入树中。如图2b所示，当读取到“a”时，由于“a”为非顶点元素，则将“a”作为“+”的子节点插入树中。
例如，按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换的方式可以是：当读取到当前逻辑元素为中置运算符或者后置运算符时，若当前逻辑元素的前向相邻逻辑元素为顶点元素，则将当前逻辑元素作为新的根节点插入树中，并将前向相邻逻辑元素变换为新的根节点的子节点。
其中，将当前逻辑元素作为新的根节点插入树中，并将前向相邻逻辑元素变换为新的根节点的子节点的过程可以是，首先将当前逻辑元素作为其前向相邻逻辑元素的子节点插入树中，然后将当前逻辑元素与其前向相邻逻辑元素互换位置。示例性的，图3是本实施例中将读取到的逻辑元素作为树节点进行树的插入或者变换的示例图，如图3所示，假设逻辑信息为“1+a”，当读取到“+”时，由于其前置相邻的逻辑元素“1”为顶点元素，则将“+”作为新的根节点，并将“1”变换为“+”的子节点。
例如，按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换的方式可以是：当读取到的当前逻辑元素为中置运算符或者后置运算符时，若当前逻辑元素的前向相邻逻辑元素为非顶点元素，则在已构建的树中向上查找运算符；若查找到优先级小于或者等于当前逻辑元素的运算符，则将当前逻辑元素作为查找到的运算符的子节点插入树中，并将当前逻辑元素的前向相邻逻辑元素变换为当前逻辑元素的子节点；若未查找到优先级小于或者等于当前逻辑元素的运算符，则将当前逻辑元素作为根节点插入树中。
其中，在已构建的树中向上查找运算符可以理解为从当前节点开始向上查找运算符，直 到查找至根节点。优先级由数学中的逻辑来确定。以公式1-2+3+4*5/6为例，图4a-图4k生成公式对应的逻辑图的示例图。如图4a所示，当读取到“1”时，将“1”作为根节点插入树中。如图4b所示，当读取到“-”时，将“-”作为新的根节点，“1”变换为“-”的子节点。如图4c所示，继续读取到“2”时，将“2”直接作为“-”的子节点。如图4d所示，当读取到“+”时，向上未查找到优先级小于或者等于当前“+”的运算符，则将“+”作为新的根节点。如图4e所示，当读取到“3”时，将“3”作为“+”的子节点插入树中。如图4f所示，当读取到“+”时，向上未查找到优先级小于或者等于当前“+”的运算符，则将“+”作为新的根节点。如图4g时，当读取到“4”时，则直接将“4”作为与其相邻的“+”的子节点。如图4h所示，当读取到“*”时，向上查找到处于根节点的“+”的优先级小于“*”，则将“*”作为“+”的子节点插入树中，并将“4”变换为“*”的子节点。如图4i所示，当读取到“5”时，将“5”直接作为“*”的子节点插入树中。如图4j所示，当读取到“/”时，向上查找到“*”的优先级与“/”的优先级相同，则将“/”作为“*”的子节点插入树中，并将“5”变换为“/”的子节点。如图4k所示，当读取到“6”时，将“6”作为“/”的子节点插入树中。
例如，按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换的方式可以是：若读取到的当前逻辑元素为多级嵌套表达式，对于多级嵌套表达式中的每一级子表达式，从起始符开始读取子表达式内的逻辑元素，对于子表达式内的逻辑元素按照设定规则进行树的插入或者变换，获得子树，并将子树作为子表达式的相邻运算符的子节点；当读取到结束符时，完成读取子表达式，则回滚至起始符的父节点继续进行树的插入和变换，直到多级嵌套表达式完成树的插入或变换。
其中，多级嵌套表达式可以理解为包含至少一级的子表达式，其中子表达式由括号包围，例如可以是函数表达式。回滚至起始符的父节点可以理解为将起始符的父节点作为当前节点。本实施例中，对于每一个子表达式，如果是起始符，如(，则继续读取起始符后的逻辑元素，并按照上述规则将读取到的逻辑元素进行树的插入和变换，如果是结束符，如)，则回滚至对应的起始符的父节点继续进行树的插入和变换。
示例性的，图5a-图5e为生成公式对应的逻辑图的示例图，以公式2-abs(a-b)+3为例。如图5a所示，首先读取到“2”，则将“2”作为根节点插入树中。如图5b所示，当读取到“-”时，将“-”作为新的根节点，“2”变换为“-”的子节点。如图5c所示，当读取到“abs”时，首先生成“abs”对应的子树。如图5d所示，将“abs”对应的子树挂载为“-”的子节点，并回滚至“abs”所在的节点。如图5e所示，则继续依次读取“+”和“3”，按照上述规则，将“+”和“3”插入树中。
步骤130，将多层树节点转化为多个图形节点。
其中，不同类型的逻辑元素转化为图形节点的类型也不同。本实施例中，对语法树从根节点开始进行层序遍历，将获得的每一层树节点保存在一个二维数组中，将每一层的树节点转化为图形节点。然后根据树节点间的从属关系(父子关系)对图形节点进行连接，获得逻辑图。其中，二维数组中其中一个维度存储层级序号，另一个维度存储多个层级包含的树节点。
例如，将多层树节点转化为多个图形节点的过程可以是：对语法树进行层级遍历，若遍历到的树节点为运算符或者函数，则将树节点转化为运算图形节点；若遍历到的树节点为数值，则将树节点转化为数值图形节点；若遍历到的树节点为变量，则将树节点转化为占位符图形节点。
其中，运算符可以是加减乘除等逻辑的符号，函数可以是例如abs或者cos等函数。数值图形节点和占位符图形节点或作为运算图形节点的输入。
例如，对于数值，可以直接将该数值映射为其父节点的输入数据，无需再生成一个数值图形节点，这样可以节省系统资源。
步骤140，将多个图形节点按照从属关系进行连接，获得目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
其中，从属关系可以理解为语法树中的父子关系。
将所述多个图形节点按照所述从属关系进行连接，包括：
例如，将多个图形节点按照从属关系进行连接的方式可以是：将语法树中子节点对应的图形节点的输出端口与其父节点对应的图形节点的输入端口相连。即本实施例中，语法树中子节点转化的图形节点会作为其父节点转化的图形节点的输入。
本实施例中，将语法树中子节点对应的图形节点的输出端口与其父节点对应的图形节点的输入端口相连的过程可以是：将数值图形节点或者占位符图形节点的输出端口与其父节点对应的运算图形节点的输入端口相连；将非根节点的运算图形节点的输出端口与其父节点对应的运算图形节点的输入端口相连。
示例性的，图6是本实施例中生成的逻辑图的示例图。如图6所示，以2-abs(a-b)+3为例，将该公式生成的语法树从根节点开始转化为图形节点，将“+”转化为“求和节点”，将“-”转化为“作差节点”，将“3”转化为数值图形节点，将“2”转化为数值图形节点，将“abs”转化为“求取绝对值节点”，将“-”转化为“作差节点”，将“a”和“b”依次转化为占位符图形节点。将“a”和“b”分别对应的占位符图形节点的输出端口与上一级的“作差节点”的输入端口相连，将“作差节点”的输出端口与“求取绝对值节点”的输入端口相连，将“2”对应的数值图形节点以及“求取绝对值节点”的输出端口与上一级的“作差节点”的输入端口相连，将“作差节点”的输出端口及“3”对应的数值图形节点的输出端口与“求和节点”的输入端口相连，从而生成逻辑图。
例如，对目标逻辑信息进行解析，获得多个逻辑元素之后，还包括如下步骤：若所述目标逻辑信息包括多级嵌套表达式，则生成设定栈；将多级嵌套表达式包含的逻辑元素从起始符开始依次压入设定栈中，当压至结束符时，依次弹出设定栈中的逻辑元素，直到弹至与结束符匹配的起始符，根据弹出的逻辑元素生成子表达式；若多级嵌套表达式解析完成未完成，则对剩余的逻辑元素返回执行依次压入设定栈中，当压至结束符时，依次弹出设定栈中的逻辑元素，直到弹至与结束符匹配的起始符，根据弹出的逻辑元素生成子表达式的操作；若多级嵌套表达式解析完成，则判断设定栈中是否存在逻辑元素，若存在，则进行报错提醒。
本实施例中，当解析到结束符时，则表明一个子表达式解析完成，此时，弹出设定栈中的逻辑元素，直到弹指匹配的起始符，从而由弹出的起始符与结束符之间的逻辑元素生成子表达式。示例性的，图7为本实施例中解析多级嵌套表达式的示例图。如图7所示，以(1+sin(3.14/2)+1)为例，对于多级嵌套表达式：(1+sin(3.14/2)+1)，当压栈至2后的结束符)时，开始弹出设定栈中的逻辑元素，直到弹出sin(，根据弹出的逻辑元素生成子表达式sin(3.14/2)，继续从sin(3.14/2)开始压栈，直到多级嵌套表达式解析完成。
本实施例中，在获得目标逻辑信息对应的逻辑图后，将该逻辑图与其他特效节点组合以实现图像特效或者音频特效的编辑。示例性的，假设在生成图像形变特效包时，需要对图像 的形变参数进行运算，此时可以调用形变公式对应的逻辑图进行运算，并将逻辑图的运算结果输入形变特效节点，以生成图像形变特效。再例如：在对音频进行特效编辑时，逻辑是将两段音频音量的平均值作为第三段音频的音量，则需要调用公式(a+b)/2对应的逻辑图进行处理。
本公开实施例的技术方案，对目标逻辑信息进行解析，获得多个逻辑元素；按照目标逻辑信息的逻辑将多个逻辑元素转化为语法树；其中，语法树包括多层树节点，且层级间树节点具有从属关系；将多层树节点转化为多个图形节点；将多个图形节点按照从属关系进行连接，获得目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。本公开实施例提供的图形生成方法，可以将逻辑信息转化为逻辑图，使得用户通过逻辑图来配置计算逻辑，以实现音频特效以及图像特效的编辑，提高配置效率。
图8是本公开实施例提供的一种图形生成装置的结构示意图，如图8所示，该装置包括：
逻辑元素获取模块210，设置为对目标逻辑信息进行解析，获得多个逻辑元素；
语法树获取模块220，设置为按照目标逻辑信息的逻辑将多个逻辑元素转化为语法树；其中，语法树包括多层树节点，且层级间树节点具有从属关系；
图形节点转化模块230，设置为将多层树节点转化为多个图形节点；
逻辑图获取模块240，设置为将多个图形节点按照从属关系进行连接，获得目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
例如，逻辑元素包括数值、变量、运算符、多级嵌套表达式；其中，多级嵌套表达式由多级子表达式构成，且子表达式包括起始符和结束符。
例如，语法树获取模块220，还设置为：
按照目标逻辑信息的编辑顺序依次读取多个逻辑元素；
按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，获得语法树。
例如，所述读取到的当前逻辑元素为如下任一类型：数值、变量或者前置运算符，语法树获取模块220，还设置为：
响应于确定当前逻辑元素为顶点元素，将当前逻辑元素作为根节点插入树中；
响应于确定当前逻辑元素为非顶点元素，将当前逻辑元素作为其相邻运算符的子节点插入树中。
例如，读取到的当前逻辑元素为中置运算符或者后置运算符，语法树获取模块220，还设置为：
响应于确定当前逻辑元素的前向相邻逻辑元素为顶点元素，将当前逻辑元素作为新的根节点插入树中，并将前向相邻逻辑元素变换为新的根节点的子节点。
例如，读取到的当前逻辑元素为中置运算符或者后置运算符，语法树获取模块220，还设置为：
响应于确定当前逻辑元素的前向相邻逻辑元素为非顶点元素，在已构建的树中向上查找运算符；
响应于确定查找到优先级小于或者等于当前逻辑元素的运算符，将当前逻辑元素作为查找到的运算符的子节点插入树中，并将当前逻辑元素的前向相邻逻辑元素变换为当前逻辑元素的子节点；
响应于确定未查找到优先级小于或者等于当前逻辑元素的运算符，将当前逻辑元素作为 根节点插入树中。
例如，语法树获取模块220，还设置为：
响应于确定读取到的当前逻辑元素为多级嵌套表达式，对于多级嵌套表达式中的每一级子表达式，从起始符开始读取子表达式内的逻辑元素，对于子表达式内的逻辑元素按照设定规则进行树的插入或者变换，获得子树，并将子树作为子表达式的相邻运算符的子节点；
响应于确定读取到结束符，完成读取子表达式，回滚至起始符的父节点继续进行树的插入和变换，直到多级嵌套表达式完成树的插入或变换。
例如，图形节点转化模块230，还设置为：
对语法树进行层级遍历，响应于确定遍历到的树节点为运算符或者函数，将树节点转化为运算图形节点；
响应于确定遍历到的树节点为数值，将树节点转化为数值图形节点；
响应于确定遍历到的树节点为变量，将树节点转化为占位符图形节点。
例如，逻辑图获取模块240，还设置为：
将语法树中子节点对应的图形节点的输出端口与所述语法树中子节点的父节点对应的图形节点的输入端口相连。
例如，逻辑图获取模块240，还设置为：
将数值图形节点的输出端口与所述数值图形节点对应语法树中子节点的父节点对应的运算图形节点的输入端口相连，或者将占位符图形节点的输出端口与数值图形节点对应语法树中子节点的父节点对应的运算图形节点的输入端口相连；
将非根节点的运算图形节点的输出端口与所述非根节点的父节点对应的运算图形节点的输入端口相连。
例如，图形生成装置还包括：多级嵌套表达式解析模块，设置为响应于确定目标逻辑信息包括多级嵌套表达式，生成设定栈；
将多级嵌套表达式包含的逻辑元素从起始符开始依次压入设定栈中，响应于确定压至结束符，依次弹出设定栈中的逻辑元素，直到弹至与结束符匹配的起始符，根据弹出的逻辑元素生成子表达式；
响应于确定多级嵌套表达式解析完成未完成，对剩余的逻辑元素返回执行依次压入设定栈中，响应于确定压至结束符，依次弹出设定栈中的逻辑元素，直到弹至与结束符匹配的起始符，根据弹出的逻辑元素生成子表达式的操作；
响应于确定多级嵌套表达式解析完成，判断设定栈中是否存在逻辑元素，基于设定栈中存在逻辑元素的判断结果，进行报错提醒。
上述装置可执行本公开前述所有实施例所提供的方法，具备执行上述方法相应的功能模块和有益效果。未在本实施例中详尽描述的技术细节，可参见本公开前述所有实施例所提供的方法。
下面参考图9，其示出了适于用来实现本公开实施例的电子设备300的结构示意图。本公开实施例中的电子设备可以包括但不限于诸如移动电话、笔记本电脑、数字广播接收器、PDA(个人数字助理)、PAD(平板电脑)、PMP(便携式多媒体播放器)、车载终端(例如车载导航终端)等等的移动终端以及诸如数字TV、台式计算机等等的固定终端，或者多种形式的服务器，如独立服务器或者服务器集群。图9示出的电子设备仅仅是一个示例，不应对本 公开实施例的功能和使用范围带来任何限制。
如图9所示，电子设备300可以包括处理装置(例如中央处理器、图形处理器等)301，其可以根据存储在只读存储装置(ROM)302中的程序或者从存储装置305加载到随机访问存储装置(RAM)303中的程序而执行多种适当的动作和处理。在RAM 303中，还存储有电子设备300操作所需的多种程序和数据。处理装置301、ROM 302以及RAM 303通过总线304彼此相连。输入/输出(I/O)接口305也连接至总线304。
通常，以下装置可以连接至I/O接口305：包括例如触摸屏、触摸板、键盘、鼠标、摄像头、麦克风、加速度计、陀螺仪等的输入装置306；包括例如液晶显示器(LCD)、扬声器、振动器等的输出装置307；包括例如磁带、硬盘等的存储装置308；以及通信装置309。通信装置309可以允许电子设备300与其他设备进行无线或有线通信以交换数据。虽然图9示出了具有多种装置的电子设备300，但是应理解的是，并不要求实施或具备所有示出的装置。可以替代地实施或具备更多或更少的装置。
根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行词语的推荐方法的程序代码。在这样的实施例中，该计算机程序可以通过通信装置309从网络上被下载和安装，或者从存储装置305被安装，或者从ROM 302被安装。在该计算机程序被处理装置301执行时，执行本公开实施例的方法中限定的上述功能。
需要说明的是，本公开上述的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读信号介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：电线、光缆、RF(射频)等等，或者上述的任意合适的组合。计算机可读存储介质可以为非暂态计算机可读存储介质。
在一些实施方式中，客户端、服务器可以利用诸如HTTP(HyperText Transfer Protocol，超文本传输协议)之类的任何当前已知或未来研发的网络协议进行通信，并且可以与任意形式或介质的数字数据通信(例如，通信网络)互连。通信网络的示例包括局域网(“LAN”)，广域网(“WAN”)，网际网(例如，互联网)以及端对端网络(例如，ad hoc端对端网络)，以及任何当前已知或未来研发的网络。
上述计算机可读介质可以是上述电子设备中所包含的；也可以是单独存在，而未装配入 该电子设备中。
上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被该电子设备执行时，使得该电子设备：对目标逻辑信息进行解析，获得多个逻辑元素；按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；将所述多层树节点转化为多个图形节点；将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
可以以一种或多种程序设计语言或其组合来编写用于执行本公开的操作的计算机程序代码，上述程序设计语言包括但不限于面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括局域网(LAN)或广域网(WAN)—连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
附图中的流程图和框图，图示了按照本公开多种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，该模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的单元可以通过软件的方式实现，也可以通过硬件的方式来实现。其中，单元的名称在某种情况下并不构成对该单元本身的限定。
本文中以上描述的功能可以至少部分地由一个或多个硬件逻辑部件来执行。例如，非限制性地，可以使用的示范类型的硬件逻辑部件包括：现场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、片上系统(SOC)、复杂可编程逻辑设备(CPLD)等等。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
根据本公开实施例的一个或多个实施例，本公开实施例公开了一种图形生成方法，包括：
对目标逻辑信息进行解析，获得多个逻辑元素；
按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；
将所述多层树节点转化为多个图形节点；
将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
例如，所述逻辑元素包括数值、变量、运算符、多级嵌套表达式；其中，多级嵌套表达式由多级子表达式构成，且所述子表达式包括起始符和结束符。
例如，按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树，包括：
按照所述目标逻辑信息的编辑顺序依次读取所述多个逻辑元素；
按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，获得语法树。
例如，所述读取到的当前逻辑元素为如下任一类型：数值、变量或者前置运算符，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
若所述当前逻辑元素为顶点元素，则将所述当前逻辑元素作为根节点插入树中；
若所述当前逻辑元素为非顶点元素，则将所述当前逻辑元素作为其相邻运算符的子节点插入树中。
例如，所述读取到的当前逻辑元素为中置运算符或者后置运算符，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
若所述当前逻辑元素的前向相邻逻辑元素为顶点元素，则将所述当前逻辑元素作为新的根节点插入树中，并将所述前向相邻逻辑元素变换为所述新的根节点的子节点。
例如，所述读取到的当前逻辑元素为中置运算符或者后置运算符，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
若所述当前逻辑元素的前向相邻逻辑元素为非顶点元素，则在已构建的树中向上查找运算符；
若查找到优先级小于或者等于所述当前逻辑元素的运算符，则将所述当前逻辑元素作为查找到的运算符的子节点插入树中，并将所述当前逻辑元素的前向相邻逻辑元素变换为所述当前逻辑元素的子节点；
若未查找到优先级小于或者等于所述当前逻辑元素的运算符，则将所述当前逻辑元素作为根节点插入树中。
例如，按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
若读取到的当前逻辑元素为多级嵌套表达式，对于所述多级嵌套表达式中的每一级子表达式，从所述起始符开始读取所述子表达式内的逻辑元素，对于所述子表达式内的逻辑元素按照设定规则进行树的插入或者变换，获得子树，并将所述子树作为所述子表达式的相邻运算符的子节点；
当读取到所述结束符时，完成读取所述子表达式，则回滚至所述起始符的父节点继续进行树的插入和变换，直到所述多级嵌套表达式完成树的插入或变换。
例如，将所述多层树节点转化为多个图形节点，包括：
对所述语法树进行层级遍历，若遍历到的树节点为运算符或者函数，则将所述树节点转化为运算图形节点；
若遍历到的树节点为数值，则将所述树节点转化为数值图形节点；
若遍历到的树节点为变量，则将所述树节点转化为占位符图形节点。
例如，将所述多个图形节点按照所述从属关系进行连接，包括：
将语法树中子节点对应的图形节点的输出端口与其父节点对应的图形节点的输入端口相连。
例如，将语法树中子节点对应的图形节点的输出端口与其父节点对应的图形节点的输入端口相连，包括：
将所述数值图形节点或者占位符图形节点的输出端口与其父节点对应的运算图形节点的输入端口相连；
将非根节点的运算图形节点的输出端口与其父节点对应的运算图形节点的输入端口相连。
例如，该方法中，在所述对目标逻辑信息进行解析，获得多个逻辑元素之后，还包括：
若所述目标逻辑信息包括多级嵌套表达式，则生成设定栈；
将所述多级嵌套表达式包含的逻辑元素从起始符开始依次压入所述设定栈中，当压至结束符时，依次弹出所述设定栈中的逻辑元素，直到弹至与所述结束符匹配的起始符，根据弹出的逻辑元素生成子表达式；
若所述多级嵌套表达式解析完成未完成，则对剩余的逻辑元素返回执行依次压入所述设定栈中，当压至结束符时，依次弹出所述设定栈中的逻辑元素，直到弹至与所述结束符匹配的起始符，根据弹出的逻辑元素生成子表达式的操作；
若所述多级嵌套表达式解析完成，则判断所述设定栈中是否存在逻辑元素，若存在，则进行报错提醒。

Claims (14)

  1. 一种图形生成方法，包括：
    对目标逻辑信息进行解析，获得多个逻辑元素；
    按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；
    将所述多层树节点转化为多个图形节点；
    将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
  2. 根据权利要求1所述的方法，其中，所述逻辑信息为逻辑表达式，所述逻辑元素包括数值、变量、运算符、多级嵌套表达式；其中，所述多级嵌套表达式由多级子表达式构成，且所述子表达式包括起始符和结束符。
  3. 根据权利要求2所述的方法，其中，所述按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树，包括：
    按照所述目标逻辑信息的编辑顺序依次读取所述多个逻辑元素；
    按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，获得语法树。
  4. 根据权利要求3所述的方法，其中，所述读取到的当前逻辑元素为如下任一类型：数值、变量或者前置运算符，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
    响应于确定所述当前逻辑元素为顶点元素，将所述当前逻辑元素作为根节点插入树中；
    响应于确定所述当前逻辑元素为非顶点元素，将所述当前逻辑元素作为其相邻运算符的子节点插入树中。
  5. 根据权利要求3所述的方法，其中，所述读取到的当前逻辑元素为中置运算符或者后置运算符，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
    响应于确定所述当前逻辑元素的前向相邻逻辑元素为顶点元素，将所述当前逻辑元素作为新的根节点插入树中，并将所述前向相邻逻辑元素变换为所述新的根节点的子节点。
  6. 根据权利要求5所述的方法，其中，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
    响应于确定所述当前逻辑元素的前向相邻逻辑元素为非顶点元素，在已构建的树中向上查找运算符；
    响应于确定查找到优先级小于或者等于所述当前逻辑元素的运算符，将所述当前逻辑元素作为查找到的运算符的子节点插入树中，并将所述当前逻辑元素的前向相邻逻辑元素变换为所述当前逻辑元素的子节点；
    响应于确定未查找到优先级小于或者等于所述当前逻辑元素的运算符，将所述当前逻辑元素作为根节点插入树中。
  7. 根据权利要求4-6任一所述的方法，其中，所述按照设定规则将读取到的逻辑元素作为树节点进行树的插入或者变换，包括：
    响应于确定读取到的当前逻辑元素为多级嵌套表达式，对于所述多级嵌套表达式中的每一级子表达式，从所述起始符开始读取所述子表达式内的逻辑元素，对于所述子表达式内的逻辑元素按照设定规则进行树的插入或者变换，获得子树，并将所述子树作为所述子表达式的相邻运算符的子节点；
    响应于确定读取到所述结束符，完成读取所述子表达式，回滚至所述起始符的父节点继续进行树的插入和变换，直到所述多级嵌套表达式完成树的插入或变换。
  8. 根据权利要求1所述的方法，其中，所述将所述多层树节点转化为多个图形节点，包括：
    对所述语法树进行层级遍历，响应于确定遍历到的树节点为运算符或者函数，将所述树节点转化为运算图形节点；
    响应于确定遍历到的树节点为数值，将所述树节点转化为数值图形节点；
    响应于确定遍历到的树节点为变量，将所述树节点转化为占位符图形节点。
  9. 根据权利要求8所述的方法，其中，所述将所述多个图形节点按照所述从属关系进行连接，包括：
    将语法树中子节点对应的图形节点的输出端口与所述语法树中子节点的父节点对应的图形节点的输入端口相连。
  10. 根据权利要求9所述的方法，其中，所述将语法树中子节点对应的图形节点的输出端口与所述语法树中子节点的父节点对应的图形节点的输入端口相连，包括：
    将所述数值图形节点的输出端口与所述数值图形节点对应语法树中子节点的父节点对应的运算图形节点的输入端口相连，或将所述占位符图形节点的输出端口与所述占位符图形节点对应语法树中子节点的父节点对应的运算图形节点的输入端口相连；
    将非根节点的运算图形节点的输出端口与所述非根节点的父节点对应的运算图形节点的输入端口相连。
  11. 根据权利要求2所述的方法，所述对目标逻辑信息进行解析，获得多个逻辑元素之后，还包括：
    响应于确定所述目标逻辑信息包括多级嵌套表达式，生成设定栈；
    将所述多级嵌套表达式包含的逻辑元素从所述起始符开始依次压入所述设定栈中，响应于确定压至结束符，依次弹出所述设定栈中的逻辑元素，直到弹至与所述结束符匹配的起始符，根据弹出的逻辑元素生成子表达式；
    响应于确定所述多级嵌套表达式解析完成未完成，对剩余的逻辑元素返回执行依次压入所述设定栈中，响应于确定压至结束符，依次弹出所述设定栈中的逻辑元素，直到弹至与所述结束符匹配的起始符，根据弹出的逻辑元素生成子表达式的操作；
    响应于确定所述多级嵌套表达式解析完成，判断所述设定栈中是否存在逻辑元素，基于所述设定栈中存在逻辑元素的判断结果，进行报错提醒。
  12. 一种图形生成装置，包括：
    逻辑元素获取模块，设置为对目标逻辑信息进行解析，获得多个逻辑元素；
    语法树获取模块，设置为按照所述目标逻辑信息的逻辑将所述多个逻辑元素转化为语法树；其中，所述语法树包括多层树节点，且层级间树节点具有从属关系；
    图形节点转化模块，设置为将所述多层树节点转化为多个图形节点；
    逻辑图获取模块，设置为将所述多个图形节点按照所述从属关系进行连接，获得所述目标逻辑信息对应的逻辑图，使得用户基于所述逻辑图进行特效的编辑。
  13. 一种电子设备，包括：
    一个或多个处理装置；
    存储装置，设置为存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理装置执行，使得所述一个或多个处理装置实现如权利要求1-11中任一所述的图形生成方法。
  14. 一种计算机可读介质，其上存储有计算机程序，所述计算机程序被处理装置执行时实现如权利要求1-11中任一所述的图形生成方法。
PCT/CN2023/071873 2022-01-20 2023-01-12 图形生成方法、装置、设备及存储介质 WO2023138466A1 (zh)

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