WO2023124372A1 - 浮点数处理装置、方法、电子设备、存储介质及芯片 - Google Patents

浮点数处理装置、方法、电子设备、存储介质及芯片 Download PDF

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WO2023124372A1
WO2023124372A1 PCT/CN2022/124517 CN2022124517W WO2023124372A1 WO 2023124372 A1 WO2023124372 A1 WO 2023124372A1 CN 2022124517 W CN2022124517 W CN 2022124517W WO 2023124372 A1 WO2023124372 A1 WO 2023124372A1
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floating
point number
target
point
processed
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French (fr)
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霍冠廷
王文强
徐宁仪
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Shanghai Sensetime Intelligent Technology Co Ltd
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Shanghai Sensetime Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
    • G06F7/10—Selecting, i.e. obtaining data of one kind from those record carriers which are identifiable by data of a second kind from a mass of ordered or randomly- distributed record carriers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular, to a floating-point number processing device, method, electronic equipment, computer-readable storage medium, and chip.
  • the floating-point number calculation is a kind of calculation in the processor with many calculation steps, large delay, and high power consumption, which has a great impact on the performance index of the processor. Therefore, it is particularly important to propose a method for optimizing the floating-point number processing process.
  • the present disclosure at least provides a floating-point number processing device, method, electronic equipment, computer-readable storage medium, and chip.
  • the present disclosure provides a floating-point number processing device, the device comprising: a selector, configured to extend the sign bit of each of the obtained multiple floating-point numbers to be processed to The target bit width is to obtain a plurality of extended floating-point numbers; wherein, the target bit-width matches the total number of floating-point numbers to be processed; an adder is connected to the selector for converting the plurality of extended The floating-point numbers are accumulated to obtain the target floating-point number.
  • a selector can be used to extend the sign bit of each floating-point number to be processed to the target bit width, and multiple extended floating-point numbers can be obtained. points, which realizes the expansion of the bit width of the floating-point numbers to be processed, and then makes it unnecessary to normalize the intermediate floating-point numbers obtained during the accumulation process during the accumulation process of multiple expanded floating-point numbers, reducing the normalization process.
  • the number of times reduces the delay and power consumption of the chip to process the accumulation process of multiple extended floating-point numbers; at the same time, after reducing the number of normalized processing, it can alleviate the data loss problem caused by normalized processing and improve the accuracy of the target floating-point number. precision.
  • the device further includes: a comparator connected to the adder, configured to normalize the target floating-point number input from the adder to obtain a target processing result, Wherein, the format of the target processing result matches the preset format.
  • the target floating-point number can be normalized once after accumulating to obtain the target floating-point number
  • the target processing result is obtained, the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple floating-point numbers processed by the target chip are reduced; at the same time, the data loss problem caused by the normalized processing can be alleviated, and the The precision of the target processing result.
  • the device further includes: an arithmetic operator connected to the adder and the selector respectively; the arithmetic operator includes a subtractor and a shifter bit device; the subtractor is used to determine the target difference between the initial exponent and the target exponent of each of the extended floating-point numbers; wherein, the target exponent is based on the initial exponent of the plurality of extended floating-point numbers The exponent is determined; the shifter is used to align the initial exponent of the extended floating-point number to the target index for each of the extended floating-point numbers, and based on the target difference corresponding to the extended floating-point number , right-shifting the mantissa of the expanded floating-point number to obtain a processed floating-point number, and input the processed floating-point number to the adder; The mantissas of the processed floating-point numbers respectively obtained by the floating-point numbers are accumulated to obtain the target floating-point number.
  • the selector after extending the sign bit of each of the acquired multiple floating-point numbers to be processed to the target bit width, obtains multiple extended floating-point numbers In point numbers, it is used to: select two floating-point numbers to be processed from the plurality of floating-point numbers to be processed, and extend the sign bits of the two floating-point numbers to the target bit width to obtain two expanded floating-point number; the subtractor is used to use the initial index of the first floating-point number in the two expanded floating-point numbers as the target index; determine the target index and the second of the two expanded floating-point numbers A first difference of the initial exponent of the floating point number; wherein, the initial exponent of the first floating point number is greater than the initial exponent of the second floating point number; the shifter is used to align the initial exponent of the second floating point number to the target index, and based on the first difference, the mantissa of the second floating point number is shifted to the right to obtain the processed second floating point number; the first floating point number and the processed The second floating-point numbers
  • the device further includes: a first register, connected to the adder and the subtractor in the pair arithmetic unit respectively, and used to store the sum obtained by the adder and The input intermediate floating-point number and the target floating-point number sent by the adder, and send the intermediate floating-point number to the subtractor.
  • the device further includes: a second register, connected to the subtractor, for storing the target index, and sending the target index to the the subtractor.
  • the selector is further configured to: select a floating point number to be processed from unselected floating point numbers to be processed, and extend the sign bit of the selected floating point number to the The target bit width is obtained to obtain the extended floating-point number corresponding to the selected floating-point number to be processed; in response to the initial exponent of the extended floating-point number corresponding to the selected floating-point number to be processed is greater than the target exponent stored in the second register, the The initial exponent of the extended floating-point number corresponding to the floating-point number to be processed is selected as a new target index, and the second register is updated by using the new target index; wherein, the second register is also used to set the The new target index is sent to the subtractor; the subtractor is used to determine a second difference between the index of the intermediate floating-point number and the target index based on the received new target index; the shift The device is used to align the exponent of the intermediate floating-point number to the target exponent, and based on the second difference, right-shift the mantiss
  • the comparator when performing normalization processing on the target floating-point number to obtain the target processing result, is configured to: use one of a shifting method, a truncation method and a rounding method In one or more ways, the target floating-point number is normalized to obtain the target processing result.
  • the target bit width is determined based on an initial bit width of an initial mantissa included in the multiple floating-point numbers to be processed and a total number of the multiple floating-point numbers to be processed.
  • the present disclosure provides a floating-point number processing method, including: obtaining a plurality of floating-point numbers to be processed in the target chip; The sign bit of the point number is extended to the target bit width to obtain a plurality of extended floating-point numbers; wherein, the target bit width matches the total number of floating-point numbers to be processed; The floating-point numbers are accumulated to obtain the target floating-point number.
  • the sign bit of each floating-point number to be processed can be extended to the target bit width, and multiple extended Floating-point numbers, which realize the expansion of the bit width of floating-point numbers to be processed, so that in the process of accumulating multiple expanded floating-point numbers in the target chip, there is no need to normalize the intermediate floating-point numbers obtained during the accumulation process, reducing
  • the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple extended floating-point numbers processed by the target chip are reduced; at the same time, after the number of normalized processing is reduced, the data loss problem caused by normalized processing can be alleviated. Improved precision of target floating point numbers.
  • the method further includes: performing normalization processing on the target floating-point number to obtain a target processing result, wherein the format of the target processing result is the same as match the default format.
  • the target floating-point number can be normalized once after accumulating to obtain the target floating-point number
  • the target processing result is obtained, the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple floating-point numbers processed by the target chip are reduced; at the same time, the data loss problem caused by the normalized processing can be alleviated, and the The precision of the target processing result.
  • the target bit width is determined according to the following steps: based on the initial bit width of the initial mantissa included in the multiple floating-point numbers to be processed, determine the corresponding Adjusting the bit width; determining the target bit width based on the adjusting bit width and the total number of floating point numbers to be processed.
  • the target bit width is determined more accurately, and then the sign bit of the floating point number to be processed is extended to the target bit width, and after obtaining multiple extended floating point numbers,
  • the bit width of the expanded floating-point number can meet the bit-width requirement of the accumulation process, and thus the intermediate floating-point number obtained during the accumulation process does not need to be normalized.
  • extending the sign bit of each of the floating-point numbers to be processed to a target bit width to obtain a plurality of extended floating-point numbers includes: Selecting two floating-point numbers to be processed from the plurality of floating-point numbers to be processed, and extending the sign bits of the two floating-point numbers to the target bit width to obtain two extended floating-point numbers;
  • the multiple expanded floating-point numbers are accumulated and processed to obtain the target floating-point number, including: using the two expanded floating-point numbers as two current floating-point numbers, and using the two expanded floating-point numbers in the target chip
  • the current floating-point numbers are added and processed to obtain an intermediate floating-point number; a floating-point number to be processed is selected from the unselected floating-point numbers to be processed, and the sign bit of the selected floating-point number to be processed is extended to the target bit width.
  • multiple floating-point numbers to be processed can be accumulated multiple times to obtain the target floating-point number, and there is no need to normalize the generated intermediate floating-point numbers during the accumulation process, which alleviates the problem caused by normalizing the intermediate floating-point numbers.
  • the problem of data loss guarantees the precision of the intermediate floating-point numbers, which in turn makes the precision of the obtained target floating-point numbers higher.
  • the adding the two current floating-point numbers in the target chip to obtain an intermediate floating-point number includes: adding the two current floating-point numbers in the target chip The initial exponent of the first floating-point number in the number is aligned to the initial exponent of the second floating-point number, and the mantissa of the first floating-point number is shifted to the right by the target digit to obtain the first floating-point number after order processing; wherein, The initial exponent of the first floating point number in the two floating point numbers is smaller than the initial exponent of the second floating point number; the target number of digits is the initial exponent of the second floating point number and the The difference between the initial exponents; in the target chip, the first floating-point number after the order processing and the second floating-point number are summed to obtain the intermediate floating-point number.
  • the performing normalization processing on the target floating-point number to obtain the target processing result includes: using one or more of a shifting method, a truncation method and a rounding method, Perform normalization processing on the target floating-point number to obtain the target processing result.
  • one or more of shifting, truncation and rounding methods can be used to flexibly normalize the target floating-point number to obtain the target processing result.
  • the present disclosure provides a chip, including: a memory for storing a plurality of floating-point numbers to be processed; the floating-point number processing device as described in the first aspect or any implementation mode above, for processing The plurality of floating-point numbers to be processed are processed to obtain a target floating-point number.
  • the present disclosure provides a floating-point number processing device, including: an acquisition module, used to acquire a plurality of floating-point numbers to be processed in the target chip; an expansion module, used to convert the plurality of floating-point numbers to be processed The sign bit of each floating-point number to be processed in the number is extended to a target bit width to obtain a plurality of extended floating-point numbers; wherein, the target bit width matches the total number of floating-point numbers to be processed; the first processing A module, configured to perform accumulation processing on the plurality of extended floating-point numbers in the target chip to obtain a target floating-point number.
  • the device further includes: a second processing module, configured to perform normalization processing on the target floating-point number to obtain a target processing result, wherein the The format of the target processing result matches the preset format.
  • the expansion module is configured to determine the target bit width according to the following steps: determine the plurality of floating point numbers to be processed based on the initial bit width of the initial mantissa included in the plurality of floating point numbers to be processed A corresponding adjustment bit width: determining the target bit width based on the adjustment bit width and the total number of floating-point numbers to be processed.
  • the extension module extends the sign bit of each of the floating-point numbers to be processed to a target bit width to obtain a plurality of extended floating-point numbers
  • the first processing module is used to: use the two extended floating-point numbers as the two current floating-point numbers when accumulating the multiple extended floating-point numbers in the target chip to obtain the target floating-point number number of points, in the target chip, the two current floating-point numbers are added and processed to obtain an intermediate floating-point number; a floating-point number to be processed is selected from unselected floating-point numbers to be processed, and the selected floating-point number is selected to be processed
  • the sign bit of the floating-point number is extended to the target bit width, and the extended floating-point number corresponding to the selected floating-point number to be processed is obtained; the
  • the first processing module is configured to add the two current floating-point numbers in the target chip to obtain an intermediate floating-point number: in the target chip Aligning the initial exponent of the first floating-point number in the two current floating-point numbers to the initial exponent of the second floating-point number, and shifting the mantissa of the first floating-point number to the right by the target digit to obtain the order-processed first A floating-point number; wherein, the initial exponent of the first floating-point number in the two floating-point numbers is smaller than the initial exponent of the second floating-point number; the target number of digits is the initial exponent of the second floating-point number and The difference between the initial exponents of the first floating-point number; in the target chip, the first floating-point number after the order processing and the second floating-point number are summed to obtain the intermediate floating-point number points.
  • the second processing module when the second processing module performs normalization processing on the target floating-point number to obtain the target processing result, it is configured to: use the shift mode, the truncation mode and the rounding mode In one or more ways, the target floating-point number is normalized to obtain the target processing result.
  • the present disclosure provides an electronic device, including: a processor, a memory, and a bus, the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the The memory communicates with each other through a bus, and when the machine-readable instructions are executed by the processor, the steps of the floating-point number processing method described in the second aspect or any implementation manner are implemented.
  • the present disclosure provides an electronic device, including the chip as described in the third aspect.
  • the present disclosure provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the floating program described in the second aspect or any implementation mode above is executed. Steps in the point processing method.
  • FIG. 1 shows a schematic flowchart of a floating-point number processing method provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a floating-point number processing device provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of another floating-point number processing device provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic structural diagram of a chip provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a floating-point number processing device provided by an embodiment of the present disclosure
  • Fig. 6 shows a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • processors are becoming more powerful and more complex in structure.
  • the floating-point calculation is a kind of calculation in the processor with many calculation steps, large delay and high power consumption, which has a great impact on the performance index of the processor.
  • Accumulation is a common floating-point arithmetic method.
  • two floating-point numbers can be accumulated first to obtain an intermediate result, and the intermediate result can be normalized; then the normalized intermediate result can be compared with the next floating-point number Accumulate until the end of the accumulation operation to obtain the target result.
  • the method of normalizing the intermediate result after each accumulation results in relatively large power consumption and delay of the processor performing the floating-point accumulation operation.
  • the accuracy of the intermediate results after normalization processing will be reduced, and then when the target result is obtained through multiple accumulation operations, the accuracy of the target result is low. .
  • an embodiment of the present disclosure provides a method for processing floating point numbers.
  • the execution subject of the floating-point number processing method provided by the embodiments of the present disclosure is generally a chip with certain computing capabilities, such as the chip can be a processor, and the processor can include a central processing unit (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), tensor processing unit (Tensor Processing Unit, TPU), embedded neural network processor (Neural-network Processing Unit, NPU), etc.
  • the method for processing floating-point numbers may be implemented in a manner in which a processor invokes computer-readable instructions stored in a memory.
  • FIG. 1 is a schematic flowchart of a floating-point number processing method provided by an embodiment of the present disclosure, the method includes S101-S103.
  • the sign bit of each floating-point number to be processed can be extended to the target bit width, and multiple extended Floating-point numbers, which realize the expansion of the bit width of floating-point numbers to be processed, so that in the process of accumulating multiple expanded floating-point numbers in the target chip, there is no need to normalize the intermediate floating-point numbers obtained during the accumulation process, reducing
  • the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple extended floating-point numbers processed by the target chip are reduced; at the same time, after the number of normalized processing is reduced, the data loss problem caused by normalized processing can be alleviated. Improved precision of target floating point numbers.
  • the target chip may be any chip that needs to perform floating-point calculations, for example, the target chip may be a CPU, GPU, NPU, or the like.
  • Floating-point numbers generally include a sign bit, a mantissa, and an exponent.
  • bit width of the mantissa including the sign bit of the floating-point number 1 is 12, and the bit width of the mantissa including the sign bit of the floating-point number 2 is 13, then the bit width of the sum of the floating-point number 1 and the floating-point number 2 may be 14 .
  • the sign bit of each floating-point number to be processed can be extended.
  • the extended bit width may be the target bit width.
  • the target bit width may be a bit width value set by the user, and the target bit width is greater than the initial bit width corresponding to the mantissa of any floating-point number to be processed.
  • the target bit width may also be determined according to the initial bit width corresponding to the mantissa of each floating point number to be processed and the total number of floating point numbers to be processed.
  • the target bit width can be determined, and the sign bit of each floating-point number to be processed is extended to the target bit width to obtain the extended floating-point number.
  • the target bit width is determined according to the following steps: based on the initial bit width of the initial mantissa included in the multiple floating-point numbers to be processed, determine the corresponding Adjusting the bit width; determining the target bit width based on the adjusting bit width and the total number of floating point numbers to be processed.
  • the initial bit width of the initial mantissa of each floating-point number to be processed may be determined, and the adjusted bit width may be determined based on the initial bit widths of multiple initial mantissas.
  • the adjusted bit width may be the maximum value among multiple initial bit widths, or any integer greater than the maximum value. The following takes the adjustment of the bit width as the maximum bit width among multiple initial bit widths as an example for illustration.
  • the number of floating-point numbers to be processed is 5, determine the maximum bit-width among the initial bit-widths of the 5 initial mantissas, and determine the maximum bit-width as the adjusted bit-width;
  • the total number of the target bit width is determined; that is, on the basis of the maximum bit width, according to the total number of floating-point numbers to be processed and the base of the floating-point numbers to be processed, the overflow digits of the sum value are determined, and then according to the overflow digits and Maximum bit width, determine the target bit width.
  • the target bit width is determined more accurately, and then the sign bit of the floating point number to be processed is extended to the target bit width, and after obtaining multiple extended floating point numbers,
  • the bit width of the expanded floating-point number can meet the bit-width requirement of the accumulation process, and thus the intermediate floating-point number obtained during the accumulation process does not need to be normalized.
  • the order processing may include: determining the target index corresponding to a plurality of extended floating-point numbers, for example, the target index may be the maximum index among the initial exponents respectively corresponding to a plurality of extended floating-point numbers, and each extended floating-point number The initial exponent of the point number is aligned to the target exponent, and the mantissa of the extended floating point number is shifted to the right by x bits to obtain the extended floating point number after order processing.
  • x is a positive integer
  • the value of x is the difference between the target exponent and the initial exponent of the expanded floating-point number.
  • two expanded floating-point numbers among multiple expanded floating-point numbers can also be accumulated and processed first, and the obtained intermediate floating-point number and the next expanded floating-point number can be accumulated and processed until each expanded floating-point number is are accumulated to obtain the target floating-point number.
  • the sign bit of each of the floating-point numbers to be processed is extended to the target bit width to obtain a plurality of extended floating-point numbers , may include: selecting two floating-point numbers to be processed from the plurality of floating-point numbers to be processed, and extending the sign bits of the two floating-point numbers to the target bit width to obtain two extended floating-point numbers .
  • two floating-point numbers to be processed can be randomly selected from multiple floating-point numbers to be processed, or the processing order of multiple floating-point numbers to be processed can be set, and two floating-point numbers to be processed are selected according to the processing order; then the selected The sign bits of the two floating-point numbers to be processed are extended to the target bit width, and two extended floating-point numbers are obtained.
  • S103 may include:
  • the two extended floating-point numbers may be used as two current floating-point numbers, and the two current floating-point numbers are summed in the target chip to obtain an intermediate floating-point number.
  • the adding the two current floating-point numbers in the target chip to obtain an intermediate floating-point number may include:
  • Step A1 aligning the initial exponent of the first floating-point number in the two current floating-point numbers to the initial exponent of the second floating-point number in the target chip, and shifting the mantissa of the first floating-point number to the right by the target bit number, to obtain the first floating-point number after order processing; wherein, the initial index of the first floating-point number in the two floating-point numbers is smaller than the initial index of the second floating-point number; the target number of digits is the the difference between the initial exponent of the second floating point number and the initial exponent of the first floating point number;
  • Step A2 Adding the first floating-point number and the second floating-point number after the pairwise processing in the target chip to obtain an intermediate floating-point number.
  • the first floating point number may be a floating point number with a smaller initial exponent among the two current floating point numbers; the second floating point number may be a floating point number with a larger initial exponent among the two current floating point numbers.
  • the first floating-point number can be processed first to obtain the first floating-point number after the order processing, so that the exponent of the first floating-point number after the order processing is the same as the second The initial exponents of floating-point numbers are consistent.
  • the process of order processing of the first floating-point number may include: aligning the initial exponent of the first floating-point number to the initial exponent of the second floating-point number in the target chip, and shifting the initial mantissa of the first floating-point number to the right by the target digit,
  • the target number of digits is the difference between the initial exponent of the second floating point number and the initial exponent of the first floating point number.
  • the initial exponent of the first floating-point number is 10 and the initial exponent of the second floating-point number is 15, align the initial exponent of the first floating-point number to 15, and shift the initial mantissa of the first floating-point number to the right by 5 bits,
  • the first floating-point number after the order processing is obtained, that is, the exponent of the first floating-point number after the order processing is 15.
  • the mantissa of the first floating-point number after the stage processing and the initial mantissa of the second floating-point number are summed to obtain an intermediate floating-point number.
  • a floating-point number to be processed can be selected from unselected floating-point numbers to be processed, and the selected floating-point number to be processed can be a randomly selected floating-point number to be processed, or can be Process the floating-point numbers selected in sequence; then extend the sign bit of the selected floating-point numbers to the target bit width to obtain the extended floating-point numbers corresponding to the selected floating-point numbers.
  • the extended floating-point number and the intermediate floating-point number corresponding to the selected floating-point number to be processed can be used as the updated two current floating-point numbers, and the step is returned to S1031 until each of the multiple floating-point numbers to be processed Until the floating-point numbers to be processed have been summed.
  • the intermediate floating-point number obtained after the last summing process may be used as the target floating-point number.
  • multiple floating-point numbers to be processed can be accumulated multiple times to obtain the target floating-point number. Since the sign bit of each floating-point number to be processed is extended to the target bit width before the floating-point number to be processed is accumulated, the accumulated The mantissa bit width of the intermediate floating-point numbers obtained in the process will not exceed the target bit width, so there is no need to normalize the generated intermediate floating-point numbers during the accumulation process, which alleviates the data loss caused by normalizing the intermediate floating-point numbers.
  • the loss problem guarantees the precision of the intermediate floating-point number, which in turn makes the precision of the obtained target floating-point number higher.
  • the method further includes: performing normalization processing on the target floating-point number to obtain a target processing result, wherein the format of the target processing result is the same as match the default format.
  • the target floating-point number can be normalized once after accumulating to obtain the target floating-point number
  • the target processing result is obtained, the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple floating-point numbers processed by the target chip are reduced; at the same time, the data loss problem caused by the normalized processing can be alleviated, and the The precision of the target processing result.
  • the floating-point numbers are stored in a normalized form in the target chip. Therefore, after accumulating multiple floating-point numbers to be processed to obtain the target floating-point number, the The obtained target floating-point number is normalized to obtain a target processing result, and the format of the target processing result matches the preset format.
  • the preset format may be determined based on a set floating-point number standard.
  • the normalization processing of the target floating-point number to obtain the target processing result may include: using one or more of a shifting method, a truncation method and a rounding method , performing normalization processing on the target floating-point number to obtain a target processing result.
  • one or more of the shifting, truncation and rounding methods can be used to normalize the target floating-point number to obtain the target processing result.
  • the shifting method may include left shifting, right shifting, etc.; the truncation method may be a method of deleting data exceeding a certain number of digits.
  • the target processing result may be a normalized floating point number.
  • one or more of shifting, truncation and rounding methods can be used to flexibly normalize the target floating-point number to obtain the target processing result.
  • the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process.
  • the specific execution order of each step should be based on its function and possible
  • the inner logic is OK.
  • the embodiment of the present disclosure also provides a floating-point number processing device.
  • FIG. 2 which is a schematic structural diagram of a floating-point number processing device provided by an embodiment of the present disclosure
  • the floating-point number processing device includes a selector 201 and an adder 202 ; wherein the adder 202 is connected to the selector 201 .
  • the selector 201 is used to extend the sign bit of each of the obtained multiple floating-point numbers to be processed to a target bit width to obtain multiple extended floating-point numbers; wherein, the target bit Width matches the total number of pending floats in question.
  • the adder 202 is used for accumulating the multiple extended floating-point numbers to obtain a target floating-point number.
  • a selector can be used to extend the sign bit of each floating-point number to be processed to the target bit width, and multiple extended floating-point numbers can be obtained. points, which realizes the expansion of the bit width of the floating-point numbers to be processed, and then makes it unnecessary to normalize the intermediate floating-point numbers obtained during the accumulation process during the accumulation process of multiple expanded floating-point numbers, reducing the normalization process.
  • the number of times reduces the delay and power consumption of the chip to process the accumulation process of multiple extended floating-point numbers; at the same time, after reducing the number of normalized processing, it can alleviate the data loss problem caused by normalized processing and improve the accuracy of the target floating-point number. precision.
  • the device further includes a comparator 203; the comparator 203 is connected to the adder 202; the adder 202 is also used to float the target The points are input to the comparator; the comparator 203 is used to normalize the target floating point number to obtain a target processing result, wherein the format of the target processing result matches a preset format.
  • the target floating-point number can be normalized once after accumulating to obtain the target floating-point number
  • the target processing result is obtained, the number of normalized processing is reduced, and the delay and power consumption of the accumulation process of multiple floating-point numbers processed by the target chip are reduced; at the same time, the data loss problem caused by the normalized processing can be alleviated, and the The precision of the target processing result.
  • the device further includes an arithmetic unit 204 .
  • the pair arithmetic unit 204 is connected to the adder 202 and the selector 201 respectively; the pair arithmetic unit includes a subtractor 241 and a shifter 242 .
  • the subtractor 241 is used to determine the target difference between the initial exponent and the target exponent of each extended floating point number in the plurality of extended floating point numbers, and the target exponent is based on a plurality of extended floating point numbers
  • the initial index of the point number is determined;
  • the shifter 242 is used for aligning the initial index of the extended floating point number to the target index for each of the extended floating point numbers, and based on the extended floating point number
  • the adder 202 is used to add the The mantissas of multiple processed floating-point numbers are accumulated to obtain the target floating-point number.
  • the selector 201 expands the sign bit of each of the obtained multiple floating-point numbers to be processed to the target bit width to obtain multiple extended floating-point numbers
  • it is used to: select two floating-point numbers to be processed from the plurality of floating-point numbers to be processed, and extend the sign bits of the two floating-point numbers to be processed to the target bit width to obtain two extended floating-point numbers;
  • the subtractor 241 is used to use the initial index of the first floating-point number in the two extended floating-point numbers as the target index; determine the target index and the second floating-point number in the two extended floating-point numbers The first difference of the initial exponent of the point number; wherein, the initial exponent of the first floating point number is greater than the initial exponent of the second floating point number;
  • the shifter 242 is used to shift the initial exponent of the second floating point number Aligning to the target index, and based on the first difference, shifting the mantissa of the second floating point number to the right to obtain a processed second floating point number;
  • the device further includes a first register 205 .
  • the first register 205 is respectively connected to the adder 202 and the subtractor 241 of the pair-order operator; the adder 202 is used to input the obtained intermediate floating-point number to the first register 205; The first register 205 is used to store the intermediate floating point number and the target floating point number sent by the adder, and send the intermediate floating point number to the subtractor 241 .
  • the device further includes a second register 206 .
  • the second register 206 is connected to the subtractor 241; the second register 206 is used to store a target index and send the target index to the subtractor 241 in the pair arithmetic unit.
  • the selector 201 is further configured to: select a floating-point number to be processed from unselected floating-point numbers to be processed, and extend the sign bit of the selected floating-point number to the target bit width, to obtain the extended floating-point number corresponding to the selected floating-point number to be processed; in response to the initial index of the extended floating-point number corresponding to the selected floating-point number to be processed is greater than the target index stored in the second register, the selected The initial exponent of the extended floating-point number corresponding to the floating-point number to be processed is used as a new target index, and the second register is updated using the new target index; the second register 206 is also used to use the new target index Send to the subtractor;
  • the subtractor 241 is used for determining the second difference between the index of the intermediate floating-point number and the target index based on the received new target index;
  • the shifter 242 is used for aligning the exponent of the intermediate floating-point number to the target exponent, and based on the second difference, right-shifting the man
  • the comparator 203 when performing normalization processing on the target floating-point number to obtain the target processing result, is configured to: use the shift mode, truncation mode and rounding mode In one or more ways, the target floating-point number is normalized to obtain a target processing result.
  • the target bit width is determined based on an initial bit width of an initial mantissa included in the multiple floating-point numbers to be processed and a total number of the multiple floating-point numbers to be processed.
  • bit width of the adder and the first register is at least the target bit width.
  • the bit width of the second register can be the maximum value in the exponent bit width of the initial index included in the plurality of floating-point numbers to be processed; that is, the index of the initial index of each floating-point number to be processed in the plurality of floating-point numbers to be processed can be determined bit width, and determine the maximum value among the multiple exponent bit widths as the bit width of the second register.
  • the method for processing floating-point numbers proposed in the above-mentioned embodiment is exemplarily described. Assuming that the plurality of floating-point numbers to be processed includes a1, a2, a3, a4, and a5, the floating-point number processing method may include the following steps.
  • Step 1 Input the two floating-point numbers (a1 and a2) to be accumulated into the selector, and the selector expands the sign bits of the two floating-point numbers to the target bit width to obtain two extended floating-point numbers , and input the two extended floating-point numbers to the pair operator.
  • Step 2 the order operator performs order processing on the two extended floating-point numbers to obtain two extended floating-point numbers aligned with the exponents, and input the two extended floating-point numbers aligned with the exponents into the adder;
  • the largest exponent among the initial exponents included in the extended floating-point numbers is used as the target index, and the target index is stored in the second register.
  • the subtractor in the order operator determines the target difference between the initial exponent of the first floating-point number and the target exponent; the shifter can align the initial exponent of the first floating-point number to the target exponent, and shift the first The mantissa of the floating-point number is shifted to the right by the target digit, and the first floating-point number after order processing is obtained.
  • the exponents of the first floating-point number and the second floating-point number after the order processing are consistent.
  • the initial exponent of the first floating-point number is smaller than the initial exponent of the second floating-point number; target difference between .
  • the initial exponent of the second floating point number may be stored in the second register as the target exponent.
  • Step 3 The adder performs a sum operation on the mantissas of the two extended floating-point numbers whose exponents are aligned to obtain an intermediate floating-point number, and stores the intermediate floating-point number in the first register.
  • Step 4 Input the floating-point number a3 to be processed into the selector, and the selector expands the sign bit of the floating-point number a3 to be processed to the target bit width to obtain the expanded floating-point number, and input the expanded floating-point number to the pair operator ; and the first register inputs the intermediate floating-point number to the arithmetic unit.
  • Step 5 The order arithmetic unit performs order processing on the extended floating-point number corresponding to the floating-point number a3 to be processed and the intermediate floating-point number to obtain two extended floating-point numbers aligned with exponents, and input the two extended floating-point numbers aligned with exponents into the adder.
  • the exponent of the intermediate floating-point number aligns the initial exponent of the extended floating-point number to the exponent of the intermediate floating-point number, and shifts the mantissa of the extended floating-point number to the right by the target digit (that is, the difference between the intermediate floating-point number and the exponent of the extended floating-point number difference), to obtain the extended floating-point number after the order processing.
  • the exponents of the extended floating-point number and the intermediate floating-point number after the order processing are the same.
  • the initial exponent of the extended floating-point number is greater than the exponent of the intermediate floating-point number, then the initial exponent of the intermediate floating-point number is aligned to the exponent of the extended floating-point number, and the mantissa of the intermediate floating-point number is shifted to the right by the target digit (that is, after the expansion The difference between the exponent of the floating-point number and the intermediate floating-point number) to obtain the intermediate floating-point number after the order processing.
  • the intermediate floating-point number and the extended floating-point number after the order processing are two extended floating-point numbers whose indices are aligned.
  • the adder directly adds the mantissa of the extended floating-point number and the mantissa of the intermediate floating-point number to obtain the intermediate floating-point number without performing the order processing.
  • Step 6 When the initial exponent in the extended floating-point number corresponding to the floating-point number a3 to be processed is greater than the index of the intermediate floating-point number, the initial exponent in the extended floating-point number can be used as the updated target index, and the updated target The exponent is updated to the second register.
  • Step 7 The adder sums the mantissas of the two expanded floating-point numbers whose exponents are aligned to obtain an intermediate floating-point number, and stores the intermediate floating-point number in the first register.
  • Step eight after obtaining the target floating-point number, the first register can input the target floating-point number to the comparator.
  • the comparator normalizes the target floating-point number to obtain a target processing result, wherein the format of the target processing result matches a preset format.
  • the chip includes: a floating-point number processing device 401 and a memory 402 described in any one of the above-mentioned implementation manners.
  • the memory 402 is used for storing a plurality of floating-point numbers to be processed; the floating-point number processing device 401 is used for processing the plurality of floating-point numbers to be processed to obtain a target floating-point number.
  • the embodiment of the present disclosure also provides a floating-point number processing device.
  • FIG. 5 it is a schematic structural diagram of a floating-point number processing device provided by an embodiment of the present disclosure.
  • the floating-point number processing device includes an acquisition module 501 , an extension module 502 and a first processing module 503 .
  • the obtaining module 501 is used for obtaining a plurality of floating-point numbers to be processed in the target chip.
  • the extension module 502 is configured to extend the sign bit of each of the floating-point numbers to be processed to a target bit width to obtain a plurality of extended floating-point numbers; wherein, the target bit width and the Describes the total number of floating-point numbers to match.
  • the first processing module 503 is configured to perform accumulation processing on the plurality of extended floating-point numbers in the target chip to obtain a target floating-point number.
  • the device further includes: a second processing module 504, configured to perform normalization processing on the target floating-point number to obtain a target processing result, wherein, The format of the target processing result matches the preset format.
  • the expansion module 502 is configured to determine the target bit width according to the following steps: based on the initial bit width of the initial mantissa included in the multiple floating-point numbers to be processed, determine the An adjustment bit width corresponding to the point number; based on the adjustment bit width and the total number of floating point numbers to be processed, the target bit width is determined.
  • the extension module 502 after extending the sign bit of each of the floating-point numbers to be processed to the target bit width, obtains a plurality of extended floating-point numbers In point number, it is used to: select two floating-point numbers to be processed from a plurality of floating-point numbers to be processed, and expand the sign bits of the two floating-point numbers to be processed to the target bit width to obtain two extended floating-point numbers;
  • the first processing module 503 is configured to: use the two expanded floating-point numbers as two current floating-point numbers when performing cumulative processing on the multiple expanded floating-point numbers in the target chip to obtain the target floating-point number, In the target chip, the two current floating-point numbers are summed to obtain an intermediate floating-point number; a floating-point number to be processed is selected from unselected floating-point numbers to be processed, and the selected floating-point number to be processed is selected The sign bit of the selected floating-point number is extended to the target bit width to obtain the extended floating-point number corresponding to the selected floating-point number to be processed;
  • the first processing module 503 is configured to add the two current floating-point numbers in the target chip to obtain an intermediate floating-point number: Align the initial exponent of the first floating-point number in the two current floating-point numbers to the initial exponent of the second floating-point number, and shift the mantissa of the first floating-point number to the right by the target digit to obtain A first floating-point number; wherein, the initial exponent of the first floating-point number in the two floating-point numbers is smaller than the initial exponent of the second floating-point number; the target number of digits is the initial exponent of the second floating-point number and the difference between the initial exponent of the first floating-point number; in the target chip, the first floating-point number after the order processing and the second floating-point number are summed to obtain an intermediate floating-point number .
  • the second processing module 504 when performing normalization processing on the target floating-point number to obtain the target processing result, is configured to: use a shifting method, a truncation method and a rounding method In one or more ways, the target floating-point number is normalized to obtain the target processing result.
  • the functions of the device provided by the embodiments of the present disclosure or the included templates can be used to execute the methods described in the above method embodiments, and its specific implementation can refer to the description of the above method embodiments. For brevity, here No longer.
  • an embodiment of the present disclosure also provides an electronic device.
  • the electronic device includes a processor 601 , a memory 602 and a bus 603 .
  • the memory 602 is used to store execution instructions, including a memory 6021 and an external memory 6022 .
  • the memory 6021 here is also called the internal memory, which is used to temporarily store the calculation data in the processor 601 and the data exchanged with the external memory 6022 such as the hard disk.
  • the processor 601 exchanges data with the external memory 6022 through the memory 6021.
  • the processor 601 communicates with the memory 602 through the bus 603, so that the processor 601 executes the following instructions:
  • an embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the floating-point number processing method described in the above-mentioned method embodiments is executed. step.
  • the storage medium may be a volatile or non-volatile computer-readable storage medium.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the floating-point number processing method described in the above method embodiment.
  • the computer program product carries a program code
  • the instructions included in the program code can be used to execute the steps of the floating-point number processing method described in the above method embodiment.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. wait.
  • a software development kit Software Development Kit, SDK
  • the device described above and the specific working process of the device can refer to the corresponding process in the foregoing method embodiment, and details are not repeated here.
  • the disclosed devices, devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components can be combined or It may be integrated into another device, or some features may be omitted, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may also be distributed to multiple network units . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage medium includes various media that can store program codes such as U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk.

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Abstract

本公开提供了一种浮点数处理装置、方法、电子设备、存储介质及芯片。该浮点数处理方法包括：获取在目标芯片中进行运算的多个待处理浮点数；将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。

Description

浮点数处理装置、方法、电子设备、存储介质及芯片
交叉引用声明
本申请要求于2021年12月31日提交中国专利局的申请号为202111667694.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种浮点数处理装置、方法、电子设备、计算机可读存储介质及芯片。
背景技术
随着半导体工艺、计算机体系结构、处理器设计架构的不断发展，处理器的功能越来越强大，结构也变得越来越复杂。其中，浮点数运算是处理器中运算步骤较多、延迟较大、功耗较大的一类计算，对处理器的性能指标有较大的影响。因此，提出一种优化浮点数处理过程的方法尤为重要。
发明内容
有鉴于此，本公开至少提供一种浮点数处理装置、方法、电子设备、计算机可读存储介质及芯片。
第一方面，本公开提供了一种浮点数处理装置，所述装置包括：选择器，用于将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；加法器，与所述选择器相连，用于将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
为了保障浮点数累加过程的精度，满足加和运算后得到的中间浮点数的位宽要求，可以利用选择器将每个待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数，实现了待处理浮点数位宽的扩展，进而使得对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理，减少了规格化处理的次数，降低了芯片处理多个扩展后浮点数的累加过程的延迟和功耗；同时，减少了规格化处理的次数后，能够缓解规格化处理带来的数据丢失问题，提高了目标浮点数的精度。
在一种可能的实施方式中，所述装置还包括：比较器，与所述加法器相连，用于对从所述加法器输入的所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
实施时，对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理；而是可以在累加得到目标浮点数后，对目标浮点数进行一次规格化处理，得到目标处理结果，减少了规格化处理的次数，降低了目标芯片处理多个浮点数的累加过程的延迟和功耗；同时，可以缓解规格化处理带来的数据丢失问题，提高了目标处理结果的精度。
在一种可能的实施方式中，所述装置还包括：对阶运算器，所述对阶运算器分别与所述加法器和所述选择器相连；所述对阶运算器包括减法器和移位器；所述减法器，用于确定每个所述扩展后浮点数的初始指数与目标指数之间的目标差值；其中，所述目标指数为基于所述多个扩展后浮点数的初始指数确定的；所述移位器用于针对每个所述扩展后浮点数，将所述扩展后浮点数的初始指数对齐至所述目标指数，并基于所述扩展后 浮点数对应的目标差值，对所述扩展后浮点数的尾数进行右移，得到处理后浮点数，并将所述处理后浮点数输入至所述加法器；其中，所述加法器用于将从所述多个扩展后浮点数分别得到的所述处理后浮点数的尾数进行累加处理，得到所述目标浮点数。
在一种可能的实施方式中，所述选择器，在将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数时，用于：从所述多个待处理浮点数中选取两个待处理浮点数，并将所述两个待处理浮点数的符号位扩展至所述目标位宽，得到两个扩展后浮点数；所述减法器用于将所述两个扩展后浮点数中的第一浮点数的初始指数作为所述目标指数；确定所述目标指数与所述两个扩展后浮点数中的第二浮点数的初始指数的第一差值；其中，所述第一浮点数的初始指数大于所述第二浮点数的初始指数；所述移位器用于将所述第二浮点数的初始指数对齐至所述目标指数，并基于所述第一差值，将所述第二浮点数的尾数进行右移，得到处理后的第二浮点数；将所述第一浮点数和所述处理后的第二浮点数输入至所述加法器；所述加法器用于将所述第一浮点数和所述处理后的第二浮点数进行加法处理，得到中间浮点数。
在一种可能的实施方式中，所述装置还包括：第一寄存器，分别与所述加法器和所述对阶运算器中的所述减法器相连，用于存储由所述加法器得到并输入的所述中间浮点数和所述加法器发送的目标浮点数，并将所述中间浮点数发送给所述减法器。
在一种可能的实施方式中，所述装置还包括：第二寄存器，与所述减法器相连，用于存储所述目标指数，并将所述目标指数发送给所述对阶运算器中的所述减法器。
在一种可能的实施方式中，所述选择器还用于：从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至所述目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；响应于所选取的待处理浮点数对应的扩展后浮点数的初始指数大于所述第二寄存器存储的目标指数，将所选取的待处理浮点数对应的扩展后浮点数的初始指数作为新的目标指数，利用所述新的目标指数对所述第二寄存器进行更新；其中，所述第二寄存器还用于将所述新的目标指数发送给所述减法器；所述减法器用于基于接收到的新的目标指数，确定所述中间浮点数的指数与所述目标指数之间的第二差值；所述移位器用于将所述中间浮点数的指数对齐至所述目标指数，并基于所述第二差值，对所述中间浮点数的尾数进行右移，得到处理后中间浮点数，并将所述处理后中间浮点数和所选取的待处理浮点数对应的扩展后浮点数发送给所述加法器；所述加法器用于将所述中间浮点数的尾数和所选取的待处理浮点数对应的扩展后浮点数的尾数进行加法处理，得到新的中间浮点数，并将所述新的中间浮点数发送给所述第一寄存器；以及将最后一次加和处理后得到的中间浮点数作为所述目标浮点数，并将所述目标浮点数发送给所述第一寄存器。
在一种可能的实施方式中，所述比较器，在对所述目标浮点数进行规格化处理，得到目标处理结果时，用于：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到所述目标处理结果。
在一种可能的实施方式中，所述目标位宽为基于所述多个待处理浮点数包括的初始尾数的初始位宽和所述多个待处理浮点数的总数量确定的。
第二方面，本公开提供了一种浮点数处理方法，包括：获取在目标芯片中进行运算的多个待处理浮点数；将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
上述方法中，为了保障浮点数累加过程的精度，满足加和运算后得到的中间浮点数的位宽要求，可以将每个待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点 数，实现了待处理浮点数位宽的扩展，进而使得在目标芯片中对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理，减少了规格化处理的次数，降低了目标芯片处理多个扩展后浮点数的累加过程的延迟和功耗；同时，减少了规格化处理的次数后，能够缓解规格化处理带来的数据丢失问题，提高了目标浮点数的精度。
在一种可能的实施方式中，在所述得到目标浮点数之后，所述方法还包括：对所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
实施时，对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理；而是可以在累加得到目标浮点数后，对目标浮点数进行一次规格化处理，得到目标处理结果，减少了规格化处理的次数，降低了目标芯片处理多个浮点数的累加过程的延迟和功耗；同时，可以缓解规格化处理带来的数据丢失问题，提高了目标处理结果的精度。
在一种可能的实施方式中，所述目标位宽为根据以下步骤确定的：基于所述多个待处理浮点数包括的初始尾数的初始位宽，确定所述多个待处理浮点数对应的调整位宽；基于所述调整位宽和所述待处理浮点数的总数量，确定所述目标位宽。
上述实施方式中，根据调整位宽和待处理浮点数的总数量，较准确的确定目标位宽，后续将待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数后，可以使得扩展后浮点数的位宽能够满足累加处理的位宽要求，进而无需对累加处理过程得到的中间浮点数进行规格化处理。
在一种可能的实施方式中，所述将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数，包括：从所述多个待处理浮点数中选取两个待处理浮点数，并将所述两个待处理浮点数的符号位扩展至所述目标位宽，得到两个扩展后浮点数；所述在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数，包括：将所述两个扩展后浮点数作为两个当前浮点数，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数；从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至所述目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；将所选取的待处理浮点数对应的扩展后浮点数和所述中间浮点数作为更新后的两个当前浮点数，返回至在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数的步骤，直至所述多个待处理浮点数中的每个待处理浮点数均进行过加和处理；将最后一次加和处理后得到的中间浮点数作为所述目标浮点数。
这里，可以将多个待处理浮点数进行多次累加，得到目标浮点数，且在累加过程中无需对生成的中间浮点数进行规格化处理，缓解了对中间浮点数进行规格化处理时造成的数据丢失问题，保障了中间浮点数的精度，进而使得得到的目标浮点数的精度较高。
在一种可能的实施方式中，所述在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数，包括：在所述目标芯片中将所述两个当前浮点数中的第一浮点数的初始指数对齐到第二浮点数的初始指数，并将所述第一浮点数的尾数右移目标位数，得到对阶处理后的第一浮点数；其中，所述两个浮点数中的所述第一浮点数的初始指数小于所述第二浮点数的初始指数；所述目标位数为所述第二浮点数的初始指数与所述第一浮点数的初始指数之间的差值；在所述目标芯片中将所述对阶处理后的第一浮点数与所述第二浮点数进行加和处理，得到所述中间浮点数。
在一种可能的实施方式中，所述对所述目标浮点数进行规格化处理，得到目标处理 结果，包括：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到所述目标处理结果。
这里，可以利用移位方式、截尾方式和舍入方式中的一种或多种方式，灵活的对目标浮点数进行规格化处理，得到目标处理结果。
以下装置、电子设备等的效果描述参见上述方法的说明，这里不再赘述。
第三方面，本公开提供了一种芯片，包括：存储器，用于存储待运算的多个待处理浮点数；如上述第一方面或任一实施方式所述的浮点数处理装置，用于对所述多个待处理浮点数进行处理，得到目标浮点数。
第四方面，本公开提供了一种浮点数处理装置，包括：获取模块，用于获取在目标芯片中进行运算的多个待处理浮点数；扩展模块，用于将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；第一处理模块，用于在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
在一种可能的实施方式中，在所述得到目标浮点数之后，所述装置还包括：第二处理模块，用于对所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
在一种可能的实施方式中，所述扩展模块用于根据以下步骤确定目标位宽：基于所述多个待处理浮点数包括的初始尾数的初始位宽，确定所述多个待处理浮点数对应的调整位宽；基于所述调整位宽和所述待处理浮点数的总数量，确定所述目标位宽。
在一种可能的实施方式中，所述扩展模块，在将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数时，用于：从所述多个待处理浮点数中选取两个待处理浮点数，将所述两个待处理浮点数的符号位扩展至所述目标位宽，得到两个扩展后浮点数；所述第一处理模块，在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数时，用于：将所述两个扩展后浮点数作为两个当前浮点数，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数；从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；将所选取的待处理浮点数对应的扩展后浮点数和所述中间浮点数作为更新后的两个当前浮点数，返回至在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数的步骤，直至所述多个待处理浮点数中的每个待处理浮点数均进行过加和处理；将最后一次加和处理后得到的中间浮点数作为所述目标浮点数。
在一种可能的实施方式中，所述第一处理模块，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数时，用于：在所述目标芯片中将所述两个当前浮点数中的第一浮点数的初始指数对齐到第二浮点数的初始指数，并将所述第一浮点数的尾数右移目标位数，得到对阶处理后的第一浮点数；其中，所述两个浮点数中的所述第一浮点数的初始指数小于所述第二浮点数的初始指数；所述目标位数为所述第二浮点数的初始指数与所述第一浮点数的初始指数之间的差值；在所述目标芯片中将所述对阶处理后的第一浮点数与所述第二浮点数进行加和处理，得到所述中间浮点数。
在一种可能的实施方式中，所述第二处理模块，在对所述目标浮点数进行规格化处理，得到目标处理结果时，用于：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到所述目标处理结果。
第五方面，本公开提供一种电子设备，包括：处理器、存储器和总线，所述存储器 存储有所述处理器可执行的机器可读指令，当电子设备运行时，所述处理器与所述存储器之间通过总线通信，所述机器可读指令被所述处理器执行时实现如上述第二方面或任一实施方式所述的浮点数处理方法的步骤。
第六方面，本公开提供一种电子设备，包括如第三方面所述的芯片。
第七方面，本公开提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行如上述第二方面或任一实施方式所述的浮点数处理方法的步骤。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍。这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种浮点数处理方法的流程示意图；
图2示出了本公开实施例所提供的一种浮点数处理装置的架构示意图；
图3示出了本公开实施例所提供的另一种浮点数处理装置的架构示意图；
图4示出了本公开实施例所提供的一种芯片的架构示意图；
图5示出了本公开实施例所提供的一种浮点数处理装置的架构示意图；
图6示出了本公开实施例所提供的一种电子设备的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述无意限制要求保护的本公开的范围。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
随着半导体工艺、计算机体系结构、处理器设计架构的不断发展，处理器的功能越来越强大，结构也变得越来越复杂。其中，浮点数运算是处理器中一类运算步骤较多、延迟较大、功耗较大的计算，对处理器的性能指标有较大的影响。
累加是一种常见的浮点数运算方式。一般的，在多个浮点数的累加运算中，可以先将两个浮点数进行累加得到中间结果，并将中间结果进行规格化处理；再将规格化处理后的中间结果与下一个浮点数进行累加，直至累加运算结束，得到目标结果。但是，每次累加后均对中间结果进行规格化处理的方式，造成执行浮点数累加运算的处理器的功耗和延时较大。同时，由于规格化处理会造成数据丢失，每次对中间结果进行规格化处理，会造成规格化处理后中间结果的精度降低，进而在多次累加运算得到目标结果时，目标结果的精度较低。
为了缓解上述问题，本公开实施例提供了一种浮点数处理方法。
应注意到，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
为便于对本公开实施例进行理解，首先对本公开实施例所公开的一种浮点数处理方法进行详细介绍。本公开实施例所提供的浮点数处理方法的执行主体一般为具有一定计算能力的芯片，该芯片比如可以为处理器，该处理器可以包括中央处理器(central processing unit，CPU)、图形处理器(graphics processing unit，GPU)、张量处理单元(Tensor Processing Unit，TPU)、嵌入式神经网络处理器(Neural-network Processing Unit，NPU)等。在一些可能的实现方式中，该浮点数处理方法可以通过处理器调用存储器中存储的计算机可读指令的方式来实现。
参见图1所示，为本公开实施例所提供的浮点数处理方法的流程示意图，所述方法包括S101-S103。
S101，获取在目标芯片中进行运算的多个待处理浮点数。
S102，将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配。
S103，在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
上述方法中，为了保障浮点数累加过程的精度，满足加和运算后得到的中间浮点数的位宽要求，可以将每个待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数，实现了待处理浮点数位宽的扩展，进而使得在目标芯片中对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理，减少了规格化处理的次数，降低了目标芯片处理多个扩展后浮点数的累加过程的延迟和功耗；同时，减少了规格化处理的次数后，能够缓解规格化处理带来的数据丢失问题，提高了目标浮点数的精度。
下述对S101-S103进行具体说明。
在S101中，目标芯片可以为任一需要进行浮点数运算的芯片，比如，目标芯片可以为CPU、GPU、NPU等。浮点数一般包括符号位、尾数和指数。比如，浮点数(0.3) 10＝(0011 1110 1001 1001 1001 1001 1001 1010) 2，其中，符号位Sa＝0，指数Ea＝011 1110 1，尾数Ma＝1.001 1001 1001 1001 1001 1010。
在S102中，考虑到在进行多个浮点数的累加时，会将进行累加的多个浮点数进行对阶处理，再将对阶处理后的多个浮点数的包含符号位的尾数进行加和处理。在将多个浮点数的包含符号位的尾数进行加和时，加和后得到的和值的位宽大于或等于加和前的每个浮点数的包括符号位的尾数的位宽。比如，若浮点数1的包含符号位的尾数的位宽为12，浮点数2的包含符号位的尾数的位宽为13，则浮点数1和浮点数2加和后的位宽可能为14。
为了保障加和后得到的浮点数的精度，满足加和运算后得到的和值的位宽要求，可以将每个待处理浮点数的符号位进行扩展。其中，扩展后的位宽可以为目标位宽。该目标位宽可以为用户设置的位宽值，该目标位宽大于任一待处理浮点数的尾数对应的初始位宽。或者，该目标位宽也可以为根据各个待处理浮点数的尾数对应的初始位宽和待处理浮点数的总数量确定的。
实施时，可以确定目标位宽，并将每个待处理浮点数的符号位扩展至目标位宽，得到扩展后浮点数。比如，上述案例中符号位Sa＝0，扩展后的符号位可以为Sa＝0000。
在一种可选实施方式中，所述目标位宽为根据以下步骤确定的：基于所述多个待处理浮点数包括的初始尾数的初始位宽，确定所述多个待处理浮点数对应的调整位宽；基于所述调整位宽和所述待处理浮点数的总数量，确定所述目标位宽。
实施时，可以确定每个待处理浮点数的初始尾数的初始位宽，并基于多个初始尾数的初始位宽，确定调整位宽。该调整位宽可以为多个初始位宽中的最大值，也可以为大于该最大值的任一整数。下述以调整位宽为多个初始位宽中的最大位宽为例进行说明。
比如，若待处理浮点数的数量为5个，则确定5个初始尾数的初始位宽中的最大位宽，将该最大位宽确定为调整位宽；再根据调整位宽和待处理浮点数的总数量，确定目标位宽；即，在最大位宽的基础上，根据待处理浮点数的总数量和待处理浮点数的进制，确定和值的溢出位数，再根据溢出位数和最大位宽，确定目标位宽。比如，目标位宽可以为n+log am，其中，n为调整位宽，m为待处理浮点数的总数量，a为待处理浮点数的数制，比如，a＝2时，表示待处理浮点数为二进制数。
其中，在n+log am的值为小数时可以向上取整，得到目标位宽。比如，在n+log am＝12+log 25＝14.32时，确定该目标位宽可以为15。若待处理浮点数为a＝(0.3) 10＝0 011 1110 1 100 1100 1100 1100 1100 1101，其中，0为符号位，011 1110 1为初始指数，100 1100 1100 1100 1100 1101为初始尾数，则将待处理浮点数的符号位扩展至目标位宽后，该待处理浮点数可以为0000 011 1110 1 100 1100 1100 1100 1100 1101。
上述实施方式中，根据调整位宽和待处理浮点数的总数量，较准确的确定目标位宽，后续将待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数后，可以使得扩展后浮点数的位宽能够满足累加处理的位宽要求，进而无需对累加处理过程得到的中间浮点数进行规格化处理。
在S103中，可以将多个扩展后浮点数进行对阶处理，使得多个扩展后浮点数的初始指数一致，再将对阶处理后的多个扩展后浮点数的初始尾数进行累加，得到目标浮点数。实施时，对阶处理可以包括：确定多个扩展后浮点数对应的目标指数，比如，该目标指数可以为多个扩展后浮点数分别对应的初始指数中的最大指数，将每个扩展后浮点数的初始指数对齐至目标指数，并将该扩展后浮点数的尾数右移x位，得到对阶处理后的扩展后浮点数。其中，x为正整数，x的值为目标指数与该扩展后浮点数的初始指数之差。
实施时，还可以先将多个扩展后浮点数中的两个扩展后浮点数进行累加处理，将得到的中间浮点数与下一个扩展后浮点数进行累加处理，直至每个扩展后浮点数均被累加，得到目标浮点数。
在一种可选实施方式中，在S102中，所述将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数，可以包括：从所述多个待处理浮点数中选取两个待处理浮点数，并将所述两个待处理浮点数的符号位扩展至所述目标位宽，得到两个扩展后浮点数。
实施时，可以从多个待处理浮点数中随机选取两个待处理浮点数，或者，也可以设置多个待处理浮点数的处理顺序，按照处理顺序选取两个待处理浮点数；再将选取的两个待处理浮点数的符号位扩展至目标位宽，得到两个扩展后浮点数。
在得到两个扩展后浮点数之后，S103可以包括：
S1031，将所述两个扩展后浮点数作为两个当前浮点数，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数；
S1032，从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处 理浮点数的符号位扩展至所述目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；
S1033，将所选取的待处理浮点数对应的扩展后浮点数和所述中间浮点数作为更新后的两个当前浮点数，返回至在所述目标芯片中将所述两个当前浮点数进行加和处理，得到所述中间浮点数的步骤，直至所述多个待处理浮点数中的每个待处理浮点数均进行过加和处理；
S1034，将最后一次加和处理后得到的中间浮点数作为所述目标浮点数。
在S1031中，可以将两个扩展后浮点数作为两个当前浮点数，在目标芯片中将两个当前浮点数进行加和处理，得到中间浮点数。
在一种可选实施方式中，所述在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数，可以包括：
步骤A1，在所述目标芯片中将所述两个当前浮点数中的第一浮点数的初始指数对齐到第二浮点数的初始指数，并将所述第一浮点数的尾数右移目标位数，得到对阶处理后的第一浮点数；其中，所述两个浮点数中的所述第一浮点数的初始指数小于所述第二浮点数的初始指数；所述目标位数为所述第二浮点数的初始指数与所述第一浮点数的初始指数之间的差值；
步骤A2，在所述目标芯片中将所述对阶处理后的第一浮点数与所述第二浮点数进行加和处理，得到中间浮点数。
实施时，第一浮点数可以为两个当前浮点数中初始指数较小的浮点数；第二浮点数可以为两个当前浮点数中初始指数较大的浮点数。在将两个当前浮点数进行加和之前，可以先对第一浮点数进行对阶处理，得到对阶处理后的第一浮点数，使得对阶处理后的第一浮点数的指数与第二浮点数的初始指数一致。
第一浮点数的对阶处理的过程可以包括：在目标芯片中将第一浮点数的初始指数对齐至第二浮点数的初始指数，并将第一浮点数的初始尾数右移目标位数，该目标位数为第二浮点数的初始指数与第一浮点数的初始指数之间的差值。比如，若第一浮点数的初始指数为10，第二浮点数的初始指数为15，则将第一浮点数的初始指数对齐至15，并将第一浮点数的初始尾数右移5位，得到对阶处理后的第一浮点数，即，对阶处理后的第一浮点数的指数为15。
在目标芯片中将对阶处理后的第一浮点数的尾数与第二浮点数的初始尾数进行加和处理，得到中间浮点数。
在S1032中，在得到中间浮点数之后，可以从未被选取的待处理浮点数中选取一个待处理浮点数，所选取的待处理浮点数可以为随机选取的待处理浮点数，也可以为按照处理顺序选取的待处理浮点数；再将所选取的待处理浮点数的符号位扩展至目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数。
在S1033中，可以将所选取的待处理浮点数对应的扩展后浮点数和中间浮点数作为更新后的两个当前浮点数，返回至S1031的步骤，直至多个待处理浮点数中的每个待处理浮点数均进行过加和处理为止。
在S1034中，可以将最后一次加和处理后得到的中间浮点数作为目标浮点数。
这里，可以将多个待处理浮点数进行多次累加，得到目标浮点数，由于在将待处理浮点数进行累加之前，将每个待处理浮点数的符号位扩展至了目标位宽，使得累加过程中得到的中间浮点数的尾数位宽不会超出该目标位宽，进而在累加过程中无需对生成 的中间浮点数进行规格化处理，缓解了对中间浮点数进行规格化处理时造成的数据丢失问题，保障了中间浮点数的精度，进而使得得到的目标浮点数的精度较高。
在一种可能的实施方式中，在所述得到目标浮点数之后，所述方法还包括：对所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
实施时，对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理；而是可以在累加得到目标浮点数后，对目标浮点数进行一次规格化处理，得到目标处理结果，减少了规格化处理的次数，降低了目标芯片处理多个浮点数的累加过程的延迟和功耗；同时，可以缓解规格化处理带来的数据丢失问题，提高了目标处理结果的精度。
由于在目标芯片中为了保证浮点数表示的唯一性，浮点数在目标芯片中都是以规格化形式存储的，因此，可以在将多个待处理浮点数进行累加处理得到目标浮点数后，对得到的目标浮点数进行规格化处理，得到目标处理结果，该目标处理结果的格式与预设格式相匹配。其中，该预设格式可以为基于设置的浮点数标准确定的。
在一种可选实施方式中，所述对所述目标浮点数进行规格化处理，得到目标处理结果，可以包括：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到目标处理结果。
实施时，可以利用移位方式、截尾方式和舍入方式中的一种或多种方式，对目标浮点数进行规格化处理，得到目标处理结果。移位方式可以包括左移、右移等；截尾方式可以为将超出特定位数的数据进行删除的方式等。该目标处理结果可以为规格化处理后的浮点数。
这里，可以利用移位方式、截尾方式和舍入方式中的一种或多种方式，灵活的对目标浮点数进行规格化处理，得到目标处理结果。
本领域技术人员可以理解，在具体实施方式的上述方法中，各步骤的撰写顺序并不意味着严格的执行顺序而对实施过程构成任何限定，各步骤的具体执行顺序应当以其功能和可能的内在逻辑确定。
基于相同的构思，本公开实施例还提供了一种浮点数处理装置。参见图2所示，为本公开实施例提供的浮点数处理装置的架构示意图，该浮点数处理装置包括选择器201和加法器202；其中，所述加法器202与所述选择器201相连。
所述选择器201用于将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配。
所述加法器202用于将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
为了保障浮点数累加过程的精度，满足加和运算后得到的中间浮点数的位宽要求，可以利用选择器将每个待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数，实现了待处理浮点数位宽的扩展，进而使得对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理，减少了规格化处理的次数，降低了芯片处理多个扩展后浮点数的累加过程的延迟和功耗；同时，减少了规格化处理的次数后，能够缓解规格化处理带来的数据丢失问题，提高了目标浮点数的精度。
在一种可能的实施方式中，参见图3所示，所述装置还包括比较器203；所述比较器203与所述加法器202相连；所述加法器202还用于将所述目标浮点数输入至所述比较器；所述比较器203用于对所述目标浮点数进行规格化处理，得到目标处理结果，其 中，所述目标处理结果的格式与预设格式相匹配。
实施时，对多个扩展后浮点数进行累加处理过程中，无需对累加处理过程中得到的中间浮点数进行规格化处理；而是可以在累加得到目标浮点数后，对目标浮点数进行一次规格化处理，得到目标处理结果，减少了规格化处理的次数，降低了目标芯片处理多个浮点数的累加过程的延迟和功耗；同时，可以缓解规格化处理带来的数据丢失问题，提高了目标处理结果的精度。
在一种可能的实施方式中，所述装置还包括对阶运算器204。所述对阶运算器204分别与所述加法器202和所述选择器201相连；所述对阶运算器包括减法器241和移位器242。其中，所述减法器241用于确定所述多个扩展后浮点数中的每个扩展后浮点数的初始指数与目标指数之间的目标差值，所述目标指数为基于多个扩展后浮点数的初始指数确定的；所述移位器242用于针对每个所述扩展后浮点数，将所述扩展后浮点数的初始指数对齐至所述目标指数，并基于所述扩展后浮点数对应的目标差值，对所述扩展后浮点数的尾数进行右移，得到处理后浮点数，并将所述处理后浮点数输入至所述加法器；所述加法器202用于将所述多个处理后浮点数的尾数进行累加处理，得到目标浮点数。
在一种可能的实施方式中，所述选择器201在将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数时，用于：从所述多个待处理浮点数中选取两个待处理浮点数，将所述两个待处理浮点数的符号位扩展至目标位宽，得到两个扩展后浮点数；所述减法器241用于将所述两个扩展后浮点数中的第一浮点数的初始指数作为所述目标指数；确定所述目标指数与所述两个扩展后浮点数中的第二浮点数的初始指数的第一差值；其中，所述第一浮点数的初始指数大于所述第二浮点数的初始指数；所述移位器242用于将所述第二浮点数的初始指数对齐至所述目标指数，并基于所述第一差值，将所述第二浮点数的尾数进行右移，得到处理后的第二浮点数；将所述第一浮点数和所述处理后的第二浮点数输入至所述加法器；所述加法器202，用于将所述第一浮点数和所述处理后的第二浮点数进行加法处理，得到中间浮点数。
在一种可能的实施方式中，所述装置还包括第一寄存器205。所述第一寄存器205分别与所述加法器202和所述对阶运算器的减法器241相连；所述加法器202用于将得到的所述中间浮点数输入至所述第一寄存器205；所述第一寄存器205用于存储所述中间浮点数和所述加法器发送的目标浮点数，并将所述中间浮点数发送给所述减法器241。
在一种可能的实施方式中，所述装置还包括第二寄存器206。所述第二寄存器206与所述减法器241相连；所述第二寄存器206用于存储目标指数，并将所述目标指数发送给所述对阶运算器中的所述减法器241。
在一种可能的实施方式中，所述选择器201还用于：从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；响应于所选取的待处理浮点数对应的扩展后浮点数的初始指数大于所述第二寄存器存储的目标指数，将所选取的待处理浮点数对应的扩展后浮点数的初始指数作为新的目标指数，利用所述新的目标指数对所述第二寄存器进行更新；所述第二寄存器206还用于将新的目标指数发送给减法器；所述减法器241用于基于接收到的新的目标指数，确定所述中间浮点数的指数与所述目标指数之间的第二差值；所述移位器242用于将所述中间浮点数的指数对齐至所述目标指数，并基于所述第二差值，对所述中间浮点数的尾数进行右移，得到处理后中间浮点数，并将所述处理后中间浮点数和选取的该待处理浮点数对应的扩展后浮点数发送给所述加法器202；所述加法器202用于将所述中间浮点数的尾数和所选取的待处理浮点数对应的扩 展后浮点数的尾数进行加法处理，得到新的中间浮点数，并将所述新的中间浮点数发送给所述第一寄存器205；以及将最后一次加和处理后得到的中间浮点数作为目标浮点数，将所述目标浮点数发送给所述第一寄存器205。
在一种可能的实施方式中，所述比较器203，在对所述目标浮点数进行规格化处理，得到目标处理结果时，用于：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到目标处理结果。
在一种可能的实施方式中，所述目标位宽为基于所述多个待处理浮点数包括的初始尾数的初始位宽和所述多个待处理浮点数的总数量确定的。
其中，加法器和第一寄存器的位宽至少为目标位宽。第二寄存器的位宽可以为多个待处理浮点数包括的初始指数的指数位宽中的最大值；即，可以确定多个待处理浮点数中的每个待处理浮点数的初始指数的指数位宽，并将多个指数位宽中的最大值确定为第二寄存器的位宽。
结合图3，对上述实施方式提出的浮点数处理方法进行示例性说明。假设多个待处理浮点数包括a1、a2、a3、a4、a5，该浮点数处理方法可以包括如下步骤。
步骤一、将进行累加运算的两个待处理浮点数(a1和a2)输入至选择器中，选择器将两个待处理浮点数的符号位扩展至目标位宽，得到两个扩展后浮点数，并将两个扩展后浮点数输入至对阶运算器。
步骤二、对阶运算器对两个扩展后浮点数进行对阶处理，得到指数对齐的两个扩展后浮点数，并将指数对齐的两个扩展后浮点数输入至加法器中；以及将两个扩展后浮点数包括的初始指数中的最大指数作为目标指数，并将该目标指数存储至第二寄存器中。
实施时，对阶运算器中的减法器确定第一浮点数的初始指数与目标指数之间的目标差值；移位器可以将第一浮点数的初始指数对齐到目标指数，并将第一浮点数的尾数右移目标位数，得到对阶处理后的第一浮点数。该对阶处理后的第一浮点数和第二浮点数的指数一致。其中，两个扩展后浮点数中，第一浮点数的初始指数小于第二浮点数的初始指数；目标位数为第二浮点数的初始指数(目标指数)与第一浮点数的初始指数之间的目标差值。这里，可以将第二浮点数的初始指数作为目标指数存储至第二寄存器中。
步骤三、加法器将指数对齐的两个扩展后浮点数的尾数进行加和运算，得到中间浮点数，并将该中间浮点数寄存在第一寄存器。
步骤四、将待处理浮点数a3输入至选择器中，选择器将待处理浮点数a3的符号位扩展至目标位宽，得到扩展后浮点数，并将扩展后浮点数输入至对阶运算器；以及第一寄存器将中间浮点数输入至对阶运算器。
步骤五、对阶运算器对待处理浮点数a3对应的扩展后浮点数和中间浮点数进行对阶处理，得到指数对齐的两个扩展后浮点数，并将指数对齐的两个扩展后浮点数输入至加法器中。
实施时，判断待处理浮点数a3对应的扩展后浮点数中初始指数与中间浮点数的指数(即，第二寄存器中存储的目标指数)之间的大小，若扩展后浮点数中初始指数小于中间浮点数的指数，则将扩展后浮点数的初始指数对齐到中间浮点数的指数，并对扩展后浮点数的尾数右移目标位数(即，中间浮点数与扩展后浮点数的指数之差)，得到对阶处理后的扩展后浮点数。该对阶处理后的扩展后浮点数和中间浮点数的指数一致。
若扩展后浮点数中初始指数大于中间浮点数的指数，则将中间浮点数的初始指数对阶到扩展后浮点数的指数，并对中间浮点数的尾数右移目标位数(即，扩展后浮点数与中间浮点数的指数之差)，得到对阶处理后的中间浮点数。该对阶处理后的中间浮点 数和扩展后浮点数为指数对齐的两个扩展后浮点数。
在扩展后浮点数中初始指数与中间浮点数的指数相同时，可以无需进行对阶处理，加法器直接将扩展后浮点数的尾数与中间浮点数的尾数进行相加，得到中间浮点数。
步骤六、在待处理浮点数a3对应的扩展后浮点数中初始指数大于中间浮点数的指数时，可以将扩展后浮点数中的初始指数作为更新后的目标指数，并将该更新后的目标指数更新至第二寄存器。
步骤七、加法器将指数对齐的两个扩展后浮点数的尾数进行加和运算，得到中间浮点数，并将该中间浮点数寄存在第一寄存器。
分别获取待处理浮点数a4、a5，并针对获取到的待处理浮点数a4和a5分别重复步骤四至步骤七，得到a1、a2、a3、a4、a5累加后的目标浮点数。
步骤八，在得到目标浮点数之后，第一寄存器可以将目标浮点数输入至比较器。比较器对目标浮点数进行规格化处理，得到目标处理结果，其中，目标处理结果的格式与预设格式相匹配。
基于相同的构思，本公开实施例提供了一种芯片。参见图4所示，该芯片包括：上述任一实施方式所述的浮点数处理装置401和存储器402。所述存储器402用于存储待运算的多个待处理浮点数；所述浮点数处理装置401用于对所述多个待处理浮点数进行处理，得到目标浮点数。
基于相同的构思，本公开实施例还提供了一种浮点数处理装置。参见图5所示，为本公开实施例提供的浮点数处理装置的架构示意图，该浮点数处理装置包括获取模块501、扩展模块502和第一处理模块503。
获取模块501用于获取在目标芯片中进行运算的多个待处理浮点数。
扩展模块502用于将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配。
第一处理模块503用于在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
在一种可能的实施方式中，在所述得到目标浮点数之后，所述装置还包括：第二处理模块504，用于对所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
在一种可能的实施方式中，所述扩展模块502用于根据以下步骤确定目标位宽：基于所述多个待处理浮点数包括的初始尾数的初始位宽，确定所述多个待处理浮点数对应的调整位宽；基于所述调整位宽和所述待处理浮点数的总数量，确定所述目标位宽。
在一种可能的实施方式中，所述扩展模块502，在将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数时，用于：从多个待处理浮点数中选取两个待处理浮点数，将所述两个待处理浮点数的符号位扩展至目标位宽，得到两个扩展后浮点数；所述第一处理模块503，在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数时，用于：将所述两个扩展后浮点数作为两个当前浮点数，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数；从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；将所选取的待处理浮点数对应的扩展后浮点数和所述中间浮点数，作为更新后的两个当前浮 点数，返回至在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数的步骤，直至所述多个待处理浮点数中的每个待处理浮点数均进行过加和处理；将最后一次加和处理后得到的中间浮点数作为所述目标浮点数。
在一种可能的实施方式中，所述第一处理模块503，在所述目标芯片中将所述两个当前浮点数进行加和处理，得到中间浮点数时，用于：在所述目标芯片中将所述两个当前浮点数中的第一浮点数的初始指数对齐到第二浮点数的初始指数，并将所述第一浮点数的尾数右移目标位数，得到对阶处理后的第一浮点数；其中，所述两个浮点数中的所述第一浮点数的初始指数小于所述第二浮点数的初始指数；所述目标位数为所述第二浮点数的初始指数与所述第一浮点数的初始指数之间的差值；在所述目标芯片中将所述对阶处理后的第一浮点数与所述第二浮点数进行加和处理，得到中间浮点数。
在一种可能的实施方式中，所述第二处理模块504，在对所述目标浮点数进行规格化处理，得到目标处理结果时，用于：利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到目标处理结果。
在一些实施例中，本公开实施例提供的装置具有的功能或包含的模板可以用于执行上文方法实施例描述的方法，其具体实现可以参照上文方法实施例的描述，为了简洁，这里不再赘述。
基于同一技术构思，本公开实施例还提供了一种电子设备。参照图6所示，为本公开实施例提供的电子设备的结构示意图，该电子设备包括处理器601、存储器602和总线603。
其中，存储器602用于存储执行指令，包括内存6021和外部存储器6022。这里的内存6021也称内存储器，用于暂时存放处理器601中的运算数据，以及与硬盘等外部存储器6022交换的数据，处理器601通过内存6021与外部存储器6022进行数据交换，当电子设备600运行时，处理器601与存储器602之间通过总线603通信，使得处理器601在执行以下指令：
获取在目标芯片中进行运算的多个待处理浮点数；将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
其中，处理器601的具体处理流程可以参照上述方法实施例的记载，这里不再赘述。
此外，本公开实施例还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行上述方法实施例中所述的浮点数处理方法的步骤。其中，该存储介质可以是易失性或非易失的计算机可读取存储介质。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的浮点数处理方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本 公开所提供的几个实施例中，应该理解到，所揭露的装置、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即，可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种浮点数处理装置，其特征在于，所述装置包括：
    选择器，用于将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；
    加法器，与所述选择器相连，用于将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
  2. 根据权利要求1所述的装置，其特征在于，所述装置还包括：
    比较器，与所述加法器相连，用于对从所述加法器输入的所述目标浮点数进行规格化处理，得到目标处理结果，其中，所述目标处理结果的格式与预设格式相匹配。
  3. 根据权利要求1或2所述的装置，其特征在于，所述装置还包括对阶运算器，所述对阶运算器分别与所述加法器和所述选择器相连；所述对阶运算器包括：
    减法器，用于确定每个所述扩展后浮点数的初始指数与目标指数之间的目标差值；其中，所述目标指数为基于所述多个扩展后浮点数的初始指数确定的；
    移位器，用于针对每个所述扩展后浮点数，
    将所述扩展后浮点数的初始指数对齐至所述目标指数；
    基于所述扩展后浮点数对应的目标差值，对所述扩展后浮点数的尾数进行右移，得到处理后浮点数；并
    将所述处理后浮点数输入至所述加法器；
    其中，所述加法器用于将从所述多个扩展后浮点数分别得到的所述处理后浮点数的尾数进行累加处理，得到所述目标浮点数。
  4. 根据权利要求3所述的装置，其特征在于，
    所述选择器，在将获取到的多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数时，用于：
    从所述多个待处理浮点数中选取两个待处理浮点数，并将所述两个待处理浮点数的符号位扩展至所述目标位宽，得到两个扩展后浮点数；
    所述减法器用于：
    将所述两个扩展后浮点数中的第一浮点数的初始指数作为所述目标指数；
    确定所述目标指数与所述两个扩展后浮点数中的第二浮点数的初始指数的第一差值；其中，所述第一浮点数的初始指数大于所述第二浮点数的初始指数；
    所述移位器用于：
    将所述第二浮点数的初始指数对齐至所述目标指数；
    基于所述第一差值，将所述第二浮点数的尾数进行右移，得到处理后的第二浮点数；
    将所述第一浮点数和所述处理后的第二浮点数输入至所述加法器；
    所述加法器用于：
    将所述第一浮点数和所述处理后的第二浮点数进行加法处理，得到中间浮点数。
  5. 根据权利要求4所述的装置，其特征在于，所述装置还包括：
    第一寄存器，分别与所述加法器和所述对阶运算器中的所述减法器相连，用于存储由所述加法器得到并输入的所述中间浮点数和所述加法器发送的目标浮点数，并将所述中间浮点数发送给所述减法器。
  6. 根据权利要求5所述的装置，其特征在于，所述装置还包括：
    第二寄存器，与所述减法器相连，用于存储所述目标指数，并将所述目标指数发送给所述对阶运算器中的所述减法器。
  7. 根据权利要求6所述的装置，其特征在于，
    所述选择器还用于：
    从未被选取的待处理浮点数中选取一个待处理浮点数，并将所选取的待处理浮点数的符号位扩展至所述目标位宽，得到所选取的待处理浮点数对应的扩展后浮点数；
    响应于所选取的待处理浮点数对应的扩展后浮点数的初始指数大于所述第二寄存器存储的目标指数，将所选取的待处理浮点数对应的扩展后浮点数的初始指数作为新的目标指数；
    利用所述新的目标指数对所述第二寄存器进行更新；其中，所述第二寄存器还用于将所述新的目标指数发送给所述减法器；
    所述减法器用于：
    基于接收到的新的目标指数，确定所述中间浮点数的指数与所述目标指数之间的第二差值；
    所述移位器用于：
    将所述中间浮点数的指数对齐至所述目标指数，并基于所述第二差值对所述中间浮点数的尾数进行右移，得到处理后中间浮点数；
    将所述处理后中间浮点数和所选取的待处理浮点数对应的扩展后浮点数发送给所述加法器；
    所述加法器用于：
    将所述中间浮点数的尾数和所选取的待处理浮点数对应的扩展后浮点数的尾数进行加法处理，得到新的中间浮点数，并将所述新的中间浮点数发送给所述第一寄存器；以及
    将最后一次加和处理后得到的中间浮点数作为所述目标浮点数，并将所述目标浮点数发送给所述第一寄存器。
  8. 根据权利要求2所述的装置，其特征在于，所述比较器，在对所述目标浮点数进行规格化处理，得到目标处理结果时，用于：
    利用移位方式、截尾方式和舍入方式中的一种或多种方式，对所述目标浮点数进行规格化处理，得到所述目标处理结果。
  9. 根据权利要求1至8任一项所述的装置，其特征在于，所述目标位宽为基于所述多个待处理浮点数包括的初始尾数的初始位宽和所述多个待处理浮点数的总数量确定的。
  10. 一种浮点数处理方法，其特征在于，包括：
    获取在目标芯片中进行运算的多个待处理浮点数；
    将所述多个待处理浮点数中的每个所述待处理浮点数的符号位扩展至目标位宽，得到多个扩展后浮点数；其中，所述目标位宽与所述待处理浮点数的总数量匹配；
    在所述目标芯片中将所述多个扩展后浮点数进行累加处理，得到目标浮点数。
  11. 一种芯片，其特征在于，包括：
    存储器，用于存储待运算的多个待处理浮点数；
    如权利要求1至9任一项所述的浮点数处理装置，用于对所述多个待处理浮点数进行处理，得到目标浮点数。
  12. 一种电子设备，其特征在于，包括：处理器、存储器和总线，所述存储器存储有所述处理器可执行的机器可读指令，当所述电子设备运行时，所述处理器与所述存储器之间通过所述总线通信，所述机器可读指令被所述处理器执行时实现如权利要求10所述的浮点数处理方法的步骤。
  13. 一种电子设备，其特征在于，包括如权利要求11所述的芯片。
  14. 一种计算机可读存储介质，其特征在于，该计算机可读存储介质上存储有计算机程序，该计算机程序被处理器运行时执行如权利要求10所述的浮点数处理方法的步骤。
PCT/CN2022/124517 2021-12-31 2022-10-11 浮点数处理装置、方法、电子设备、存储介质及芯片 Ceased WO2023124372A1 (zh)

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