WO2023079726A1 - 光半導体装置 - Google Patents

光半導体装置 Download PDF

Info

Publication number
WO2023079726A1
WO2023079726A1 PCT/JP2021/040924 JP2021040924W WO2023079726A1 WO 2023079726 A1 WO2023079726 A1 WO 2023079726A1 JP 2021040924 W JP2021040924 W JP 2021040924W WO 2023079726 A1 WO2023079726 A1 WO 2023079726A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
optical semiconductor
support
semiconductor layer
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/040924
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
喜之 小川
和重 川▲崎▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2021/040924 priority Critical patent/WO2023079726A1/ja
Priority to US18/688,165 priority patent/US20250038474A1/en
Priority to JP2022502068A priority patent/JP7046294B1/ja
Priority to CN202180103423.4A priority patent/CN118120121A/zh
Publication of WO2023079726A1 publication Critical patent/WO2023079726A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04254—Electrodes, e.g. characterised by the structure characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2301/00—Functional characteristics
    • H01S2301/17—Semiconductor lasers comprising special layers
    • H01S2301/176—Specific passivation layers on surfaces other than the emission facet

Definitions

  • a support that has a flat surface with the maximum thickness and supports a jig when coating the reflective film, and a region on the mounting surface in which the bonding surface is formed in the direction perpendicular to the stretching direction a shielding mechanism that extends a portion higher than the joint surface in the stacking direction between the sides adjacent to the both end surfaces of the mounting surface and the joint surface.
  • the support surface and the shielding mechanism that can stably support the dummy bar are formed, it is possible to obtain an optical semiconductor device that can prevent the wrap around the coating with good reproducibility.
  • a resonator 2r for emitting laser light is formed extending in the y direction in the drawing, and both ends in the extending direction, that is, the direction in which light travels, are cut by crystal cleavage or the like. It is formed as an end face 2fe, and a reflective film 2ce is formed on the surface. Further, on both sides of the resonator 2r, recesses 2d of the semiconductor layer 2 are provided along the resonator 2r. A nitride film 2cn is formed on the outermost surface (mounting surface 2ft) of the semiconductor layer 2 to protect the surface of the semiconductor layer.
  • the support surface 4fs can be closely attached to the dummy bar 92 without any gap.
  • the bottom surface of the semiconductor bar 1B which is not denoted by reference numerals, is also flat, it can be brought into close contact with the dummy bar 91 without a gap. Therefore, the support 4 acts as a barrier when coating the end face, and the effect of preventing the coat from running around the support 4 toward the inside (y direction) of the mounting surface 2ft can be obtained.
  • the end face coating for the semiconductor bar 1B of the optical semiconductor device 1 according to the second embodiment will be described.
  • the semiconductor bars 1B before chip separation by dicing are end-face coated while being alternately arranged with the dummy bars 90 .
  • Embodiment 3 In the above-described first and second embodiments, the example in which the support made of resin is formed on the mounting surface has been described. In the third embodiment, an example of forming a support with an electrode pattern formed at the same time as an electrode pad will be described.
  • the semiconductor layer 2 is shaped by etching or the like, and electrode pads 31 and the like are formed in the same manner as in the first embodiment. It is equipped with components.
  • the semiconductor layer 2 is composed of a semiconductor substrate such as an InP substrate or a GaAs substrate, and various crystal layers epitaxially grown thereon by metalorganic vapor phase epitaxy or the like, and has a substantially rectangular parallelepiped shape.
  • the regions where the electrode pads 31 are formed are recessed.
  • a counterbore 2g is formed.
  • a nitride film 2cn is formed on the mounting surface 2ft of the semiconductor layer 2, and an electrode pad 31 electrically connected to the resonator 2r is provided on the counterbore 2g. is provided with an electrode pattern 32 as in the first or second embodiment.
  • the height of the bonding surface 3fp located on the uppermost surface of the electrode pad 31 is lower than the height of the surrounding nitride film upper surface (mounting surface 2ft).
  • this semiconductor layer 2 is etched to a depth of about 6 ⁇ m or more in order to obtain electrical isolation.
  • the recess in the semiconductor layer 2 in the recess 2g where the electrode pad 31 is provided may be formed in the same process as the recess 2d in the semiconductor layer 2 on the side of the resonator 2r. For this reason, it may be formed in a separate process.
  • the engraving of the semiconductor layer 2 is formed by patterning and etching of a photoresist, regardless of whether it is the same process or a different process. Etching may be dry or wet.
  • the outermost surface of the electrode pattern 32 is the flat supporting surface 3fs, only the supporting surface 3fs is in contact with the flat dummy bar 90 on the mounting surface 2ft side. Moreover, since the electrode patterns 32 (supporting surfaces 3fs) are arranged on the front and rear sides (y-direction) of the semiconductor bar 1B, the dummy bar 90 is not inclined with respect to the semiconductor bar 1B.
  • the electrode patterns 32 are separated from the electrode pads 31 in the front and rear (y direction), and are provided at positions closer to the ends than to the center in the front and rear directions. Due to the electrode pattern 32 arranged in such a manner, the highest level (z direction) of the semiconductor bar 1B is the flat supporting surface 3fs distributed and arranged in the front-rear direction. It is possible to prevent coat wraparound.
  • the metal (electrode pattern 32) other than the electrode pad 31 is formed on the surface where the semiconductor layer 2 is not dug, and only the electrode pad 31 is formed on the portion where the semiconductor layer 2 is dug. Therefore, the portion of the semiconductor layer 2 and the nitride film 2cn surrounding the counterbore 2g and higher than the bonding surface 3fp serves as a barrier against the coating agent entering the bonding surface 3fp of the electrode pad 31.
  • the electrode patterns 32 formed in front and behind the electrode pads 31 are extended so as to cover the area of the bonding surface of the electrode pads 31 in the left-right direction, it is possible to more reliably suppress coat wraparound.
  • the optical semiconductor device 1 there is no need to use an extra material such as resin for the support 4. Also, if the counterbores 2g are formed in the same process as the recesses 2d, there is no increase in the number of processes, which is advantageous in terms of manufacturing cost.
  • the semiconductor layer 2 is shaped by etching or the like, and electrode pads 31 and the like are formed in the same manner as in the above embodiments. It is equipped with the member of The semiconductor layer 2 is composed of a semiconductor substrate such as an InP substrate or a GaAs substrate, and various crystal layers epitaxially grown thereon by metalorganic vapor phase epitaxy or the like, and has a substantially rectangular parallelepiped shape.
  • Both ends in the extending direction of the resonator 2r formed inside the semiconductor layer 2 are cut by crystal cleavage or the like to form end faces 2fe.
  • a recess 2d in the semiconductor layer 2 is provided along the resonator 2r.
  • a nitride film 2cn is formed on the mounting surface 2ft of the semiconductor layer 2 to protect the surface of the semiconductor layer.
  • the electrode pattern 32 and the ridge 3d have the highest (z-direction) surfaces (support surface 3fs, contact surface 3fd) in the optical semiconductor device 1, as in the third embodiment.
  • the metal layer 3 is formed by a method such as sputtering, plating, vapor deposition, etc., so that it is finished in a flat and leveled state without post-processing.
  • the support surface 3fs by the electrode pattern 32 is provided separately in the front and rear (y-direction) with a distance from the electrode pad 31 in the same manner as in the first embodiment. is located near the edge.
  • the end surface coating for the semiconductor bar 1B of the optical semiconductor device 1 according to the fourth embodiment will be described.
  • the semiconductor bars 1B before chip separation by dicing are end-face coated while being alternately arranged with the dummy bars 90 .
  • the outermost surface of the electrode pattern 32 is the flat support surface 3fs and the contact surface 3fd, only the support surface 3fs and the contact surface 3fd are in contact with the flat dummy bar 90 on the mounting surface 2ft side. . Moreover, since the supporting surfaces 3fs of the electrode patterns 32 are arranged on the front and rear sides (y-direction) of the semiconductor bar 1B, the dummy bar 90 is not inclined with respect to the semiconductor bar 1B.
  • the electrode patterns 32 are separated from the electrode pads 31 in the front and rear (y direction), and are provided at positions closer to the ends than to the center in the front and rear directions. Since the dummy bar 90 is supported by the flat supporting surface 3fs of the electrode pattern 32 arranged in such a manner, the flat dummy bar 90 is not tilted and the annular contact surface 3fd and the dummy bar 90 are brought into close contact with each other.
  • the joint surface 3fp of the electrode pad 31 is located inside the bank 3d, the joint surface 3fp is covered with the inner peripheral surface of the bank 3d and the dummy bar 90 during the end face coating. As a result, it is possible to reliably prevent the coating from spreading to the bonding surface 3fp of the electrode pad 31 .
  • the optical semiconductor device 1 there is no need to use an extra material such as resin for the support 4 . Also, with respect to the bank 3d, it is only necessary to mask the bonding surface 3fp with one of a plurality of patterns used in the process of forming the metal layer 3, and the number of steps does not increase, so the manufacturing cost is reduced. Superiority in
  • the electrode pad having the bank 3d is formed only with the metal layer 3, unlike the case of forming a recessed resin layer on the base as in Patent Document 2, an extra step for adjusting the height is required.
  • the height of the electrode pattern 32 can be precisely aligned. For this reason, for example, the dummy bar 90 is supported only by the bank portion, which causes the dummy bar 90 to be tilted, or a gap is created between the bank portion and the dummy bar 90, thereby degrading the shielding function. do not have.
  • a plurality of crystal layers are laminated on the semiconductor substrate, and the semiconductor layer 2 in which the resonator 2r extending in the direction perpendicular to the lamination direction (z direction) is formed.
  • a reflective film 2ce covering both end faces 2fe of the semiconductor layer 2 in the extending direction (y-direction) of the container 2r;
  • an electrode pad 31 for injecting a current into the semiconductor layer 2 is locally formed so as to have a bonding surface 3fp with a bonding wire by stacking a metal layer on the back surface electrode.
  • the supporting body 4 (electrode pattern 32 functioning as a supporting body) supporting (dummy bar 90) and the area in which the bonding surface 3fp is formed in the direction (x direction) perpendicular to the extending direction of the mounting surface 2ft are covered.
  • a portion higher than the bonding surface 3fp in the stacking direction extends between the sides adjacent to the both end surfaces 2fe of the mounting surface 2ft and the bonding surface 3fp, respectively, and a coating agent is applied to the bonding surface 3fp when coating the reflective film 2ce.
  • It is configured to have a shielding mechanism (supporting body 4, electrode pattern 32, mounting surface 2ft around counterbore 2g, bank 3d) for shielding the intrusion of . Therefore, it is possible to stably support the dummy bar 90 during coating, and to prevent coating wraparound with good reproducibility.
  • the support 4 (or the electrode pattern 32 that functions as a support) functions as a shielding mechanism, it is possible to reliably prevent the coat from running around without increasing the installation area.
  • the formation pattern on the mounting surface 2ft can be freely formed, and the height can be easily adjusted.
  • the support 4 has an opening 4a through which the bonding surface 3fp is exposed, and a flat surface (supporting surface 4fs) continues from one end side to the other end side in the extending direction (y direction).
  • a flat surface supporting surface 4fs
  • the dummy bar 90 can be reliably supported even if there is a positional deviation in the extending direction (y direction).

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Device Packages (AREA)
PCT/JP2021/040924 2021-11-08 2021-11-08 光半導体装置 Ceased WO2023079726A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2021/040924 WO2023079726A1 (ja) 2021-11-08 2021-11-08 光半導体装置
US18/688,165 US20250038474A1 (en) 2021-11-08 2021-11-08 Optical semiconductor device
JP2022502068A JP7046294B1 (ja) 2021-11-08 2021-11-08 光半導体装置
CN202180103423.4A CN118120121A (zh) 2021-11-08 2021-11-08 光半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/040924 WO2023079726A1 (ja) 2021-11-08 2021-11-08 光半導体装置

Publications (1)

Publication Number Publication Date
WO2023079726A1 true WO2023079726A1 (ja) 2023-05-11

Family

ID=81255864

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/040924 Ceased WO2023079726A1 (ja) 2021-11-08 2021-11-08 光半導体装置

Country Status (4)

Country Link
US (1) US20250038474A1 (https=)
JP (1) JP7046294B1 (https=)
CN (1) CN118120121A (https=)
WO (1) WO2023079726A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317565A (ja) * 1998-05-07 1999-11-16 Toshiba Corp 半導体表面処理用治具
JP2008124218A (ja) * 2006-11-10 2008-05-29 Sony Corp 半導体発光素子およびその製造方法
JP2008141180A (ja) * 2006-11-10 2008-06-19 Sony Corp 半導体発光素子、光ピックアップ装置および情報記録再生装置
US20170031115A1 (en) * 2015-07-29 2017-02-02 Corning Optical Communications LLC Wafer-level integrated opto-electronic module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7241572B2 (ja) * 2019-03-08 2023-03-17 日本ルメンタム株式会社 半導体光素子、光モジュール、及び半導体光素子の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317565A (ja) * 1998-05-07 1999-11-16 Toshiba Corp 半導体表面処理用治具
JP2008124218A (ja) * 2006-11-10 2008-05-29 Sony Corp 半導体発光素子およびその製造方法
JP2008141180A (ja) * 2006-11-10 2008-06-19 Sony Corp 半導体発光素子、光ピックアップ装置および情報記録再生装置
US20170031115A1 (en) * 2015-07-29 2017-02-02 Corning Optical Communications LLC Wafer-level integrated opto-electronic module

Also Published As

Publication number Publication date
JP7046294B1 (ja) 2022-04-01
CN118120121A (zh) 2024-05-31
JPWO2023079726A1 (https=) 2023-05-11
US20250038474A1 (en) 2025-01-30

Similar Documents

Publication Publication Date Title
US7023891B2 (en) Semiconductor optical device
KR0184372B1 (ko) 반도체장치 및 그 제조방법
US8563342B2 (en) Method of making semiconductor optical integrated device by alternately arranging spacers with integrated device arrays
US20110281382A1 (en) Nitride-based semiconductor device and method of fabricating the same
US11233174B2 (en) Semiconductor optical device, optical module, and manufacturing method of semiconductor optical device
JP6125166B2 (ja) マルチビーム半導体レーザ装置
JPH01184892A (ja) 半導体レーザ装置
US7772085B2 (en) Controlling overspray coating in semiconductor devices
WO2021200549A1 (ja) 量子カスケードレーザ素子及び量子カスケードレーザ装置
WO2023079726A1 (ja) 光半導体装置
US7998766B2 (en) Semiconductor element and manufacturing method thereof
JP7748266B2 (ja) リッジ型半導体光素子
JP7810330B2 (ja) 光半導体装置
US8617911B2 (en) Method for forming coating film on facet of semiconductor optical device
US20230114599A1 (en) Semiconductor laser element, semiconductor laser device, and method for manufacturing semiconductor laser element
JP2017034080A (ja) 半導体発光素子
CN118281687A (zh) 脊型半导体光学器件
JP2020068286A (ja) 光デバイス及びその製造方法
JP2002057401A (ja) 半導体レーザおよび半導体装置
WO2022254770A1 (ja) 半導体発光素子及び半導体発光素子の製造方法
JP2004087564A5 (https=)
JP2018046227A (ja) 半導体レーザ装置およびその製造方法
JP6334772B2 (ja) マルチビーム半導体レーザ装置
JP2024110797A (ja) 光半導体素子、および光半導体素子の製造方法
JPH1168253A (ja) 光半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2022502068

Country of ref document: JP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21963320

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18688165

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 202180103423.4

Country of ref document: CN

122 Ep: pct application non-entry in european phase

Ref document number: 21963320

Country of ref document: EP

Kind code of ref document: A1