WO2023073802A1 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
WO2023073802A1
WO2023073802A1 PCT/JP2021/039441 JP2021039441W WO2023073802A1 WO 2023073802 A1 WO2023073802 A1 WO 2023073802A1 JP 2021039441 W JP2021039441 W JP 2021039441W WO 2023073802 A1 WO2023073802 A1 WO 2023073802A1
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Prior art keywords
voltage
current
circuit
output
semiconductor integrated
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English (en)
French (fr)
Japanese (ja)
Inventor
理 錦戸
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023555927A priority Critical patent/JP7558424B2/ja
Priority to PCT/JP2021/039441 priority patent/WO2023073802A1/ja
Publication of WO2023073802A1 publication Critical patent/WO2023073802A1/ja
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Definitions

  • the present disclosure relates to semiconductor integrated circuit devices.
  • IC Integrated Circuit
  • checking whether the voltage is correctly output from the analog circuit to the internal node is an important factor in detecting failures.
  • the voltage of the internal node can be measured via the external terminal.
  • the voltages of the plurality of internal nodes can be measured by sharing the external terminal.
  • Patent Document 1 discloses that a voltage comparator is provided inside an IC to detect a DC voltage at a specific circuit node of an analog integrated circuit. is within a certain range, and the determination result is output to the outside of the IC.
  • the present disclosure has been made to solve such problems, and an object of the present disclosure is to speed up the normality determination of the voltage of the internal node of a semiconductor integrated circuit device with a simple circuit configuration. is.
  • the current comparator when switching between a plurality of voltage-to-current converters, can compare the measured voltage with the judgment voltage by comparing the output current obtained by voltage-to-current conversion of the measured voltage with the reference current. , the time required to stabilize the output current input to the current comparator can be shortened. As a result, it is possible to speed up the normality judgment of the voltage of the internal node of the semiconductor integrated circuit device with a simple circuit configuration.
  • FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a first embodiment
  • FIG. 2 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 1
  • FIG. FIG. 2 is a circuit diagram for explaining an internal configuration of each block shown in FIG. 1 according to Modification 1 of Embodiment 1
  • FIG. 10 is a circuit diagram illustrating a configuration of a voltage-current conversion circuit according to Modification 1 of Embodiment 1
  • FIG. 10 is a circuit diagram illustrating the configuration of a reference current source according to Modification 1 of Embodiment 1
  • 3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a second embodiment
  • FIG. 7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6;
  • FIG. 7 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 6;
  • FIG. 3 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a third embodiment
  • FIG. 9 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 8
  • FIG. 12 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fourth embodiment
  • FIG. 11 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 10
  • FIG. FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a fifth embodiment
  • 13 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 12
  • FIG. FIG. 11 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a sixth embodiment
  • 15 is a circuit diagram for explaining the internal configuration of each block shown in FIG. 14;
  • the suffixes a to d will be omitted and, for example, the internal circuit 10, the internal node NT, the voltage current It will be described like the conversion circuit 20 .
  • the gate of the NMOS transistor 201a is connected to the internal node NTa, which is the measurement node. That is, the measurement voltage Vout is input to the gate of the NMOS transistor 201a.
  • the selection circuit 30 has switches 301a to 301d. Switches 301a-301d are connected between nodes N1a-N1d and node N2 of current comparator 50, respectively. Nodes N1a-N1d are connected to internal nodes NTa-NTd via voltage-current conversion circuits 20a-20d, respectively, as shown in FIG.
  • the voltage-to-current conversion circuits 20b to 20d are configured similarly to the voltage-to-current conversion circuit 20a, and have series circuits of NMOS transistors and resistance elements between the nodes N1b to N1c and the ground line NL. .
  • Current comparator 50 includes P-type MOS transistors (hereinafter referred to as PMOS transistors) 501 and 502 and NMOS transistors 503 and 504, which constitute two sets of current mirrors. It is connected between the power supply line NP transmitting VDD and the node N2, and the PMOS transistor 502 is connected between the power supply line NP and the node N3.
  • the PMOS transistors 501 and 502 form a current mirror by having their gates commonly connected to the node N2 (that is, the drain of the PMOS transistor 501). Assume that the current ratio of the current mirror is 1:1.
  • NMOS transistor 503 is connected between the node N3 and the ground line NL
  • the NMOS transistor 504 is connected between the node N4 and the ground line NL.
  • NMOS transistors 503 and 504 form a current mirror by having their gates commonly connected to node N4 (that is, the drain of NMOS transistor 504). In the following, it is assumed that the current ratio of the current mirror is 1:1.
  • the reference current source 40 has resistance elements 401 , 402 and 404 , an NMOS transistor 403 and PMOS transistors 405 and 406 .
  • the PMOS transistor 406 is connected between the power supply line NP and the node N4, and the PMOS transistor 405 is connected between the power supply line NP and the node N5.
  • PMOS transistors 405 and 406 form a current mirror by having their gates commonly connected to node N5 (that is, the drain of PMOS transistor 405). Assume that the current ratio of the current mirror is 1:1.
  • the resistance element 401 is connected between the power supply line NP and the node N6, and the resistance element 402 is connected between the ground line NL and the node N6. Therefore, a reference voltage Vref obtained by dividing the power supply voltage VDD by the resistance elements 401 and 402 is generated at the node N6.
  • the selection circuit 30 turns on one of the switches 301a to 301d corresponding to the internal node to be measured, and turns off the remaining switches.
  • the switch 301a is turned on. This creates a path for output current Iout from power supply line NP to ground line NL, including PMOS transistor 501, switch 301a (node N1a), NMOS transistor 201a, and resistance element 202a.
  • the output current Iout is expressed by the following formula (1) using the measured voltage Vout, the electrical resistance value RO of the resistive element 202a, and the gate-source voltage Vgs2 of the NMOS transistor 201a. That is, the voltage-current conversion circuit 20 converts the measured voltage Vout into the output current Iout according to the conversion gain according to Equation (1).
  • (1/RO) corresponds to an example of "first conversion gain”.
  • the output current Iout (Vout ⁇ Vgs2)/RO (1)
  • the output current Iout is copied by a current mirror (1:1 current ratio) by PMOS transistors 501 and 502 .
  • the PMOS transistor 502 supplies a current corresponding to the output current Iout to the node N3.
  • the reference current Iref is expressed by the following equation (2) using the reference voltage Vref of the node N6, the electrical resistance value RP of the resistance element 404, and the gate-source voltage Vgs4 of the NMOS transistor 403. That is, the reference current source 40 converts the reference voltage Vref into the reference current Iref according to the conversion gain according to equation (2).
  • (1/RP) corresponds to an example of "second conversion gain".
  • Iref (Vref ⁇ Vgs4)/RP (2)
  • the reference current Iref is copied by a current mirror by PMOS transistors 405 and 406 (current ratio 1:1) and by NMOS transistors 504 and 503 (current ratio 1:1).
  • the NMOS transistor 503 extracts a current corresponding to the reference current Iref from the node N3.
  • a voltage V3 is generated at the node N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when Iout>Iref, the voltage V3 becomes a high-level voltage (hereinafter also simply referred to as "H level”) corresponding to the power supply voltage VDD. On the other hand, when Iout ⁇ Iref, the voltage V3 becomes a low level voltage (hereinafter also simply referred to as "L level”) corresponding to the ground voltage GND.
  • the voltage V3 of the node N3 is output as the determination signal Sjd to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5a.
  • RO (Vto ⁇ Vgs2)/(Vref ⁇ Vgs4) ⁇ RP (4)
  • the voltage stabilization time of the node N3 when the selection circuit 30 switches the measurement voltage Vout in the present embodiment is described in Patent Document 1. Compared with the settling time of the input voltage of the voltage comparison circuit that compares the voltages, it is greatly shortened. In particular, in a configuration in which the circuit scale is suppressed by sharing the current comparator 50 among a plurality of internal nodes, the effect of shortening the test time is great.
  • the reference current Iref which is fixed in the reference current source 40, is used to determine the determination voltage Vout to be compared with the measurement voltage Vout.
  • Vto can be changed equivalently. That is, by changing the conversion gain according to the electrical resistance value RO of the resistance element 202a in the voltage-to-current conversion circuit 20, the reference current Iref is fixed and the normal range of the measured voltage Vout at each internal node NT is adjusted. , the determination voltage Vto can be freely changed. That is, the electrical resistance value RO (that is, the conversion gain) in the voltage-current conversion circuit 20 is determined by reflecting at least the determination voltage Vto, and is preferably set according to Equation (4). This makes it possible to switch the determination voltage for a plurality of measurement voltages with a simple configuration. As a result, the manufacturing cost of the semiconductor integrated circuit device can be reduced.
  • Vgs2 and Vgs4 can be set to the same value by matching the current and transistor size (W/L) ratios between the NMOS transistor 201a and the NMOS transistor 403. can.
  • FIG. 2 shows an example in which the voltage-to-current conversion circuit 20 is configured using NMOS transistors, it is also possible to adopt a configuration that performs voltage-to-current conversion using PMOS transistors.
  • the determination voltage Vto is low, it is preferable to increase the voltage applied to the resistance element 202a (electric resistance value RO) in order to reduce the influence of Vgs2 in equation (1).
  • FIG. 3 shows a circuit diagram for explaining the internal configuration of each block in FIG. 1, according to a modification in which voltage-to-current conversion is performed using PMOS transistors.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 1 shows a circuit diagram for explaining the internal configuration of each block in FIG. 1, according to a modification in which voltage-to-current conversion is performed using PMOS transistors.
  • the voltage-current conversion circuit 20pa has a PMOS transistor 201pa and a resistance element 202a.
  • Resistance element 202a (electric resistance value RO) is connected between power supply line NP and PMOS transistor 201pa.
  • PMOS transistor 201pa is connected between resistance element 202a and node N1a.
  • the gate of PMOS transistor 201pa is connected to internal node NTa to be measured, like NMOS transistor 201 (FIG. 2).
  • the configuration of the selection circuit 30 is the same as in FIG.
  • the current comparator 50p includes NMOS transistors 501p and 502p and PMOS transistors 503p and 504p that form two sets of current mirrors.
  • NMOS transistor 501p is connected between node N2 and ground line NL
  • NMOS transistor 502p is connected between node N3 and ground line NL.
  • NMOS transistors 501p and 501n form a current mirror similar to PMOS transistors 501 and 502 (FIG. 2).
  • the output current Iout is the voltage-current conversion of the measured voltage Vout according to the following equation (5) instead of the equation (1) in FIG. From Equation (5), the conversion gain of the voltage-to-current conversion circuit 20pa is also (1/RO).
  • the reference current source 40 has resistance elements 401, 402, 404, a POS transistor 403p, and NMOS transistors 405p, 406p.
  • NMOS transistor 406p is connected between ground line NL and node N4, and NMOS transistor 405p is connected between ground line NL and node N7.
  • NMOS transistors 405p and 406p form a current mirror similar to PMOS transistors 405 and 406 (FIG. 2).
  • the PMOS transistor 403p is connected between the node N5 and the node N7, and the resistance element 404 (electrical resistance value RP) is connected between the node N5 and the power supply line NP.
  • a path of the reference current Iref corresponding to the reference voltage Vref is generated from the power supply line NP to the ground line NL, including the resistance element 404, the PMOS transistor 403p, and the NMOS transistor 405p.
  • the reference current Iref is expressed by the following formula (6) instead of formula (2) in FIG. From equation (6), the conversion gain at the reference current source 40p is also (1/RP).
  • reference current Iref (VDD ⁇ Vref ⁇ Vgs4)/RP (6)
  • reference current Iref is copied by a current mirror (1:1 current ratio) by PMOS transistors 503p and 504p.
  • the PMOS transistor 503p supplies a current corresponding to the reference current Iref to the node N3, contrary to FIG.
  • the output current Iout generated in the voltage-current conversion circuit 20p is copied by a current mirror (current ratio 1:1) by the NMOS transistors 501p and 502p.
  • a current corresponding to the output current Iout is drawn from the node N3 by the NMOS transistor 502p.
  • a voltage V3 is generated at N3 by amplifying the current difference between the output current Iout and the reference current Iref. Specifically, when the polarity is opposite to that of the current comparator 50 (FIG. 2) and Iref>Iout, the voltage V3 becomes H level (VDD). On the other hand, when Iout>Iref, the voltage V3 becomes L level (GND). Voltage V3 of node N3 is output from current comparator 50p as determination signal Sjd.
  • the ratio between the electrical resistance value RO of the resistor element 202a and the electrical resistance value RP of the resistor element 404 is determined according to the following equation (7).
  • the measured voltage Vout can be compared with the determination voltage Vto by comparing the output current Iout obtained by current-converting the measured voltage Vout with the reference current Iref.
  • the modified example of FIG. 3 when the determination voltage Vto is low, the same effect as described with reference to FIG. 2 can be obtained.
  • FIG. 4 is a circuit diagram illustrating a modification of the voltage-current conversion circuit 20a shown in FIG. Voltage-current conversion circuit 20a# according to Modification 2 of FIG. 4 further includes an operational amplifier buffer 230a in addition to NMOS transistor 201a and resistance element 202a similar to voltage-current conversion circuit 20a (FIG. 2).
  • the operational amplifier buffer 230a has PMOS transistors 2033a and 2034a, NMOS transistors 2031a, 2032a and 2035a, and current sources 2036a and 2037a.
  • the PMOS transistors 2033a and 2034a are connected between the power supply line NP and the nodes N10 and N11, respectively, and the NMOS transistors 2031a and 2032a are connected between the nodes N10 and N11, respectively, and the node N12.
  • Current source 2036a is connected between node N12 and ground line NL. Furthermore, the gates of PMOS transistors 2033a and 2034a are connected to node N10.
  • the PMOS transistors 2033a and 2034a, the NMOS transistors 2031a and 2032a, and the current source 2036a form a current mirror type differential amplifier.
  • the gate of NMOS transistor 2031a is connected to internal node NTa corresponding to the measurement node.
  • the NMOS transistor 2035a is connected between the power supply line NP and the node N13 connected to the gate of the NMOS transistor 2032a.
  • Current source 2037a is connected between node N13 and ground line NL.
  • the gate of NMOS transistor 2035a is connected to node N11.
  • the NMOS transistor 2035a, the NMOS transistor 201a, and the NMOS transistor 403 (reference current source 40) are designed with the same characteristics (transistor size).
  • the gate voltage of the NMOS transistor 2032a becomes equal to the gate voltage of the NMOS transistor 2031a, that is, the measurement voltage Vout. Furthermore, if the current of the current source 2037a is made equal to the reference current Iref, the gate-to-source voltage of the NMOS transistor 2035a becomes equal to Vgs4 in FIG. Therefore, the gate voltage of the NMOS transistor 2035a, that is, the voltage of the node N11, is equivalent to Vout+Vg4.
  • the same gate-source voltage Vgs2 as in FIG. 2 is generated in the NMOS transistor 201a.
  • the voltage applied to the resistance element 202a is Vout+Vgs4-Vg2.
  • FIG. 5 is a circuit diagram illustrating a modification of reference current source 40 shown in FIG.
  • Reference current source 40# according to Modification 2 of FIG. 2 in that an operational amplifier buffer 407 is further included.
  • the operational amplifier buffer 407 is configured similarly to the operational amplifier buffer 230a of FIG.
  • NMOS transistor 4071 The gate of NMOS transistor 4071 is connected to node N6 where reference voltage Vref is generated.
  • NMOS transistor 4075 is connected between power supply line NP and node N14, and current source 4077 is connected between node N14 and ground line NL.
  • the gate of the NMOS transistor 4075 is connected to the node N15, which is the connection point between the PMOS transistor 4074 and the NMOS transistor 4072 .
  • the gate of NMOS transistor 403 is also connected to node N15.
  • the NMOS transistor 4075 is designed with the same characteristics (transistor size and threshold voltage) as the NMOS transistor 403 (reference current source 40).
  • the gate voltage of the NMOS transistor 4072 becomes equal to the gate voltage of the NMOS transistor 4071, that is, the reference voltage Vref. Furthermore, if the current of the current source 4077 is made equal to the current flowing through the resistance element 404 , that is, the reference current Iref, the gate-source voltage of the NMOS transistor 4075 becomes equal to the gate-source voltage Vgs4 of the NMOS transistor 403 . Therefore, the gate voltage of the NMOS transistor 4075, that is, the voltage of the node N15 is equivalent to Vout+Vg4.
  • semiconductor integrated circuit device 5b has N voltage-current conversion circuits 21 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. and a selection circuit 31 instead of the selection circuit 30 .
  • Each selection circuit 21 has a node that generates two output currents with different conversion gains for the measurement voltage Vout at the internal node NT corresponding to the measurement node of the corresponding internal circuit 10 . Accordingly, the selection circuit 31 is configured to select one of the (2 ⁇ N) nodes of the N voltage-to-current conversion circuits 21 and connect it to the current comparator 50 .
  • the measured voltage Vout can be compared with two types of determination voltages. For example, by comparing the determination voltage Vtl corresponding to the lower limit of the normal range of the measured voltage Vout and the determination voltage Vtu corresponding to the upper limit of the normal range with the measured voltage Vout, the measured voltage Vout is within the normal range. It is possible to determine whether or not there is
  • voltage-current conversion circuit 21a includes NMOS transistors 203a and 205a and resistance elements 204a and 206a.
  • the gates of NMOS transistors 203a and 205a are commonly connected to internal node NTa. That is, the gate voltages of NMOS transistors 203a and 205a are the measured voltage Vout.
  • the NMOS transistor 203a is connected between the node N1ax and the resistance element 204a, and the resistance element 204a is connected between the NMOS transistor 203a and the ground line NL.
  • Resistive element 204a has an electrical resistance value RU.
  • the NMOS transistor 205a is connected between the node N1ay and the resistance element 206a, and the resistance element 206a is connected between the NMOS transistor 205a and the ground line NL.
  • the resistive element 206a has an electrical resistance value RL.
  • the voltage-current conversion circuit 21a is provided with two "voltage-current conversion units" corresponding to the series circuit of the NMOS transistor 201a and the resistance element 202a in FIG.
  • the number of nodes where Iout is generated is increased to two, nodes N1xa and N1ya. Due to the different electrical resistance values of resistive elements 204a and 206a, the two voltage-to-current conversion units convert a common measured voltage Vout to output currents with different conversion gains.
  • the voltage-to-current conversion circuits 21b to 21d are configured in the same manner as the voltage-to-current conversion circuit 21a.
  • a series circuit (voltage-to-current conversion unit) is arranged respectively.
  • the selection circuit 31 has switches 302a to 302d and 303a to 303d.
  • Switches 303a-303d are connected between one of two nodes of voltage-current conversion circuit 21 (node N1ax in FIG. 7) and node N2, respectively.
  • Switches 302a-302d are connected between the other of the two nodes of voltage-current conversion circuit 21 (node N1ay in FIG. 7) and node N2, respectively.
  • the configuration after the node N2 that is, the configurations of the current comparator 50 and the reference current source 40 are the same as in FIG. 2, so detailed description will not be repeated.
  • the selection circuit 31 turns on one of the switches 302a to 302d and 303a to 303d, and turns off the remaining switches.
  • the output current (Iou) generated at the node N1ax and the output current (Iol ) are sequentially input to the current comparator 50 one by one.
  • the measured voltage Vout can be sequentially compared with the two determination voltages Vtu and Vtl.
  • the switch 302a While the switch 302a is turned on, the remaining switches are turned off. As a result, the path of the output current Iol from the power supply line NP to the ground line NL, including the PMOS transistor 501, the switch 302a (node N1ay), the NMOS transistor 205a, and the resistance element 206a, changes from the output current Iout in FIG. It occurs in the same way as the path.
  • the voltage-to-current conversion circuit 21 can generate a plurality of output currents Iol and Iou with different conversion gains for the common measurement voltage Vout.
  • the respective conversion gains of the output currents Iol and Iou with respect to the measured voltage Vout are adjusted by the electrical resistance values RL and RL.
  • Vtl corresponding to the lower limit of the normal range of the measurement voltage Vout described above
  • Vgs22 in equation (9) indicates the gate-source voltage of the NMOS transistor 205a.
  • Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 2. That is, in the voltage-to-current conversion circuit 21, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is replaced. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • Embodiment 3 In the third embodiment, as in the second embodiment, another example of a configuration for comparing the measured voltage Vout with a plurality of determination voltages will be described.
  • FIG. 8 is a block diagram showing the configuration of a semiconductor integrated circuit device 5c according to the third embodiment.
  • semiconductor integrated circuit device 5c has N voltage-current conversion circuits 22 instead of N voltage-current conversion circuits 20, as compared with semiconductor integrated circuit device 5a according to the first embodiment. The difference is that the A control signal Schg for switching the conversion gain is input to each voltage-current conversion circuit 22 .
  • FIG. 9 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 9 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 9 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 9 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the voltage-current conversion circuit 22a has series-connected resistance elements 209a and 201a instead of the resistance element 202a between the source of the NMOS transistor 201a and the ground line NL. It has a connected configuration.
  • Transistor switch 208a is connected in parallel with resistive element 210a. Transistor switch 208a is turned on when control signal Schg is at H level, and turned off when it is at L level.
  • the configuration after the nodes N1a to N1d that is, the configuration of the selection circuit 30, the current comparator 50, and the reference current source 40 is the same as that of FIG. 2, so the detailed description will be repeated. do not have.
  • RO1+RO2 (Vtu ⁇ Vgs2)/(Vref ⁇ Vgs4) ⁇ RP (12)
  • current comparator 50 a current equivalent to reference current Iref is drawn from node N3 by NMOS transistor 503, as in FIG. Therefore, at the node N3, a voltage V3 is generated by amplifying the current difference between the output current Iout whose conversion gain is switched according to the control signal Schg and the reference current Iref.
  • one set of the reference current source 40 and the current comparator 50 is used to suppress an increase in circuit size.
  • the measured voltage Vout can be compared with a plurality of decision voltages.
  • the configuration of the third embodiment it is possible to determine the measured voltage Vout in the same manner as in the second embodiment without using the selection circuit 31 that doubles the number of switches. That is, the same effect as in the second embodiment can be obtained, and the circuit scale can be suppressed as compared with the second embodiment.
  • Modification 1 and Modification 2 described in Embodiment 1 can be applied. That is, in the voltage-current conversion circuit 22, the current comparator 50, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged to replace the PMOS transistor. It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 22 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • Embodiment 4 a configuration capable of simultaneously comparing the measurement voltage Vout and a plurality of determination voltages (for example, Vtu and Vtl) described in the second and third embodiments will be described.
  • FIG. 10 is a block diagram showing the configuration of a semiconductor integrated circuit device 5d according to the fourth embodiment.
  • a semiconductor integrated circuit device 5d differs from the semiconductor integrated circuit device 5b (FIG. 6) according to the second embodiment in that a selection circuit 32 is arranged instead of the selection circuit 31. It differs in that a current comparator 51 is arranged instead of the current comparator 50 and that a decision logic circuit 60 is further arranged.
  • the voltage-current conversion circuit 21 and the reference current source 40 are the same as those in the second embodiment (FIG. 6).
  • FIG. 11 shows a circuit diagram for explaining the internal configuration of each block shown in FIG.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 11 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 11 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the node N1ax of the voltage-current conversion circuit 21a is connected to the node N2x of the current comparator 51 via the switch 305a of the selection circuit 32, and the node N1ay of the voltage-current conversion circuit 21a connects the switch 304a of the selection circuit 32. It is connected to the node N2y of the current comparator 51 via.
  • the selection circuit 32 connects the two nodes (corresponding to Niax and N1ay) of one of the voltage-to-current conversion circuits 21a to 21d to the nodes N2x and N2y of the current comparator 51, respectively. Controlled to connect.
  • the current comparator 51 has PMOS transistors 505 to 508 and NMOS transistors 509 to 511 that form four sets of current mirrors.
  • the PMOS transistors 507 and 508 are connected between the power line NP and the nodes N2y and N3y, respectively.
  • the PMOS transistors 507 and 508 form a current mirror (current ratio is 1:1) by commonly connecting the gates to the node N2y (that is, the drain of the PMOS transistor 507).
  • the switch 305a creates a path for the output current Ioutx from the power supply line NP to the ground line NL, including the PMOS transistor 505, the switch 305a (node N1ax), the NMOS transistor 203a, and the resistance element 204a.
  • the output current Ioutx is equivalent to the output current Iou in FIG.
  • the switch 304a turns on the switch 304a creates a path for the output current Iouty from the power supply line NP to the ground line NL, including the PMOS transistor 507, the switch 304a (node N1ay), the NMOS transistor 205a, and the resistance element 206a.
  • the output current Iouty is equivalent to the output current Iol in FIG.
  • the output currents Ioutx and Iouty respectively corresponding to the output currents Iou and Iol in FIG. 7 are generated at the same time. That is, a plurality of output currents Ioutx and Iouty with different conversion ratios generated by the voltage-current conversion circuit 22 are input in parallel to the current comparator 50 .
  • the output current Ioutx is copied by a current mirror (current ratio 1:1) by PMOS transistors 505 and 506.
  • the output current Iouty is copied by a current mirror (1:1 current ratio) by PMOS transistors 507 and 508 .
  • PMOS transistor 506 supplies a current equivalent to output current Ioutx to node N3x
  • PMOS transistor 508 supplies a current equivalent to output current Iouty to node N3y.
  • the reference current Iref supplied from the reference current source 40 to the node N4 is a current mirror by the NMOS transistors 511 and 509 (current ratio 1:1) and a current mirror by the NMOS transistors 511 and 510 (current ratio 1:1). 1).
  • the PMOS transistor 509 extracts a current equivalent to the reference current Iref from the node N3x.
  • a current equivalent to reference current Iref is drawn from node N3y by PMOS transistor 510 .
  • the voltage V3x is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtu (on the upper limit side).
  • Vout ⁇ Vtu, Iout ⁇ Iref so the determination signal Sidx corresponding to the voltage V3x is set to L level.
  • the voltage V3y is set to a voltage level indicating the comparison result between the measured voltage Vout and the determination voltage Vtl (lower limit side).
  • the determination signal Sidy corresponding to the voltage V3y is set to H level.
  • the decision logic circuit 60 has an inverter 601 and a NAND (negative logical product) gate 602 .
  • Inverter 601 inverts and outputs determination signal Sidx.
  • the output voltage of the inverter 610 and the determination signal Sidy are input to the NAND gate 602 to output the determination signal Sjd.
  • the determination signal Sjd from the determination logic circuit 60 can be output to the terminal 6 that can be contacted from the outside of the semiconductor integrated circuit device 5f.
  • the measured voltage Vout is in the voltage range (normal range) of Vtl ⁇ Vout ⁇ Vtu.
  • the determination signal Sjd is set to L level.
  • the determination signal Sjd H level.
  • the current comparator 52 compares the measured voltage Vout and the determination voltage Vtl (lower limit side), and compares the measured voltage Vout and the determination voltage Vtu (upper limit side). side) can be performed at the same time.
  • the measured voltage Vout can be compared with only one judgment voltage, so that the measured voltage Vout falls within the normal range defined by the upper and lower limits. It is necessary to use the determination signal Sjd at different timings to determine whether or not it will be possible.
  • the measured voltage Vout obtained by comparing the same measured voltage Vout as in the second embodiment with a plurality of judgment voltages, for example, the lower limit value and the upper limit value of the normal range is It is possible to determine whether or not it is within the normal range at a higher speed than in the second embodiment. That is, in the semiconductor integrated circuit device according to the fourth embodiment, in addition to the effect described in the second embodiment, it is possible to further shorten the test time.
  • Modification 1 and Modification 2 described in Embodiment 1 can also be applied to Embodiment 4. That is, in the voltage-current conversion circuit 21, the current comparator 51, and the reference current source 40, the positions of the power supply line NP and the ground line NL are exchanged, and the NMOS transistor and the PMOS transistor are exchanged, so that the PMOS transistor is It is possible to perform voltage-to-current conversion using Alternatively, by adding operational amplifier buffers (FIGS. 4 and 5) to the voltage-current conversion circuit 21 and the reference current source 40, the effects of variations in MOS transistors and temperature fluctuations can be suppressed to improve the accuracy of determination. can be done.
  • operational amplifier buffers FIGS. 4 and 5
  • FIG. 12 is a block diagram showing the configuration of a semiconductor integrated circuit device 5e according to the fifth embodiment.
  • a semiconductor integrated circuit device 5e is different from the semiconductor integrated circuit device 5d (FIG. 10) according to the fourth embodiment in that the arrangement of the selection circuit 32 is omitted, and voltage-current conversion is performed.
  • the difference is that a voltage-current conversion circuit 23 is arranged instead of the circuit 21 .
  • An enable signal EN is input to each voltage-current conversion circuit 21 .
  • One of enable signals ENa-ENd is set to H level to select internal nodes NTa-NTd of internal circuits 10a-10d to be measured.
  • the remaining three enable signals ENa-ENd are set to L level.
  • FIG. 13 shows a circuit diagram for explaining the internal configuration of each block shown in FIG.
  • the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • FIG. 13 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 13 as well, the structure corresponding to internal circuit 10a is representatively shown with a subscript a, and similar structures are arranged corresponding to each internal circuit 10.
  • the two nodes of each voltage-to-current conversion circuit 23 are connected to the nodes N2x and N2y of the current comparator 51 and through switches. connected without For example, nodes N1ax and N1ay of the voltage-current conversion circuit 23a are connected to nodes N2x and N2y of the current comparator 51, respectively, without switches.
  • Embodiment 5 can be combined with Embodiments 1 to 3 and configurations obtained by applying Modification 1 and/or Modification 2 to Embodiments 1 to 3. Specifically, by connecting the enable switch 207a in series with the resistance element 202a in the voltage-current conversion circuit 20a (FIG. 2) and the voltage-current conversion circuit 20a# (FIG. 4), the first embodiment or the modified example 1 Applied Embodiment 1 and Embodiment 5 can be combined. Similarly, by connecting the enable switch 207a in series with the resistance element 202pa in the voltage-current conversion circuit 20pa (FIG. 3), it is possible to combine the first embodiment to which the modification 2 is applied and the fifth embodiment. can.
  • Embodiment 6 In a sixth embodiment, an abnormality handling configuration using the determination results in the fourth and fifth embodiments will be described.
  • FIG. 14 is a block diagram showing the configuration of a semiconductor integrated circuit device 5f according to the sixth embodiment.
  • a semiconductor integrated circuit device 5f includes N internal circuits 10 each composed of an internal circuit (hereinafter also referred to as "first internal circuit") 11 having the same function and an internal circuit (hereinafter also referred to as " 12, and each internal circuit 10 has an abnormality response configuration that switches to the second internal circuit 12 when a failure is detected in the first internal circuit 11.
  • first internal circuit an internal circuit having the same function
  • 12 an internal circuit (hereinafter also referred to as "12”
  • each internal circuit 10 has an abnormality response configuration that switches to the second internal circuit 12 when a failure is detected in the first internal circuit 11.
  • the semiconductor integrated circuit device 5f includes voltage-to-current conversion circuits 21a to 21d, a selection circuit 32, a reference current source 40, a current comparator 51, and a decision logic circuit 60 similar to the semiconductor integrated circuit device 5d (FIG. 10). Further, selection circuits 15a to 15d, a judgment result selection circuit 70, recording devices 80a to 80d, and control logic circuits 9a to 9d are further provided for the above-described abnormality handling configuration.
  • FIG. 15 shows a circuit diagram for explaining the internal configuration of each block shown in FIG. 15 as well, the structure corresponding to internal circuit 10a is indicated with a suffix a, and the same structure is arranged corresponding to each internal circuit 10. As shown in FIG. 15
  • the selection circuit 15 has switches 1001a to 1004a.
  • the switches 1001a and 1002a connect the first internal circuit 11a, the second internal circuit 12a, and another actual circuit (not shown) mounted on the semiconductor integrated circuit device 5f to which the output voltage of the internal circuit 10a is input. connected between Switch 1001a is turned on and off according to control signal Aa, while switch 1001a is turned on and off according to control signal /Aa (inverted signal of Aa). As a result, the output voltage of one of the first internal circuit 11a and the second internal circuit 12a is input to the actual circuit.
  • the switch 1003a is connected between the internal node NT1a corresponding to the output node of the first internal circuit 11a and the voltage-current conversion circuit 21a.
  • Switch 1004a is connected between internal node NT2a corresponding to the output node of second internal circuit 12a and voltage-current conversion circuit 21a.
  • the switch 1003a When the switch 1003a is turned on, the voltage of the internal node NT1a, that is, the output voltage of the first internal circuit 11a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.
  • the switch 1004a when the switch 1004a is turned on, the voltage of the internal node NT2a, that is, the output voltage of the second internal circuit 12a is input to the voltage-current conversion circuit 21a as the measurement voltage Vout.
  • a determination signal Sjd indicating whether the voltage (Vout) is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) can be obtained at the node N20.
  • the determination result selection circuit 70 has switches 701a to 701d and 702a to 702d.
  • a recording device 80a corresponding to the internal circuit 10a has a first latch circuit 801a, a second latch circuit 802a, and a NAND gate 803a.
  • the switch 701a is connected between the node N20 and the first latch circuit 801a.
  • the first latch circuit 801a is arranged to store the determination signal Sjd for the first internal circuit 11a included in the internal circuit 10a. Therefore, the switch 701a is provided with an ON period in conjunction with the switch 1003a.
  • the switch 702a is connected between the node N20 and the second latch circuit 802a.
  • Second latch circuit 802a is arranged to store determination signal Sjd for second internal circuit 12a included in internal circuit 10a. Therefore, the switch 702a is provided with an ON period in conjunction with the switch 1004a.
  • each of the recording devices 80b to 80d arranged corresponding to each of the internal circuits 10b to 10d also has a first latch circuit 801 for storing the judgment result of the first internal circuit 11, and , and a second latch circuit 802 for storing the determination result of the second internal circuit 12 .
  • a switch 701 leading to the first latch circuit and a second latch circuit are provided.
  • a switch 702 is provided.
  • the NAND gate 803a receives the latch data S11a of the first latch circuit 801a and the latch data S12a of the second latch circuit 802a, and outputs the internal circuit normal signal /Ea.
  • the control logic circuit 9a has a NAND gate 901a and an inverter 902a.
  • the NAND gate 901a receives the latch data S11a and the inverted data of the latch data S12a as inputs, and outputs a control signal Aa for the switch 1001a.
  • Inverter 902a inverts the output signal of NAND gate 901a to output control signal /Aa for switch 1002a.
  • the output voltage of the first internal circuit 11a and the output voltage of the second internal circuit 12a are determined in order.
  • the determination signal Sjd indicating whether the output voltage (Vout) of the first internal circuit 11a is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) is output to the first It is input to the latch circuit 801a. If the determination result of the first internal circuit 11a is normal, the latch data S11a of the first latch circuit 801a becomes L level.
  • the determination signal Sjd indicating whether the output voltage (Vout) of the second internal circuit 12a is within the range of Vtl ⁇ Vout ⁇ Vtu (normal range) is generated. 2 is input to the latch circuit 802a. If the determination result of the first internal circuit 11a is normal, the latch data S12a of the second latch circuit 802a becomes L level.
  • the first latch circuit 801a corresponds to an example of "first storage circuit”
  • the latch data S11a corresponds to an example of "first information”.
  • the second latch circuit 802a corresponds to an example of the "second storage circuit”
  • the latch data S12a corresponds to an example of the "second information”.
  • the switches 1003a and 1004a in the selection circuit 15a can constitute an embodiment of the "measurement selection circuit”.
  • switches 1003b, 1004b, 304b, 305b, and 701b corresponding to the internal circuit 10b are selected so that the output voltage of the first internal circuit 11b and the output voltage of the second internal circuit 12b are sequentially determined.
  • 702b are turned on and off in the same manner as switches 1003a, 1004a, 304a, 305a, 701a and 702a at the test timing of internal circuit 10a.
  • FIG. 17 shows a chart for explaining the operation of the abnormality detection configuration with respect to the judgment results of the first and second internal circuits. As shown in FIG. 17, there are cases 1 to 4 in combination of determination results of the first and second internal circuits.
  • control signal Aa is set to H level
  • control signal /Aa is set to L level. That is, the output of the first internal circuit 11a is transmitted to the actual circuit by the switch 1001a.
  • the internal circuit abnormality signal /Ea is set to H level.
  • the first internal circuit 11a is used as the default circuit for actual use, and when the first internal circuit 11a fails, the second internal circuit 12a for backup is used as the circuit for actual use on condition that the determination result is normal.
  • An abnormality handling configuration that automatically switches to .
  • the operation of semiconductor integrated circuit device 5e can be continued even when a failure occurs in the internal circuit.
  • the internal circuit abnormality signal /Ea is set to L level, thereby notifying that the internal circuit 10a cannot be used.
  • the semiconductor integrated circuit device As described above, according to the semiconductor integrated circuit device according to the sixth embodiment, it is possible to automatically detect a failure in the internal circuit 10 and switch over to the backup circuit when a failure occurs. In addition to the effect described in Embodiment 4, it is possible to improve the reliability of circuit operation continuation. Further, by monitoring the control signals Aa, /Aa and the internal circuit abnormality signal /Ea from the outside of the semiconductor integrated circuit device 5f, the failure state of each internal circuit 10 can also be grasped. That is, the control signals Aa, /Aa and the internal circuit error signal /Ea can be output to terminals (not shown) that can be contacted from the outside of the semiconductor integrated circuit device 5f, similarly to the terminal 6. FIG.
  • FIG. 15 illustrates an example in which the abnormality handling configuration of the sixth embodiment is applied to the semiconductor integrated circuit device of the fourth embodiment.
  • modifications 1 and 2 it is possible to further combine the sixth embodiment.
  • the number of latch circuits of the recording device 80 and the content of the logic operation in the control logic circuit 9 can be changed as needed.
  • Embodiments 1 to 3 in order to determine normality and ⁇ using the same determination result related to the voltage range (Vtl ⁇ Vout ⁇ Vtu) as in Embodiment 4, the determination voltages Vtl and Vtu Four latch circuits are required in each recording device 80 in order to hold the determination signal Sjd for comparison with each other.
  • the logic in the control logic circuit 9 is adjusted so that the control signals Aa and /Aa and the internal circuit abnormality signal /Ea similar to those in FIG. It is necessary to change the operation.
  • Embodiment 7 In the seventh embodiment, a configuration will be described in which two voltage differences (voltage differences) relating to measurement nodes of an internal circuit are used as measurement voltages, ie, determination targets.
  • FIG. 18 is a block diagram showing the configuration of a semiconductor integrated circuit device 5g according to the seventh embodiment.
  • a semiconductor integrated circuit device 5g differs from the semiconductor integrated circuit device 5b according to the fourth embodiment (FIG. 10) in that two voltages Vout1 and Vout2 are applied from the internal circuit 10a. It differs in that Vout2 is output and in that a voltage-current conversion circuit 24a is arranged instead of the voltage-current conversion circuit 21a. Further, an upper peak detector 13a and a lower peak detector 14a are provided for the internal node NTa (output voltage Vout) of the internal circuit 10a, which corresponds to the "measurement node".
  • the upper peak detector 13a extracts the maximum value (upper peak value) of the output voltage Vout and outputs it as the first voltage Vout1.
  • the lower peak detector 14a extracts the minimum value (lower peak value) of the output voltage Vout and outputs it as the second voltage Vout2.
  • Vout1-Vout2 represents the peak-to-peak value of the AC voltage.
  • a first voltage Vout1 and a second voltage Vout2 are input to the voltage-current conversion circuit 24a.
  • the voltage-current conversion circuit 24a converts the voltage difference (Vout1-Vout2) between the first voltage Vout1 and the second voltage Vout2 into output currents Ioutx and Iouty in FIG. 11 with different conversion gains.
  • the selection circuit 32, the current comparator 50, the reference current source 40, and the decision logic circuit 60, which are shared by the N internal circuits 10, are the same as in the fourth embodiment (FIG. 10).
  • the structure corresponding to internal circuit 10a is representatively shown with the suffix a.
  • FIG. 19 shows a circuit diagram for explaining the configuration of the voltage-current conversion circuit according to Embodiment 7, that is, the voltage-current conversion circuit 24a of FIG.
  • the NMOS transistor 2301a is connected between the power supply line NP and the node N31, and the current source 2302a is connected between the node N31 and the ground line NL.
  • a second voltage Vout2 is input to the gate of the NMOS transistor 2301a.
  • a current source 2303a is connected between the power supply line NP and the node N32, and a PMOS transistor 2304a is connected between the node N32 and the ground line NL.
  • a first voltage Vout1 is input to the gate of the PMOS transistor 2304a.
  • the NMOS transistor 2305a is connected between the node N1ax and the node N33.
  • Resistive element 2306a is connected between node N33 and PMOS transistor 2307a, and PMOS transistor 2307a is connected between resistive element 2306a and ground line NL.
  • Resistive element 2306a has an electrical resistance value RDU.
  • the NMOS transistor 2308a is connected between the node N1ay and the node N34.
  • Resistive element 2309a is connected between node N34 and PMOS transistor 2310a, and PMOS transistor 2310a is connected between resistive element 2309a and ground line NL.
  • Resistance element 2309a has an electrical resistance value RDL.
  • NMOS transistors 2305a and 2038a are commonly connected to node N32.
  • PMOS transistors 2307a and 2310a are commonly connected to node N31.
  • the NMOS transistor 2308a, the resistance element 2309a, and the PMOS transistor 2310a are omitted from the voltage-current conversion circuit 24a of FIG. 19, and the NMOS transistor 2305a is connected between the node N1a and the node N33.
  • the electrical resistance value of the resistive element 2306a at that time can be obtained by replacing the determination voltage Vtu with the determination voltage Vdt in the equation (15).
  • the first voltage Vout1 and the second voltage Vout2 related to the measurement node of the internal circuit 10 are two voltages at different timings of the same node. It is also possible to take the voltages as the first voltage Vout1 and the second voltage Vout2 and the voltage difference between the two internal nodes as the measured voltage Vout.
  • the circuits subsequent to the nodes N1ax and N1ay can be the same as those of any one of the first to sixth embodiments.
  • the difference between the two voltages (voltage difference) associated with the internal circuit 10 can be determined in the same manner as in the first to sixth embodiments, or an abnormality handling configuration based on the determination result can be performed.
  • the voltage-to-current conversion circuit 25a further includes a PMOS transistor 2312a, an NMOS transistor 2313a, and current sources 2311a and 2314a compared to the voltage-to-current conversion circuit 24a shown in FIG. and that the connection destinations of the gates of the NMOS transistor 2308a and the PMOS transistor 2310a are changed.
  • the current source 2311a is connected between the power supply line NP and the node N35, and the PMOS transistor 2312a is connected between the node N35 and the ground line NL.
  • a second voltage Vout2 is input to the gate of the PMOS transistor 2312a in common with the gate of the NMOS transistor 2301a.
  • the NMOS 2313a is connected between the power supply line NP and the node N36, and the current source 2314a is connected between the node N36 and the ground line NL.
  • a first voltage Vout1 is input to the gate of the NMOS transistor 2313a in common with the gate of the PMOS transistor 2304a.
  • the gate of the NMOS transistor 2308 is connected to the node N35 generating a voltage according to the second voltage Vout2, and the gate of the PMOS transistor 2310a is connected to the node N36 generating a voltage according to the first voltage Vout1. Therefore, a voltage according to the voltage difference (Vout2-Vout1) is applied across the resistance element 2309a. As a result, the output current Iouty becomes a current obtained by converting the voltage difference (Vout2-Vout1) by the conversion gain according to the electrical resistance value RDL.
  • the polarity (positive/negative) of the conversion gain of the output current Iouty is inverted with respect to the voltage-current conversion circuit 24a. Therefore, as a whole, it can be understood that the polarity (positive/negative) of the determination voltage Vdl can be reversed and compared with the voltage difference (Vout1-Vout2) as compared with the case of using the voltage-current conversion circuit 24a.
  • the voltage-current conversion circuit 25a shown in FIG. 20 even if the lower limit of the normal range of the voltage difference (Vout1-Vout2) is a negative voltage, the same as in the first to sixth embodiments , the voltage difference between the first voltage Vout1 and the second voltage Vout2 can be compared with the determination voltage as the measurement voltage Vout.
  • the current ratio of each current mirror is 1:1, but other current ratios are also possible.
  • the current ratio A of the output current Iout generated in the current comparator 50 transistors, 51 (nodes N3, N3x, N3y) to the output currents Iout, Ioutx, Iouty of the voltage-current conversion circuit 20, etc., and the reference (A /B) Multiplication is required.
  • two NMOS transistors having a transistor size equivalent to that of the NMOS transistor 403 are connected in parallel to configure the NMOS transistor 201a, so that the ratio of current and transistor size can be made uniform between the NMOS transistor 201a and the NMOS transistor 403. can be done.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Tests Of Electronic Circuits (AREA)
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Citations (9)

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JPS6232714A (ja) * 1985-08-06 1987-02-12 Clarion Co Ltd オフセツト電圧補正回路
JPH0829493A (ja) * 1994-07-14 1996-02-02 Fujitsu Ltd 半導体集積回路装置
JPH09139635A (ja) * 1995-09-12 1997-05-27 Toshiba Corp カレントミラー回路
US6008673A (en) * 1997-09-30 1999-12-28 Intel Corporation High speed, low power, current mode comparator
US20110012605A1 (en) * 2009-07-20 2011-01-20 Texas Instruments Incorporated Current based overvoltage and undervoltage detector
JP2012117983A (ja) * 2010-12-02 2012-06-21 Advantest Corp 電子デバイスおよび測定装置
JP2016211917A (ja) * 2015-05-01 2016-12-15 国立研究開発法人産業技術総合研究所 半導体チップ、半導体装置及び半導体検査システム
JP2017005609A (ja) * 2015-06-15 2017-01-05 株式会社デンソー 過電圧検出回路
JP2021173554A (ja) * 2020-04-21 2021-11-01 株式会社デンソー 過電圧判定回路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6232714A (ja) * 1985-08-06 1987-02-12 Clarion Co Ltd オフセツト電圧補正回路
JPH0829493A (ja) * 1994-07-14 1996-02-02 Fujitsu Ltd 半導体集積回路装置
JPH09139635A (ja) * 1995-09-12 1997-05-27 Toshiba Corp カレントミラー回路
US6008673A (en) * 1997-09-30 1999-12-28 Intel Corporation High speed, low power, current mode comparator
US20110012605A1 (en) * 2009-07-20 2011-01-20 Texas Instruments Incorporated Current based overvoltage and undervoltage detector
JP2012117983A (ja) * 2010-12-02 2012-06-21 Advantest Corp 電子デバイスおよび測定装置
JP2016211917A (ja) * 2015-05-01 2016-12-15 国立研究開発法人産業技術総合研究所 半導体チップ、半導体装置及び半導体検査システム
JP2017005609A (ja) * 2015-06-15 2017-01-05 株式会社デンソー 過電圧検出回路
JP2021173554A (ja) * 2020-04-21 2021-11-01 株式会社デンソー 過電圧判定回路

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