WO2023061052A1 - 自动跳线装置及通信设备 - Google Patents

自动跳线装置及通信设备 Download PDF

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Publication number
WO2023061052A1
WO2023061052A1 PCT/CN2022/114245 CN2022114245W WO2023061052A1 WO 2023061052 A1 WO2023061052 A1 WO 2023061052A1 CN 2022114245 W CN2022114245 W CN 2022114245W WO 2023061052 A1 WO2023061052 A1 WO 2023061052A1
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WIPO (PCT)
Prior art keywords
port
module
serial data
terminal
electrically connected
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PCT/CN2022/114245
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English (en)
French (fr)
Inventor
林秋培
邹紧跟
陈清平
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上海矽睿科技股份有限公司
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Publication of WO2023061052A1 publication Critical patent/WO2023061052A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to an automatic jumper and communication equipment.
  • the I2C (Inter-Integrated Circuit, built-in integrated circuit) bus is a synchronous serial data transmission bus defined by Philips. It is a 2-wire serial interface bus, including 2 signal lines, which are serial data lines. (Serial Data Line, SDA) and Serial Clock Line (Serial Clock Line, SCL). There is usually only one master device on the I2C bus, and multiple slave devices can be connected.
  • SDA Serial Data Line
  • SCL Serial Clock Line
  • the slave device includes: as the slave device SDA interface communicating with SDA, and As a slave device SCL interface communicating with SCL; the slave device SDA interface is connected to the SDA output interface in the I2C bus circuit, and the slave device SCL interface is connected to the SCL output interface in the I2C bus circuit, so that the master device can communicate with the slave through the I2C bus circuit devices to interact.
  • the purpose of this application is to provide an automatic jumper device and communication equipment that can automatically adjust the connection mode according to the different connection modes of the serial data port SDA and the serial clock port SCL.
  • An embodiment of the present application provides an automatic jumper device, which includes: a serial data port, a serial clock port, a serial data output port, a serial clock output port, a detection module, and a switching module;
  • the detection module is electrically connected to the serial data port and the serial clock port, and is used to detect the connection state of the serial data port and the serial clock port, and output a control signal to the switching module ;
  • the switching module is electrically connected to the serial data port, the serial clock port, the serial data output port, and the serial clock output port, and the switching module is in the first state according to the control signal and switch between the second state;
  • the serial data port and the serial data output port are turned on, and the serial clock port and the serial clock output port are turned on; when the When the switching module is in the second state, the serial data port is connected to the serial clock output port, and the serial clock port is connected to the serial data output port.
  • the detection module has a first detection terminal, a second detection terminal and a control signal output terminal;
  • the first detection terminal of the detection module is electrically connected to the serial data port
  • the second detection terminal of the detection module is electrically connected to the serial clock port
  • the control signal output terminal of the detection module is connected to the serial data port.
  • the switching module is electrically connected, and the first detection terminal and the second detection terminal are used to detect the connection status of the serial data port and the serial clock port.
  • the detection module includes: a first detection submodule, a second detection submodule, and a signal output submodule;
  • the serial data terminal of the first detection submodule is electrically connected to the first detection terminal
  • the serial clock terminal of the first detection submodule is electrically connected to the second detection terminal
  • the first detection submodule The output end of the module is electrically connected to the first signal input end of the signal output sub-module, and outputs a first detection signal to the signal output sub-module;
  • the serial data terminal of the second detection submodule is electrically connected to the second detection terminal
  • the serial clock terminal of the second detection submodule is electrically connected to the first detection terminal
  • the second detection submodule The output end of the module is electrically connected to the second signal input end of the signal output sub-module, and outputs a second detection signal to the signal output sub-module;
  • the signal output sub-module receives the first detection signal and the second detection signal, and outputs a control signal to the switching module through the control signal output terminal.
  • the switching module has a first input terminal, a second input terminal, a first output terminal and a second output terminal;
  • the first input terminal is electrically connected to the serial data port, and the second input terminal is electrically connected to the serial clock port;
  • the first output terminal is electrically connected to the serial data output port, and the second output terminal is electrically connected to the serial clock output port;
  • the switching module When the switching module is in the second state, the first input terminal is connected to the second output terminal, and the second input terminal is connected to the first output terminal.
  • the switching module includes a first switching submodule and a second switching submodule
  • the first end of the first switching submodule is electrically connected to the first input end, the second end of the first switching submodule is electrically connected to the second input end, and the first switching submodule
  • the third end is electrically connected to the first output end, and the fourth end of the first switching sub-module is electrically connected to the detection module;
  • the first end of the second switching sub-module is electrically connected to the first input end, the second end of the second switching sub-module is electrically connected to the second input end, and the second switching sub-module
  • the third end is electrically connected to the second output end, and the fourth end of the second switching sub-module is electrically connected to the detection module;
  • the switching module When the switching module is in the first state, the first end and the third end of the first switching sub-module are turned on, and the second end and the third end of the second switching sub-module are turned on;
  • the switching module When the switching module is in the second state, the second terminal of the first switching submodule is conducted with the third terminal, and the first terminal and the third terminal of the second switching submodule are conducted.
  • the connection state is positive connection, so The switching module is in the first state according to the control signal
  • connection state is reverse connection
  • the switching module is in a second state according to the control signal.
  • the bus is an I2C bus or an I3C bus.
  • the automatic jumper device further includes a power port and a ground port.
  • An embodiment of the present application provides a communication device, and the communication device includes the automatic jumper device described in any one of the above items.
  • the communication device further includes a slave device, the serial data terminal of the slave device is electrically connected to the serial data output port of the automatic jumper device, and the serial clock terminal of the slave device It is electrically connected with the serial clock output port of the automatic jumper.
  • the automatic jumper device includes: a serial data port, a serial clock port, a serial data output port, a serial clock output port, a detection module and a switching module, the detection module The module is electrically connected to the serial data port and the serial clock port, and is used to detect the connection status of the serial data port and the serial clock port, and output a control signal to the switching module; the switching module is connected to the serial data port and the serial clock port , the serial data output port, and the serial clock output port are electrically connected, and the switching module switches between the first state and the second state according to the control signal; when the switching module is in the first state, the serial data port and the serial data output The port is turned on, the serial clock port and the serial clock output port are turned on; when the switching module is in the second state, the serial data port and the serial clock output port are turned on, and the serial clock port and the serial data output port are turned on Pass.
  • Fig. 1 is a schematic diagram of SDA signal and SCL signal in an embodiment
  • Fig. 2 is a schematic diagram of SDA signal and SCL signal in another embodiment
  • FIG. 3 is a schematic diagram of a communication device in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a detection module in an embodiment of the present application.
  • Fig. 5 is a schematic diagram of a switching module in an embodiment of the present application.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection” and the like if there is transmission of electrical signals or data between the connected objects.
  • the master device communicates with the slave device through the serial data bus and the serial clock bus.
  • the I2C start condition is defined as when the serial data signal SDA is switched from high to low, and the serial clock signal SCL is high
  • the I2C stop condition is defined as when the serial data signal SDA is switched from low to high
  • the serial clock signal SCL is high.
  • the bus is exchanged and connected with each other, for example, the I2C serial data bus and the serial clock bus are exchanged with each other, resulting in the exchange of the serial data signal and the serial clock signal.
  • the SDA port of the slave device receives the serial clock signal
  • the SCL port of the slave device receives the serial data signal, so that the normal communication between the slave device and the master device will not be possible.
  • the start condition is triggered when the serial clock signal SCL and the serial data signal SDA are not exchanged.
  • the start condition will not be triggered.
  • the application provides an automatic jumper device 10, which can automatically switch the connection between the slave device and the bus when the bus is exchanged, so that the SDA port of the slave device can receive serial data signals, and the SCL port of the slave device can receive serial data signals. clock signal.
  • the automatic jumper device 10 provided by the present application includes a serial data port 11 , a serial clock port 12 , a serial data output port 13 , a serial clock output port 14 , a detection module 100 and a switching module 200 .
  • the serial data port 11 and the serial clock port 12 can be electrically connected to the bus, and the serial data output port 13 and the serial clock output port 14 are electrically connected to the slave device 300 .
  • the master device 400 is electrically connected to the bus, and communicates with the slave device 300 through the bus through the automatic jumper device 10 .
  • the detection module 100 is electrically connected to the serial data port 11 and the serial clock port 12 for detecting the connection state of the serial data port 11 and the serial clock port 12 and outputting a control signal to the switching module 200 .
  • the connection state of the serial data port 11 and the serial clock port 12 includes a positive connection state and a reverse connection state.
  • the serial data bus includes a first end and a second end
  • the serial clock bus also includes a first end and a second end.
  • the serial data port 11 When the SDA output interface of the master device 400 is electrically connected to the first end of the serial data bus, the serial data port 11 is electrically connected to the second end of the serial data bus, and the SCL output interface of the master device 400 is electrically connected to the first end of the serial clock bus. One end is electrically connected, and when the serial clock port 12 is electrically connected to the second end of the serial clock bus, the detection module 100 judges that the connection state between the serial data port 11 and the serial clock port 12 is a positive connection state.
  • the serial data port 11 When the SDA output interface of the master device 400 is electrically connected to the first end of the serial clock bus, the serial data port 11 is electrically connected to the second end of the serial clock bus, and the SCL output interface of the master device 400 is electrically connected to the first end of the serial data bus. One end is electrically connected, and when the serial clock port 12 is electrically connected to the second end of the serial data bus, the detection module 100 judges that the connection state between the serial data port 11 and the serial clock port 12 is a positive connection state.
  • the detection module 100 judges that the serial data The connection status of port 11 and serial clock port 12 is positive connection. That is to say, when the serial data port 11 can receive the serial data signal through one of the buses, and the serial clock port 12 can receive the serial clock signal through the other bus, the detection module 100 judges that the serial data port 11 and the The connection state of the serial clock port 12 is a positive connection state.
  • the serial clock port 12 When the SDA output interface of the master device 400 is electrically connected to the first end of the serial clock bus, the serial clock port 12 is electrically connected to the second end of the serial clock bus, and the SCL output interface of the master device 400 is electrically connected to the first end of the serial data bus. One end is electrically connected, and when the serial data port 11 is electrically connected to the second end of the serial data bus, the detection module 100 judges that the connection state of the serial data port 11 and the serial clock port 12 is a reverse connection state.
  • the serial clock port 12 When the SDA output interface of the master device 400 is electrically connected to the first end of the serial data bus, the serial clock port 12 is electrically connected to the second end of the serial data bus, and the SCL output interface of the master device 400 is electrically connected to the first end of the serial clock bus. One end is electrically connected, and when the serial data port 11 is electrically connected to the second end of the serial clock bus, the detection module 100 judges that the connection state of the serial data port 11 and the serial clock port 12 is a reverse connection state.
  • the detection module 100 judges that the serial data The connection state of port 11 and serial clock port 12 is reverse connection state. That is to say, when the serial data port 11 can receive the serial clock signal through one of the buses, and the serial clock port 12 can receive the serial data signal through the other bus, the detection module 100 judges that the serial data port 11 and the The connection state of the serial clock port 12 is reverse connection state.
  • the detection module 100 judges the connection state of the serial data port 11 and the serial clock port 12 , and outputs a control signal to the switching module 200 according to the connection state.
  • the switching module 200 is electrically connected to the serial data port 11, the serial clock port 12, the serial data output port 13, and the serial clock output port 14, and the switching module 200 switches between the first state and the second state according to the control signal.
  • the serial data port 11 and the serial data output port 13 are turned on, and the serial clock port 12 and the serial clock output port 14 are turned on; when the switching module 200 is in the second state, The serial data port 11 and the serial clock output port 14 are turned on, and the serial clock port 12 and the serial data output port 13 are turned on.
  • the detection module 100 detects that the serial data port 11 and the serial clock port 12 are in the positive connection state, the detection module 100 outputs a control signal to the switching module 200, so that the switching module 200 is in the first state, and the serial port of the master device 400
  • the row data signal is delivered to the serial data port of the slave device 300 through the serial data port 11 and the serial data output port 13 through one of the buses; the serial clock signal of the master device 400 is passed through the serial clock port 12 and the serial clock port 13 through another bus.
  • the serial clock output port 14 feeds to the serial clock port of the slave device 300 .
  • the detection module 100 When the detection module 100 detects that the serial data port 11 and the serial clock port 12 are in a reverse connection state, the detection module 100 outputs a control signal to the switching module 200, so that the switching module 200 is in the second state, and the serial data of the master device 400
  • the signal is delivered to the serial data port of the slave device 300 through the serial clock port 12 and the serial data output port 13 through one of the buses; the serial clock signal of the master device 400 is passed through the serial data port 11 and the serial port through another bus
  • the clock output port 14 feeds to the serial clock port of the slave device 300 .
  • connection mode between the bus and the slave device 300 is fixed, and the connection between the master device 400 and the bus is exchanged.
  • the SDA output interface of the master device 400 is electrically connected to the first end of the serial clock bus
  • the SCL output interface of the master device 400 is electrically connected to the first end of the serial data bus.
  • connection between the master device 400 and the bus is fixed, and the connection mode between the slave device 300 and the bus is switched.
  • the serial data end of the slave device 300 is electrically connected to the second end of the serial clock bus
  • the serial clock end of the slave device 300 is electrically connected to the second end of the serial data bus.
  • the serial data end of the slave device 300 is electrically connected to the serial data output port 13 of the automatic jumper device, and the serial clock end of the slave device 300 is connected to the serial port of the automatic jumper device.
  • the clock output port 14 is electrically connected, and the serial data port 11 of the automatic jumper device 10 is just equivalent to the serial data end of the slave device 300 like this, and the serial clock port 12 of the automatic jumper device 10 is just equivalent to the serial data port of the slave device 300. row clock terminal.
  • Port 11 and serial clock port 12 are switched to the correct connection mode, so that the serial data end of the slave device 300 can receive the serial data signal, and the serial clock end of the slave device 300 can receive the serial clock signal, to ensure that the master device Communication between 400 and slave device 300 can be carried out smoothly.
  • the detection module 100 has a first detection terminal 101 , a second detection terminal 102 and a control signal output terminal 103 .
  • the first detection end 101 of the detection module 100 is electrically connected to the serial data port 11, the second detection end 102 of the detection module 100 is electrically connected to the serial clock port 12, and the control signal output end 103 of the detection module 100 is electrically connected to the switching module 200.
  • the first detection terminal 101 and the second detection terminal 102 are used to detect the connection state of the serial data port 11 and the serial clock port 12, so as to judge whether the serial data port 11 and the serial clock port 12 are in a positive connection state or a reverse connection state state.
  • the detection module 100 judges whether the serial data port 11 and the serial clock port 12 are in the positive connection state or the reverse connection state by detecting the busy signal of the bus.
  • the detection module 100 includes: a first detection sub-module 110 , a second detection sub-module 120 and a signal output sub-module 130 .
  • the serial data terminal 111 of the first detection submodule 110 is electrically connected to the first detection terminal 101
  • the serial clock terminal 112 of the first detection submodule 110 is electrically connected to the second detection terminal 102
  • the output of the first detection submodule 110 The terminal 113 is electrically connected to the first signal input terminal 131 of the signal output sub-module 130 , and outputs the first detection signal to the signal output sub-module 130 .
  • the serial data terminal 122 of the second detection submodule 120 is electrically connected to the second detection terminal 102
  • the serial clock terminal 121 of the second detection submodule 120 is electrically connected to the first detection terminal 101
  • the output of the second detection submodule 120 The terminal 123 is electrically connected to the second signal input terminal 132 of the signal output sub-module 130 , and outputs the second detection signal to the signal output sub-module 130 .
  • the signal output sub-module 130 receives the first detection signal and the second detection signal, and outputs a control signal to the switching module 200 through the control signal output terminal 133 .
  • the first detection sub-module 110 and the second detection sub-module 120 determine the connection status of the serial data port 11 and the serial clock port 12 by detecting the busy signal of the bus.
  • the signal output sub-module 130 generates a control signal according to the first detection signal and the second detection signal, and outputs the control signal to the switching module 200 .
  • the control signal 0 can be generated and output to the switching module 200 .
  • the control signal 1 is generated and output to the switching module 200 .
  • the switching module 200 receives the control signal 0, the switching module 200 maintains the first state; when the switching module 200 receives the control signal 1, the switching module 200 switches to the second state.
  • the switching module 200 has a first input terminal 201 , a second input terminal 202 , a first output terminal 203 and a second output terminal 204 .
  • the first input end 201 is electrically connected to the serial data port 11
  • the second input end 202 is electrically connected to the serial clock port 12
  • the first output end 203 is electrically connected to the serial data output port 13
  • the second output end 204 is electrically connected to the serial clock output port 14 .
  • the switching module 200 When the switching module 200 is in the first state, the first input terminal 201 and the first output terminal 203 are turned on, and the second input terminal 202 and the second output terminal 204 are turned on. At this time, the serial data signal is delivered to the serial data port of the slave device 300 through the serial data port 11, the first input terminal 201, the first output terminal 203, and the serial data output port 13; The clock port 12 , the second input port 202 , the second output port 204 , and the serial clock output port 14 are delivered to the serial clock port of the slave device 300 .
  • the switching module 200 When the switching module 200 is in the second state, the first input terminal 201 and the second output terminal 204 are turned on, and the second input terminal 202 and the first output terminal 203 are turned on.
  • the serial data signal is delivered to the serial data port of the slave device 300 through the serial clock port 12, the second input terminal 202, the first output terminal 203, and the serial data output port 13;
  • the data port 11 , the first input port 201 , the second output port 204 , and the serial clock output port 14 are sent to the serial clock port of the slave device 300 . In this way, when the serial data signal and the serial clock signal are reversely connected, the slave device 300 can also work normally.
  • the switching module 200 includes a first switching submodule 210 and a second switching submodule 220 .
  • the first terminal 211 of the first switching submodule 210 is electrically connected to the first input terminal 201
  • the second terminal 212 of the first switching submodule 210 is electrically connected to the second input terminal 202
  • the third terminal of the first switching submodule 210 213 is electrically connected to the first output terminal 203
  • the fourth terminal 214 of the first switching sub-module 210 is electrically connected to the control signal output terminal 103 of the detection module 100 .
  • the first terminal 221 of the second switching submodule 220 is electrically connected to the first input terminal 201
  • the second terminal 222 of the second switching submodule 220 is electrically connected to the second input terminal 202
  • the third terminal of the second switching submodule 220 223 is electrically connected to the second output terminal 204
  • the fourth terminal 224 of the second switching sub-module 220 is electrically connected to the control signal output terminal 103 of the detection module 100
  • the first switching submodule 210 and the second switching submodule 220 may be a multiplexer (MUX), which is not limited in this application.
  • MUX multiplexer
  • the switching module 200 When the switching module 200 is in the first state, the first terminal 211 and the third terminal 213 of the first switching submodule 210 are conducted, and the second terminal 222 and the third terminal 223 of the second switching submodule 220 are conducted.
  • the serial data signal is delivered to the serial data port of the slave device 300 through the first input terminal 201, the first terminal 211, the third terminal 213 and the first output terminal 203 of the first switching submodule 210; the serial clock The signal is sent to the serial clock port of the slave device 300 through the second input terminal 202 , the second terminal 222 and the third terminal 223 of the second switching sub-module 220 , and the second output terminal 204 .
  • the switching module 200 When the switching module 200 is in the second state, the second terminal 212 and the third terminal 213 of the first switching submodule 210 are conducted, and the first terminal 221 and the third terminal 223 of the second switching submodule 220 are conducted.
  • the serial data signal is delivered to the serial data port of the slave device 300 through the second input terminal 202, the second terminal 212, the third terminal 213 and the first output terminal 203 of the first switching submodule 210; the serial clock The signal is sent to the serial clock port of the slave device 300 through the first input terminal 201 , the first terminal 221 and the third terminal 223 of the second switching sub-module 220 , and the second output terminal 204 .
  • serial data port 11 when the serial data port 11 is electrically connected to the serial data output interface of the master device 400 through one of the buses, and the serial clock port 12 is electrically connected to the serial clock output interface of the master device 400 through another bus,
  • the connection state of the serial data port 11 and the serial clock port 12 is forward connection, and the switching module 200 is in the first state according to the control signal.
  • serial data port 11 When the serial data port 11 is electrically connected to the serial clock interface of the master device 400 through one of the buses, and the serial clock port 12 is electrically connected to the serial data interface of the master device 400 through another bus, the serial data port 11 and The connection state of the serial clock port 12 is reverse connection, and the switching module 200 is in the second state according to the control signal.
  • the automatic jumper device 10 also includes a power port (not shown in the figure) and a ground port (not shown in the figure).
  • the automatic jumper device 10 in the embodiment of the present application may be applicable to an I2C bus or an I3C bus.
  • the switching module 200 switches to the second state, so that the serial The clock signal is delivered to the serial clock port of the slave device 300 through the serial data port 11, the first input end 201, the second output end 204, and the serial clock output port 14; the serial data signal is passed through the serial clock port 12, the second The second input terminal 202 , the first output terminal 203 , and the serial data output port 13 are sent to the serial data port of the slave device 300 to ensure normal communication between the slave device 300 and the master device 400 .
  • the slave device 300 cannot work normally due to the exchange of the serial data signal and the serial clock signal in the prior art, so that when the serial data signal and the serial clock signal are transmitted, there is no need to pay special attention to the transmission route of the signal,
  • the adaptability of the device is improved, and the connection method of the device is simplified.
  • Another embodiment of the present application provides a communication device, which includes the above-mentioned automatic jumper device 10 and a slave device 300 .
  • the serial data terminal of the slave device 300 is electrically connected to the serial data output port 13 of the automatic jumper device 10
  • the serial clock terminal of the slave device 300 is electrically connected to the serial clock output port 14 of the automatic jumper device.
  • the automatic jumper device 10 can be independent from the slave device 300 and serve as an independent device connecting the master device 400 and the slave device 300 .
  • the automatic jumper device 10 can also be integrated in the slave device 300 as a connection module in the slave device 300; like this, no matter how the serial data end and the serial clock end of the slave device 300 are connected with the master device 400, the automatic jumper The device 10 can switch to the correct connection mode to ensure normal communication between the slave device 300 and the master device 400 .
  • Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory or optical memory, etc.
  • Volatile memory can include Random Access Memory (RAM) or external cache memory.
  • RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

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Abstract

本申请涉及一种自动跳线装置及通信设备。自动跳线装置包括：串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口、检测模块和切换模块，检测模块与串行数据端口和串行时钟端口电连接，用于检测串行数据端口和串行时钟端口的连接状态，并向切换模块输出控制信号；切换模块与串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口电连接，切换模块根据控制信号在第一状态和第二状态之间切换；解决了现有技术中串行数据信号和串行时钟信号交换时，从设备与主设备之间的通信将失败的问题，实现了自动调整从设备SCL接口和SDA接口与总线的连接关系，使得从设备始终能够与主设备通信。

Description

自动跳线装置及通信设备 技术领域
本申请涉及集成电路技术领域，特别是涉及一种自动跳线装置及通信设备。
背景技术
I2C(Inter-Integrated Circuit，内置集成电路)总线是飞利浦(Philips)公司定义的同步串行数据传输总线，是一种2线串行接口总线，其中包括2路信号线，分别为串行数据线(Serial Data Line，SDA)和串行时钟线(Serial Clock Line，SCL)。I2C总线上通常只有一个主设备，可挂接多个从设备。
现有技术的I2C总线电路中，通常是设置固定的两个信号线输出接口，其中一个作为SDA，另一个作为SCL；使用时，从设备中包括：作为与SDA通信的从设备SDA接口，以及作为与SCL通信的从设备SCL接口；从设备SDA接口与I2C总线电路中的SDA输出接口连接，从设备SCL接口与I2C总线电路中的SCL输出接口连接，使得主设备可以通过I2C总线电路与从设备进行交互。
然而，当从设备的SDA接口与I2C总线电路中的SCL输出接口连接，从设备的SCL接口与I2C总线电路中的SDA输出接口连接时，从设备与主设备之间的通信将会失败。
申请内容
本申请的目的是提供一种依据串行数据端口SDA和串行时钟端口SCL连接方式不同，自动调节连接方式的自动跳线装置和通信设备。
本申请一实施例提供一种自动跳线装置，所述自动跳线装置包括：串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口、检测模块和切换模块；
所述检测模块与所述串行数据端口和所述串行时钟端口电连接，用于检测所述串行数据端口和所述串行时钟端口的连接状态，并向所述切换模块输出控制信号；
所述切换模块与所述串行数据端口、所述串行时钟端口、所述串行数据输出端口、所述串行时钟输出端口电连接，所述切换模块根据所述控制信号在第一状态和第二状态之间切换；
当所述切换模块处于所述第一状态时，所述串行数据端口和所述串行数据输出端口导通，所述串行时钟端口和所述串行时钟输出端口导通；当所述切换模块处于第二状态时，所述串行数据端口和所述串行时钟输出端口导通，所述串行时钟端口和所述串行数据输出端口导通。
在一种实施方式中，所述检测模块具有第一检测端、第二检测端和控制信号输出端；
所述检测模块的第一检测端与所述串行数据端口电连接，所述检测模块的第二检测端与所述串行时钟端口电连接，所述检测模块的控制信号输出端与所述切换模块电连接，所述第一检测端和所述第二检测端用于检测所述串行数据端口和所述串行时钟端口的连接状态。
在一种实施方式中，所述检测模块包括：第一检测子模块、第二检测子模块和信号输出子模块；
所述第一检测子模块的串行数据端与所述第一检测端电连接，所述第一检测子模块的串行时钟端与所述第二检测端电连接，所述第一检测子模块的输出端与所述信号输出子模块的第一信号输入端电连接，向所述信号输出子模块输出第一检测信号；
所述第二检测子模块的串行数据端与所述第二检测端电连接，所述第二检测子模块的串行时钟端与所述第一检测端电连接，所述第二检测子模块的输出端与所述信号输出子模块的第二信号输入端电连接，向所述信号输出子模块输出第二检测信号；
所述信号输出子模块接收所述第一检测信号和所述第二检测信号，并通 过所述控制信号输出端向所述切换模块输出控制信号。
在一种实施方式中，所述切换模块具有第一输入端、第二输入端、第一输出端和第二输出端；
所述第一输入端与所述串行数据端口电连接，所述第二输入端与所述串行时钟端口电连接；
所述第一输出端与所述串行数据输出端口电连接，所述第二输出端与所述串行时钟输出端口电连接；
当所述切换模块处于第一状态时，所述第一输入端和所述第一输出端导通，所述第二输入端和所述第二输出端导通；
当所述切换模块处于第二状态时，所述第一输入端和所述第二输出端导通，所述第二输入端和所述第一输出端导通。
在一种实施方式中，所述切换模块包括第一切换子模块和第二切换子模块；
所述第一切换子模块的第一端与所述第一输入端电连接，所述第一切换子模块的第二端与所述第二输入端电连接，所述第一切换子模块的第三端与所述第一输出端电连接，所述第一切换子模块的第四端与所述检测模块电连接；
所述第二切换子模块的第一端与所述第一输入端电连接，所述第二切换子模块的第二端与所述第二输入端电连接，所述第二切换子模块的第三端与所述第二输出端电连接，所述第二切换子模块的第四端与所述检测模块电连接；
当所述切换模块处于第一状态时，所述第一切换子模块的第一端和第三端导通，所述第二切换子模块的第二端和第三端导通；
当所述切换模块处于第二状态时，所述第一切换子模块的第二端和所述第三端导通，所述第二切换子模块的第一端和第三端导通。
在一种实施方式中，当所述串行数据端口通过总线用于接收串行数据信号，所述串行时钟端口通过总线用于接收串行时钟信号时，所述连接状态为 正连接，所述切换模块根据所述控制信号处于第一状态；
当所述串行数据端口通过所述总线用于接收所述串行时钟信号，所述串行时钟端口通过所述总线用于接收所述串行数据信号时，所述连接状态为反连接，所述切换模块根据所述控制信号处于第二状态。
在一种实施方式中，所述总线为I2C总线或I3C总线。
在一种实施方式中，所述自动跳线装置还包括电源端口和接地端口。
本申请一实施例提供一种通信设备，所述通信设备包括上述任一项所述的自动跳线装置。
在一种实施方式中，所述通信设备还包括从设备，所述从设备的串行数据端与所述自动跳线装置的串行数据输出端口电连接，所述从设备的串行时钟端与所述自动跳线装置的串行时钟输出端口电连接。
本申请提供的一种自动跳线装置及通信设备，其中自动跳线装置包括：串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口、检测模块和切换模块，检测模块与串行数据端口和串行时钟端口电连接，用于检测串行数据端口和串行时钟端口的连接状态，并向切换模块输出控制信号；切换模块与串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口电连接，切换模块根据控制信号在第一状态和第二状态之间切换；当切换模块处于第一状态时，串行数据端口和串行数据输出端口导通，串行时钟端口和串行时钟输出端口导通；当切换模块处于第二状态时，串行数据端口和串行时钟输出端口导通，串行时钟端口和串行数据输出端口导通。解决了现有技术中从设备的SDA接口与I2C总线电路中的SCL输出接口连接，从设备的SCL接口与I2C总线电路中的SDA输出接口连接时，从设备与主设备之间的通信将失败的问题，实现了自动对SCL接口和SDA接口检测，并根据检测结果自动调整从设备SCL接口和SDA接口与I2C总线的连接关系，使得从设备始终能够与主设备通信。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种实施例中SDA信号和SCL信号示意图；
图2为另一个实施例中SDA信号和SCL信号示意图；
图3为本申请一个实施例中通信设备的示意图；
图4为本申请一个实施例中检测模块的示意图；
图5为本申请一个实施例中切换模块的示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将一个元件与另一个元件区分。
需要说明的是，当一个元件被认为是“连接”另一个元件时，它可以是直接连接到另一个元件，或者通过居中元件连接另一个元件。此外，以下实施例中的“连接”，如果被连接的对象之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具 有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。
在I2C或I3C总线通信系统中，主设备通过串行数据总线和串行时钟总线与从设备进行通信。例如在I2C总线通信系统中，I2C启动条件定义为串行数据信号SDA由高位切换为低位时，串行时钟信号SCL为高位；I2C停止条件定义为串行数据信号SDA由低位切换为高位时，串行时钟信号SCL为高位。
在实际使用过程中，可能会发生总线被相互交换连接的情况，例如I2C串行数据总线和串行时钟总线相互交换，导致串行数据信号和串行时钟信号交换。此时，从设备的SDA端口接收串行时钟信号，从设备的SCL端口接收串行数据信号，使得从设备和主设备之间将无法正常通信。如图1所示，当串行时钟信号SCL和串行数据信号SDA没有交换时，启动条件会被触发。如图2所示，当串行时钟信号SCL和串行数据信号SDA被交换时，启动条件将不会被触发。
本申请提供一种自动跳线装置10，当总线被相互交换时，能够自动切换从设备与总线的连接，使得从设备的SDA端口能够接收串行数据信号，从设备的SCL端口能够接收串行时钟信号。
请参考图3，本申请提供的自动跳线装置10包括串行数据端口11、串行时钟端口12、串行数据输出端口13、串行时钟输出端口14、检测模块100和切换模块200。
串行数据端口11和串行时钟端口12可与总线电连接，串行数据输出端口13和串行时钟输出端口14与从设备300电连接。主设备400与总线电连接，且通过总线经过自动跳线装置10与从设备300进行通信。
检测模块100与串行数据端口11和串行时钟端口12电连接，用于检测串行数据端口11和串行时钟端口12的连接状态，并向切换模块200输出控制信号。串行数据端口11和串行时钟端口12的连接状态包括正接状态和反 接状态。
串行数据总线包括第一端和第二端，串行时钟总线也包括第一端和第二端。
当主设备400的SDA输出接口与串行数据总线的第一端电连接，串行数据端口11与串行数据总线的第二端电连接，主设备400的SCL输出接口与串行时钟总线的第一端电连接，串行时钟端口12与串行时钟总线的第二端电连接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为正接状态。
当主设备400的SDA输出接口与串行时钟总线的第一端电连接，串行数据端口11与串行时钟总线的第二端电连接，主设备400的SCL输出接口与串行数据总线的第一端电连接，串行时钟端口12与串行数据总线的第二端电连接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为正接状态。
即，当主设备400的SDA输出接口通过其中一条总线与串行数据端口11电连接，主设备400的SCL输出接口通过另一条总线与串行时钟端口12电连接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为正接状态。也就是说，当串行数据端口11通过其中一条总线能够接收到串行数据信号，串行时钟端口12通过另一条总线能够接收到串行时钟信号时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为正接状态。
当主设备400的SDA输出接口与串行时钟总线的第一端电连接，串行时钟端口12与串行时钟总线的第二端电连接，主设备400的SCL输出接口与串行数据总线的第一端电连接，串行数据端口11与串行数据总线的第二端电连接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为反接状态。
当主设备400的SDA输出接口与串行数据总线的第一端电连接，串行时钟端口12与串行数据总线的第二端电连接，主设备400的SCL输出接口与串行时钟总线的第一端电连接，串行数据端口11与串行时钟总线的第二端电连 接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为反接状态。
即，当主设备400的SDA输出接口通过其中一条总线与串行时钟端口12电连接，主设备400的SCL输出接口通过另一条总线与串行数据端口11电连接时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为反接状态。也就是说，当串行数据端口11通过其中一条总线能够接收到串行时钟信号，串行时钟端口12通过另一条总线能够接收到串行数据信号时，检测模块100判断串行数据端口11和串行时钟端口12的连接状态为反接状态。
检测模块100判断串行数据端口11和串行时钟端口12的连接状态，并根据连接状态向切换模块200输出控制信号。
切换模块200与串行数据端口11、串行时钟端口12、串行数据输出端口13、串行时钟输出端口14电连接，切换模块200根据控制信号在第一状态和第二状态之间切换。
当切换模块200处于第一状态时，串行数据端口11和串行数据输出端口13导通，串行时钟端口12和串行时钟输出端口14导通；当切换模块200处于第二状态时，串行数据端口11和串行时钟输出端口14导通，串行时钟端口12和串行数据输出端口13导通。
进一步的，当检测模块100检测到串行数据端口11、串行时钟端口12为正接状态时，检测模块100向切换模块200输出控制信号，使得切换模块200处于第一状态，主设备400的串行数据信号通过其中一条总线经过串行数据端口11和串行数据输出端口13输送到从设备300的串行数据端口；主设备400的串行时钟信号通过另一条总线经过串行时钟端口12和串行时钟输出端口14输送到从设备300的串行时钟端口。
当检测模块100检测到串行数据端口11和串行时钟端口12为反接状态时，检测模块100向切换模块200输出控制信号，使得切换模块200处于第二状态，主设备400的串行数据信号通过其中一条总线经过串行时钟端口12和串行数据输出端口13输送到从设备300的串行数据端口；主设备400的串 行时钟信号通过另一条总线经过串行数据端口11和串行时钟输出端口14输送到从设备300的串行时钟端口。
需要说明的一点是，在本申请实施例中，总线被互相交换连接通常有两种情况：
1、总线与从设备300的连接方式固定，主设备400与总线的连接交换。例如，主设备400的SDA输出接口与串行时钟总线的第一端电连接，主设备400的SCL输出接口与串行数据总线的第一端电连接。
2、主设备400与总线的连接固定，从设备300与总线的连接方式交换。例如，从设备300的串行数据端与串行时钟总线的第二端电连接，从设备300的串行时钟端与串行数据总线的第二端电连接。
通过设置上述自动跳线装置10，将从设备300的串行数据端和自动跳线装置的串行数据输出端口13电连接，将从设备300的串行时钟端和自动跳线装置的串行时钟输出端口14电连接，这样自动跳线装置10的串行数据端口11就相当于从设备300的串行数据端，自动跳线装置10的串行时钟端口12就相当于从设备300的串行时钟端。这样，在串行数据信号和串行时钟信号发生交换时，无论是自动跳线装置10与总线连接方式固定，主设备400与总线的连接交换；还是主设备400与总线的连接固定，自动跳线装置10的串行数据端口11和串行时钟端口12与总线的连接方式交换，自动跳线装置10均可根据串行数据端口11和串行时钟端口12的连接状态，自动将串行数据端口11和串行时钟端口12切换到正确的连接方式，使得从设备300的串行数据端能够接收串行数据信号，从设备300的串行时钟端能够接收串行时钟信号，以确保主设备400和从设备300之间能够顺利进行通信。
继续参考图3，在一种实施方式中，检测模块100具有第一检测端101、第二检测端102和控制信号输出端103。
检测模块100的第一检测端101与串行数据端口11电连接，检测模块100的第二检测端102与串行时钟端口12电连接，检测模块100的控制信号输出端103与切换模块200电连接，第一检测端101和第二检测端102用于 检测串行数据端口11和串行时钟端口12的连接状态，以判断串行数据端口11和串行时钟端口12处于正接状态还是反接状态。可选的，检测模块100通过检测总线的忙碌信号来判断串行数据端口11和串行时钟端口12处于正接状态还是反接状态。
进一步的，请参考图4，检测模块100包括：第一检测子模块110、第二检测子模块120和信号输出子模块130。第一检测子模块110的串行数据端111与第一检测端101电连接，第一检测子模块110的串行时钟端112与第二检测端102电连接，第一检测子模块110的输出端113与信号输出子模块130的第一信号输入端131电连接，向信号输出子模块130输出第一检测信号。
第二检测子模块120的串行数据端122与第二检测端102电连接，第二检测子模块120的串行时钟端121与第一检测端101电连接，第二检测子模块120的输出端123与信号输出子模块130的第二信号输入端132电连接，向信号输出子模块130输出第二检测信号。
信号输出子模块130接收第一检测信号和第二检测信号，并通过控制信号输出端133向切换模块200输出控制信号。
在本申请实施例中，第一检测子模块110和第二检测子模块120通过检测总线的忙碌信号来确定串行数据端口11和串行时钟端口12的连接状态。信号输出子模块130根据第一检测信号和第二检测信号生成控制信号，并向切换模块200输出该控制信号。具体的，当串行数据端口11和串行时钟端口12处于正接状态，说明串行数据信号和串行时钟信号没有被交换，那可生成控制信号0，并向切换模块200输出该控制信号。当串行数据端口11和串行时钟端口12处于反接状态，说明串行数据信号和串行时钟信号被交换，则生成控制信号1，并向切换模块200输出该控制信号。当切换模块200接收到控制信号0时，切换模块200保持第一状态；当切换模块200接收到控制信号1时，切换模块200切换至第二状态。
在一种实施方式中，请参考图3，切换模块200具有第一输入端201、第 二输入端202、第一输出端203和第二输出端204。
第一输入端201与串行数据端口11电连接，第二输入端202与串行时钟端口12电连接。第一输出端203与串行数据输出端口13电连接，第二输出端204与串行时钟输出端口14电连接。
当切换模块200处于第一状态时，第一输入端201和第一输出端203导通，第二输入端202和第二输出端204导通。此时，串行数据信号通过串行数据端口11、第一输入端201、第一输出端203、串行数据输出端口13输送到从设备300的串行数据端口；串行时钟信号通过串行时钟端口12、第二输入端202、第二输出端204、串行时钟输出端口14输送到从设备300的串行时钟端口。
当切换模块200处于第二状态时，第一输入端201和第二输出端204导通，第二输入端202和第一输出端203导通。此时，串行数据信号通过串行时钟端口12、第二输入端202、第一输出端203、串行数据输出端口13输送到从设备300的串行数据端口；串行时钟信号通过串行数据端口11、第一输入端201、第二输出端204、串行时钟输出端口14输送到从设备300的串行时钟端口。如此，当串行数据信号和串行时钟信号反接时，从设备300也能够正常工作。
进一步的，结合参考图5，切换模块200包括第一切换子模块210和第二切换子模块220。
第一切换子模块210的第一端211与第一输入端201电连接，第一切换子模块210的第二端212与第二输入端202电连接，第一切换子模块210的第三端213与第一输出端203电连接，第一切换子模块210的第四端214与检测模块100的控制信号输出端103电连接。
第二切换子模块220的第一端221与第一输入端201电连接，第二切换子模块220的第二端222与第二输入端202电连接，第二切换子模块220的第三端223与第二输出端204电连接，第二切换子模块220的第四端224与检测模块100的控制信号输出端103电连接。可选的，第一切换子模块210 和第二切换子模块220可以是多任务器multiplexer(MUX)，本申请对此不做限定。
当切换模块200处于第一状态时，第一切换子模块210的第一端211和第三端213导通，第二切换子模块220的第二端222和第三端223导通。此时，串行数据信号通过第一输入端201、第一切换子模块210的第一端211、第三端213和第一输出端203输送至从设备300的串行数据端口；串行时钟信号通过第二输入端202、第二切换子模块220的第二端222和第三端223、第二输出端204输送到从设备300的串行时钟端口。
当切换模块200处于第二状态时，第一切换子模块210的第二端212和第三端213导通，第二切换子模块220的第一端221和第三端223导通。此时，串行数据信号通过第二输入端202、第一切换子模块210的第二端212、第三端213和第一输出端203输送至从设备300的串行数据端口；串行时钟信号通过第一输入端201、第二切换子模块220的第一端221和第三端223、第二输出端204输送到从设备300的串行时钟端口。
可选的，当串行数据端口11通过其中一条总线与主设备400的串行数据输出接口电连接，串行时钟端口12通过另一条总线与主设备400的串行时钟输出接口电连接时，串行数据端口11和串行时钟端口12的连接状态为正向连接，切换模块200根据控制信号处于第一状态。当串行数据端口11通过其中一条总线与主设备400的串行时钟接口电连接，串行时钟端口12通过另一条总线与主设备400的串行数据接口电连接时，串行数据端口11和串行时钟端口12的连接状态为反向连接，切换模块200根据控制信号处于第二状态。
进一步的，在本申请实施例中，自动跳线装置10还包括电源端口(图中未示出)和接地端口(图中未示出)。
需要说明的一点是，本申请实施例中的自动跳线装置10可适用于I2C总线也可适用于I3C总线。
综上所述，当检测模块100检测到自动跳线装置10的串行数据端口11接收时钟信号，串行时钟端口12接收串行数据信号时，切换模块200切换至 第二状态，使得串行时钟信号通过串行数据端口11、第一输入端201、第二输出端204、串行时钟输出端口14输送到从设备300的串行时钟端口；串行数据信号通过串行时钟端口12、第二输入端202、第一输出端203、串行数据输出端口13输送到从设备300的串行数据端口，确保从设备300和主设备400能够正常通信。解决了现有技术中串行数据信号和串行时钟信号交换，导致从设备300无法正常工作的问题，使得在进行串行数据信号和串行时钟信号传输时，无需特别注意信号的传输路线，提高了设备的适配性，简化了设备连接方式。
本申请另一实施例提供一种通信设备，该通信设备包括上述自动跳线装置10和从设备300。从设备300的串行数据端与自动跳线装置10的串行数据输出端口13电连接，从设备300的串行时钟端与自动跳线装置的串行时钟输出端口14电连接。
需要说明的一点是，在本申请实施例中，自动跳线装置10可以独立于从设备300，作为一个连接主设备400和从设备300的独立装置。自动跳线装置10也可以集成于从设备300中，作为从设备300中的一个连接模块；这样，无论从设备300的串行数据端和串行时钟端与主设备400怎么连接，自动跳线装置10都能切换到正确的连接方式，以确保从设备300与主设备400的正常通信。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和易失性存储器中的至少一种。非易失性存储器可包括只读存储器(Read-Only Memory，ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory，RAM)或外部高速缓冲存储器。作为说明而非局限，RAM可以是多种形式，比如静态随机存取存储器(Static Random  Access Memory，SRAM)或动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种自动跳线装置，其特征在于，所述自动跳线装置包括：串行数据端口、串行时钟端口、串行数据输出端口、串行时钟输出端口、检测模块和切换模块；
    所述检测模块与所述串行数据端口和所述串行时钟端口电连接，用于检测所述串行数据端口和所述串行时钟端口的连接状态，并向所述切换模块输出控制信号；
    所述切换模块与所述串行数据端口、所述串行时钟端口、所述串行数据输出端口、所述串行时钟输出端口电连接，所述切换模块根据所述控制信号在第一状态和第二状态之间切换；
    当所述切换模块处于所述第一状态时，所述串行数据端口和所述串行数据输出端口导通，所述串行时钟端口和所述串行时钟输出端口导通；当所述切换模块处于第二状态时，所述串行数据端口和所述串行时钟输出端口导通，所述串行时钟端口和所述串行数据输出端口导通。
  2. 根据权利要求1所述的自动跳线装置，其特征在于，所述检测模块具有第一检测端、第二检测端和控制信号输出端；
    所述检测模块的第一检测端与所述串行数据端口电连接，所述检测模块的第二检测端与所述串行时钟端口电连接，所述检测模块的控制信号输出端与所述切换模块电连接，所述第一检测端和所述第二检测端用于检测所述串行数据端口和所述串行时钟端口的连接状态。
  3. 根据权利要求2所述的自动跳线装置，其特征在于，所述检测模块包括：第一检测子模块、第二检测子模块和信号输出子模块；
    所述第一检测子模块的串行数据端与所述第一检测端电连接，所述第一检测子模块的串行时钟端与所述第二检测端电连接，所述第一检测子模块的输出端与所述信号输出子模块的第一信号输入端电连接，向所述信号输出子模块输出第一检测信号；
    所述第二检测子模块的串行数据端与所述第二检测端电连接，所述第二检测子模块的串行时钟端与所述第一检测端电连接，所述第二检测子模块的输出端与所述信号输出子模块的第二信号输入端电连接，向所述信号输出子模块输出第二检测信号；
    所述信号输出子模块接收所述第一检测信号和所述第二检测信号，并通过所述控制信号输出端向所述切换模块输出控制信号。
  4. 根据权利要求1所述的自动跳线装置，其特征在于，所述切换模块具有第一输入端、第二输入端、第一输出端和第二输出端；
    所述第一输入端与所述串行数据端口电连接，所述第二输入端与所述串行时钟端口电连接；
    所述第一输出端与所述串行数据输出端口电连接，所述第二输出端与所述串行时钟输出端口电连接；
    当所述切换模块处于第一状态时，所述第一输入端和所述第一输出端导通，所述第二输入端和所述第二输出端导通；
    当所述切换模块处于第二状态时，所述第一输入端和所述第二输出端导通，所述第二输入端和所述第一输出端导通。
  5. 根据权利要求4所述的自动跳线装置，其特征在于，所述切换模块包括第一切换子模块和第二切换子模块；
    所述第一切换子模块的第一端与所述第一输入端电连接，所述第一切换子模块的第二端与所述第二输入端电连接，所述第一切换子模块的第三端与所述第一输出端电连接，所述第一切换子模块的第四端与所述检测模块电连接；
    所述第二切换子模块的第一端与所述第一输入端电连接，所述第二切换子模块的第二端与所述第二输入端电连接，所述第二切换子模块的第三端与所述第二输出端电连接，所述第二切换子模块的第四端与所述检测模块电连接；
    当所述切换模块处于第一状态时，所述第一切换子模块的第一端和第三端导通，所述第二切换子模块的第二端和第三端导通；
    当所述切换模块处于第二状态时，所述第一切换子模块的第二端和所述第三端导通，所述第二切换子模块的第一端和第三端导通。
  6. 根据权利要求1所述的自动跳线装置，其特征在于，当所述串行数据端口通过总线用于接收串行数据信号，所述串行时钟端口通过所述总线用于接收串行时钟信号时，所述连接状态为正连接，所述切换模块根据所述控制信号处于第一状态；
    当所述串行数据端口通过所述总线用于接收所述串行时钟信号，所述串行时钟端口通过所述总线用于接收所述串行数据信号时，所述连接状态为反连接，所述切换模块根据所述控制信号处于第二状态。
  7. 根据权利要求6所述的自动跳线装置，其特征在于，所述总线为I2C总线或I3C总线。
  8. 根据权利要求1所述的自动跳线装置，其特征在于，所述自动跳线装置还包括电源端口和接地端口。
  9. 一种通信设备，其特征在于，所述通信设备包括权利要求1至8任一项所述的自动跳线装置。
  10. 根据权利要求9所述的通信设备，其特征在于，所述通信设备还包括从设备，所述从设备的串行数据端与所述自动跳线装置的串行数据输出端口电连接，所述从设备的串行时钟端与所述自动跳线装置的串行时钟输出端口电连接。
PCT/CN2022/114245 2021-10-14 2022-08-23 自动跳线装置及通信设备 WO2023061052A1 (zh)

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