WO2023045046A1 - 无金欧姆接触电极、半导体器件和射频器件及其制法 - Google Patents

无金欧姆接触电极、半导体器件和射频器件及其制法 Download PDF

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WO2023045046A1
WO2023045046A1 PCT/CN2021/129681 CN2021129681W WO2023045046A1 WO 2023045046 A1 WO2023045046 A1 WO 2023045046A1 CN 2021129681 W CN2021129681 W CN 2021129681W WO 2023045046 A1 WO2023045046 A1 WO 2023045046A1
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layer
gate
gold
ohmic contact
epitaxial structure
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French (fr)
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蒋洋
汪青
于洪宇
郑韦志
杜方洲
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Southern University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • the present application relates to the field of radio frequency devices, in particular to a gold-free ohmic contact electrode, a semiconductor device, a radio frequency device and a manufacturing method thereof.
  • InAlN-based radio frequency devices have gradually emerged. It has a very wide range of applications in 5G, radar and millimeter wave communications.
  • the application provides a gold-free ohmic contact electrode, a semiconductor device, a radio frequency device and a manufacturing method thereof. This solution can partially or completely improve or even solve the problem of high on-resistance of InAlN radio frequency devices.
  • examples of the present application provide a gold-free ohmic contact electrode formed on an epitaxial structure of a semiconductor device.
  • Gold-free ohmic contact electrodes include:
  • the contact layer includes alloy structure, silicon-containing structure or metal structure with low work function.
  • the material of the metal cap layer includes TiN, Ti, Ta or W; and/or, the contact layer has any of the following limitations:
  • the alloy structure includes Ti x Al 1-x , Tax Al 1-x , Ti x AlySi 1-xy or Tax AlySi 1-xy ;
  • the silicon-containing structure includes Si/Ti/Al, Si/Ta/Al, Si/Ti x Al 1-x , Si/Tax Al 1-x arranged sequentially from the top surface or the top surface A silicon doped layer formed by doping silicon;
  • the metal structure containing low work function includes Sc/Ti/Al, Sc/Ta/Al, Sc/Ti x Al 1-x , Sc/Tax Al 1-x , Ti stacked in order from the top surface x AlySc 1-xy , Tax AlySc 1-xy , La/Ti/Al, La/Ta/Al, La/Ti x Al 1-x , La/Tax Al 1-x , Ti x AlyLa 1-xy or Tax AlyLa 1-xy .
  • the present application exemplarily proposes a semiconductor device having an epitaxial structure and a gold-free ohmic contact electrode as described above. Wherein, no gold ohmic contact electrodes are formed on the top surface of the epitaxial structure.
  • the semiconductor device is a power device or a radio frequency device; and/or, the semiconductor device includes an insulated gate field effect transistor, a HEMT device, an MIS-HEMT device, and an insulated gate HEMT device.
  • the gold-free ohmic contact electrode protrudes from the top surface or is at least partially embedded into the epitaxial structure from the top surface; and/or, the epitaxial structure has a gate groove, and the gate groove is recessed from the top surface, The gate is formed on the gate groove.
  • the epitaxial structure has a gate groove, and the gate groove is recessed from the top surface, the surface of the gate groove has a gate dielectric layer, and the gate is formed on the gate dielectric layer.
  • the present application exemplarily proposes a radio frequency device, which includes an epitaxial structure and the aforementioned gold-free ohmic contact electrode.
  • the epitaxial structure has a substrate, a buffer layer, a channel layer, an insertion layer and a barrier layer which are sequentially stacked; the barrier layers of the epitaxial structure are respectively formed with a source, a gate and a drain. Also, the source electrode and the drain electrode are independently selected from gold-free ohmic contact electrodes.
  • the radio frequency device has any one or two of the following limitations:
  • the gate is embedded in the barrier layer and directly contacts the insertion layer; or, the gate is embedded in the barrier layer and indirectly contacts the insertion layer through the gate dielectric layer.
  • the gate dielectric layer is an oxide layer formed by oxidation of part of the barrier layer and/or part of the insertion layer; or the gate dielectric layer is in-situ SiNx , deposited Al 2 O 3 , HfO 2 or SiN x ; or the gate dielectric layer is any one of HfO 2 , AlN and ZnO and the deposited Al 2 O 3 or a part of the barrier layer and/or a part of the insertion layer is formed by oxidation of a double layer of Al 2 O 3 structure; or the gate dielectric layer is a double-layer structure composed of in-situ SiN x or deposited SiN x and any one of HfO 2 , AlN and ZnO.
  • the thickness of the bilayer structure is 3nm to 10nm.
  • the source electrode and the drain electrode are respectively embedded in the barrier layer and are in direct contact with the insertion layer; or, the barrier layer has a groove that does not penetrate the insertion layer, and the gate and the drain electrode are respectively embedded in the barrier layer that does not penetrate the insertion layer. in the groove.
  • the substrate includes high resistance Si, sapphire, single crystal GaN, SiC, diamond, AlN, QST substrate.
  • the buffer layer includes AlGaN or GaN.
  • the channel layer includes GaN.
  • the insertion layer includes AlN; optionally, the AlN insertion layer has a thickness of 1 nm to 3 nm.
  • the barrier layer includes a single layer of InAlN, or InAlN/AlGaN, in-situ SiN/InAlN, in-situ SiN/InAlN/AlGaN, GaN cap layer/InAlN stacked sequentially from top to bottom until it contacts the insertion layer Or GaN cap layer/InAlN/AlGaN.
  • the in-situ SiN and GaN cap layers have a thickness of 1-3 nm respectively; or the thickness of In c Al 1-c N is 1 nm to 10 nm, wherein the value of c ranges from 0.1 to 0.2 ; or, the thickness of Al d Ga 1-d N is 1 nm to 5 nm, wherein the value of d ranges from 0.3 to 0.5.
  • the channel layer, the insertion layer, and the barrier layer form a heterojunction; and/or the channel layer, the insertion layer, and the barrier layer are etched together to form device isolation trenches.
  • the present application exemplarily proposes a method for manufacturing the aforementioned radio frequency device.
  • the method includes: providing an epitaxial structure; fabricating a source, a drain and a gate in an optional order, and one or both of the source and the drain are constructed in a gold-free ohmic contact electrode manner.
  • the barrier layer is etched with the insertion layer as an etch stop layer to forming a slot to accommodate either;
  • the etching method includes sequentially performing an oxidation step to form an oxide layer and a removal step to remove the oxide layer by chemical gas or chemical plasma etching.
  • the gold-free ohmic contact electrode provided by the embodiment of the present application has a lower ohmic contact resistance, so that the on-resistance of the semiconductor device fabricated based on it can be reduced.
  • Fig. 1 is a schematic structural diagram of a radio frequency device in the example of the present application.
  • Fig. 2 shows the schematic diagram of the epitaxial structure in the example of the present application
  • FIG. 3 shows a schematic structural diagram of isolation grooves formed on the basis of the epitaxial structure in FIG. 1;
  • FIG. 4 shows a schematic diagram of a structure in which source grooves and drain grooves are formed on the basis of the structure in FIG. 3;
  • FIG. 5 shows a schematic structural diagram of a source and a drain formed on the basis of the structure in FIG. 4;
  • FIG. 6 shows a schematic structural diagram of gate grooves formed on the basis of the structure in FIG. 5;
  • FIG. 7 shows a schematic structural diagram of a gate dielectric layer formed on the basis of the structure in FIG. 6;
  • FIG. 8 shows a schematic structural diagram of a radio frequency device with a gate formed on the basis of the structure in FIG. 7 .
  • Icons 101-substrate; 102-buffer layer; 103-channel layer; 104-insertion layer; 105-barrier layer; 106-gate dielectric layer; 107-two-dimensional electron gas; 108-isolation trench.
  • Ron on-resistance
  • R on represents the conduction resistance
  • R c represents the ohmic contact resistance
  • R sh represents the channel resistance
  • L sd represents the channel length. Therefore, adjusting each item in the previous formula can reduce the on-resistance of the device.
  • InAlN radio frequency devices A class of InAlN radio frequency devices that are currently being studied is InAlN HEMT (High Electron Mobility Transistor/High Electron Mobility Transistor).
  • InAlN/GaN heterojunction materials have the characteristics of large interfacial bandgap difference and strong spontaneous polarization, only a few nanometers thick ultra-thin barrier layer (ie InAlN) can make the device obtain a high carrier concentration. and electron mobility.
  • the high carrier concentration can not only effectively suppress the short channel effect caused by the scaling down of the device size, but also greatly reduce the parasitic channel resistance.
  • the InAlN barrier layer is lattice-matched with the GaN buffer layer, so there is no stress and piezoelectric polarization, which can greatly suppress the lattice mismatch and piezoelectric polarization.
  • the lattice defects can effectively prevent device failure caused by the inverse piezoelectric effect under high voltage.
  • InAlN/GaN HEMTs an important candidate for higher frequency and higher power applications of GaN devices.
  • the inventors have found in their research that the on-resistance can be reduced mainly through the following methods. For example, increasing the two-dimensional electron gas (2DEG) concentration of the channel from the epitaxial structure of the device to reduce the channel resistance of the epitaxial material, increasing the gate length per unit area in terms of device design, or reducing the contact of ohmic contact electrodes in terms of device technology resistance, etc.
  • 2DEG two-dimensional electron gas
  • ohmic contact electrodes are usually realized based on gold (Au).
  • Au is prone to thermal melting, and may react with other elements in the ohmic contact electrode to cause pilling, which in turn leads to roughening of the electrode surface, and thus may cause problems such as degradation of breakdown characteristics of the device.
  • Au is easy to cause pollution, and has defects such as high manufacturing cost and incompatibility with the existing Si CMOS process, so it is necessary to modify the ohmic contact electrode.
  • a solution for reducing the on-resistance of the device based on reducing the ohmic contact resistance (R c ) is proposed.
  • This solution mainly achieves the effect of reducing the ohmic contact resistance by improving the ohmic contact electrode structure of the device.
  • the inventor realized a gold-free ohmic contact electrode (no gold element; neither gold element nor its alloy/ie gold alloy, etc.).
  • the gold-free ohmic contact electrode can be used as the source electrode of the device, or as the drain electrode, or both (the specific electrode material composition can be different).
  • the gold-free ohmic contact electrodes in the example can be applied to various semiconductor devices.
  • the semiconductor devices therein may be, for example, various power devices in the field, or radio frequency devices.
  • the semiconductor device includes but is not limited to an insulated gate field effect transistor, a HEMT device, a MIS-HEMT device, an insulated gate type HEMT device, etc.; or the semiconductor device may also be other types of field effect transistors.
  • the gold-free ohmic contact electrodes in the example will be described in detail below.
  • the "and/or" involved in the descriptions in the examples means that they exist simultaneously or independently.
  • a and/or B means that A exists alone, or B exists alone, or A and B exist simultaneously.
  • the example gold-free ohmic contact electrode includes a contact layer and a metal cap layer.
  • the contact layer is stacked on the top surface of the epitaxial structure, and the metal cap layer is stacked on the contact layer.
  • the gold-free ohmic contact electrodes can be provided either in a protruding manner from the top surface of the epitaxial structure, or in a stacked manner from a recessed area on the top surface of the epitaxial structure.
  • the region where the gold-free ohmic contact electrode is in contact with the top surface of the epitaxial structure may be flush with other regions of the top surface; or, the contact region may also be recessed relative to other regions of the top surface ( That is, the top surface of the epitaxial structure is etched, such as a barrier layer recess).
  • the contact layer may include any one of alloy structure, silicon-containing structure, or low-work function metal-containing structure.
  • the alloy structure is such as titanium aluminum alloy ( Tix Al 1-x ), tantalum aluminum alloy ( Tax Al 1-x ), titanium aluminum silicon alloy ( Tix Al y Si 1-xy ) or tantalum aluminum silicon Alloy ( TaxAlySi1 -xy ).
  • the alloy layer and the metal cap layer can constitute an electrode with a double-layer alloy structure.
  • the silicon-containing structure may be, for example, a multilayer structure with simple silicon, or may also be a silicon-doped layer formed by doping the top surface of the epitaxial structure with silicon.
  • the multilayer structure with simple silicon is, for example, Si/Ti/Al, Si/Ta/Al, Si/ TixAl 1-x or Si/ TaxAl 1-x arranged sequentially from the top surface of the epitaxial structure. x .
  • the thin-layer structure containing metal with low work function can be an alloy material layer, and the number of layers can be one or more; or, the thin-layer structure containing metal with low work function can also be a layer of simple metal material, and the number of layers is multiple and at least The material of one layer is different from that of other layers; alternatively, the thin layer structure containing low work function metal can also be a stacked structure composed of a metal element material layer and an alloy material layer.
  • the thin-layer structure containing metal with low work function may be Sc/Ti/Al, Sc/Ta/Al, Sc/Ti x Al 1-x , Sc/ Tax Al 1-x , Ti x Al y Sc 1-xy , Tax Al y Sc 1-xy , La/Ti/Al, La/Ta/Al, La/Ti x Al 1-x , La / Tax Al 1-x , Ti x Al y La 1-xy or Tax Al y La 1-xy .
  • the A layer is a layer embedded in the groove of the barrier layer
  • the B layer is superimposed on it
  • the C layer is superimposed on the B layer of.
  • the cap layer is superimposed on C.
  • Metal work function refers to the minimum energy that must be provided to make an electron escape from the metal surface. Therefore, in the above description, the low work function metals mentioned in the examples of the present application refer to some metal materials whose work function is lower than that of Ti, Ta or Al metals, for example. Since, in the preparation process of the ohmic contact electrode, the first layer electrode in contact with the barrier layer is usually more critical, so the low work function metal in the examples of the present application is generally designated as the first layer metal, that is, the aforementioned A/ A floor in B/C format.
  • gold has a work function of 5.1eV
  • aluminum has a work function of 4.28eV
  • titanium has a work function of 4.33eV
  • tantalum Ta has a work function of 4.25eV.
  • the work function of Sc scandium used in the example of this application is 3.5 eV
  • the work function of La lanthanum is 3.5 eV.
  • metal cap layer in the electrode can be TiN, Ti, Ta or W, for example.
  • the above-mentioned gold-free ohmic contact electrodes are made as source and/or drain, and can be distributed on both sides of the gate.
  • the gate can be arranged on the top surface of the epitaxial structure, or can be embedded in the epitaxial structure.
  • the epitaxial structure may have a gate recess formed from the top surface; correspondingly, the gate is formed in the gate recess. That is, one end of the gate contacts into the gate groove, while the other end can optionally protrude out of the gate groove.
  • a gate dielectric layer on the surface of the gate groove.
  • the gate dielectric layer can cover the bottom surface of the gate groove, and can also cover the side surface of the gate groove.
  • the gate cooperates with the gate groove through the gate dielectric layer. That is, the gate is in contact with the gate dielectric layer, and the gate dielectric layer is in contact with the surface of the gate groove.
  • the inventor elaborates in detail the gold-free ohmic contact electrode in the example of the present application.
  • a radio frequency device is also proposed in the example of the present application, which includes an epitaxial structure and a gold-free ohmic contact electrode.
  • FIG. 1 for the structure of the radio frequency device, which is based on InAlN/GaN (indium aluminum nitride/gallium nitride) heterojunction material. Because the InAlN/GaN heterojunction material has a strong spontaneous polarization effect. With a thinner barrier layer (provided by InAlN), there is higher electron mobility, channel saturation current, etc. And a thin barrier layer is more conducive to reducing the short channel effect in radio frequency devices.
  • InAlN/GaN indium aluminum nitride/gallium nitride
  • the conduction of the radio-frequency device can also be reduced by selecting the heterojunction material of the radio-frequency device. resistance.
  • the epitaxial structure of a radio frequency device has a substrate 101 , a buffer layer 102 , a channel layer 103 (capable of forming 2DEG/two-dimensional electron gas 107 ), an insertion layer 104 and a barrier layer 105 which are sequentially stacked.
  • the channel layer, the insertion layer and the barrier layer are etched together to form device isolation trenches 108 for forming isolation between devices. In other words, when only a single device is fabricated, the device isolation trench 108 is not necessary.
  • the epitaxial structure of the radio frequency device has, for example, the following layered structure: Barrier Layer/AlN/GaN/Buffer Layer/Substrate.
  • the barrier layer can be either a single layer or a multilayer structure. Further, the barrier layer can be a single-layer or multi-layer structure made of one material. Alternatively, the barrier layer can also be a multilayer structure made of different materials; for the multilayer structure made of different materials, the material of each layer can be selected to be different.
  • the barrier layer may be a single layer of InAlN or a stacked structure of multiple layers of InAlN.
  • the barrier layer is a double or triple layer structure made of different materials.
  • in-situ means in-situ growth
  • cap means cap layer.
  • the writing order of the above-mentioned materials indicates the arrangement from high to low relative to the insertion layer as the reference .
  • InAlN/AlGaN means that in the example of the barrier layer, AlGaN is between InAlN and the insertion layer; while GaN cap/InAlN/AlGaN means that AlGaN is on the insertion layer, InAlN is on AlGaN, and GaN cap is on InAlN .
  • the thickness of the epitaxial structure can be controlled to meet functional requirements.
  • the thickness of the in-situ SiN and GaN cap layers can be, for example, 1-3nm (or 2nm, etc., although the thickness of an integer value is usually selected, but other thicknesses of 1nm to 3nm can also be made according to needs.
  • the thickness of InAlN is 1nm to 10nm (1nm or 2nm or 3nm or 4nm or 6nm or 8nm or 10nm, etc., usually choose the thickness of integer value, but can also make other 1nm to 10nm according to needs 10nm or other required thickness); alternatively, AlGaN has a thickness of 1nm to 5nm (2nm or 3nm or 4nm or 5nm, etc.).
  • the thickness of the insertion layer AlN may be 1-3 nm.
  • the composition of each layer in the epitaxial structure can also be controlled.
  • the composition content of In in InAlN may be 0.1-0.2
  • the composition content of Al may be 0.8-0.9.
  • the composition content of Al in AlGaN may be 0.3-0.5 (example may be 0.3, 0.4 or 0.5, etc.), and the composition content of Ga may be 0.5-0.7 (example may be 0.5, 0.6 or 0.7, etc.).
  • the epitaxial structure is realized by growing a multilayer structure on the substrate/substrate.
  • the substrate therein has an important influence on the quality of the epitaxial structure. Therefore it is necessary to choose the substrate material carefully.
  • Substrate can be high resistance Si, sapphire, GaN, diamond, AlN, QST substrate or SiC.
  • the QST substrate refers to a substrate technology proposed by Qromis, which can well match the thermal expansion and thus be used to grow high-quality GaN epitaxial layers.
  • the substrate/substrate can be selected as GaN single crystal, which can effectively reduce the defects of other layers grown on it (the dislocation density of InAlN grown on GaN is 5 ⁇ 10 6 cm 2 , compared to GaN The dislocation density of AlGaN grown on it is smaller than 5 ⁇ 10 8 cm 2 ), which can effectively prevent the current from flowing out from the epitaxial defects.
  • an AlGaN back barrier layer can also be added to the device to further reduce device leakage and increase device breakdown voltage.
  • the above-mentioned epitaxial structure of the present application can achieve reduced channel resistance (for example, 200 ⁇ / ⁇ ), and the surface roughness of the epitaxial material is better.
  • a source S, a gate G and a drain D are respectively formed on the top surface of the epitaxial structure of the radio frequency device.
  • the source electrode and the drain electrode are independently selected from any one of the above-mentioned gold-free ohmic contact electrodes.
  • the gate G can also be embedded into the barrier layer 105 through the gate dielectric layer 106 .
  • the source S, the gate G and the drain D of the radio frequency device are all embedded in the barrier layer 105 of the epitaxial structure (ie embedded in the top surface of the epitaxial structure).
  • the three can also be chosen not to be embedded in the barrier layer 105 , but to protrude from the surface of the barrier layer 105 .
  • the gate G can directly contact the insertion layer 104 through the groove of the barrier layer 105 ; or, as shown in FIG. 1 , can indirectly contact the insertion layer 104 through the gate dielectric layer 106 .
  • the inventors found that by selecting and regulating the gate dielectric, the leakage current of the gate can be suppressed and reduced. And such a scheme can be applied to MIS-HEMT devices.
  • other schemes can also be used to control the gate leakage current, for example, performing surface pretreatment on the gate region of the epitaxial structure.
  • the pretreatment may be surface pretreatment methods such as hydrogen peroxide sulfuric acid solution, ammonia solution, ozone and pre-sputtering.
  • the gate dielectric layer is mainly described as being located in the barrier layer; that is, the barrier layer has grooves and its surface covers the gate dielectric. But in other examples, the gate dielectric layer can also be located in the barrier layer and the insertion layer, that is, the barrier layer and the insertion layer have substantially aligned or aligned grooves, and the bottom surface of the groove of the insertion layer and the Both the side surface and the side surface of the groove of the buffer layer cover the gate dielectric. In an example, the gate dielectric layer also covers regions on the top surface of the barrier layer where the source and drain are located.
  • the gate dielectric layer may be an oxide layer formed by partially oxidizing the barrier layer (such as InAlN).
  • the gate dielectric layer may also be an oxide layer formed by oxidation of a part of the insertion layer. That is, an oxide is formed on the bottom surface and side surfaces of the groove by oxidation and used as a gate dielectric.
  • the gate dielectric layer may also be formed by "growing" a layer of dielectric material in the groove after etching to form the groove.
  • a layer of dielectric material for example, in-situ SiNx grown in the groove, deposited Al 2 O 3 , HfO 2 , or a single layer of SiNx ; its thickness may be 3nm to 10nm, for example.
  • the gate dielectric layer may also be a multilayer structure composed of different materials.
  • the gate dielectric layer is a double-layer structure composed of any one of HfO 2 , AlN and ZnO and deposited Al 2 O 3 .
  • the gate dielectric layer is a double-layer structure composed of any one of HfO 2 , AlN and ZnO and Al 2 O 3 formed by oxidation of a part of the barrier layer and/or a part of the insertion layer.
  • the gate dielectric layer may also be a double-layer structure composed of in-situ SiN x or deposited SiN x and any one of HfO 2 , AlN and ZnO.
  • the thickness of these multilayer structures may be, for example, 3 nm to 10 nm; for example, the thickness may also be 4 nm, 5 nm, 6 nm, 7 nm, or 8 nm or 9 nm, and so on.
  • the gate is embedded in the barrier layer by at least configuring a groove in the barrier layer. Therefore, by selecting an etching process to achieve precise etching, a normally-off/enhanced radio frequency device can be obtained.
  • the etching scheme is a novel self-stopping atomic layer etching scheme (such as ALE etching).
  • ALE etching atomic layer etching scheme
  • the self-stopping atomic layer etching scheme can be realized, for example, in the following manner:
  • a very thin (for example, 0.1 nm to 0.3 nm) oxide layer is formed by oxidation on the region to be etched, and then the oxide layer is removed.
  • the oxidation method therein may be oxidation using oxygen as an oxidizing agent.
  • oxygen not using oxygen plasma, which can reduce damage
  • chemical reagents such as BCl 3 or Cl 2 ; with gas or plasma The way to use
  • etching to remove the thin oxide layer on the surface, so as to achieve low speed, low damage and controllable depth of etching.
  • the etching scheme in the example of the present application hardly introduces plasma damage, so that the surface roughness of the etched sample can be reduced and the surface morphology can be improved.
  • the self-stop etching solution can also realize self-stop when the etching reaches the insertion layer (AlN), so it can realize accurate control of the etching depth.
  • this etching scheme can ensure that the barrier layer is completely etched, and at the same time, it can control not to etch or slightly etch the insertion layer.
  • this etching scheme also has the advantage of not introducing etching damage.
  • This etching scheme can not only realize the preparation of normally-off devices, but also help to reduce device gate leakage, improve device withstand voltage and threshold voltage, and reduce device on-resistance.
  • the circuit design can be optimized, the capacity loss can be reduced and the circuit can be protected.
  • this etching scheme is not only applicable to etching the gate region of the epitaxial structure, but also can be used to etch the source region and the drain region.
  • the source and drain regions of the barrier layer can also be etched using the aforementioned scheme to form a source trench and drain tank.
  • annealing can be performed at a lower temperature (500-700°C) to form an ohmic contact and realize low-temperature ohmic contact craft. Therefore, the process can reduce the influence of the high temperature in the annealing process on the epitaxial structure, so as to avoid affecting the reliability of the device. Further, when a gold-free ohmic contact electrode is used for the source and/or the drain, its performance can be better improved.
  • a depletion/enhancement device with low on-resistance, high saturation current, and low leakage current, such as a radio frequency device can be obtained.
  • the preparation method includes:
  • An epitaxial structure is provided, and then a source, a drain, and a gate are respectively fabricated on the epitaxial structure.
  • one or both of the source and the drain are constructed in a gold-free ohmic contact electrode manner.
  • the source, the drain and the gate can be implemented in any selected order. That is, the gate can be made first, and then the source and drain can be made, or the source and drain can be made first, and then the gate can be made, and so on. That is, source, drain and gate are fabricated in an optional order. In addition, in the example where the source, the drain and the gate need to be etched, all three can be etched first, and then the corresponding electrodes can be fabricated.
  • any one of the source, drain and gate when any one of the source, drain and gate is constructed by embedding or penetrating the barrier layer in the epitaxial structure, it can be made by making grooves, and then making electrode.
  • the way of making grooves is, for example: the insertion layer in the epitaxial structure is used as an etching stop layer, and the barrier layer is etched to form grooves for accommodating any of the above-mentioned electrodes.
  • the above-mentioned etching method includes an oxidation step of oxidation to form an oxide layer and a removal step of removing the oxide layer by chemical vapor etching, which are performed sequentially.
  • a fabrication process of a normally-off InAlN-based MIS-HEMT device includes the following steps performed in sequence.
  • the substrate was ultrasonically cleaned with acetone for 5 minutes, isopropanol for 10 minutes, deionized water for 10 minutes, and dried with nitrogen to remove impurities on the surface of the sample. Then, the epitaxial structure is manufactured, and the process can be various existing and known to the inventors in the semiconductor manufacturing process, such as chemical vapor deposition, atomic layer deposition and so on.
  • the following epitaxial structure is obtained by the above method, which includes InAlN/AlN/GaN/Buffer Layer/GaN substrates stacked sequentially from top to bottom (for example, 10nm In 0.17 Al 0.83 N/1nmAlN/1000nm GaN/300nm Buffer Layer /GaN substrate); the epitaxial structure is shown in Figure 2.
  • the steps of uniform coating, pre-baking, photolithography, development, and post-baking are performed in order to define the isolation pattern of the device.
  • step 3 Place the sample processed in step 2 in the transmission chamber of the ICP-RIE etching equipment, etch away the InAlN buffer layer/insertion layer AlN/GaN layer in the isolation part in the BCl 3 /Cl 2 etching gas, and etch
  • the etching depth is 300-500nm; its structure can be seen in Figure 3.
  • step 4 The sample etched in step 3 was ultrasonically cleaned with acetone for 5 minutes, isopropanol for 10 minutes, deionized water for 10 minutes, and dried with nitrogen.
  • step 5 Place the sample processed in step 5 in the ICP-ALE etching equipment for recess etching of the source and drain regions; see Figure 4 for its structure.
  • step 7 Put the sample processed in step 7 into the transmission chamber of the magnetron sputtering evaporation equipment immediately to avoid further oxidation of the sample and affect the ohmic contact effect.
  • Z/Y double-stack ohmic contact metals are vapor-deposited sequentially; see Figure 5 for its structure.
  • step 8 Submerge the ohmic metal vapor-deposited sample in step 8 in the dimethyl sulfoxide solution, and realize metal peeling by heating in a water bath at 60-80°C. After the stripping is completed, rinse with isopropanol for 10 minutes, deionized water for 10 minutes, and blow dry with nitrogen.
  • the annealing temperature can be set between 500-700°C in order to obtain a better ohmic contact effect.
  • the annealing scheme may be, for example, laser annealing, rapid thermal annealing, microwave annealing and the like.
  • the barrier layer is etched, and the electrodes are formed in the etched grooves.
  • step 10 The sample processed in step 10 is subjected to the steps of uniform glue, pre-baking, photolithography, development, and post-baking in order to define the gate etching area.
  • step 11 Place the sample processed in step 11 in the ICP-ALE etching equipment to perform recess etching of the gate area; refer to Figure 6 for its structure.
  • step 13 The sample etched in step 12 was ultrasonically cleaned with acetone for 5 minutes, isopropanol for 10 minutes, deionized water for 10 minutes, and dried with nitrogen.
  • step 13 Put the sample processed in step 13 into an atomic layer deposition device (ALD) to deposit a gate dielectric; its structure is shown in FIG. 7 .
  • ALD atomic layer deposition device
  • step 14 The sample processed in step 14 is subjected to the steps of uniform coating, pre-baking, photolithography, development, and post-baking in order to define the gate metal area.
  • step 16 Put the sample processed in step 15 into the electron beam evaporation equipment to deposit the gate metal; its structure refers to FIG. 8 .
  • step 17 Submerge the sample of the gate metal vapor-deposited in step 16 in the dimethyl sulfoxide solution, and realize metal peeling by heating in a water bath at 60-80°C. After the stripping is completed, rinse with isopropanol for 10 minutes, deionized water for 10 minutes, and blow dry with nitrogen.

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Abstract

一种无金欧姆接触电极、半导体器件和射频器件及其制法，属于射频器件领域。该形成于半导体器件的外延结构上的无金欧姆接触电极包括：接触层，堆叠于所述外延结构的顶表面；金属帽层，堆叠于所述接触层之上。其中，接触层包括合金结构、含硅结构或含低功函金属结构。该无金欧姆接触电极具有低的欧姆接触电阻，从而在基于其制作射频器件时，可以降低导通电阻，进而有助于获得输出功率的改善的效果。

Description

无金欧姆接触电极、半导体器件和射频器件及其制法
相关申请的交叉引用
本申请要求于2021年09月27日提交中国国家知识产权局的申请号为202111136252.3、名称为“无金欧姆接触电极、半导体器件和射频器件及其制法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及射频器件领域，具体而言，涉及一种无金欧姆接触电极、半导体器件和射频器件及其制法。
背景技术
近年来，基于InAlN的射频器件已逐渐崭露头角。其在5G、雷达以及毫米波通信方面有非常广泛的应用。
但是，目前基于InAlN的射频器件普遍存在诸如导通电阻过高的问题。
发明内容
本申请提供了一种无金欧姆接触电极、半导体器件和射频器件及其制法。该方案能够部分或全部地改善、甚至解决InAlN的射频器件导通电阻过高的问题。
本申请是这样实现的：
在第一方面，本申请的示例提供了一种形成于半导体器件的外延结构上的无金欧姆接触电极。
无金欧姆接触电极包括：
接触层，堆叠于外延结构的顶表面；
金属帽层，堆叠于接触层之上；
其中，接触层包括合金结构、含硅结构或含低功函金属结构。
根据本申请的一些示例，金属帽层的材料包括TiN、Ti、Ta或W；和/或，接触层具有以下任意一项的限定：
第一限定、合金结构包括Ti xAl 1-x、Ta xAl 1-x、Ti xAlySi 1-x-y或Ta xAlySi 1-x-y；
第二限定、含硅结构包括从顶表面依次叠层布置的Si/Ti/Al、Si/Ta/Al、Si/Ti xAl 1-x、Si/Ta xAl 1-x或对顶表面进行硅掺杂形成的硅掺杂层；
第三限定、含低功函金属结构包括从顶表面依次叠层布置的Sc/Ti/Al、Sc/Ta/Al、Sc/Ti xAl 1-x、Sc/Ta xAl 1-x、Ti xAlySc 1-x-y、Ta xAlySc 1-x-y、La/Ti/Al、La/Ta/Al、La/Ti xAl 1-x、La/Ta xAl 1-x、Ti xAlyLa 1-x-y或Ta xAlyLa 1-x-y。
在第二方面，本申请示例提出了一种半导体器件，其具有外延结构和如上述的无金欧 姆接触电极。其中，无金欧姆接触电极形成于外延结构的顶表面。
根据本申请的一些示例，半导体器件是功率器件或射频器件；和/或，半导体器件包括绝缘栅型场效应晶体管、HEMT器件、MIS-HEMT器件、绝缘栅型HEMT器件。
根据本申请的一些示例，无金欧姆接触电极从顶表面凸出设置或者至少部分从顶表面嵌入至外延结构中；和/或，外延结构具有栅凹槽，且栅凹槽从顶表面凹陷，栅极形成于栅凹槽之上。
可选地，外延结构具有栅凹槽，且栅凹槽从顶表面凹陷，栅凹槽的表面具有栅介质层，栅极形成于栅介质层之上。
在第三方面，本申请示例提出了一种射频器件，其包括外延结构和上述的无金欧姆接触电极。
其中的外延结构具有依次叠层设置的衬底、缓冲层、沟道层、插入层以及势垒层；外延结构的势垒层分别形成有源极、栅极以及漏极。并且，源极和漏极分别独立地选自无金欧姆接触电极。
根据本申请的一些示例，射频器件具有以下的任意一项或两项之限定：
第四限定、栅极嵌入至势垒层中与插入层直接接触；或者，栅极嵌入至势垒层中并通过栅介质层与插入层间接接触。
可选地，栅介质层是由势垒层的局部和/或插入层的局部通过氧化形成的氧化物层；或者栅介质层是原位SiN x、沉积的Al 2O 3、HfO 2或SiN x；或者栅介质层是HfO 2、AlN和ZnO中的任意一者与沉积的Al 2O 3或势垒层的局部和/或插入层的局部通过氧化形成的Al 2O 3构成的双层结构；或者栅介质层是原位SiN x或沉积的SiN x与HfO 2、AlN和ZnO中的任意一者构成的双层结构。
可选地双层结构的厚度为3nm至10nm。
第五限定、源极和漏极分别嵌入至势垒层中与插入层直接接触；或者，势垒层具有未贯穿至插入层的凹槽，栅极和漏极分别嵌入至未贯穿至插入层的凹槽内。
第六限定、衬底包括高阻Si、蓝宝石、单晶GaN、SiC、金刚石、AlN、QST衬底。
第七限定、缓冲层包括AlGaN或GaN。
第八限定、沟道层包括GaN。
第九限定、插入层包括AlN；可选地，AlN插入层的厚度为1nm至3nm。
第十限定、势垒层包括单层的InAlN，或从上至下依次叠层直至与插入层接触的InAlN/AlGaN、原位SiN/InAlN、原位SiN/InAlN/AlGaN、GaN帽层/InAlN或GaN帽层/InAlN/AlGaN。
可选地，在势垒层中，原位SiN和GaN帽层的厚度分别为1-3nm；或者In cAl 1-cN的厚 度为1nm至10nm，其中c的取值范围为0.1至0.2；或者，Al dGa 1-dN的厚度为1nm至5nm，其中d的取值范围为0.3至0.5。
根据本申请的一些示例，沟道层、插入层以及势垒层构成异质结；和/或沟道层、插入层以及势垒层一并被刻蚀形成器件隔离槽。
在本申请的第四方面，本申请示例提出了一种制作前述射频器件的方法。该方法包括：提供外延结构；以任选的顺序制作源极、漏极和栅极，且源极和漏极中的一者或两者采取无金欧姆接触电极方式进行构造。
根据本申请的一些示例，当源极、漏极和栅极中的任意一者采用嵌入或穿透势垒层方式进行构造时，以插入层为刻蚀停止层对势垒层进行刻蚀以形成容纳任意一者的槽；
可选地，刻蚀的方法包括顺序执行的氧化以形成氧化层的氧化步骤和通过化学气体或化学等离子体腐蚀去除氧化层的去除步骤。
在以上实现过程中，本申请实施例提供的无金欧姆接触电极具有更低的欧姆接触电阻，从而可以降低基于其所制作的半导体器件的导通电阻。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，以下将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为本申请示例中的一种射频器件的结构示意图；
图2示出了本申请示例中的外延结构的示意图；
图3示出了在图1外延结构的基础上形成了隔离槽的结构示意图；
图4示出了在图3结构的基础上形成了源极槽和漏极槽的结构示意图；
图5示出了在图4结构的基础上形成了源极和漏极的结构示意图；
图6示出了在图5结构的基础上形成了栅极槽的结构示意图；
图7示出了在图6结构的基础上形成了栅介质层的结构示意图；
图8示出了在图7结构的基础上形成了栅极的射频器件的结构示意图。
图标：101-衬底；102-缓冲层；103-沟道层；104-插入层；105-势垒层；106-栅介质层；107-二维电子气；108-隔离槽。
具体实施方式
就本申请发明人所知，在InAlN射频器件中，导通电阻(Ron)是直接影响器件性能的重要指标之一。例如，导通电阻过大会导致射频器件的输出功率密度降低，同时还会导致器件的发热量增大，进而会增加散热成本，甚至影响器件的可靠性和使用寿命。
一般地，在InAlN射频器件中，导通电阻的计算方法可以表述为R on＝2R c+R sh*L sd。该式中，R on表示导通电阻；R c表示欧姆接触电阻；R sh表示沟道电阻；L sd表示沟道长度。因此，针对前式中的各项进行调整，都可以降低器件的导通电阻。
目前研究的较多的一类InAlN射频器件，例如是InAlN HEMT(High Electron Mobility Transistor/高电子迁移率晶体管)。
由于InAlN/GaN异质结材料具有界面带隙差大和自发极化强的特点，因此，只需几纳米厚的超薄势垒层(即InAlN)就能使器件获得很高的载流子浓度和电子迁移率。而高的载流子浓度不仅可以有效地抑制由于器件尺寸等比例缩小所带来的短沟道效应，还能大幅降低寄生沟道电阻。
此外，当In组分含量为17％时，InAlN势垒层与GaN缓冲层晶格匹配，因此，无应力和压电极化的产生，从而可大幅抑制晶格失配和压电极化引起的晶格缺陷，进而有效防止高压下逆压电效应导致的器件失效。
这些特点使得InAlN/GaN HEMT成为GaN器件向更高频、更大功率应用的重要候选。
因此，有必要研究和降低这种基于InAlN/GaN异质结的器件的导通电阻。目前，发明人在研究中发现主要通过下述一些方式降低其导通电阻。例如，从器件的外延结构方面增加沟道的二维电子气(2DEG)浓度来降低外延材料的沟道电阻、在器件设计方面增加单位面积的栅长或者在器件工艺方面降低欧姆接触电极的接触电阻等。
在本申请的示例方案中，一个研究的重点之一就是改造欧姆接触电极。
就目前而言，欧姆接触电极通常都是基于金(Au)而实现的。
然而，金容易发生受热融化，还可能与欧姆接触电极中的其他元素反应导致起球，进而导致电极表面的粗糙化，并因此可能导致器件的诸如击穿特性下降等问题。并且，Au容易造成污染，并且存在制造成本较高、与现有的Si的COMS工艺不兼容等缺陷，所以有必要进行欧姆接触电极的改造。
在本申请示例中，提出了一种基于降低欧姆接触电阻(R c)的方式来降低器件导通电阻的方案。该方案主要通过对器件的欧姆接触电极结构进行改进，而达到降低欧姆接触电阻的效果。示例中，发明人实现了一种无金欧姆接触电极(未含金元素；既不含金单质，也不含其合金/即不含金合金等)。并且，无金欧姆接触电极可以被用于器件的源极电极，也可以是漏极电极，或者二者都采用(具体电极材料组成可以有所区别)。
大体上而言，示例中的无金欧姆接触电极可以适用于各种半导体器件。其中的半导体器件例如可以是本领域中的各种功率器件，也可以是射频器件。例如，该半导体器件包括但不限于绝缘栅型场效应晶体管、HEMT器件、MIS-HEMT器件、绝缘栅型HEMT器件等；或者半导体器件也可以是其他类型的场效应晶体管。
以下将就示例中的无金欧姆接触电极进行详述。示例中描述涉及的“和/或”，表示同时存在或独立存在。例如A和/或B，表示单独存在A，或单独存在B，或同时存在A、B。
示例中的无金欧姆接触电极包括接触层和金属帽层。
其中，接触层堆叠于外延结构的顶表面，而金属帽层则堆叠于接触层之上。需要指出的是，无金欧姆接触电极既可以是从外延结构的顶表面上以凸出的方式设置，也可以是从外延结构的顶表面的凹陷区域以层叠的方式设置。换言之，无金欧姆接触电极与外延结构的顶表面接触的区域可以是与顶表面的其他区域齐平；或者，该接触的区域也可以是相对于所述的顶表面的其他区域是凹陷的(即外延结构的顶表面进行了刻蚀，例如势垒层recess)。
在电极中，接触层可以包括合金结构、含硅结构或含低功函金属结构三者中的任意一种结构。
示例性地，合金结构例如是钛铝合金(Ti xAl 1-x)、钽铝合金(Ta xAl 1-x)、钛铝硅合金(Ti xAl ySi 1-x-y)或钽铝硅合金(Ta xAl ySi 1-x-y)。该合金层与金属帽层可以构成双层合金结构的电极。
含硅结构例如可以是具有硅单质的多层结构，或者也可以是通过对外延结构的顶表面进行硅掺杂形成的硅掺杂层。其中的具有硅单质的多层结构例如是从外延结构的顶表面依次叠层布置的Si/Ti/Al、Si/Ta/Al、Si/Ti xAl 1-x或Si/Ta xAl 1-x。
含低功函金属薄层结构可以是合金材料层，其层数可以是一个或多个；或者，含低功函金属薄层结构也可以是金属单质材料层，其层数为多层且至少存在一层与其他层的材料不同；或者，含低功函金属薄层结构也可以由金属单质材料层和合金材料层组合的叠层结构。
示例性地，例如含低功函金属薄层结构可以是从外延结构的顶表面上依次叠层布置的Sc/Ti/Al、Sc/Ta/Al、Sc/Ti xAl 1-x、Sc/Ta xAl 1-x、Ti xAl ySc 1-x-y、Ta xAl ySc 1-x-y、La/Ti/Al、La/Ta/Al、La/Ti xAl 1-x、La/Ta xAl 1-x、Ti xAl yLa 1-x-y或Ta xAl yLa 1-x-y。上述以A/B/C的形式表示的结构中，A层是嵌入到势垒层的凹槽内的一层，B层则是叠置在其上的，C层是叠置在B层上的。而帽层则叠置于C上。
金属功函数是指使一粒电子从金属表面中逸出，所必须提供的最小能量。因此，在以上的阐述中，本申请示例中所述的低功函金属例如是指功函低于Ti、Ta或者Al金属的功函数的一些金属材料。由于，在欧姆接触电极的制备工艺中，与势垒层接触的第一层电极通常是较关键的，所以本申请示例中的低功函数金属一般指定的是第一层金属，即前述A/B/C形式中的A层。例如，金的功函数为5.1eV，而铝的功函数为4.28eV，钛的功函数为4.33eV，钽Ta的功函数为4.25eV。本申请示例中使用的Sc钪的功函数为3.5eV、La镧的功函数为3.5eV。
而电极中的金属帽层例如可以是TiN、Ti、Ta或W。
在半导体器件中，上述的无金欧姆接触电极作为源极和/或漏极被制作，并可以分布于栅极的两侧。其中的栅极可以是设置于外延结构的顶表面之上，也可以是嵌入到外延结构中。换言之，部分示例中，外延结构可以具有从顶表面下陷/凹陷形成的栅凹槽；相应地，栅极则形成于栅凹槽内。即栅极的一端接触到栅凹槽内，而另一端则可以选择伸出到栅凹槽之外。
进一步地，在其他的一些实例中，栅凹槽的表面上还可以具有栅介质层。栅介质层可以覆盖于栅凹槽的底表面，还可以覆盖于栅凹槽的侧表面。栅极通过该栅介质层与栅凹槽配合。即栅极与栅介质层接触，而栅介质层则与栅凹槽的表面接触。
通过上文的描述，发明人详细地阐述了本申请示例中的无金欧姆接触电极。作为该无金欧姆接触电极的一种应用实例，在本申请的示例中还提出了一种射频器件，其包括外延结构和无金欧姆接触电极。
射频器件的结构参阅图1，其基于InAlN/GaN(铟铝氮/氮化镓)异质结材料。由于InAlN/GaN异质结材料具有强的自发极化效应。在较薄的势垒层(由InAlN提供)的情况下，具有更高的电子迁移率、沟道饱和电流等。并且薄的势垒层更有利于降低射频器件中的短沟道效应。因此，除了使用上述的无金欧姆接触电极可以降低射频器件的欧姆接触电阻，从而降低导通电阻之外，还可以通过对射频器件的异质结材料的选择等方式来降低射频器件的导通电阻。
参阅图1，射频器件的外延结构具有依次叠层设置的衬底101、缓冲层102、沟道层103(能够形成2DEG/二维电子气107)、插入层104以及势垒层105。另外，在图1的结构中，沟道层、插入层以及势垒层一并被刻蚀形成器件隔离槽108，用于在器件之间形成隔离。换言之，在仅仅制作单个器件时，该器件隔离槽108并不是必须的。
在本申请的一些示例中，射频器件的外延结构例如具有如下的层状结构：Barrier Layer/AlN/GaN/Buffer Layer/Substrate。
在前述结构中，势垒层(Barrier Layer)既可以是单层，也可以是多层结构。进一步地，势垒层可以是由一种材料制作的单层或多层结构。或者，势垒层也可以是由不同材料制作的多层结构；对于由不同材料制作的多层结构，其中的每层的材料可以选择为不同。
例如，势垒层可以是单层的InAlN或多层的InAlN的堆叠结构。
例如，势垒层是不同材料制作的双层或三层结构。示例性地，InAlN/AlGaN、in-situ SiN/InAlN、in-situ SiN/InAlN/AlGaN、GaN cap/InAlN、GaN cap/InAlN/AlGaN。其中的in-situ表示原位生长、cap表示帽层。此外，对于上述势垒层为多层且不同的材料制作的组合结构的上述示例，以插入层为基准，上述材料的撰写顺序表示的是相对于作为基准的插入层由 高至低的排布。例如，InAlN/AlGaN表示势垒层的示例中，AlGaN位于InAlN和插入层之间；而GaN cap/InAlN/AlGaN则表示，AlGaN位于插入层上，InAlN位于AlGaN之上，GaN cap位于InAlN之上。
部分示例中，可以对外延结构的厚度进行控制，以便满足功能需求。
例如，在势垒层中，in-situ SiN和GaN帽层的厚度例如可以为1-3nm(或者是2nm等等，虽然通常选择整数值的厚度，但是也可以根据需要制作其他1nm至3nm之间的或其他需要的厚度)；或者InAlN的厚度为1nm至10nm(1nm或2nm或3nm或4nm或6nm或8nm或10nm等等，通常选择整数值的厚度，但是也可以根据需要制作其他1nm至10nm之间的或其他需要的厚度)；或者，AlGaN的厚度为1nm至5nm(2nm或3nm或4nm或5nm等等)。
例如，插入层AlN的厚度则可以为1-3nm。
另外，还可对外延结构中的各层的成分进行控制。例如，InAlN中In的组分含量可以为0.1-0.2，Al的组分含量可以为0.8-0.9。AlGaN中Al的组分含量可以为0.3-0.5(示例性可以是0.3、0.4或0.5等)，Ga的组分含量可以为0.5-0.7(示例性可以是0.5、0.6或0.7等)。
由于外延结构是在衬底/基板上生长多层结构而实现。其中的衬底对外延结构的质量有重要的影响。因此有必要慎重地选择衬底材料。例如，Substrate可以为高阻Si、蓝宝石、GaN、金刚石、AlN、QST衬底或SiC。其中QST衬底是指Qromis公司提出的一种衬底技术，其能够很好地匹配热膨胀性，从而被用于生长高质量的GaN外延层。
或者，其中的substrate/衬底可以选择为GaN单晶，其能够有效降低在其上外延生长的其他层的缺陷(GaN上生长InAlN的位错密度在5×10 6cm 2，相比于GaN上生长AlGaN的位错密度为5×10 8cm 2要小)，可以有效避免电流从外延缺陷中流出。并且在GaN单晶衬底方案的基础上，还可以在器件中增加AlGaN背势垒层来进一步降低器件漏电，提升器件击穿电压。
相比于传统AlGaN/GaN的异质结外延结构，通过采用本申请的上述形式的外延结构可以实现降低的沟道电阻(例如200Ω/□)，并且，且外延材料表面粗糙度较好。
在射频器件的外延结构的顶表面上分别形成有源极S、栅极G以及漏极D。其中，源极和漏极分别独立地选自上述的任意一种无金欧姆接触电极。进一步地，该栅极G还可通过栅介质层106而嵌入到势垒层105中。
在图1中，射频器件的源极S、栅极G以及漏极D均嵌入到外延结构的势垒层105内(即嵌入到外延结构的顶表面内)。但是，三者也可以选择不嵌入到势垒层105内，而是从势垒层105的表面凸出地延伸布置。另外，其中的栅极G既可以通过势垒层105的凹槽与插入层104直接接触；或者也可以如图1所示，通过栅介质层106与插入层104间接接触。
特别地，发明人发现通过对栅介质的选择和调控，可以对栅极的漏电流起到抑制和降低的效果。并且这样的方案可以适用于MIS-HEMT器件。除了调控栅介质之外，其他一些方案也可以被用于控制栅极漏电流，例如，对外延结构的栅极区域进行表面预处理。其中的预处理可以是使用硫酸双氧水溶液、氨基溶液、臭氧与预溅射等表面预处理方法。
上述示例中，栅介质层主要被描述位于势垒层中；即，势垒层具有凹槽，且其表面覆盖栅介质。但是在其他的示例中，栅介质层也可以是位于势垒层和插入层中，即势垒层和插入层具有基本上对准或对齐的凹槽，且插入层的凹槽的底表面和侧表面以及缓冲层的凹槽的侧表面均覆盖栅介质。示例中，栅介质层还覆盖到势垒层的顶表面的位于源极和漏极的区域。
因此，一些情况下，栅介质层可以是通过将势垒层(如InAlN)的局部通过氧化形成的氧化物层。或者，栅介质层也可以是将插入层的局部通过氧化形成的氧化物层。即在凹槽的底表面和侧表面通过氧化形成氧化物并将其作为栅介质。
或者，栅介质层也可以是在刻蚀形成凹槽之后，在凹槽中“生长”一层介质材料构成栅介质层。例如，在凹槽中生长的原位SiN x、沉积的Al 2O 3、HfO 2或SiN x等单层材料；其厚度例如可以是3nm至10nm。
或者栅介质层还可以是不同的材料组成的多层结构。例如栅介质层是由HfO 2、AlN和ZnO中的任意一者与沉积的Al 2O 3构成的双层结构。或者，栅介质层是由HfO 2、AlN和ZnO中的任意一者与势垒层的局部和/或插入层的局部通过氧化形成的Al 2O 3构成的双层结构。
或者栅介质层还可以是原位SiN x或沉积的SiN x，与HfO 2、AlN和ZnO中的任意一者构成的双层结构。这些多层结构的厚度例如可以为3nm至10nm；示例性地，厚度也可以是4nm、5nm、6nm、7nm或8nm或9nm等等。
除此之外，需要指出的，在本申请示例的射频器件结构中，栅极通过至少在势垒层中配制凹槽而嵌入到势垒层中。因此，通过对刻蚀工艺的选择以达到精准刻蚀，从而可以实现获得常关型/增强型的射频器件。
示例中，该刻蚀方案是一种新型的可自停止的原子层刻蚀方案(如ALE刻蚀)。通过对外延结构的顶部的对应于需要制作栅极的区域进行刻蚀，精确地控制刻蚀的深度，从而获得更精确的深度的槽(recess)，进而可以使栅极区域的二维电子气被耗尽而实现常关型器件。
该可自停止的原子层刻蚀方案例如可以通过下述方式实现：
对需要进行刻蚀的区域通过氧化的方式形成很薄(例如0.1nm至0.3nm)的氧化层，然后将该氧化层去除。其中的氧化方法可以是使用氧气作为氧化剂进行氧化。当外延层的顶表面是InAlN势垒层时，则可以通过使用氧气(不使用氧等离子体，从而可以减少损伤) 进行氧化，然后再通过化学试剂(如BCl 3或Cl 2；以气体或等离子的方式使用)刻蚀，以去除表面的薄的氧化层，从而实现低速、低损伤和可控深度的刻蚀。
相比于传统的ICP刻蚀方案，本申请示例中的该刻蚀方案几乎不会引入等离子体损伤，从而可以降低刻蚀后的样品的表面的粗糙度，提高表面形貌。并且，该自停止刻蚀方案还能够实现在刻蚀达到插入层(AlN)时自停止，因此可以实现准确控制刻蚀深度。简言之，该刻蚀方案能够确保将势垒层刻蚀尽，同时也可以控制不对插入层进行刻蚀或进行轻微的刻蚀。并且，该刻蚀方案还具有不引入刻蚀损伤的优点。
该刻蚀方案不仅能够实现常关型器件的制备，还有助于降低器件栅极漏电、提高器件耐压和阈值电压、降低器件导通电阻等。另外，由于实现了常关型的器件，从而可以优化电路设计、降低能力损耗和保护电路。
需要指出的是，该刻蚀方案不仅适用于对外延结构的栅极区域进行刻蚀，还可以用来对源极区域和漏极区域进行刻蚀。换言之，当源极和漏极以插入到器件的顶部的势垒层如InAlN层中时，该势垒层的源极区域和漏极区域也可以采用前述方案进行刻蚀，从而形成源极槽和漏极槽。
此外，在使用该方案进行源极槽和漏极槽的刻蚀，并且在制作源极和漏极后，可以在较低温度(500-700℃)下进行退火，形成欧姆接触，实现低温欧姆接触工艺。由此，该工艺可以减少退火工艺中温度过高对外延结构产生的影响，从而避免影响器件的可靠性。进一步地，当源极和/或漏极使用无金欧姆接触电极时，可以更好地改善其性能。
综上所述，通过上述方案的实施，在本申请的示例中可以获得一种具有低的导通电阻、高饱和电流、低的漏电流的耗尽型/增强型器件，例如是射频器件。
为了使本领域技术人员能够更易于实施本申请的方案，示例中还提出了一种射频器件的制备方法。该制备方法包括：
提供外延结构，然后在外延结构上分别制作源极、漏极以及栅极。
作为该射频器件的其中一个通过对可选的结构的优化而实现的优点，其源极和漏极中的一者或两者采取无金欧姆接触电极方式进行构造。
其中，源极、漏极和栅极可以是以任意选择的顺序进行实施。即可以先制作栅极，然后再制作源极和漏极，或者先制作源极和漏极，再制作栅极等等。即任选的顺序制作源极、漏极和栅极。另外，制作源极、漏极以及栅极且需要进行刻蚀的示例中，可以先将三者都进行刻蚀，然后再制作对应的电极。
进一步地，在制作过程中，当源极、漏极和栅极中的任意一者采用嵌入或穿透外延结构中的势垒层的方式进行构造时，可以通过制槽，再于槽中制电极。其中的制槽方式例如是：以外延结构中的插入层为刻蚀停止层，对势垒层进行刻蚀以形成容纳上述任意电极的 槽。作为一种可选的方案，上述的刻蚀的方法包括顺序执行的氧化以形成氧化层的氧化步骤和通过化学气相腐蚀去除氧化层的去除步骤。
下面将结合实施例对本申请的实施方案进行详细描述，但是本领域技术人员将会理解，下列实施例仅用于说明本申请，而不应视为限制本申请的范围。实施例中未注明具体条件者，按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者，均为可以通过市售购买获得的常规产品。
示例中，制备方法被阐述如下。
一种常关型的基于InAlN的MIS-HEMT器件的制备工艺包括以下顺序执行的步骤。
1.将基底依次经过丙酮超声清洗5min，异丙醇超声清洗10min，去离子水冲洗10min，氮气吹干，去除样品表面杂质。然后进行外延结构的制作，其工艺可以是半导体制程中的各种既有和发明人所知晓的各种工艺，例如化学气相沉积、原子层沉积等等。
通过上述方式获得如下的外延结构，其包括从上至下依次堆叠的InAlN/AlN/GaN/Buffer Layer/GaN衬底(示例性地，10nm In 0.17Al 0.83N/1nmAlN/1000nm GaN/300nm Buffer Layer/GaN衬底)；外延结构参阅图2所示。
2.在清洗好的外延结构样品上依次进行匀胶，前烘，光刻，显影，后烘等步骤，定义器件的隔离图形。
3.将步骤2处理好的样品放置于ICP-RIE刻蚀设备的传输腔中，在BCl 3/Cl 2刻蚀气体中刻蚀掉隔离部分的InAlN缓冲层/插入层AlN/GaN层，刻蚀深度为300-500nm；其结构可以参阅图3。
4.将步骤3中刻蚀后的样品依次经过丙酮超声清洗5min，异丙醇超声清洗10min，去离子水冲洗10min，氮气吹干。
5.在清洗好的样品上依次进行匀胶，前烘，光刻，显影，后烘等步骤，定义源极和漏极的欧姆接触图形。
6.将步骤5处理好的样品放置于ICP-ALE刻蚀设备中，进行源漏区域的recess刻蚀；其结构参阅图4。
7.将步骤6处理好的样品浸没于稀释的盐酸溶液(HCl：H 2O＝1：4)中3min去除样品表面的自然氧化层，然后用去离子水冲洗15min，最后氮气吹干。
8.将步骤7处理好的样品立即放入磁控溅射蒸镀设备传输腔，避免样品进一步氧化，影响欧姆接触效果。镀膜工艺中，依次蒸镀Z/Y双叠层欧姆接触金属；其结构参阅图5。
9.将步骤8蒸镀好欧姆金属的样品浸没于二甲基亚砜溶液中，通过60-80℃的水浴加热方式实现金属剥离。剥离完成后，依次经过异丙醇冲洗10min，去离子水冲洗10min，氮气吹干。
10.对金属剥离后的样品在N 2或H 2氛围中进行热退火，退火温度可设置在500-700℃之间，以便得到较好的欧姆接触效果。其中的退火方案，例如可以是激光退火、快速热退火、微波退火等。在前述步骤中是通过对势垒层进行刻蚀，在于刻蚀的槽中制作电极。在另一些示例中，也可以选择不对外延结构的顶表面的势垒层进行刻蚀的情况下，而是在顶表面之上制作无金欧姆接触电极，然后再结合退火实现低的欧姆接触电阻(如0.1-0.3Ω·mm)。
11.将步骤10处理好的样品依次进行匀胶，前烘，光刻，显影，后烘等步骤，定义栅极刻蚀区域。
12.将步骤11处理好的样品放置于ICP-ALE刻蚀设备中，进行栅极区域的recess刻蚀；其结构参阅图6。
13.将步骤12中刻蚀后样品依次经过丙酮超声清洗5min，异丙醇超声清洗10min，去离子水冲洗10min，氮气吹干。
14.将步骤13中处理后样品放入原子层沉积设备(ALD)中进行栅介质的沉积；其结构如图7所示。
15.将步骤14处理好的样品依次进行匀胶，前烘，光刻，显影，后烘等步骤，定义栅极金属区域。
16.将步骤15处理好的样品放入电子束蒸镀设备中沉积栅极金属；其结构参阅图8。
17.将步骤16蒸镀好栅极金属的样品浸没于二甲基亚砜溶液中，通过60-80℃的水浴加热方式实现金属剥离。剥离完成后，依次经过异丙醇冲洗10min，去离子水冲洗10min，氮气吹干。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种无金欧姆接触电极，形成于半导体器件的外延结构上，其特征在于，所述无金欧姆接触电极包括：
    接触层，堆叠于所述外延结构的顶表面；
    金属帽层，堆叠于所述接触层之上；
    其中，所述接触层包括合金结构、含硅结构或含低功函金属结构。
  2. 根据权利要求1所述的无金欧姆接触电极，其特征在于，所述金属帽层的材料包括TiN、Ti、Ta或W；
    和/或，所述接触层具有以下任意一项的限定：
    第一限定、所述合金结构包括Ti xAl 1-x、Ta xAl 1-x、Ti xAl ySi 1-x-y或Ta xAl ySi 1-x-y；
    第二限定、所述含硅结构包括从所述顶表面依次叠层布置的Si/Ti/Al、Si/Ta/Al、Si/Ti xAl 1-x、Si/Ta xAl 1-x或对所述顶表面进行硅掺杂形成的硅掺杂层；
    第三限定、所述含低功函金属结构包括从所述顶表面依次叠层布置的Sc/Ti/Al、Sc/Ta/Al、Sc/Ti xAl 1-x、Sc/Ta xAl 1-x、Ti xAl ySc 1-x-y、Ta xAl ySc 1-x-y、La/Ti/Al、La/Ta/Al、La/Ti xAl 1-x、La/Ta xAl 1-x、Ti xAl yLa 1-x-y或Ta xAl yLa 1-x-y。
  3. 一种半导体器件，其特征在于，具有外延结构、如权利要求1或2所述的无金欧姆接触电极，所述无金欧姆接触电极形成于所述外延结构的顶表面。
  4. 根据权利要求3所述的半导体器件，其特征在于，所述半导体器件是功率器件或射频器件；
    和/或，所述半导体器件包括绝缘栅型场效应晶体管、HEMT器件、MIS-HEMT器件或绝缘栅型HEMT器件。
  5. 根据权利要求3或4所述的半导体器件，其特征在于，所述无金欧姆接触电极从所述顶表面凸出设置或者至少部分从所述顶表面嵌入至所述外延结构中；
    和/或，所述外延结构具有栅凹槽，且所述栅凹槽从所述顶表面凹陷，栅极形成于所述栅凹槽之上；
    可选地，所述外延结构具有栅凹槽，且所述栅凹槽从所述顶表面凹陷，所述栅凹槽的表面具有栅介质层，栅极形成于所述栅介质层之上。
  6. 一种射频器件，其特征在于，包括外延结构和根据权利要求1或2所述的无金欧姆接触电极；
    所述外延结构具有依次叠层设置的衬底、缓冲层、沟道层、插入层以及势垒层；所述外延结构的势垒层分别形成有源极、栅极以及漏极，其中，所述源极和所述漏极分别独立地选自所述无金欧姆接触电极。
  7. 根据权利要求6所述的射频器件，其特征在于，所述射频器件具有以下的任意一项或两项之限定：
    第四限定、所述栅极嵌入至所述势垒层中与所述插入层直接接触；或者，所述栅极嵌入至所述势垒层中并通过栅介质层与所述插入层间接接触；
    可选地，所述栅介质层是由所述势垒层的局部和/或所述插入层的局部通过氧化形成的氧化物层；或者所述栅介质层是原位SiN x、沉积的Al 2O 3、HfO 2或SiN x；或者所述栅介质层是HfO 2、AlN和ZnO中的任意一者与沉积的Al 2O 3或所述势垒层的局部和/或所述插入层的局部通过氧化形成的Al 2O 3构成的双层结构；或者所述栅介质层是原位SiN x或沉积的SiN x与HfO 2、AlN和ZnO中的任意一者构成的双层结构；
    可选地所述双层结构的厚度为3nm至10nm；
    第五限定、所述源极和所述漏极分别嵌入至所述势垒层中与所述插入层直接接触；或者，所述势垒层具有未贯穿至所述插入层的凹槽，所述栅极和所述漏极分别嵌入至未贯穿至所述插入层的凹槽内；
    第六限定、所述衬底包括高阻Si、蓝宝石、单晶GaN、SiC、金刚石、AlN、QST衬底；
    第七限定、所述缓冲层包括AlGaN或GaN；
    第八限定、所述沟道层包括GaN；
    第九限定、所述插入层包括AlN，可选地，AlN插入层的厚度为1nm至3nm；
    第十限定、所述势垒层包括单层的InAlN，或从上至下依次叠层直至与所述插入层接触的InAlN/AlGaN、原位SiN/InAlN、原位SiN/InAlN/AlGaN、GaN帽层/InAlN或GaN帽层/InAlN/AlGaN；
    可选地，在所述势垒层中，原位SiN和GaN帽层的厚度分别为1-3nm；或者In cAl 1-cN的厚度为1nm至10nm，其中c的取值范围为0.1至0.2；或者，Al dGa 1-dN的厚度为1nm至5nm，其中d的取值范围为0.3至0.5。
  8. 根据权利要求6或7所述的射频器件，其特征在于，所述沟道层、插入层以及势垒层构成异质结；和/或所述沟道层、插入层以及势垒层一并被刻蚀形成器件隔离槽。
  9. 一种制作根据权利要求6或7或8所述的射频器件的方法，其特征在于，所述方法包括：提供所述外延结构；以任选的顺序制作源极、漏极和栅极，且所述源极和所述漏极中的一者或两者采取所述无金欧姆接触电极方式进行构造。
  10. 根据权利要求9所述的方法，其特征在于，当所述源极、所述漏极和所述栅极中的任意一者采用嵌入或穿透所述势垒层方式进行构造时，以所述插入层为刻蚀停止层对所述势垒层进行刻蚀以形成容纳所述任意一者的槽；
    可选地，所述刻蚀的方法包括顺序执行的氧化以形成氧化层的氧化步骤和通过化学气 体或化学等离子体腐蚀去除所述氧化层的去除步骤。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118016689A (zh) * 2024-01-15 2024-05-10 湖北九峰山实验室 一种无沟道耦合效应的GaN多沟道结构及GaN HEMT器件
CN119922961A (zh) * 2024-12-30 2025-05-02 西安电子科技大学 一种非对称工艺单刀双掷射频开关器件及其制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116994954B (zh) * 2023-09-26 2023-12-26 贵州芯际探索科技有限公司 一种igbt沟槽栅的排布方法及排布结构
CN117810253B (zh) * 2024-02-23 2024-06-07 深圳天狼芯半导体有限公司 双栅hemt器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1802728A (zh) * 2003-07-16 2006-07-12 昭和电工株式会社 用于n型Ⅲ族氮化物半导体的n型欧姆电极、具有该电极的半导体发光器件及用于形成n型欧姆电极的方法
JP2007081103A (ja) * 2005-09-14 2007-03-29 Fujitsu Ltd 半導体装置
US20140346568A1 (en) * 2013-05-22 2014-11-27 Imec Low Temperature Ohmic Contacts for III-N Power Devices
CN111640797A (zh) * 2020-06-02 2020-09-08 南方科技大学 半导体器件的制作方法
CN112670337A (zh) * 2020-12-11 2021-04-16 中山市华南理工大学现代产业技术研究院 基于Ti/Ti-Al/Cu-W的GaN基HEMT无金欧姆接触电极及其制备方法
CN112864242A (zh) * 2020-12-30 2021-05-28 南方科技大学 一种GaN器件及其制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4858791B2 (ja) * 2009-05-22 2012-01-18 住友電気工業株式会社 半導体装置およびその製造方法
US8466555B2 (en) * 2011-06-03 2013-06-18 Raytheon Company Gold-free ohmic contacts
CN109742021B (zh) * 2018-12-26 2021-09-28 芜湖启迪半导体有限公司 一种氮化镓基欧姆接触结构及其制备方法
CN110797397A (zh) * 2019-11-12 2020-02-14 南方科技大学 一种AlGaN/GaN欧姆接触电极及其制备方法和用途
CN112820774A (zh) * 2020-12-30 2021-05-18 南方科技大学 一种GaN器件及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1802728A (zh) * 2003-07-16 2006-07-12 昭和电工株式会社 用于n型Ⅲ族氮化物半导体的n型欧姆电极、具有该电极的半导体发光器件及用于形成n型欧姆电极的方法
JP2007081103A (ja) * 2005-09-14 2007-03-29 Fujitsu Ltd 半導体装置
US20140346568A1 (en) * 2013-05-22 2014-11-27 Imec Low Temperature Ohmic Contacts for III-N Power Devices
CN111640797A (zh) * 2020-06-02 2020-09-08 南方科技大学 半导体器件的制作方法
CN112670337A (zh) * 2020-12-11 2021-04-16 中山市华南理工大学现代产业技术研究院 基于Ti/Ti-Al/Cu-W的GaN基HEMT无金欧姆接触电极及其制备方法
CN112864242A (zh) * 2020-12-30 2021-05-28 南方科技大学 一种GaN器件及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118016689A (zh) * 2024-01-15 2024-05-10 湖北九峰山实验室 一种无沟道耦合效应的GaN多沟道结构及GaN HEMT器件
CN119922961A (zh) * 2024-12-30 2025-05-02 西安电子科技大学 一种非对称工艺单刀双掷射频开关器件及其制备方法

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