WO2023029020A1 - 显示面板和电子设备 - Google Patents

显示面板和电子设备 Download PDF

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Publication number
WO2023029020A1
WO2023029020A1 PCT/CN2021/116583 CN2021116583W WO2023029020A1 WO 2023029020 A1 WO2023029020 A1 WO 2023029020A1 CN 2021116583 W CN2021116583 W CN 2021116583W WO 2023029020 A1 WO2023029020 A1 WO 2023029020A1
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WO
WIPO (PCT)
Prior art keywords
voltage
display
refresh mode
compensation
display panel
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PCT/CN2021/116583
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English (en)
French (fr)
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WO2023029020A9 (zh
Inventor
胡崇淋
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2023029020A1 publication Critical patent/WO2023029020A1/zh
Publication of WO2023029020A9 publication Critical patent/WO2023029020A9/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and electronic equipment.
  • Timing controllers support the variable refresh rate (Varied refresh rate, VRR) function, that is, by changing the duration of the vertical blanking (Vertical Blanking, VBlank) period in the frame period of the display panel
  • VRR variable refresh rate
  • the vertical blanking phase of the frame period will last for a certain period of time, and the display panel will generate leakage current during this period, which will affect the display quality.
  • the present application provides a display panel and electronic equipment, capable of compensating the leakage current generated by the display panel during the vertical blanking phase, and improving the display effect.
  • the application provides a display panel, which includes:
  • a pixel unit the pixel unit is connected to the data line;
  • the data line is configured to output a data voltage to the pixel unit in each frame display period, and the picture display period includes a display period and a vertical blanking period; in the first preset refresh mode, at least one frame In the picture display period, the data voltage includes a display voltage and a compensation voltage; in the display period, the data line outputs the display voltage to the pixel unit, and in the vertical blanking period, the data outputting the compensation voltage to the pixel unit via a line;
  • the voltage value of the display voltage is smaller than the voltage value of the compensation voltage, and when the display voltage is a negative polarity voltage, the voltage value of the display voltage is greater than the compensation voltage voltage value.
  • the compensation voltage is a positive polarity voltage corresponding to the highest display grayscale of the display panel
  • the compensation voltage is a negative polarity voltage corresponding to the highest display gray scale of the display panel.
  • the voltage value of the compensation voltage is adjusted in real time according to the voltage value of the display voltage.
  • the absolute value of the display voltage is smaller than the absolute value of the compensation voltage.
  • the first preset refresh mode includes a first refresh mode and a second refresh mode, and the refresh frequency of the first refresh mode is lower than the refresh frequency of the second refresh mode ;
  • the data voltage includes a first display voltage and a first compensation voltage
  • the data line outputs the first display voltage to the pixel unit
  • the data line outputs the first compensation voltage to the pixel unit; when the first display voltage is a positive polarity voltage, the voltage value of the first display voltage is smaller than the first compensation voltage
  • the voltage value of the voltage when the first display voltage is a negative polarity voltage, the voltage value of the first display voltage is greater than the voltage value of the first compensation voltage;
  • the data voltage includes a second display voltage and a second compensation voltage
  • the data line outputs the second display voltage to the pixel unit
  • the data line outputs the second compensation voltage to the pixel unit
  • the second display voltage is a positive polarity voltage
  • the voltage value of the second display voltage is smaller than the second compensation voltage
  • the voltage value of the second display voltage is greater than the voltage value of the first compensation voltage
  • the voltage difference between the first compensation voltage and the first display voltage is greater than the voltage difference between the second compensation voltage and the second display voltage.
  • the display panel further has a second preset refresh mode, and the refresh frequency of the second preset refresh mode is higher than the refresh frequency of the first preset refresh mode;
  • each of the vertical blanking periods includes a first time period and a second time period, and the duration of the second time period is equal to all the time periods in the second preset refresh mode.
  • the data line outputs the compensation voltage to the pixel unit.
  • the display panel further has a second preset refresh mode, and the refresh frequency of the second preset refresh mode is higher than the refresh frequency of the first preset refresh mode;
  • the data voltage includes a third display voltage and a third compensation voltage, and during the display period, the data line outputs the third display voltage to the pixel unit. In the vertical blanking phase, the data line outputs the third compensation voltage to the pixel unit;
  • the voltage value of the third compensation voltage is greater than the positive polarity voltage value corresponding to the lowest display gray scale of the display panel; when the third display voltage is a negative polarity voltage , the voltage value of the third compensation voltage is smaller than the negative polarity voltage value corresponding to the lowest display gray scale of the display panel.
  • the display panel further includes scanning lines, and the scanning lines are arranged to intersect with the data lines;
  • the scan line is configured to output a reference low-level voltage; a voltage value of the reference low-level voltage is greater than or less than a preset reference low-level voltage.
  • the first preset refresh mode includes a first refresh mode and a second refresh mode, and the refresh frequency of the first refresh mode is lower than the refresh frequency of the second refresh mode ;
  • the scan line In the first refresh mode, during the vertical blanking period, the scan line is configured to output a first reference low-level voltage; in the second refresh mode, during the vertical blanking period, The scan line is configured to output a second reference low-level voltage; the voltage value of the first reference low-level voltage and the voltage value of the second reference low-level voltage are both greater than or less than the preset reference The voltage value of the low level voltage.
  • the voltage value of the first reference low-level voltage is equal to the voltage value of the second reference low-level voltage.
  • the voltage value of the first reference low-level voltage when both the voltage value of the first reference low-level voltage and the voltage value of the second reference low-level voltage are smaller than the preset reference low-level voltage voltage value, the voltage value of the first reference low-level voltage is smaller than the voltage value of the second reference low-level voltage;
  • the first reference low-level voltage When both the voltage value of the first reference low-level voltage and the voltage value of the second reference low-level voltage are greater than the voltage of the preset reference low-level voltage, the first reference low-level voltage The voltage value is greater than the voltage value of the second reference low-level voltage.
  • the present application also provides an electronic device, which includes a display panel and a driving device, the driving device is used to provide a data voltage to the display panel, and the display panel includes:
  • a pixel unit the pixel unit is connected to the data line;
  • the data line is configured to output a data voltage to the pixel unit in each frame display period, and the picture display period includes a display period and a vertical blanking period; in the first preset refresh mode, at least one frame In the picture display period, the data voltage includes a display voltage and a compensation voltage; in the display period, the data line outputs the display voltage to the pixel unit, and in the vertical blanking period, the data outputting the compensation voltage to the pixel unit via a line;
  • the voltage value of the display voltage is smaller than the voltage value of the compensation voltage, and when the display voltage is a negative polarity voltage, the voltage value of the display voltage is greater than the compensation voltage voltage value.
  • the compensation voltage is a positive polarity voltage corresponding to the highest display grayscale of the display panel
  • the compensation voltage is a negative polarity voltage corresponding to the highest display gray scale of the display panel.
  • the voltage value of the compensation voltage is adjusted in real time according to the voltage value of the display voltage.
  • the absolute value of the display voltage is smaller than the absolute value of the compensation voltage.
  • the first preset refresh mode includes a first refresh mode and a second refresh mode, and the refresh frequency of the first refresh mode is lower than the refresh frequency of the second refresh mode ;
  • the data voltage includes a first display voltage and a first compensation voltage
  • the data line outputs the first display voltage to the pixel unit
  • the data line outputs the first compensation voltage to the pixel unit; when the first display voltage is a positive polarity voltage, the voltage value of the first display voltage is smaller than the first compensation voltage
  • the voltage value of the voltage when the first display voltage is a negative polarity voltage, the voltage value of the first display voltage is greater than the voltage value of the first compensation voltage;
  • the data voltage includes a second display voltage and a second compensation voltage
  • the data line outputs the second display voltage to the pixel unit
  • the data line outputs the second compensation voltage to the pixel unit
  • the second display voltage is a positive polarity voltage
  • the voltage value of the second display voltage is smaller than the second compensation voltage
  • the voltage value of the second display voltage is greater than the voltage value of the first compensation voltage
  • the voltage difference between the first compensation voltage and the first display voltage is greater than the voltage difference between the second compensation voltage and the second display voltage.
  • the display panel further has a second preset refresh mode, and the refresh frequency of the second preset refresh mode is higher than the refresh frequency of the first preset refresh mode;
  • each of the vertical blanking periods includes a first time period and a second time period, and the duration of the second time period is equal to all the time periods in the second preset refresh mode.
  • the data line outputs the compensation voltage to the pixel unit.
  • the display panel further has a second preset refresh mode, and the refresh frequency of the second preset refresh mode is higher than the refresh frequency of the first preset refresh mode;
  • the data voltage includes a third display voltage and a third compensation voltage, and during the display period, the data line outputs the third display voltage to the pixel unit. In the vertical blanking phase, the data line outputs the third compensation voltage to the pixel unit;
  • the voltage value of the third compensation voltage is greater than the positive polarity voltage value corresponding to the lowest display gray scale of the display panel; when the third display voltage is a negative polarity voltage , the voltage value of the third compensation voltage is smaller than the negative polarity voltage value corresponding to the lowest display gray scale of the display panel.
  • the display panel further includes scanning lines, and the scanning lines are arranged to intersect with the data lines;
  • the scan line is configured to output a reference low-level voltage; a voltage value of the reference low-level voltage is greater than or less than a preset reference low-level voltage.
  • the first preset refresh mode includes a first refresh mode and a second refresh mode, and the refresh frequency of the first refresh mode is lower than the refresh frequency of the second refresh mode ;
  • the scan line In the first refresh mode, during the vertical blanking period, the scan line is configured to output a first reference low-level voltage; in the second refresh mode, during the vertical blanking period, The scan line is configured to output a second reference low-level voltage; the voltage value of the first reference low-level voltage and the voltage value of the second reference low-level voltage are both greater than or less than the preset reference The voltage value of the low level voltage.
  • the present application provides a display panel and electronic equipment.
  • the display panel includes data lines and pixel units connected to the data lines. Wherein, the data lines are configured to output data voltages to the pixel units in each frame display period.
  • the picture display period includes a display period and a vertical blanking period.
  • the data line in at least one frame display period in the first preset refresh mode, is set to output the display voltage to the pixel unit during the display period, and the data line is set to output the compensation voltage to the pixel unit during the vertical blanking period.
  • the voltage value of the display voltage is smaller than the voltage value of the compensation voltage, and when the display voltage is a negative polarity voltage, the voltage value of the display voltage is greater than the voltage value of the compensation voltage. Therefore, the leakage current generated by the display panel during the vertical blanking phase is compensated by means of micro-charging, and the display effect of the display panel is improved.
  • FIG. 1 is a schematic structural diagram of a display panel provided by the present application.
  • Fig. 2 is a schematic structural diagram of a display frame cycle in the display panel provided by the present application.
  • FIG. 3 is a first timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 4 is a second timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 5 is a third timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 6 is a fourth timing diagram of driving signals of the display panel provided by the present application.
  • FIG. 7 is a fifth timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 8 is a schematic diagram of a leakage current curve of an N-type transistor provided by the present application.
  • FIG. 9 is a sixth timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 10 is a seventh timing diagram of the driving signals of the display panel provided by the present application.
  • FIG. 11 is a schematic structural diagram of an electronic device provided by the present application.
  • the present application provides a display panel and an electronic device, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic structural diagram of a display panel provided by the present application.
  • FIG. 2 is a schematic structural diagram of a display frame cycle in the display panel provided by the present application.
  • FIG. 3 is a first timing diagram of driving signals of the display panel provided by the present application.
  • the display panel 100 includes data lines 11 and pixel units 20 .
  • the pixel unit 20 is connected to the data line 11 .
  • the data line 11 is configured to output a data voltage to the pixel unit 20 in each frame display period.
  • the picture display period includes a display period AA and a vertical blanking period VB.
  • the data voltage includes a display voltage D and a compensation voltage V in at least one frame display period.
  • the data line 11 outputs a display voltage D to the pixel unit 20 .
  • the vertical blanking period VB the data line 11 outputs a compensation voltage V to the pixel unit 20 .
  • the voltage value of the display voltage D is smaller than the voltage value of the compensation voltage V.
  • the voltage value of the display voltage D is greater than the voltage value of the compensation voltage V.
  • the display panel 100 further includes scan lines 12 .
  • the pixel unit 20 is defined by the intersection of the data line 11 and the scan line 12 .
  • the pixel unit 20 includes a transistor 21 and a pixel electrode 22 .
  • the control end of the transistor 21 is connected to the scan line 12 .
  • the input end of the transistor 21 is connected to the data line 11 .
  • the output terminal of the transistor 21 is connected to the pixel electrode 22 .
  • the refresh rate determines the refresh rate of the displayed image.
  • the numbers of the data lines 11 , the scan lines 12 and the pixel units 20 can be set according to the size and resolution specifications of the display panel 100 .
  • the data lines 11 and the scan lines 12 may intersect vertically, or only intersect but not perpendicularly.
  • the drawings are only examples and should not be construed as limiting the application.
  • the display panel 100 provided in the present application adopts a 1G1D (one gate one data, one scan line and one data line) driving architecture, but the present application is not limited thereto.
  • the display panel 100 of the present application can also adopt HG2D (half Gate two data, half-gate double data) and other drive architectures will not be described here.
  • the scan line 12 is configured to output a scan signal.
  • the scan signal controls the transistors 21 to be turned on, and then controls the pixel units 20 to be turned on row by row.
  • the data lines 11 are configured to output data voltages to charge corresponding pixel units 20 .
  • the transistor 21 is turned off.
  • the pixel unit 20 maintains the display image of the current frame.
  • each frame in the display panel 100 includes a display period AA and a vertical blanking period VB.
  • a plurality of data lines 11 are configured to respectively output display data corresponding to each row of pixel units 20, such as red, green and blue (RGB) display voltages, so as to light up all pixel units in one frame 20.
  • a plurality of data lines 11 are configured to respectively output the blanking data corresponding to each row of pixel units 20, for example, the blanking data corresponding to each row of pixel units 20 are 0 grayscale signals (the lowest grayscale signal), that is, the black level signal.
  • the display panel 100 provided in this application is a liquid crystal display panel.
  • the brightness is determined by the voltage difference between the two sides of the liquid crystal.
  • the voltage on one side of the liquid crystal is fixed, which is the common voltage VCOM.
  • the voltage on the other side is the voltage of the pixel electrode 22 .
  • the voltage difference between the pixel electrode 22 and the common voltage VCOM will decrease, causing the brightness of the pixel unit 20 to decrease.
  • a voltage with a voltage value greater than the common voltage VCOM is a positive polarity voltage
  • a voltage with a voltage value smaller than the common voltage VCOM is a negative polarity voltage
  • the voltage value of the display voltage D in at least one frame display period, when the display voltage D is a positive polarity voltage, the voltage value of the display voltage D is set to be smaller than the voltage value of the compensation voltage V. Then the voltage at the input terminal of the transistor 21 is greater than the voltage at the output terminal, and the input terminal of the transistor 21 leaks electricity to the output terminal. Therefore, the potential of the pixel electrode 22 is increased by means of micro-charging, the voltage difference between the two sides of the liquid crystal is increased, and the brightness of the pixel unit 20 is increased. When the display voltage D is a negative polarity voltage, the voltage value of the display voltage D is set to be greater than the voltage value of the compensation voltage V.
  • the voltage at the input terminal of the transistor 21 is lower than the voltage at the output terminal, and the output terminal of the transistor 21 leaks electricity to the input terminal.
  • the potential of the pixel electrode 22 decreases, which also increases the voltage difference between the two sides of the liquid crystal, thereby increasing the brightness of the pixel unit 20 .
  • the leakage current of the pixel electrode 22 in the vertical blanking period VB is compensated, and the display effect of the display panel 100 is improved.
  • the source and drain of the transistor used in this application are symmetrical, the source and drain can be interchanged.
  • one pole is called the source, and the other pole is called the drain.
  • the control terminal of the transistor 21 is the gate, the input terminal of the transistor 21 is the source, and the output terminal of the transistor 21 is the drain.
  • the transistors used in this application may include P-type transistors and/or N-type transistors, wherein, the P-type transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level. It turns on when the gate is high and turns off when the gate is low.
  • the transistors in the following embodiments of the present application are all described by taking N-type transistors as examples, but this should not be construed as a limitation of the present application.
  • the value of the common voltage VCOM of the display panel 100 needs to be set according to the display requirements of the display panel 100 .
  • the common voltage VCOM of the display panel 100 is 0, the absolute value of the display voltage D is smaller than the absolute value of the compensation voltage V.
  • the common voltage VCOM of the display panel 100 may not be set to zero.
  • the common voltage VCOM of the display panel 100 is set to 7V or other voltage values. It needs to be satisfied that when the display voltage D is a positive polarity voltage, the voltage value of the display voltage D is smaller than the voltage value of the compensation voltage V. When the display voltage D is a negative polarity voltage, the voltage value of the display voltage D is greater than the voltage value of the compensation voltage V.
  • the leakage compensation in the first preset frequency mode, can be performed only for at least one frame display period, so as to reduce the power consumption of the display panel 100 .
  • equal leakage compensation can also be performed for all picture display periods, so as to ensure the maximum display brightness of the display panel 100 in the first preset frequency mode.
  • the following embodiments of the present application are described by taking the leakage compensation of the pixel electrode 22 in the vertical blanking period VB of each frame display period as an example, but it should not be construed as a limitation of the present application.
  • the compensation voltage V when the display voltage D is a positive polarity voltage, the compensation voltage V is a positive polarity voltage corresponding to the highest display gray scale of the display panel 100 .
  • the compensation voltage V is a negative polarity voltage corresponding to the highest display gray scale of the display panel 100 .
  • the image display data input to the display panel 100 is binary 8-bit
  • 2 to the power of 8 brightness gray scales from the darkest to the brightest will be generated. That is, 256 gray levels with different brightness levels (for example, recorded as the 0th gray level to the 255th gray level) are generated.
  • the display brightness corresponding to the 255th gray scale is the largest, that is, the voltage value corresponding to the 255th gray scale is the largest.
  • the image display data received by the display panel 100 of the present application may also be binary 6 bits, binary 10 bits, and the like.
  • the present application uses 8bit as an example for description, but it should not be understood as a limitation to the present application.
  • each pixel unit 20 corresponds to a display voltage D in each display frame period in the first preset refresh mode.
  • the display voltage D can be any gray scale voltage in 0-255 gray scales.
  • the compensation voltage V is correspondingly set according to the highest display gray scale of the display panel 100 .
  • the display voltage D is a positive polarity voltage
  • setting the compensation voltage V as the positive polarity voltage corresponding to the highest display gray scale of the display panel 100 can ensure that the voltage at the input terminal of each transistor 21 is uniform during the vertical blanking period VB. greater than or equal to the voltage at the output.
  • the input terminal of the transistor 21 leaks electricity to the output terminal, thereby slightly charging the pixel electrode 22, increasing the potential of the pixel electrode 22, and then compensating the leakage electricity of the pixel electrode 22 in the vertical blanking period VB of the first refresh mode.
  • the display voltage D is a negative polarity voltage, which will not be repeated here.
  • the driving device of the display panel 100 it is usually necessary to design a logic circuit to judge and output the compensation voltage V corresponding to each pixel unit 20, so as to ensure that the compensation voltage V corresponding to each pixel unit 20
  • the voltage value of V is greater than the voltage value of the corresponding display voltage D.
  • the compensation voltage V is uniformly set as the positive polarity voltage corresponding to the highest display gray scale of the display panel 100 .
  • the logic circuit can be simplified and the signal complexity of the display panel 100 can be reduced.
  • it can also ensure that the voltage value of the compensation voltage V corresponding to each pixel unit 20 is greater than the corresponding voltage value of the display voltage D, so as to achieve the compensation effect.
  • the voltage value of the compensation voltage V can be adjusted according to the voltage value of the display voltage D in real time. That is, the compensation voltage V can be set for the display voltage D corresponding to each pixel unit 20 , as long as the voltage value of the compensation voltage V is greater than the voltage value of the display voltage D, thereby reducing the power consumption of the display panel 100 .
  • the first preset frequency mode may only include one refresh mode.
  • this refresh mode the leakage current of the display panel 100 is compensated by means of micro-charging, and the display brightness of the display panel 100 can be improved.
  • the first preset frequency mode may also include multiple refresh modes. It can be understood that, under different refresh rates, the duration of the vertical blanking phase VB of the picture display period is different, and leakage currents of different magnitudes will be generated. Different magnitudes of leakage currents will result in different brightness of images displayed on the display panel. Therefore, when the refresh rate of the display panel changes, the display panel may flicker.
  • FIG. 4 is a second timing diagram of the driving signals of the display panel provided by the present application.
  • the difference from the driving signal of the display panel 100 shown in FIG. 3 is that in this embodiment, the first preset refresh mode includes a first refresh mode and a second refresh mode.
  • the refresh frequency of the first refresh mode is smaller than the refresh frequency of the second refresh mode.
  • the data voltage in the first refresh mode, includes the first display voltage D1 and the first compensation voltage V1.
  • the data line 11 outputs the first display voltage D1 to the pixel unit 20 .
  • the data line 11 outputs the first compensation voltage V1 to the pixel unit 20 .
  • the first display voltage D1 is a positive polarity voltage
  • the voltage value of the first display voltage D1 is smaller than the voltage value of the first compensation voltage V1 .
  • the first display voltage D1 is a negative polarity voltage
  • the voltage value of the first display voltage D1 is greater than the voltage value of the first compensation voltage V1 .
  • the data voltage includes the second display voltage D2 and the second compensation voltage V2.
  • the data line 11 outputs the second display voltage D2 to the pixel unit 20 .
  • the data line 11 outputs the second compensation voltage V2 to the pixel unit 20 .
  • the voltage value of the second display voltage D2 is smaller than the voltage value of the second compensation voltage V2.
  • the second display voltage D2 is a negative polarity voltage.
  • the voltage value of the second display voltage D2 is greater than the voltage value of the second compensation voltage V2.
  • the duration of each vertical blanking period VB in the first refresh mode is longer than the duration of each vertical blanking period VB in the second refresh mode.
  • the longer the duration of the vertical blanking period VB the longer the duration of the image currently displayed on the display panel 100 is.
  • the voltage on the pixel electrode 22 also needs to be maintained for a longer time.
  • the leakage of the transistor 21 is also more serious. That is, in the first refresh mode, the brightness of the pixel electrode 22 is reduced more than in the second refresh mode.
  • the pixel electrode 22 in the first refresh mode will also generate more leakage during the vertical blanking period VB .
  • the leakage of the pixel electrode 22 is compensated by micro-charging the pixel electrode 22, which can reduce the pixel electrode 22’s leakage in the first refresh mode and the second refresh mode. Potential difference due to transistor 21 leakage.
  • compensation is performed on the pixel electrodes 22 in both the first refresh mode and the second refresh mode, so as to achieve a balance between compensation and leakage, and improve the overall display effect of the display panel 100 .
  • the voltage difference between the first compensation voltage V1 and the first display voltage D1 is greater than the voltage difference between the second compensation voltage V2 and the second display voltage D2.
  • micro-current compensation is performed on the pixel electrode 22 according to the leakage characteristics of the transistor 21 .
  • Due to the longer duration of each vertical blanking period VB in the first refresh mode the leakage degree of the pixel electrode 22 in the first refresh mode is greater than that in the second refresh mode. Therefore, in this embodiment, by setting the voltage difference between the first compensation voltage V1 and the first display voltage D1 to be greater than the voltage difference between the second compensation voltage V2 and the second display voltage D2, it is possible to improve the performance of the first refresh mode.
  • the charging amount of the pixel electrode 22 increases the compensation for the pixel electrode 22 in the first refresh mode, thereby further reducing the brightness difference of the display screen of the display panel 100 under different refresh frequencies.
  • the duration of the display phase AA in the first refresh mode and the second refresh mode is the same. That is, the charging time of the pixel unit 20 in the first refresh mode and the second refresh mode is equal. Therefore, usually only by changing the duration of the vertical blanking period VB in the frame period of the display panel 100 to dynamically adjust the refresh frequency of the display panel 100 .
  • FIG. 5 is a third timing diagram of the driving signals of the display panel provided by the present application.
  • the difference from the driving signal of the display panel 100 shown in FIG. 3 is that in this embodiment, the display panel also has a second preset refresh mode.
  • the refresh frequency of the second preset refresh mode is higher than the refresh frequency of the first preset refresh mode.
  • This application only provides a compensation voltage V to the pixel unit 20 in the vertical blanking period VB of at least one frame of the first preset refresh mode, and through micro-charging, the leakage of the pixel electrode 22 in the vertical blanking period VB Compensation is performed to reduce the brightness difference of the display screen of the display panel 100 in the first preset refresh mode and the second preset refresh mode, so as to avoid screen flickering when the screen is switched.
  • FIG. 6 is a fourth timing diagram of the driving signals of the display panel provided by the present application.
  • the difference from the driving signal of the display panel 100 shown in FIG. 5 is that in this embodiment, in the first preset refresh mode, each vertical blanking period VB includes a first time period T1 and a second time period segment T2.
  • the duration of the second time period T2 is equal to the duration of the vertical blanking period VB in the second preset refresh mode.
  • the data line 11 outputs the compensation voltage V to the pixel unit 20 .
  • the degree of leakage of the pixel electrode 22 in the first refresh mode and the second refresh mode is different, mainly because the duration of each vertical blanking period VB in the first preset refresh mode is longer than that in the second preset refresh mode The duration of each vertical blanking phase VB. Therefore, in this embodiment, the first compensation voltage V1 is configured for the data line 11 only in the first time period T1, and the duration of the second time period T2 is set equal to the duration of each vertical blanking period VB in the second refresh mode.
  • the duration of leakage caused by the transistor 21 of the pixel electrode 22 in the first preset refresh mode and the second preset refresh mode can be kept consistent, thereby reducing the difference in leakage caused by the transistor 21 .
  • micro-charge compensation can be performed on the pixel electrode 22 in the first time period T1, and then the leakage of the pixel electrode 22 caused by other factors in the first refresh mode can be compensated to further reduce the pixel electrode 22 in the first refresh mode.
  • the leakage difference between the preset refresh mode and the second preset refresh mode reduces the brightness difference of the display images of the display panel 100 at different refresh rates.
  • FIG. 7 is a fifth timing diagram of the driving signals of the display panel provided by the present application.
  • the difference from the driving signal of the display panel 100 shown in FIG. 5 is that in this embodiment, in the second preset refresh mode, the data voltage includes the third display voltage D3 and the third compensation voltage V3.
  • the data line 11 outputs a third display voltage D3 to the pixel unit 20 .
  • VB during the vertical blanking phase.
  • the data line 11 outputs the third compensation voltage V3 to the pixel unit 20 .
  • the voltage value of the third compensation voltage V3 is greater than the positive polarity voltage value corresponding to the lowest display gray scale of the display panel 100 .
  • the voltage value of the third compensation voltage V3 is smaller than the negative polarity voltage value corresponding to the lowest display gray scale of the display panel 100 .
  • the data lines are configured to output a black grayscale signal to the pixel unit 20 , that is, the lowest display grayscale signal of the display panel 100 . Therefore, in this embodiment, when the third display voltage D3 is a positive polarity voltage, the voltage value of the third compensation voltage V3 is set to be greater than the positive polarity voltage value corresponding to the lowest display gray scale of the display panel 100, which can aggravate the vertical disappearance of the pixel electrode 22. Leakage within VB during hidden phase. That is, by increasing the leakage of the display panel 100 in the second preset refresh mode, the difference of the leakage of the pixel electrode 22 in the first preset refresh mode and the second preset refresh mode is reduced.
  • the voltage value of the third compensation voltage V3 is set to be smaller than the negative polarity voltage value corresponding to the lowest display gray scale of the display panel 100, which can aggravate the pixel electrode 22 in the vertical direction. Leakage current within VB during blanking phase.
  • the scanning line 12 outputs a corresponding reference low level voltage, so that the transistor 21 is turned off.
  • the potential of the reference low-level voltage can be designed according to the switching characteristics of the transistor 21 .
  • FIG. 8 is a schematic diagram of a leakage current curve of an N-type transistor provided in the present application.
  • the abscissa is the voltage value of the reference low-level voltage, and the unit is volt (V).
  • the ordinate is the leakage current of the transistor 21, and the unit is A (I). It can be seen from FIG. 6 that when the transistor 21 is turned off, it is not in a completely off state, and there will still be a certain off-state leakage current. However, for the transistor 21, under the control of the preset reference low-level voltage V0, the transistor 21 has the smallest leakage current.
  • FIG. 9 is a fourth timing diagram of the driving signals of the display panel provided by the present application.
  • the scan line 12 is configured to output the reference low-level voltage VSSG during the vertical blanking period VB of one frame.
  • the voltage value of the reference low-level voltage VSSG is greater than or lower than a voltage value of a preset reference low-level voltage V0 .
  • the micro-charging compensation is performed on the pixel electrode 22 in the vertical blanking period VB, and the leakage of the transistor 21 is utilized.
  • the preset reference low level voltage V0 corresponds to the minimum leakage current of the transistor 21 .
  • setting the voltage value of the reference low-level voltage VSSG to be greater than or smaller than the voltage value of the preset reference low-level voltage V0 can improve the leakage capability of the transistor 21 and increase the compensation for the potential of the pixel electrode 22, thereby avoiding The brightness of the display panel 100 is dimmed.
  • leakage current curve of the P-type transistor is similar to the leakage current curve of the N-type transistor, which will not be repeated here.
  • FIG. 10 is a fifth timing diagram of the driving signals of the display panel provided by the present application.
  • the difference from the driving sequence of the display panel 100 shown in FIG. 9 is that in this embodiment, in the first preset refresh mode, in the vertical blanking period VB of each frame, the scanning lines 12 are configured To output the first reference low-level voltage VSSQ1. In the second preset refresh mode, the scan line 12 is configured to output the second reference low-level voltage VSSQ2 during the vertical blanking period VB of each frame.
  • the voltage value of the first reference low-level voltage VSSQ1 is greater than or lower than the voltage value of the preset reference low-level voltage V0 .
  • the voltage value of the second reference low-level voltage VSSQ2 is greater than or lower than the voltage value of the preset reference low-level voltage V0 .
  • the voltage value of the first reference low-level voltage VSSQ1 is equal to the voltage value of the second reference low-level voltage VSSQ2 .
  • the first reference low-level voltage VSSQ1 and the voltage value of the second reference low-level voltage VSSQ2 are smaller than the voltage value of the reference low-level voltage VSSQ
  • the first reference low-level voltage The voltage value of the level voltage VSSQ1 is smaller than the voltage value of the second reference low level voltage VSSQ2.
  • the first reference low-level voltage VSSQ1 and the voltage value of the second reference low-level voltage VSSQ2 are smaller than the voltage value of the reference low-level voltage V0, the first reference low-level voltage is set The voltage value of VSSQ1 is less than the voltage value of the second reference low-level voltage VSSQ2, then the leakage current of the transistor 21 under the control of the first reference low-level voltage VSSQ1 is greater than that of the transistor 21 under the control of the second reference low-level voltage VSSQ2 leakage current.
  • the leakage of the transistor 21 is used to compensate the micro charging of the pixel electrode 22 .
  • the leakage degree of the pixel electrode 22 in the first refresh mode is larger than that in the second refresh mode. Therefore, in this embodiment, by setting the voltage value of the first reference low-level voltage VSSQ1 to be lower than the voltage value of the second reference low-level voltage VSSQ2, the charging amount of the pixel electrode 22 in the first refresh mode can be increased, and the charging capacity of the pixel electrode 22 can be increased.
  • the compensation strength of the pixel electrode 22 in the first refresh mode can further reduce the brightness difference of the displayed images of the display panel 100 under different refresh frequencies.
  • the first reference low-level voltage VSSQ1 and the voltage value of the second reference low-level voltage VSSQ2 are greater than the voltage of the reference low-level voltage V0
  • the first reference low-level The voltage value of the voltage VSSQ1 is greater than the voltage value of the second reference low-level voltage VSSQ2.
  • the first reference low-level voltage VSSQ1 and the second reference low-level voltage VSSQ2 are both greater than the voltage value of the reference low-level voltage V0
  • the first reference low-level voltage is set
  • the voltage value of VSSQ1 is greater than the voltage value of the second reference low-level voltage VSSQ2
  • the leakage current of the transistor 21 under the control of the first reference low-level voltage VSSQ1 is greater than that of the transistor 21 under the control of the second reference low-level voltage VSSQ2 leakage current.
  • the leakage of the transistor 21 is used to compensate the micro charging of the pixel electrode 22 .
  • the leakage degree of the pixel electrode 22 in the first refresh mode is larger than that in the second refresh mode. Therefore, in this embodiment, by setting the voltage value of the first reference low-level voltage VSSQ1 to be greater than the voltage value of the second reference low-level voltage VSSQ2, the charging amount of the pixel electrode 22 in the first refresh mode can be increased, and the charging capacity of the pixel electrode 22 can be increased.
  • the compensation strength of the pixel electrode 22 in the first refresh mode can further reduce the brightness difference of the displayed images of the display panel 100 under different refresh frequencies.
  • the present application also provides an electronic device, which includes a display panel and a driving device.
  • the driving device is used for providing driving signals to the display panel.
  • the driving signal may be the reference low level voltage, the first display voltage, the first compensation voltage, the second display voltage, the second compensation voltage, etc. in the above embodiments.
  • the display panel is the display panel described in any one of the above embodiments, which will not be repeated here.
  • the electronic device in this application may be a smart phone, a tablet computer, a video player, a personal computer (PC), etc., which is not limited in this application.
  • FIG. 11 is a schematic structural diagram of an electronic device provided in this application.
  • the electronic device 1000 includes a display panel 100 and a driving device 200 .
  • the driving device 200 is used for providing a driving signal to the display panel 100 .
  • the driving device 200 includes but not limited to a timing controller 201 , a data driving circuit 202 and a gate driving circuit 203 .
  • the timing controller 201 is used to provide display data to the data driving circuit 202 .
  • the data driving circuit 202 is used for outputting the data voltage to the pixel unit 20 through the data line 11 in the display phase of each frame.
  • the data driving circuit 202 is also used to output the compensation voltage to the pixel unit 20 through the data line 11 during the vertical blanking period of each frame.
  • the gate driving circuit 203 is used for outputting scan signals such as reference low potential voltages to the scan lines 12 .
  • an array substrate gate driver circuit (Gate Driver Array, GOA for short) may be integrated in the display panel 100 to replace the gate driver circuit 203 , so as to realize a narrow border.
  • the present application provides an electronic device, which includes a display panel 100 .
  • the display panel 100 includes data lines 11 and pixel units 20 connected to the data lines 11 .
  • the data line 11 is configured to output a data voltage to the pixel unit 20 in each frame display period.
  • the picture display period includes a display period and a vertical blanking period.
  • This application sets the data line 11 to output the display voltage to the pixel unit 20 during the display period, and sets the data line 11 to output the display voltage to the pixel unit 20 during the vertical blanking period during at least one frame display period in the first preset refresh mode. Output compensation voltage.
  • the display voltage is a positive polarity voltage
  • the voltage value of the display voltage is smaller than the voltage value of the compensation voltage
  • the display voltage is a negative polarity voltage
  • the voltage value of the display voltage is greater than the voltage value of the compensation voltage. Therefore, the leakage current generated by the display panel 100 during the vertical blanking phase is compensated by means of micro-charging, and the display effect of the display panel is improved.
  • the display panel 100 includes multiple refresh modes, the brightness difference of the screens displayed by the display panel 100 at different refresh rates can be reduced to avoid screen flickering during screen switching.

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Abstract

公开了一种显示面板和电子设备。在第一预设刷新模式下，在至少一帧画面显示周期内的显示时段(AA)，数据线(11)向像素单元(20)输出显示电压(D)，在垂直消隐阶段(VB)，数据线(11)向像素单元(20)输出补偿电压(V)。当显示电压(D)为正极性电压时，显示电压(D)的电压值小于补偿电压(V)的电压值，当显示电压(D)为负极性电压时，显示电压(D)的电压值大于补偿电压(V)的电压值。

Description

显示面板和电子设备 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板和电子设备。
 背景技术
现有的时序控制器(Timer Control Register, TCON)大都支持可变刷新率(Varied refresh rate, VRR)功能，即通过改变显示面板的帧周期中的垂直消隐(Vertical Blanking, VBlank)周期的时长来动态调节显示面板的刷新率，以使显示面板的刷新率与显卡的刷新率匹配，从而解决显示面板显示的画面撕裂和波动的问题，提高画面的流畅性。
 技术问题
然而，当刷新频率较小时，帧周期的垂直消隐阶段会维持一定的时长，在这段时间内显示面板会产生漏电流，影响显示质量。
 技术解决方案
本申请提供一种显示面板和电子设备，能够补偿显示面板在垂直消隐阶段产生的漏电，改善显示效果。
本申请提供一种显示面板，其包括：
数据线；
像素单元，所述像素单元与所述数据线连接；其中，
所述数据线被配置为在每一帧画面显示周期内向所述像素单元输出数据电压，所述画面显示周期包括显示时段和垂直消隐阶段；在第一预设刷新模式下，在至少一帧所述画面显示周期内，所述数据电压包括显示电压和补偿电压；在所述显示时段，所述数据线向所述像素单元输出所述显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述补偿电压；
当所述显示电压为正极性电压时，所述显示电压的电压值小于所述补偿电压的电压值，当所述显示电压为负极性电压时，所述显示电压的电压值大于所述补偿电压的电压值。
可选的，在本申请一些实施例中，当所述显示电压为正极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的正极性电压；
当所述显示电压为负极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的负极性电压。
可选的，在本申请一些实施例中，所述补偿电压的电压值根据所述显示电压的电压值实时调整。
可选的，在本申请一些实施例中，当所述显示面板的公共电压为零时，所述显示电压的绝对值小于所述补偿电压的绝对值。
可选的，在本申请一些实施例中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
在所述第一刷新模式下，所述数据电压包括第一显示电压和第一补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第一显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第一补偿电压；当所述第一显示电压为正极性电压时，所述第一显示电压的电压值小于所述第一补偿电压的电压值，当所述第一显示电压为负极性电压时，所述第一显示电压的电压值大于所述第一补偿电压的电压值；
在所述第二刷新模式下，所述数据电压包括第二显示电压和第二补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第二显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第二补偿电压；当所述第二显示电压为正极性电压时，所述第二显示电压的电压值小于所述第二补偿电压的电压值，当所述第二显示电压为负极性电压时，所述第二显示电压的电压值大于所述第一补偿电压的电压值；
其中，所述第一补偿电压与所述第一显示电压之间的压差大于所述第二补偿电压与所述第二显示电压之间的压差。
可选的，在本申请一些实施例中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
在所述第一预设刷新模式下，每一所述垂直消隐阶段包括第一时间段和第二时间段，所述第二时间段的时长等于所述第二预设刷新模式中的所述垂直消隐阶段的时长；
在所述第一时间段内，所述数据线向所述像素单元输出所述补偿电压。
可选的，在本申请一些实施例中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
在所述第二预设刷新模式下，所述数据电压包括第三显示电压和第三补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第三显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第三补偿电压；
当所述第三显示电压为正极性电压时，所述第三补偿电压的电压值大于所述显示面板的最低显示灰阶对应的正极性电压值，当所述第三显示电压为负极性电压时，所述第三补偿电压的电压值小于所述显示面板的最低显示灰阶对应的负极性电压值。
可选的，在本申请一些实施例中，所述显示面板还包括扫描线，所述扫描线与所述数据线交叉设置；
在所述垂直消隐阶段，所述扫描线被配置为输出参考低电平电压；所述参考低电平电压的电压值大于或小于一预设参考低电平电压的电压值。
可选的，在本申请一些实施例中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
在所述第一刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第一参考低电平电压；在所述第二刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第二参考低电平电压；所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于或小于所述预设参考低电平电压的电压值。
可选的，在本申请一些实施例中，所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值相等。
可选的，在本申请一些实施例中，当所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均小于所述预设参考低电平电压的电压值时，所述第一参考低电平电压的电压值小于所述第二参考低电平电压的电压值；
当所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于所述预设参考低电平电压的电压时，所述第一参考低电平电压的电压值大于所述第二参考低电平电压的电压值。
相应的，本申请还提供一种电子设备，其包括显示面板和驱动装置，所述驱动装置用于提供数据电压至所述显示面板，所述显示面板包括：
数据线；
像素单元，所述像素单元与所述数据线连接；其中，
所述数据线被配置为在每一帧画面显示周期内向所述像素单元输出数据电压，所述画面显示周期包括显示时段和垂直消隐阶段；在第一预设刷新模式下，在至少一帧所述画面显示周期内，所述数据电压包括显示电压和补偿电压；在所述显示时段，所述数据线向所述像素单元输出所述显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述补偿电压；
当所述显示电压为正极性电压时，所述显示电压的电压值小于所述补偿电压的电压值，当所述显示电压为负极性电压时，所述显示电压的电压值大于所述补偿电压的电压值。
可选的，在本申请一些实施例中，当所述显示电压为正极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的正极性电压；
当所述显示电压为负极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的负极性电压。
可选的，在本申请一些实施例中，所述补偿电压的电压值根据所述显示电压的电压值实时调整。
可选的，在本申请一些实施例中，当所述显示面板的公共电压为零时，所述显示电压的绝对值小于所述补偿电压的绝对值。
可选的，在本申请一些实施例中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
在所述第一刷新模式下，所述数据电压包括第一显示电压和第一补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第一显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第一补偿电压；当所述第一显示电压为正极性电压时，所述第一显示电压的电压值小于所述第一补偿电压的电压值，当所述第一显示电压为负极性电压时，所述第一显示电压的电压值大于所述第一补偿电压的电压值；
在所述第二刷新模式下，所述数据电压包括第二显示电压和第二补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第二显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第二补偿电压；当所述第二显示电压为正极性电压时，所述第二显示电压的电压值小于所述第二补偿电压的电压值，当所述第二显示电压为负极性电压时，所述第二显示电压的电压值大于所述第一补偿电压的电压值；
其中，所述第一补偿电压与所述第一显示电压之间的压差大于所述第二补偿电压与所述第二显示电压之间的压差。
可选的，在本申请一些实施例中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
在所述第一预设刷新模式下，每一所述垂直消隐阶段包括第一时间段和第二时间段，所述第二时间段的时长等于所述第二预设刷新模式中的所述垂直消隐阶段的时长；
在所述第一时间段内，所述数据线向所述像素单元输出所述补偿电压。
可选的，在本申请一些实施例中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
在所述第二预设刷新模式下，所述数据电压包括第三显示电压和第三补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第三显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第三补偿电压；
当所述第三显示电压为正极性电压时，所述第三补偿电压的电压值大于所述显示面板的最低显示灰阶对应的正极性电压值，当所述第三显示电压为负极性电压时，所述第三补偿电压的电压值小于所述显示面板的最低显示灰阶对应的负极性电压值。
可选的，在本申请一些实施例中，所述显示面板还包括扫描线，所述扫描线与所述数据线交叉设置；
在所述垂直消隐阶段，所述扫描线被配置为输出参考低电平电压；所述参考低电平电压的电压值大于或小于一预设参考低电平电压的电压值。
可选的，在本申请一些实施例中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
在所述第一刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第一参考低电平电压；在所述第二刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第二参考低电平电压；所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于或小于所述预设参考低电平电压的电压值。
 有益效果
本申请提供一种显示面板和电子设备。显示面板包括数据线以及与数据线连接的像素单元。其中，数据线被配置为在每一帧画面显示周期内向像素单元输出数据电压。画面显示周期包括显示时段和垂直消隐阶段。本申请通过在第一预设刷新模式下的至少一帧画面显示周期内，在显示时段，设置数据线向像素单元输出显示电压，在垂直消隐阶段，设置数据线向像素单元输出补偿电压。且当显示电压为正极性电压时，显示电压的电压值小于补偿电压的电压值，当显示电压为负极性电压时，显示电压的电压值大于补偿电压的电压值。从而利用微充电的方式，补偿显示面板在垂直消隐阶段产生的漏电，改善显示面板的显示效果。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的显示面板的一种结构示意图；
图2是本申请提供的显示面板中显示画面周期的一种结构示意图；
图3是本申请提供的显示面板的驱动信号的第一时序图；
图4是本申请提供的显示面板的驱动信号的第二时序图；
图5是本申请提供的显示面板的驱动信号的第三时序图；
图6是本申请提供的显示面板的驱动信号的第四时序图；
图7是本申请提供的显示面板的驱动信号的第五时序图；
图8是本申请提供的N型晶体管的漏电流曲线示意图；
图9是本申请提供的显示面板的驱动信号的第六时序图；
图10是本申请提供的显示面板的驱动信号的第七时序图；
图11是本申请提供的电子设备的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。
本申请提供一种显示面板和电子设备，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1-图3，图1是本申请提供的显示面板的一种结构示意图。图2是本申请提供的显示面板中显示画面周期的一种结构示意图。图3是本申请提供的显示面板的驱动信号的第一时序图。
其中，显示面板100包括数据线11和像素单元20。像素单元20与数据线11连接。数据线11被配置为在每一帧画面显示周期内向像素单元20输出数据电压。画面显示周期包括显示时段AA和垂直消隐阶段VB。在第一预设刷新模式下，在至少一帧画面显示周期内，数据电压包括显示电压D和补偿电压V。在显示时段AA，数据线11向像素单元20输出显示电压D。在垂直消隐阶段VB，数据线11向像素单元20输出补偿电压V。当显示电压D为正极性电压时，显示电压D的电压值小于补偿电压V的电压值。当显示电压D为负极性电压时，显示电压D的电压值大于补偿电压V的电压值。
具体的，显示面板100还包括扫描线12。像素单元20由数据线11和扫描线12交叉限定。像素单元20包括晶体管21和像素电极22。晶体管21的控制端与扫描线12连接。晶体管21的输入端与数据线11连接。晶体管21的输出端与像素电极22连接。此为本领域技术人员熟知的技术，在此不作过多描述。
其中，在显示面板100的画面显示过程中，刷新频率的大小决定了显示画面刷新速率的快慢。其中，刷新频率越大，显示画面的刷新速率越快，即显示画面的切换越频繁。
其中，数据线11、扫描线12以及像素单元20的数量可根据显示面板100的尺寸以及分辨率规格进行设置。数据线11和扫描线12可以垂直交叉，也可以只交叉不垂直。附图仅为示例，不能理解为对本申请的限定。此外，本申请提供的显示面板100采用1G1D（one gate onedata, 一条扫描线一条数据线）的驱动架构，但本申请并不限于此。比如，本申请的显示面板100还可以采用HG2D(half gate two data, 半栅极双数据)等驱动架构，在此不作赘述。
其中，在每一帧的显示阶段AA内，扫描线12被配置为输出扫描信号。扫描信号控制晶体管21打开，进而控制像素单元20逐行打开。数据线11被配置为输出数据电压，以向相应的像素单元20充电。在每一帧的垂直消隐阶段VB内，晶体管21均关闭。像素单元20维持当前帧的显示画面。
具体的，显示面板100中的每一帧均包括显示阶段AA和垂直消隐阶段VB。在每一帧的显示阶段AA内，多条数据线11被配置为分别输出每一行像素单元20对应的显示数据，例如红绿蓝(RGB)显示电压，从而在一帧内点亮所有像素单元20。在垂直消隐阶段VB内，多条数据线11被配置为分别输出每一行像素单元20对应的消隐数据，例如每一行像素单元20对应的消隐数据均为0灰阶信号（最低灰阶信号），即黑阶信号。只有当下一帧同一行像素单元20的显示数据来到时，才能把上一帧此行像素单元20的内容覆盖。因此，理想情况下，在垂直消隐阶段VB内，每一像素单元20的像素电极22的电位维持在当前帧的显示电压的电位。
但是，由于晶体管21的开关特性，在每一帧的垂直消隐阶段VB内，晶体管21并不能完全关闭，会存在一定的漏电流。可以理解的是，本申请提供的显示面板100为液晶显示面板。液晶显示面板在显示时，亮度强弱由加在液晶两侧的电压差决定。液晶一侧的电压是固定的，即为公共电压VCOM。另一侧的电压即为像素电极22的电压。则当像素电极22处漏电时，像素电极22与公共电压VCOM之间的压差会减小，导致像素单元20的亮度会降低。此外，由于液晶的特性，故需不断地交替提供正负极性的电压给像素单元20。其中，电压值大于公共电压VCOM的为正极性电压，电压值小于公共电压VCOM的为负极性电压。
由此，本申请在第一预设刷新模式下，在至少一帧画面显示周期内，当显示电压D为正极性电压时，设置显示电压D的电压值小于补偿电压V的电压值。则晶体管21的输入端的电压大于输出端的电压，晶体管21的输入端向输出端漏电。从而通过微充电的方式提高像素电极22的电位，增大液晶两侧的电压差，提高像素单元20的亮度。当显示电压D为负极性电压时，设置显示电压D的电压值大于补偿电压V的电压值。则晶体管21的输入端的电压小于输出端的电压，晶体管21的输出端向输入端漏电。像素电极22的电位减小，同样增大液晶两侧的电压差，提高像素单元20的亮度。由此，对像素电极22在垂直消隐阶段VB内的漏电进行补偿，提高显示面板100的显示效果。
需要说明的是，由于本申请采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。在本申请中，晶体管21的控制端为栅极，晶体管21的输入端为源极，晶体管21的输出端为漏极。
此外，本申请中所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。需要说明的是，本申请以下实施例中的晶体管均以N型晶体管为例进行说明，但不能理解为对本申请的限制。
可以理解的是，显示面板100的公共电压VCOM的取值需要根据显示面板100的显示需求进行设定。当显示面板100的公共电压VCOM为0时，显示电压D的绝对值小于补偿电压V的绝对值。
当然，显示面板100的公共电压VCOM也可不设置为0。比如，在一些实施例中，显示面板100的公共电压VCOM设置为7V或其它电压值。则需要满足，当显示电压D为正极性电压时，显示电压D的电压值小于补偿电压V的电压值。当显示电压D为负极性电压时，显示电压D的电压值大于补偿电压V的电压值。
在本申请中，在第一预设频率模式中，可以仅对至少一帧画面显示周期进行漏电补偿，降低显示面板100的功耗。在第一预设频率模式中，也可以对所有画面显示周期进行均漏电补偿，以最大限度的保证显示面板100在第一预设频率模式下的显示亮度。本申请以下各实施例均以在每一帧画面显示周期的垂直消隐阶段VB内，对像素电极22进行漏电补偿为例进行说明，但不能理解为对本申请的限定。
在本申请中，当显示电压D为正极性电压时，补偿电压V为显示面板100的最高显示灰阶对应的正极性电压。当显示电压D为负极性电压时，补偿电压V为显示面板100的最高显示灰阶对应的负极性电压。
比如，若输入显示面板100的图像显示数据是二进制8bit，则会产生2的8次方个从最暗到最亮的亮度灰阶。即产生256级不同亮度灰阶(比如，记作第0灰阶～第255灰阶)。其中，假设第255灰阶对应的显示亮度最大，也即第255灰阶对应的电压值最大。当然，本申请的显示面板100接收的图像显示数据也可以是二进制6bit、二进制10bit等。本申请以8bit为例进行说明，但不能理解为对本申请的限定。
可以理解的是，在第一预设刷新模式下的每一帧显示画面周期中，每一像素单元20均对应有一显示电压D。显示电压D可以是0-255灰阶中的任一灰阶电压。本申请根据显示面板100的最高显示灰阶对应设置补偿电压V。比如，当显示电压D为正极性电压时，设置补偿电压V为显示面板100的最高显示灰阶对应的正极性电压，可以保证在垂直消隐阶段VB内，每一晶体管21的输入端的电压均大于或等于输出端的电压。由此，晶体管21的输入端向输出端漏电，从而对像素电极22进行微充电，提高像素电极22的电位，进而补偿像素电极22在第一刷新模式的垂直消隐阶段VB内的漏电。当显示电压D为负极性电压时亦然，在此不再赘述。
此外，以正极性电压为例，在显示面板100的驱动装置中，通常需要设计逻辑电路以对每一像素单元20对应的补偿电压V进行判断输出，以保证每一像素单元20对应的补偿电压V的电压值均大于相应的显示电压D的电压值。本申请将补偿电压V统一设置为显示面板100的最高显示灰阶对应的正极性电压。一方面，可以简化逻辑电路，降低显示面板100的信号复杂度。另一方面，也可保证每一像素单元20对应的补偿电压V的电压值均大于相应的显示电压D的电压值，达到补偿的效果。
当然，在本申请其它实施例中，补偿电压V的电压值可根据显示电压D的电压值实时调整。也即，可针对每一像素单元20对应的显示电压D设置补偿电压V，只要保证补偿电压V的电压值大于显示电压D的电压值即可，从而降低显示面板100的功耗。
在本申请中，第一预设频率模式可以只包括一种刷新模式。在该刷新模式下，通过微充电的方式对显示面板100的漏电进行补偿，可以提高显示面板100的显示亮度。
当然，第一预设频率模式也可以包括多种刷新模式。可以理解的是，在不同刷新频率下，画面显示周期的垂直消隐阶段VB时长不同，会产生不同大小的漏电流。不同大小的漏电流会导致显示面板显示画面的亮度不同。因此，当显示面板的刷新率变化时，显示面板可能会出现闪烁现象。
对此，请同时参阅图1和图4，图4是本申请提供的显示面板的驱动信号的第二时序图。与图3所示的显示面板100的驱动信号的不同之处在于，在本实施例中，第一预设刷新模式包括第一刷新模式和第二刷新模式。第一刷新模式的刷新频率小于第二刷新模式的刷新频率。
其中，在第一刷新模式下，数据电压包括第一显示电压D1和第一补偿电压V1。在显示时段AA，数据线11向像素单元20输出第一显示电压D1。在垂直消隐阶段VB，数据线11向像素单元20输出第一补偿电压V1。当第一显示电压D1为正极性电压时，第一显示电压D1的电压值小于第一补偿电压V1的电压值。当第一显示电压D1为负极性电压时，第一显示电压D1的电压值大于第一补偿电压V1的电压值。
其中，在第二刷新模式下，数据电压包括第二显示电压D2和第二补偿电压V2。在显示时段AA，数据线11向像素单元20输出第二显示电压D2。在垂直消隐阶段VB，数据线11向像素单元20输出第二补偿电压V2。当第二显示电压D2为正极性电压时，第二显示电压D2的电压值小于第二补偿电压V2的电压值。当第二显示电压D2为负极性电压时。第二显示电压D2的电压值大于第二补偿电压V2的电压值。
由于第一刷新模式的刷新频率小于第二刷新模式的刷新模式，第一刷新模式的每一垂直消隐阶段VB的时长大于第二刷新模式的每一垂直消隐阶段VB的时长。垂直消隐阶段VB的时长越长，代表显示面板100当前显示的画面维持时间越久。像素电极22上的电压也需维持更长的时间。同时，晶体管21漏电的情况也越严重。也即，相较于第二刷新模式，在第一刷新模式中，像素电极22的亮度减小更多。
此外，除了晶体管21关闭不彻底导致的漏电，显示面板100中还存在其它导致漏电的因素，如光致漏电等。同理，由于第一刷新模式的垂直消隐阶段VB的时长较长，同样相较于第二刷新模式，第一刷新模式中的像素电极22在垂直消隐阶段VB也会产生更多的漏电。
因此，本实施例在第一刷新模式和第二刷新模式中，均通过向像素电极22微充电的方式补偿像素电极22的漏电，可以减少像素电极22在第一刷新模式和第二刷新模式下因晶体管21漏电导致的电位差异。同时对第一刷新模式和第二刷新模式下的像素电极22均进行补偿，达到补偿和漏电的平衡，提高显示面板100的整体显示效果。
进一步的，在本申请一些实施例中，第一补偿电压V1和第一显示电压D1之间的压差大于第二补偿电压V2与第二显示电压D2之间的压差。
可以理解的是，本申请根据晶体管21的漏电特性，对像素电极22进行微电流补偿。晶体管21的输入端与输出端之间的压差越大，漏电流越大，对像素电极22的补偿效果越好。由于第一刷新模式下每一垂直消隐阶段VB的时长较长，像素电极22在第一刷新模式下的漏电程度大于在第二刷新模式下的漏电程度。因此，本实施例通过设置第一补偿电压V1和第一显示电压D1之间的压差大于第二补偿电压V2与第二显示电压D2之间的压差，可以提高对第一刷新模式下的像素电极22的充电量，增大对第一刷新模式下的像素电极22的补偿力度，从而进一步减小显示面板100在不同刷新频率下显示画面的亮度差。
当然，在本申请其它实施例中，当第一刷新模式和第二刷新模式下的亮度相差较大时，也可以仅对第一刷新模式下的像素单元20进行补偿，以避免在画面切换时出现画面闪烁。
在本申请中，第一刷新模式和第二刷新模式的显示阶段AA的持续时长相同。也即，像素单元20在第一刷新模式和第二刷新模式下的充电时间相等。因此，通常仅通过改变显示面板100的帧周期中的垂直消隐阶段VB的时长来动态调节显示面板100的刷新频率。
请同时参阅图1和图5，图5是本申请提供的显示面板的驱动信号的第三时序图。与图3所示的显示面板100的驱动信号的不同之处在于，在本实施例中，显示面板还具有第二预设刷新模式。第二预设刷新模式的刷新频率大于第一预设刷新模式的刷新频率。
本申请仅在第一预设刷新模式的至少一帧的垂直消隐阶段VB内，向像素单元20提供补偿电压V，通过微充电的方式，对像素电极22在垂直消隐阶段VB内的漏电进行补偿，减小显示面板100在第一预设刷新模式和第二预设刷新模式下显示画面的亮度差，避免在画面切换时出现画面闪烁。
进一步的，请同时参阅图1和图6，图6是本申请提供的显示面板的驱动信号的第四时序图。与图5所示的显示面板100的驱动信号的不同之处在于，在本实施例中，在第一预设刷新模式下，每一垂直消隐阶段VB包括第一时间段T1和第二时间段T2。第二时间段T2的时长等于第二预设刷新模式中的垂直消隐阶段VB的时长。在第一时间段T1内，数据线11向像素单元20输出补偿电压V。
可以理解的是，像素电极22在第一刷新模式和第二刷新模式中的漏电程度不同，主要是由于第一预设刷新模式中每一垂直消隐阶段VB的时长大于第二预设刷新模式中每一垂直消隐阶段VB的时长。因此，本实施例仅在第一时间段T1内，为数据线11配置第一补偿电压V1，并设置第二时间段T2的时长等于第二刷新模式中每一垂直消隐阶段VB的时长。一方面，可以使像素电极22在第一预设刷新模式中和第二预设刷新模式中，由于晶体管21导致漏电的时长保持一致，从而减少由晶体管21产生的漏电差异。另一方面，可以在第一时间段T1内对像素电极22进行微充电补偿，进而对像素电极22在第一刷新模式下由于其它因素造成的漏电进行补偿，进一步减小像素电极22在第一预设刷新模式和第二预设刷新模式中的漏电差异，减小显示面板100在不同刷新频率下显示画面的亮度差。
请同时参阅图1和图7，图7是本申请提供的显示面板的驱动信号的第五时序图。与图5所示的显示面板100的驱动信号的不同之处在于，在本实施例中，在第二预设刷新模式下，数据电压包括第三显示电压D3和第三补偿电压V3。在显示时段AA，数据线11向像素单元20输出第三显示电压D3。在垂直消隐阶段VB。数据线11向像素单元20输出第三补偿电压V3。
当第三显示电压D3为正极性电压时，第三补偿电压V3的电压值大于显示面板100的最低显示灰阶对应的正极性电压值。当第三显示电压D3为负极性电压时，第三补偿电压V3的电压值小于显示面板100的最低显示灰阶对应的负极性电压值。
可以理解的是，在垂直消隐阶段VB，通常数据线被配置为向像素单元20输出黑灰阶信号，即显示面板100的最低显示灰阶信号。因此，本实施例在第三显示电压D3为正极性电压时，设置第三补偿电压V3的电压值大于显示面板100的最低显示灰阶对应的正极性电压值，可以加剧像素电极22在垂直消隐阶段VB内的漏电。也即通过提高显示面板100在第二预设刷新模式下漏电，减小像素电极22在第一预设刷新模式和第二预设刷新模式中的漏电差异。同理，本实施例在第三显示电压D3为负极性电压时，设置第三补偿电压V3的电压值小于显示面板100的最低显示灰阶对应的负极性电压值，可以加剧像素电极22在垂直消隐阶段VB内的漏电。
当然，在本申请其它实施例中，为了减少显示面板100的功耗。当第一刷新模式和第二刷新模式下的亮度相差较小时，也可以仅对第二刷新模式下的像素单元20进行进一步的漏电，以减小像素电极22在第一预设刷新模式和第二预设刷新模式中的漏电差异。
进一步的，在本申请中，在每一帧画面显示周期的垂直消隐阶段VB内，扫描线12输出相应的参考低电平电压，使得晶体管21关闭。参考低电平电压的电位可根据晶体管21的开关特性进行设计。
具体的，请参阅图8，图8是本申请提供的N型晶体管的漏电流曲线示意图。其中，横坐标为参考低电平电压的电压值，单位为伏特（V）。纵坐标为晶体管21的漏电流，单位为安（I）。由图6可知，晶体管21在关闭时，并不是处于完全关闭状态，仍会有一定的关态漏电流产生。但是，对于晶体管21而言，在预设参考低电平电压V0的控制下，晶体管21具有最小的漏电流。
对此，请同时参阅图1和图9，图9是本申请提供的显示面板的驱动信号的第四时序图。与图6所示的显示面板100的驱动时序的不同之处在于，在本实施例中，在一帧的垂直消隐阶段VB内，扫描线12被配置为输出参考低电平电压VSSG。参考低电平电压VSSG的电压值大于或小于一预设参考低电平电压V0的电压值。
对此，可以理解的是，本实施例在垂直消隐阶段VB内对像素电极22进行微充电补偿，利用的就是晶体管21的漏电。由于预设参考低电平电压V0对应晶体管21的最小漏电流。则本实施例设置参考低电平电压VSSG的电压值大于或小于预设参考低电平电压V0的电压值，可以提高晶体管21的漏电能力，增大对像素电极22的电位的补偿，进而避免显示面板100的亮度变暗。
需要说明的是，P型晶体管的漏电流曲线与N型晶体管的漏电流曲线类似，在此不再赘述。
请同时参阅图1和图10，图10是本申请提供的显示面板的驱动信号的第五时序图。与图9所示的显示面板100的驱动时序的不同之处在于，在本实施例中，在第一预设刷新模式中，在每一帧的垂直消隐阶段VB内，扫描线12被配置为输出第一参考低电平电压VSSQ1。在第二预设刷新模式中，在每一帧的垂直消隐阶段VB内，扫描线12被配置为输出第二参考低电平电压VSSQ2。
其中，第一参考低电平电压VSSQ1的电压值大于或小于预设参考低电平电压V0的电压值。第二参考低电平电压VSSQ2的电压值大于或小于预设参考低电平电压V0的电压值。
由上述分析可知，在预设参考低电平电压V0的驱动下，晶体管21在关闭状态下的漏电流最小。因此，本实施例设置第一参考低电平电压VSSQ1的电压值大于或小于预设参考低电平电压V0的电压值，可以增大晶体管21在第一刷新模式的垂直消隐阶段VB内的漏电。同理，本实施例设置第二参考低电平电压VSSQ2的电压值大于或小于预设参考低电平电压V0的电压值，可以增大晶体管21在第二刷新模式的垂直消隐阶段VB内的漏电。
进一步的，在本申请一些实施例中，第一参考低电平电压VSSQ1的电压值和第二参考低电平电压VSSQ2的电压值相等。
可以理解的是，在显示面板100的驱动装置中，通常需要设计逻辑电路以输出相应的参考低电平电压VSSQ1和参考低电平电压VSSQ2。本申请设置参考低电平电压VSSQ1的电压值和参考低电平电压VSSQ2的电压值相等，可以简化逻辑电路，降低显示面板100中的信号复杂度。
在本申请一些实施例中，当第一参考低电平电压VSSQ1的电压值和第二参考低电平电压VSSQ2的电压值均小于参考低电平电压VSSQ的电压值时，第一参考低电平电压VSSQ1的电压值小于第二参考低电平电压VSSQ2的电压值。
由上述分析可知，当第一参考低电平电压VSSQ1的电压值和第二参考低电平电压VSSQ2的电压值均小于参考低电平电压V0的电压值时，设置第一参考低电平电压VSSQ1的电压值小于第二参考低电平电压VSSQ2的电压值，则晶体管21在第一参考低电平电压VSSQ1的控制下的漏电流大于晶体管21在第二参考低电平电压VSSQ2的控制下的漏电流。
可以理解的是，本申请通过晶体管21的漏电对像素电极22进行微充电补偿。晶体管21的漏电流越大，对像素电极22的补偿效果越好。由于像素电极22在第一刷新模式下的漏电程度大于在第二刷新模式下的漏电程度。因此，本实施例通过设置第一参考低电平电压VSSQ1的电压值小于第二参考低电平电压VSSQ2的电压值，可以提高对第一刷新模式下的像素电极22的充电量，增大对第一刷新模式下的像素电极22的补偿力度，从而进一步减小显示面板100在不同刷新频率下显示画面的亮度差。
在本申请一些实施例中，当第一参考低电平电压VSSQ1的电压值和第二参考低电平电压VSSQ2的电压值均大于参考低电平电压V0的电压时，第一参考低电平电压VSSQ1的电压值大于第二参考低电平电压VSSQ2的电压值。
由上述分析可知，当第一参考低电平电压VSSQ1的电压值和第二参考低电平电压VSSQ2的电压值均大于参考低电平电压V0的电压值时，设置第一参考低电平电压VSSQ1的电压值大于第二参考低电平电压VSSQ2的电压值，则晶体管21在第一参考低电平电压VSSQ1的控制下的漏电流大于晶体管21在第二参考低电平电压VSSQ2的控制下的漏电流。
可以理解的是，本申请通过晶体管21的漏电对像素电极22进行微充电补偿。晶体管21的漏电流越大，对像素电极22的补偿效果越好。由于像素电极22在第一刷新模式下的漏电程度大于在第二刷新模式下的漏电程度。因此，本实施例通过设置第一参考低电平电压VSSQ1的电压值大于第二参考低电平电压VSSQ2的电压值，可以提高对第一刷新模式下的像素电极22的充电量，增大对第一刷新模式下的像素电极22的补偿力度，从而进一步减小显示面板100在不同刷新频率下显示画面的亮度差。
相应的，本申请还提供一种电子设备，其包括显示面板和驱动装置。驱动装置用于提供驱动信号至显示面板。驱动信号可以是上述实施例中的参考低电平电压、第一显示电压、第一补偿电压、第二显示电压、第二补偿电压等。显示面板为上述任一实施例所述的显示面板，在此不再赘述。
本申请中的电子设备可以是智能手机、平板电脑、视频播放器、个人计算机（PC）等，本申请对此不作限定。
具体的，请参阅图11，图11是本申请提供的电子设备的一种结构示意图。其中，电子设备1000包括显示面板100和驱动装置200。驱动装置200用于提供驱动信号至显示面板100。
其中，驱动装置200包括但不限于时序控制器201、数据驱动电路202以及栅极驱动电路203。具体的，时序控制器201用于提供显示数据至数据驱动电路202。数据驱动电路202用于在每一帧的显示阶段，通过数据线11向像素单元20输出数据电压。数据驱动电路202还用于在每一帧的垂直消隐阶段，通过数据线11向像素单元20输出补偿电压。栅极驱动电路203用于输出参考低电位电压等扫描信号至扫描线12。
当然，在其它实施例中，可以在显示面板100中集成设置阵列基板栅极驱动电路(Gate DriveronArray，简称GOA)，以替代栅极驱动电路203，从而实现窄边框。
本申请提供一种电子设备，其包括显示面板100。显示面板100包括数据线11以及与数据线11连接的像素单元20。其中，数据线11被配置为在每一帧画面显示周期内向像素单元20输出数据电压。画面显示周期包括显示时段和垂直消隐阶段。本申请通过在第一预设刷新模式下的至少一帧画面显示周期内，在显示时段，设置数据线11向像素单元20输出显示电压，在垂直消隐阶段，设置数据线11向像素单元20输出补偿电压。且当显示电压为正极性电压时，显示电压的电压值小于补偿电压的电压值，当显示电压为负极性电压时，显示电压的电压值大于补偿电压的电压值。从而利用微充电的方式，补偿显示面板100在垂直消隐阶段产生的漏电，改善显示面板的显示效果。且当显示面板100包括多个刷新模式时，减小显示面板100在不同刷新频率下显示画面的亮度差，避免在画面切换时出现画面闪烁。
以上对本申请提供的显示面板和电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其包括：
    数据线；
    像素单元，所述像素单元与所述数据线连接；其中，
    所述数据线被配置为在每一帧画面显示周期内向所述像素单元输出数据电压，所述画面显示周期包括显示时段和垂直消隐阶段；在第一预设刷新模式下，在至少一帧所述画面显示周期内，所述数据电压包括显示电压和补偿电压；在所述显示时段，所述数据线向所述像素单元输出所述显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述补偿电压；
    当所述显示电压为正极性电压时，所述显示电压的电压值小于所述补偿电压的电压值，当所述显示电压为负极性电压时，所述显示电压的电压值大于所述补偿电压的电压值。
  2. 根据权利要求1所述的显示面板，其中，当所述显示电压为正极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的正极性电压；
    当所述显示电压为负极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的负极性电压。
  3. 根据权利要求1所述的显示面板，其中，所述补偿电压的电压值根据所述显示电压的电压值实时调整。
  4. 根据权利要求1所述的显示面板，其中，当所述显示面板的公共电压为零时，所述显示电压的绝对值小于所述补偿电压的绝对值。
  5. 根据权利要求1所述的显示面板，其中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
    在所述第一刷新模式下，所述数据电压包括第一显示电压和第一补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第一显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第一补偿电压；当所述第一显示电压为正极性电压时，所述第一显示电压的电压值小于所述第一补偿电压的电压值，当所述第一显示电压为负极性电压时，所述第一显示电压的电压值大于所述第一补偿电压的电压值；
    在所述第二刷新模式下，所述数据电压包括第二显示电压和第二补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第二显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第二补偿电压；当所述第二显示电压为正极性电压时，所述第二显示电压的电压值小于所述第二补偿电压的电压值，当所述第二显示电压为负极性电压时，所述第二显示电压的电压值大于所述第一补偿电压的电压值；
    其中，所述第一补偿电压与所述第一显示电压之间的压差大于所述第二补偿电压与所述第二显示电压之间的压差。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
    在所述第一预设刷新模式下，每一所述垂直消隐阶段包括第一时间段和第二时间段，所述第二时间段的时长等于所述第二预设刷新模式中的所述垂直消隐阶段的时长；
    在所述第一时间段内，所述数据线向所述像素单元输出所述补偿电压。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
    在所述第二预设刷新模式下，所述数据电压包括第三显示电压和第三补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第三显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第三补偿电压；
    当所述第三显示电压为正极性电压时，所述第三补偿电压的电压值大于所述显示面板的最低显示灰阶对应的正极性电压值，当所述第三显示电压为负极性电压时，所述第三补偿电压的电压值小于所述显示面板的最低显示灰阶对应的负极性电压值。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括扫描线，所述扫描线与所述数据线交叉设置；
    在所述垂直消隐阶段，所述扫描线被配置为输出参考低电平电压；所述参考低电平电压的电压值大于或小于一预设参考低电平电压的电压值。
  9. 根据权利要求8所述的显示面板，其中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
    在所述第一刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第一参考低电平电压；在所述第二刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第二参考低电平电压；所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于或小于所述预设参考低电平电压的电压值。
  10. 根据权利要求9所述的显示面板，其中，所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值相等。
  11. 根据权利要求9所述的显示面板，其中，当所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均小于所述预设参考低电平电压的电压值时，所述第一参考低电平电压的电压值小于所述第二参考低电平电压的电压值；
    当所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于所述预设参考低电平电压的电压时，所述第一参考低电平电压的电压值大于所述第二参考低电平电压的电压值。
  12. 一种电子设备，其包括显示面板和驱动装置，所述驱动装置用于提供数据电压至所述显示面板，所述显示面板包括：
    数据线；
    像素单元，所述像素单元与所述数据线连接；其中，
    所述数据线被配置为在每一帧画面显示周期内向所述像素单元输出数据电压，所述画面显示周期包括显示时段和垂直消隐阶段；在第一预设刷新模式下，在至少一帧所述画面显示周期内，所述数据电压包括显示电压和补偿电压；在所述显示时段，所述数据线向所述像素单元输出所述显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述补偿电压；
    当所述显示电压为正极性电压时，所述显示电压的电压值小于所述补偿电压的电压值，当所述显示电压为负极性电压时，所述显示电压的电压值大于所述补偿电压的电压值。
  13. 根据权利要求12所述的电子设备，其中，当所述显示电压为正极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的正极性电压；
    当所述显示电压为负极性电压时，所述补偿电压为所述显示面板的最高显示灰阶对应的负极性电压。
  14. 根据权利要求12所述的电子设备，其中，所述补偿电压的电压值根据所述显示电压的电压值实时调整。
  15. 根据权利要求12所述的电子设备，其中，当所述显示面板的公共电压为零时，所述显示电压的绝对值小于所述补偿电压的绝对值。
  16. 根据权利要求12所述的电子设备，其中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
    在所述第一刷新模式下，所述数据电压包括第一显示电压和第一补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第一显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第一补偿电压；当所述第一显示电压为正极性电压时，所述第一显示电压的电压值小于所述第一补偿电压的电压值，当所述第一显示电压为负极性电压时，所述第一显示电压的电压值大于所述第一补偿电压的电压值；
    在所述第二刷新模式下，所述数据电压包括第二显示电压和第二补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第二显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第二补偿电压；当所述第二显示电压为正极性电压时，所述第二显示电压的电压值小于所述第二补偿电压的电压值，当所述第二显示电压为负极性电压时，所述第二显示电压的电压值大于所述第一补偿电压的电压值；
    其中，所述第一补偿电压与所述第一显示电压之间的压差大于所述第二补偿电压与所述第二显示电压之间的压差。
  17. 根据权利要求12所述的电子设备，其中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
    在所述第一预设刷新模式下，每一所述垂直消隐阶段包括第一时间段和第二时间段，所述第二时间段的时长等于所述第二预设刷新模式中的所述垂直消隐阶段的时长；
    在所述第一时间段内，所述数据线向所述像素单元输出所述补偿电压。
  18. 根据权利要求12所述的电子设备，其中，所述显示面板还具有第二预设刷新模式，所述第二预设刷新模式的刷新频率大于所述第一预设刷新模式的刷新频率；
    在所述第二预设刷新模式下，所述数据电压包括第三显示电压和第三补偿电压，在所述显示时段，所述数据线向所述像素单元输出所述第三显示电压，在所述垂直消隐阶段，所述数据线向所述像素单元输出所述第三补偿电压；
    当所述第三显示电压为正极性电压时，所述第三补偿电压的电压值大于所述显示面板的最低显示灰阶对应的正极性电压值，当所述第三显示电压为负极性电压时，所述第三补偿电压的电压值小于所述显示面板的最低显示灰阶对应的负极性电压值。
  19. 根据权利要求12所述的电子设备，其中，所述显示面板还包括扫描线，所述扫描线与所述数据线交叉设置；
    在所述垂直消隐阶段，所述扫描线被配置为输出参考低电平电压；所述参考低电平电压的电压值大于或小于一预设参考低电平电压的电压值。
  20. 根据权利要求19所述的电子设备，其中，所述第一预设刷新模式包括第一刷新模式和第二刷新模式，所述第一刷新模式的刷新频率小于所述第二刷新模式的刷新频率；
    在所述第一刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第一参考低电平电压；在所述第二刷新模式下，在所述垂直消隐阶段，所述扫描线被配置为输出第二参考低电平电压；所述第一参考低电平电压的电压值和所述第二参考低电平电压的电压值均大于或小于所述预设参考低电平电压的电压值。
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