WO2023019909A1 - 谐波抑制电路、功率放大器模组、通信设备、通信系统 - Google Patents

谐波抑制电路、功率放大器模组、通信设备、通信系统 Download PDF

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WO2023019909A1
WO2023019909A1 PCT/CN2022/078355 CN2022078355W WO2023019909A1 WO 2023019909 A1 WO2023019909 A1 WO 2023019909A1 CN 2022078355 W CN2022078355 W CN 2022078355W WO 2023019909 A1 WO2023019909 A1 WO 2023019909A1
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harmonic suppression
suppression circuit
capacitor
resonator
inductor
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PCT/CN2022/078355
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English (en)
French (fr)
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许靓
龙华
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深圳飞骧科技股份有限公司
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Publication of WO2023019909A1 publication Critical patent/WO2023019909A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • This application relates to the field of communications, in particular to a harmonic suppression circuit suitable for 5G-NR radio frequency power amplifiers, a power amplifier module, a communication device, a communication system and a chip.
  • 5G NR generally adopts the global 5G standard based on the new air interface design based on OFDM.
  • the technology standard is 100 times faster than the previous 4G LTE cellular network.
  • the data transfer rate can reach up to 10Gbit/s. Such a high data transmission rate puts forward higher linear power requirements for the power amplifier in the RF front-end module.
  • the power amplifier PA is a nonlinear device. When outputting high linear power, the power amplifier PA works in the non-linear region, which will generate a series of harmonic components. Therefore, the ability of the power amplifier module itself to suppress harmonics has become an important indicator for evaluating its overall performance.
  • harmonic suppression circuits of the existing mobile phone power amplifier module products use a series resonant circuit-trap or a parallel resonant circuit-tank on the Laminate substrate to improve the ability to suppress harmonics.
  • Most of the components that make up the trap or tank circuit network are composed of SMT. As the number of integrated components in 5G PA modules increases, the substrate design becomes more complex, and the space left for SMT becomes more limited.
  • the application provides a harmonic suppression circuit suitable for 5G-NR radio frequency power amplifiers, including: a first resonator and a second resonator connected in parallel; the first resonator includes a first resonator connected in series an inductor and a first capacitor; the second resonator includes a second inductor and a second capacitor connected in series; the harmonic suppression circuit operates at a first frequency; the first resonator and the second resonator At least one of the oscillators resonates at the first frequency; the first resonator and the second resonator resonate in parallel at a first preset integer multiple of the first frequency.
  • the first inductor and the second capacitor may satisfy the following formula:
  • f1 is the first preset frequency
  • L1 is the first inductor
  • C1 is the first capacitor
  • L2 is the second inductor
  • C2 is the second capacitor
  • the first inductor, the first capacitor, the second inductor, and the second capacitor may satisfy the following formula:
  • f 2 is the first preset integer multiple of the first preset frequency
  • L 1 is the first inductor
  • L 2 is the second inductor
  • C 1 is the first capacitor
  • C 2 is the second capacitor.
  • the first preset integer multiple is 2 times; the first preset frequency is 2.5GHz; the first inductor is 0.2nH; the first capacitor is 2.5pF; the second The inductor is 0.28nH; the second capacitor is 13pF.
  • At least one of the first inductor and the second inductor is a microstrip line.
  • At least one of the first capacitor and the second capacitor is integrated on an element directly connected to the harmonic suppression circuit.
  • one end of the harmonic suppression circuit is connected to a radio frequency power amplifier, and the other end is connected to a radio frequency switch; at least one of the first capacitor and the second capacitor is integrated in the radio frequency switch and/or the radio frequency power amplifier.
  • An embodiment of the present application also provides a power amplifier module, including: a power amplifier; any one of the aforementioned harmonic suppression circuits, connected to the power amplifier.
  • An embodiment of the present application further provides a communication device, including: any one of the foregoing harmonic suppression circuits and/or any one of the foregoing power amplifier modules.
  • An embodiment of the present application further provides a communication system, including: any one of the foregoing harmonic suppression circuits and/or any one of the foregoing power amplifier modules.
  • An embodiment of the present application further provides a chip, including: any one of the aforementioned harmonic suppression circuits and/or any of the aforementioned power amplifier modules.
  • two groups of LC series resonators connected in parallel can achieve almost lossless transmission of fundamental wave signals and at the same time realize harmonic suppression of preset harmonic signals.
  • At least one of the two sets of LC series resonators can resonate near the fundamental frequency. So that at the fundamental frequency, the parallel impedance of the two LC series resonators can be close to zero. Therefore, at the fundamental frequency, the influence of the harmonic suppression circuit provided by the present application on the transmission impedance can be very small, for example, it can be very close to 50 ⁇ .
  • the harmonic suppression circuit provided in the present application two groups of LC series resonators can resonate in parallel around the preset harmonic frequency of the fundamental frequency signal. Therefore, the parallel impedance of the two sets of LC series resonators can be relatively large. The larger impedance can cause the harmonic suppression circuit provided in the present application to have a larger attenuation effect on the harmonic frequency. Therefore, it can be realized that the predetermined harmonic frequency signal is greatly attenuated while almost not affecting the transmission of the fundamental wave signal.
  • the circuit topology of the harmonic suppression circuit provided by the present application is very simple, the aforementioned technical effects can be achieved without increasing the complexity of the substrate circuit. Since the LC parameter of the harmonic suppression circuit provided by the application can be small, the inductor involved in the harmonic suppression circuit provided by the application can be a microstrip line, and the capacitor involved in the application can be integrated directly with the harmonic suppression circuit. connected device. Therefore, the complexity of the circuit can be further reduced, and the cost can be reduced.
  • FIG. 1 shows a schematic diagram of the principle of a harmonic suppression circuit according to an embodiment of the present application.
  • Fig. 2 shows a schematic diagram of the principle of a harmonic suppression circuit according to an embodiment of the present application.
  • FIG. 5 shows a schematic diagram of the Smith circle simulation at the terminal Term1 of the harmonic suppression circuit shown in FIG. 2 .
  • Fig. 6 shows a schematic diagram of topology connection of a power amplifier module according to an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of the principle of a harmonic suppression circuit according to an embodiment of the present application.
  • the harmonic suppression circuit 1000 can work at the fundamental frequency f 1 .
  • the harmonic suppression circuit 1000 can pass the fundamental signal with the fundamental frequency f 1 and can be used to suppress the harmonic signal of the fundamental signal with the frequency f 2 .
  • the harmonic suppression circuit 1000 may include a resonator 11 and a resonator 12 connected in parallel.
  • the resonator 11 may include an inductor L 1 and a capacitor C 1 connected in series.
  • Resonator 12 may include an inductor L 2 and a capacitor C 2 connected in series.
  • inductor L1 and capacitor C1 can satisfy the following relationship:
  • the resonator 11 and the resonator 12 can resonate in parallel around the harmonic frequency f 2 , wherein the harmonic frequency f 2 can be a preset integer multiple of the fundamental frequency f 1 .
  • the harmonic frequency f 2 may be twice the fundamental frequency f 1 .
  • inductors L 1 , L 2 and capacitors C 1 , C 2 may satisfy the following relationship:
  • At least one of the two ends Term1 and Term2 of the harmonic suppression circuit 1000 may be connected with a matching resistor.
  • the matching resistor can make the output/output impedance of at least one of the terminals Term1 and Term2 be 50 ⁇ .
  • the resonator 11 consisting of the inductor L1 and the capacitor C1 connected in series can be equivalent to a capacitance as seen from the port Term1.
  • a resonator 12 composed of an inductor L2 and a capacitor C2 connected in series can be equivalent to an inductance.
  • the equivalent inductance and equivalent capacitance form a parallel resonator tank.
  • the resonant frequency of the parallel resonator tank can be located just around the harmonic frequency f2 .
  • the resonator 11 and/or the resonator 12 resonate precisely in the vicinity of the fundamental frequency f 1 . Therefore, at the fundamental frequency f1 , viewed from the port Term1, the impedance of the harmonic suppression circuit 1000 basically does not change, and is still 50 ⁇ .
  • the impedance Z11 of the resonator 11 can be expressed as:
  • the impedance Z 11 can have a pair of zero points, which is:
  • the impedance Z 11 of the resonator 11 can be very small.
  • the impedance Z 1000 of the harmonic suppression circuit 1000 is also very small. Therefore, for the fundamental signal with the fundamental frequency f 1 , the harmonic suppression circuit 1000 has relatively small attenuation.
  • the resonator 12 may also resonate near the fundamental frequency f 1 .
  • the inductor L 2 and the capacitor C 2 can satisfy the relationship shown in formula (2). Similar to the resonator 11, when the resonator 12 resonates at the fundamental frequency f1 , that is, when the inductor L2 and the capacitor C2 satisfy the relationship shown in formula (2), the resonator 12 at the fundamental frequency f1
  • the impedance Z 12 is very small, and correspondingly, at the fundamental frequency f 1 , the impedance Z of the harmonic suppression circuit 1000 must also be very small. That is, for the signal whose fundamental frequency is f 1 , the harmonic suppression circuit 1000 has very good transmission characteristics.
  • the impedance Z of the harmonic suppression circuit 1000 is very small at the fundamental frequency f 1 .
  • the transmission impedance of the signal with the fundamental frequency f 1 embedded in the power amplifier circuit of the harmonic suppression circuit 1000 may be less affected by the harmonic suppression circuit 1000 .
  • the impedance Z 1000 of the harmonic suppression circuit 1000 can have two pairs of zeros, which are: and
  • the impedance Z 1000 of the harmonic suppression circuit 1000 also has a pair of poles, which are:
  • the impedance Z 1000 of the harmonic suppression circuit 1000 can be very large. Therefore, the harmonic suppression circuit 1000 can have a greater suppression effect on the harmonic signal with frequency f2 .
  • At least one of Term1 and Term2 at both ends of the harmonic suppression circuit 1000 may be used to connect to a radio frequency power amplifier.
  • at least one of both ends Term1 and Term2 of the harmonic suppression circuit 1000 may be connected to a radio frequency switch.
  • At least one of the inductors L 1 , L 2 may be a microstrip line.
  • at least one of the capacitors C 1 , C 2 may be integrated in other components directly connected to the harmonic suppression circuit 1000 .
  • at least one of the capacitors C 1 and C 2 may be connected to the aforementioned radio frequency switch, and at least one of the capacitors C 1 and C 2 may also be directly connected to the aforementioned radio frequency power amplifier.
  • the harmonic suppression circuit 1000 may also include multiple cascaded circuit structures shown in FIG. 1 .
  • Each of the structures shown in FIG. 1 can be used to suppress multiple harmonic frequency signals that are the same and/or different from the fundamental signal.
  • Fig. 2 shows a schematic diagram of the principle of a harmonic suppression circuit according to an embodiment of the present application.
  • the harmonic frequency f2 may be an integer multiple of the fundamental frequency f1 .
  • the harmonic suppression circuit 2000 may include two LC series resonators connected in parallel, namely the resonator 21 and the resonator 22 . Both ends Term1 and Term2 of the harmonic suppression circuit 2000 may be 50 ⁇ impedance ports.
  • the inductor L 1 can be 0.2nH, and the inductor L 2 can be 0.28nH.
  • Capacitor C1 can be 2.5pF and capacitor C2 can be 13pF.
  • the impedance Z 21 of the resonator 21 and the impedance Z 22 of the resonator 22 can be expressed as:
  • the impedance Z 2000 of the harmonic suppression circuit 2000 can be expressed as:
  • the influence of the harmonic suppression circuit 2000 on the transmission impedance is small and can be ignored. Therefore, the attenuation of the fundamental wave signal by the harmonic suppression circuit 2000 is small and can be ignored.
  • the gain of the harmonic suppression circuit 2000 is -7.681dB, and at a frequency of 5.03GHz, the gain of the harmonic suppression circuit 2000 is -8.185dB. That is, the harmonic suppression circuit 2000 has an attenuation effect of not less than 7.5 dB on the harmonic signals within the frequency range of 4.97-5.03 GHz.
  • FIG. 5 shows a schematic diagram of the Smith circle simulation at the terminal Term1 of the harmonic suppression circuit shown in FIG. 2 .
  • the input impedance at the terminal Term1 is Z 0 ⁇ (1-0.009j).
  • Z 0 is the matching impedance at the terminal Term1
  • its impedance value may be 50 ⁇ .
  • the input impedance at the terminal Term1 is also approximately 50 ⁇ , and its deviation relative to 50 ⁇ is extremely small.
  • the deviation of the output impedance at the terminal Term2 relative to 50 ⁇ can also be extremely small.
  • the inductance of the inductor L 1 and the inductor L 2 is small, optionally, at least one of the inductor L 1 and the inductor L 2 can be a microstrip line. Since the capacitance of the capacitor C1 and the capacitor C2 is relatively small, optionally, at least one of the capacitor C1 and the capacitor C2 can be integrated into a component directly connected to the harmonic suppression circuit 2000 .
  • At least one of the capacitor C1 and the capacitor C2 may be connected to the terminal Term2.
  • the terminal Term2 can serve as the signal output terminal of the harmonic suppression circuit 2000 and be directly connected to a radio frequency switch (not shown).
  • At least one of capacitor C1 and capacitor C2 may be integrated in the radio frequency switch.
  • capacitor C1 can swap places with inductor L1
  • capacitor C2 can also swap places with inductor L2 .
  • the terminal Term1 can be used as a signal input terminal of the harmonic suppression circuit 2000, and is directly connected to a radio frequency power amplifier (not shown). At least one of capacitor C1 and capacitor C2 may be integrated in the RF power amplifier.
  • Fig. 6 shows a schematic diagram of topology connection of a power amplifier module according to an embodiment of the present application.
  • the amplifier module may include a power amplifier PA and a harmonic suppression circuit 31 .
  • the harmonic suppression circuit 31 may be any one of the aforementioned harmonic suppression circuits.
  • the power amplifier PA may be a radio frequency power amplifier.
  • the harmonic suppression circuit 31 can be directly or indirectly connected to the output terminal of the power amplifier PA.
  • the power amplifying module 3000 may further include a radio frequency switch SOI_Switch.
  • the radio frequency switch SOI_Switch may be directly connected to the harmonic suppression circuit 32 or to the harmonic suppression circuit 31 .
  • the present application also provides a communication device in an embodiment.
  • the electronic device may include any of the aforementioned harmonic suppression circuits and/or any of the aforementioned power amplification modules.
  • the present application also provides an embodiment, a communication system.
  • the electronic system may include any of the aforementioned harmonic suppression circuits and/or any of the aforementioned power amplification modules.
  • the present application also provides an embodiment of a chip.
  • the chip may include any of the aforementioned harmonic suppression circuits and/or any of the aforementioned power amplification modules.
  • two groups of LC series resonators connected in parallel can achieve almost lossless transmission of fundamental wave signals and at the same time realize harmonic suppression of preset harmonic signals.
  • At least one of the two sets of LC series resonators can resonate near the fundamental frequency. So that at the fundamental frequency, the parallel impedance of the two LC series resonators can be close to zero. Therefore, at the fundamental frequency, the influence of the harmonic suppression circuit provided by the present application on the transmission impedance can be very small, for example, it can be very close to 50 ⁇ .
  • the harmonic suppression circuit provided in the present application two groups of LC series resonators can resonate in parallel around the preset harmonic frequency of the fundamental frequency signal. Therefore, the parallel impedance of the two sets of LC series resonators can be relatively large. The larger impedance can cause the harmonic suppression circuit provided in the present application to have a larger attenuation effect on the harmonic frequency. Therefore, it can be realized that the predetermined harmonic frequency signal is greatly attenuated while almost not affecting the transmission of the fundamental wave signal.
  • the circuit topology of the harmonic suppression circuit provided by the present application is very simple, the aforementioned technical effects can be achieved without increasing the complexity of the substrate circuit. Since the LC parameter of the harmonic suppression circuit provided by the application can be small, the inductor involved in the harmonic suppression circuit provided by the application can be a microstrip line, and the capacitor involved in the application can be integrated directly with the harmonic suppression circuit. connected device. Therefore, the complexity of the circuit can be further reduced, and the cost can be reduced.

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Abstract

本申请提供了一种谐波抑制电路、功率放大器模组、通信设备、通信系统。其中适用于5G-NR射频功率放大器的谐波抑制电路，包括：并联连接的第一谐振器和第二谐振器；所述第一谐振器包括串联连接的第一电感器和第一电容器；所述第二谐振器包括串联连接的第二电感器和第二电容器；所述谐波抑制电路工作于第一频率；所述第一谐振器和所述第二谐波器中的至少一项谐振于所述第一频率；所述第一谐振器和第二谐振器并联谐振于第一频率的第一预设整数倍。

Description

谐波抑制电路、功率放大器模组、通信设备、通信系统 技术领域
本申请涉及通信领域，特别涉及一种适用于5G-NR射频功率放大器的谐波抑制电路、一种功率放大器模组、一种通信设备、一种通信系统及一种芯片。
背景技术
目前，5GNR一般采用基于OFDM的全新空口设计的全球性5G标准。该技术标准比先前的4G LTE蜂窝网络快100倍。数据传输速率最高可达10Gbit/s。如此高的数据传输速率对射频前端模组中的功率放大器提出了更高的线性功率要求。
由于功率放大器PA属于非线性器件。高线性功率输出时，功率放大器PA工作在非线性区，会产生一系列的谐波分量。因此功率放大器模组自身对谐波的抑制能力也就成为评判其整体性能的一项重要指标。
现有手机功率放大器模组产品的谐波抑制电路，大多通过在Laminate基板上采用串联谐振电路-trap或并联谐振电路-tank来提升对谐波抑制能力。其中组成trap或tank电路网络的元器件大多由SMT组成。随着5G PA模组所集成元件数目越来越多，基板设计更加复杂，其留给SMT的空间变得更加有限。
此外，传统trap或tank电路网络的引入，除增加了对谐波抑制能力的同时，也或多或少改变了基波阻抗。基波阻抗的改变会使得PA输出性能发生变化。所以，如何在不改变基波阻抗，且不增加基板电路复杂度的前提下，还能实现较高的谐波抑制，已引起电路设计者的广泛关注。
实用新型内容
基于此，本申请提供了一种适用于5G-NR射频功率放大器的谐波抑制电路，包括：并联连接的第一谐振器和第二谐振器；所述第一谐振器包括串联连接的第一电感器和第一电容器；所述第二谐振器包括串联连接的第二电感器和第二电容器；所述谐波抑制电路工作于第一频率；所述第一 谐振器和所述第二谐波器中的至少一项谐振于所述第一频率；所述第一谐振器和第二谐振器并联谐振于第一频率的第一预设整数倍。
可选地，所述第一电感器与所述第二电容器可以满足下式：
Figure PCTCN2022078355-appb-000001
和/或所述第二电感器与所述第二电容器可以满足下式：
Figure PCTCN2022078355-appb-000002
其中，f 1为所述第一预设频率，L 1为所述第一电感器，C 1为所述第一电容器，L 2为所述第二电感器，C 2为所述第二电容器。
可选地，所述第一电感器、所述第一电容器、所述第二电感器与所述第二电容器可以满足下式：
Figure PCTCN2022078355-appb-000003
其中，f 2为所述第一预设频率的第一预设整数倍，L 1为所述第一电感器，L 2为所述第二电感器，C 1为所述第一电容器，C 2为所述第二电容器。
可选地，所述第一预设整数倍为2倍；所述第一预设频率为2.5GHz；所述第一电感器为0.2nH；所述第一电容器为2.5pF；所述第二电感器为0.28nH；所述第二电容器为13pF。
可选地，所述第一电感器和所述第二电感器中的至少一个为微带线。
可选地，所述第一电容器和所述第二电容器中的至少一个集成于与所述谐波抑制电路直接连接的元件上。
进一步地，所述谐波抑制电路的一端连接于射频功率放大器，另一端连接射频开关；所述第一电容器和所述第二电容器中的至少一个集成于所述射频开关和/或所述射频功率放大器。
本申请的一个实施例还提供一种功率放大器模组，包括：功率放大器；前述任意一种谐波抑制电路，与所述功率放大器连接。
本申请的一个实施例还提供一种通信设备，包括：前述任意一种的谐波抑制电路和/或前述任意一种功率放大器模组。
本申请的一个实施例还提供一种通信系统，，包括：前述任意一种的谐波抑制电路和/或前述任意一种功率放大器模组。
本申请的一个实施例还提供一种芯片，包括：前述任意一种的谐波抑制电路和/或前述任意一种功率放大器模组。
利用前述谐波抑制电路、通信设备和通信系统，可以通过并联的两组LC串联谐振器可以在实现几乎无损传输基波信号的同时，实现对预设谐波信号的谐波抑制。
在本申请提供的谐波抑制电路中，两组LC串联谐振器中的至少一个可以谐振于基波频率附近。使得在基波频率处，两个LC串联谐振器的并联阻抗可以接近于零。从而在基波频率处，可以使得本申请提供的谐波抑制电路对传输阻抗的影响可以很小，比如可以非常接近50Ω。
在本申请提供的谐波抑制电路中，两组LC串联谐振器可以并联谐振于基波频率信号的预设谐波频率附近。从而可以使得两组LC串联串联谐振器的并联阻抗可以较大。该较大的阻抗可以造成本申请提供的谐波抑制电路对该谐波频率产生较大的衰减效果。从而可以实现，在几乎不影响基波信号传输的同时，对预设谐波频率信号产生较大衰减。
由于本申请提供的谐波抑制电路的电路拓扑结构非常简单，因而可以在不增加基板电路复杂度的前提下实现前述技术效果。由于本申请提供的谐波抑制电路的LC参数可以较小，因而本申请提供的谐波抑制电路涉及的电感器可以是微带线，该本申请涉及的电容器可以集成于与谐波抑制电路直接连接的器件上。从而可以进一步降低电路复杂度，降低成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图，而并不超出本申请要求保护的范围。
图1示出了本申请的一个实施例谐波抑制电路的原理示意图。
图2示出了本申请的一个实施例谐波抑制电路的原理示意图。
图3示出了图2所示谐波抑制电路在频率f 1＝2.5GHz附近的传输特性仿真曲线示意图。
图4出了图2所示谐波抑制电路在频率f 2＝5GHz附近的传输特性仿真曲线示意图。
图5示出了图2所示谐波抑制电路在在端Term1处的史密斯圆仿真示意图。
图6示出了本申请的一个实施例功率放大器模组的拓扑连接示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1示出了本申请的一个实施例谐波抑制电路的原理示意图。其中谐波抑制电路1000可以工作于基波频率f 1。谐波抑制电路1000可以通过基波频率为f 1的基波信号，并可以用于抑制频率为f 2的该基波信号的谐波信号。
如图1所示，谐波抑制电路1000可以包括并联连接的谐振器11和谐振器12。其中，谐振器11可以包括串联连接的电感器L 1和电容器C 1。谐振器12可以包括串联连接的电感器L 2和电容器C 2。
可选地，谐振器11和谐振器12中的至少一项可以谐振于基波频率f 1附近。例如：电感器L 1和电容器C 1可以满足如下关系：
Figure PCTCN2022078355-appb-000004
和/或电感器L 2和电容器C 2可以满足如下关系：
Figure PCTCN2022078355-appb-000005
可选地，谐振器11和谐振器12可以并联谐振于谐波频率f 2附近，其中谐波频率f 2可以是基波频率f 1的预设整数倍。可选地，谐波频率f 2可以是基波频率f 1的2倍。可选地，电感器L 1、L 2和电容器C 1、C 2可以满足如下关系：
Figure PCTCN2022078355-appb-000006
如图1所示，谐波抑制电路1000的两端Term1和Term2中的至少一项可以连接匹配电阻。该匹配电阻可以使得端Term1和Term2中的至少一项的输出/输出阻抗为50Ω。
在谐波频率f 2处，从端口Term1看过去，由串联连接的电感器L 1和电容器C 1组成的谐振器11可以等效于电容。从端口Term1看过去，由串联连接的电感器L 2和电容器C 2组成的谐振器12可以等效于电感。该等效的电感和等效的电容组成了并联谐振器tank。该并联谐振器tank的谐振频率可以恰好位于谐波频率f 2的附近。另外谐振器11和/或谐振器12恰好谐振于基波频率f 1附近。因此在基波频率f 1处，从端口Term1看过去，谐波抑制电路1000的阻抗基本没有变化，还是50Ω。
如图1所示，谐振器11的阻抗Z 11可以表现为：
Figure PCTCN2022078355-appb-000007
整理得到：
Figure PCTCN2022078355-appb-000008
由式(5)可知，阻抗Z 11可以具备一对零点，为：
Figure PCTCN2022078355-appb-000009
当电感器L 1和电容器C 1满足式(1)所示关系时，在基波频率f 1处，谐振器11的阻抗Z 11可以非常小。相应地，在频率f 1处，谐波抑制电路1000的阻抗Z 1000也为非常小。因而，对基波频率为f 1的基波信号，谐波抑制电路1000有较小的衰减。
可选地，谐振器12也可以谐振于基波频率f 1附近。例如：电感器L 2和电容器C 2可以满足式(2)所示关系。与谐振器11相似，当谐振器12谐振于基波频率f 1时，即当电感器L 2和电容器C 2满足式(2)所示关系时，在基波频率f 1处谐振器12的阻抗Z 12非常小，相应地，在基波频率f 1处，谐波抑制电路1000的阻抗Z必然也非常小。即，对基波频率为f 1的信号，谐波抑制电路1000有着很好的传输特性。由于在基波频率f 1处谐波抑制电路1000的阻抗Z非常小。在基波频率f 1处，嵌入谐波抑制电路1000的功放电路的基波频率f 1信号的传输阻抗受谐波抑制电路1000的影响可以较小。
由图1所示，谐振器11和谐振器12的并联阻抗Z 1000满足一下关系：
Figure PCTCN2022078355-appb-000010
整理得到：
Figure PCTCN2022078355-appb-000011
由式(6)可知，谐波抑制电路1000的阻抗Z 1000可以具备两对零点，分别为：
Figure PCTCN2022078355-appb-000012
和
Figure PCTCN2022078355-appb-000013
谐波抑制电路1000的阻抗Z 1000同时还具备一对极点，为：
Figure PCTCN2022078355-appb-000014
当电感器L 1、L 2和电容器C 1、C 2满足时(3)所示关系时，在谐波频率f 2处，谐波抑制电路1000的阻抗Z 1000可以非常大。因而，在谐波抑制电路1000对频率为f 2的谐波信号可以有着较大的抑制作用。
如图1所示，可选地，谐波抑制电路1000两端Term1和Term2中的至少一项可以用于连接射频功率放大器。可选地，谐波抑制电路1000的两端Term1和Term2中的至少一项可以连接射频开关。
可选地，电感器L 1、L 2中的至少一项可以是微带线。可选地，电容器C 1、C 2中的至少一项可以集成于与谐波抑制电路1000直接连接的其他元件。比如：电容器C 1、C 2中的至少一项可以连接前述射频开关，电容器C 1、C 2中的至少一项也可以直接连接前述射频功率放大器。
可选地，谐波抑制电路1000也可以包括级联的多个图1所示的电路结构。其中每个图1所示的结构可以分别用于抑制基波信号相同和/或不同的多个谐波频率信号。
图2示出了本申请的一个实施例谐波抑制电路的原理示意图。
谐波抑制电路2000可以用于通过基波频率f 1＝2.5GHz的基波信号。并可以用于抑制频率为谐波频率f 2的谐波信号。谐波频率f 2可以是基波频率f 1的整数倍。如示例实施例所示，谐波频率f 2可以是基波频率f 1的2倍，即谐波频率f 2＝5GHz。
如图2所示，谐波抑制电路2000可以包括并联连接的两个LC串联谐振器，分别为谐振器21和谐振器22。谐波抑制电路2000的两端Term1和Term2可以均为50Ω阻抗端口。可选地，电感器L 1可以为0.2nH，电感器L 2可以为0.28nH。电容器C 1可以为2.5pF，电容器C 2可以为13pF。
如图2所示，谐振器21的阻抗Z 21和谐振器22的阻抗Z 22可以分别表 示为：
Figure PCTCN2022078355-appb-000015
Figure PCTCN2022078355-appb-000016
谐波抑制电路2000的阻抗Z 2000可以表示为：
Figure PCTCN2022078355-appb-000017
由式(8)-(10)可知，谐振器21的谐振频率f 21、谐振器22的谐振频率f 22、谐振器21和谐振器22的并联谐振频率f 2000可以分别表示为：
Figure PCTCN2022078355-appb-000018
Figure PCTCN2022078355-appb-000019
Figure PCTCN2022078355-appb-000020
把L 1＝0.2nH，C 1＝2.5pF，L 1＝0.28nH，C 1＝13pF分别带入式(11)-(13)，得到f 21＝7.12GHz，f 22＝2.63GHz，f 2000＝5.02GHz。即谐振器22谐振于基波频率f 1＝2.5GHz附近，谐振器21和谐振器22的并联谐振于谐波频率f 2＝5GHz附近。
把L 1＝0.2nH，C 1＝2.5pF，L 1＝0.28nH，C 1＝13pF，s＝j×2×π×2.5GHz带入式(8)-(10)，得到Z 21＝-22.32j，Z 22＝-0.49j，Z 2000＝-0.48j。当端Term1的匹配电阻为50Ω时，谐波抑制电路2000在端Term1的传输阻抗为：50+Z 2000＝50-0.48j。该阻抗非常接近50Ω。即在基波频率f 1＝2.5GHz处，谐振器21和谐振器22的并联谐阻抗Z 2000的阻抗可以较小。对嵌入谐波抑制电路2000的电路而言，在基波频率f 1＝2.5GHz处，谐波抑制电路2000的对传输阻抗影响较小，可以忽略不计。因而谐波抑制电路2000对基波信号的衰减较小，可以忽略不计。
把L 1＝0.2nH，C 1＝2.5pF，L 1＝0.28nH，C 1＝13pF，s＝j×2×π×5GHz带入式(8)-(10)，得到Z 21＝-6.45j，Z 22＝6.35j，Z 2000＝409.6j。在谐波频率f 2＝5GHz处，谐振器21呈容性，谐振器22呈感性。二者并联谐振，使得谐波抑制电路2000的阻抗Z 2000较大。因而谐波抑制电路2000可以对频率为f 2＝5GHz的谐波信号有着较好的抑制作用。
图3示出了图2所示谐波抑制电路在频率f 1＝2.5GHz附近的传输特性仿 真曲线示意图。
如图3所示，在频率f 1＝2.5GHz处，谐波抑制电路2000增益为-8.5×10 -5dB。且在频率f 1＝2.5GHz附近，谐波抑制电路2000的增益曲线非常平坦。谐波抑制电路2000对频率f 1＝2.5GHz附近的基波信号的影响可以忽略不计。
图4出了图2所示谐波抑制电路在频率f 2＝5GHz附近的传输特性仿真曲线示意图。
如图4所示，在频率f 2＝5GHz处，谐波抑制电路2000增益为-35.4dB。即谐波抑制电路2000对谐波频率f 2＝5GHz处的谐波信号有着35.4dB的衰减。在频率4.97GHz处，谐波抑制电路2000增益为-7.681dB，在频率5.03GHz处，谐波抑制电路2000增益为-8.185dB。即谐波抑制电路2000对频率范围4.97-5.03GHz内的谐波信号有着不小于7.5dB的衰减效果。
图5示出了图2所示谐波抑制电路在在端Term1处的史密斯圆仿真示意图。
如图5所示，端Term1处的输入阻抗为Z 0×(1-0.009j)。其中，Z 0为端Term1处的匹配阻抗，其阻抗值可以为50Ω。显然端Term1处的输入阻抗也近似为50Ω，其相对于50Ω的偏差极小。同理，端Term2处的输出阻抗相对于50Ω的偏差也可以极小。
由于电感器L 1和电感器L 2的电感值较小，可选地，电感器L 1和电感器L 2中的至少一项可以是微带线。由于电容器C 1和电容器C 2的电容值较小，可选地，电容器C 1和电容器C 2中的至少一项可以集成于与谐波抑制电路2000直接连接的元器件。
如示例实施例所示：电容器C 1和电容器C 2中的至少一项可以连接于端Term2。端Term2可以作为谐波抑制电路2000的信号输出端，直接连接于射频开关(未示出)。电容器C 1和电容器C 2中的至少一项可以集成于该射频开关。
可选地，电容器C 1可以与电感器L 1交换位置，电容器C 2也可以与电感器L 2交换位置。端Term1可以作为谐波抑制电路2000的信号输入端，与射频功率放大器(未示出)直接连接。电容器C 1和电容器C 2中的至少一项可以集成于该射频功率放大器。
图6示出了本申请的一个实施例功率放大器模组的拓扑连接示意图。
如图6所示，放大器模组可以包括功率放大器PA、谐波抑制电路31。其中谐波抑制电路31可以是前述任意一种谐波抑制电路。功率放大器PA可以是射频功率放大器。谐波抑制电路31可以直接或者间接连接于功率放大器PA的输出端。
如示例实施例所示，功率放大模组3000还可以包括射频开关SOI_Switch。可选地，射频开关SOI_Switch可以与谐波抑制电路32也可以与谐波抑制电路31直接连接。
本申请还提供一个实施例一种通信设备。该电子设备可以包括前述任意之中谐波抑制电路和/或前述任意一种功率放大模组。
本申请还提供一个实施例一种通信系统。该电子系统可以包括前述任意之中谐波抑制电路和/或前述任意一种功率放大模组。
本申请还提供一个实施例一种芯片。该芯片可以包括前述任意之中谐波抑制电路和/或前述任意一种功率放大模组。
利用前述谐波抑制电路、通信设备和通信系统，可以通过并联的两组LC串联谐振器可以在实现几乎无损传输基波信号的同时，实现对预设谐波信号的谐波抑制。
在本申请提供的谐波抑制电路中，两组LC串联谐振器中的至少一个可以谐振于基波频率附近。使得在基波频率处，两个LC串联谐振器的并联阻抗可以接近于零。从而在基波频率处，可以使得本申请提供的谐波抑制电路对传输阻抗的影响可以很小，比如可以非常接近50Ω。
在本申请提供的谐波抑制电路中，两组LC串联谐振器可以并联谐振于基波频率信号的预设谐波频率附近。从而可以使得两组LC串联串联谐振器的并联阻抗可以较大。该较大的阻抗可以造成本申请提供的谐波抑制电路对该谐波频率产生较大的衰减效果。从而可以实现，在几乎不影响基波信号传输的同时，对预设谐波频率信号产生较大衰减。
由于本申请提供的谐波抑制电路的电路拓扑结构非常简单，因而可以在不增加基板电路复杂度的前提下实现前述技术效果。由于本申请提供的谐波抑制电路的LC参数可以较小，因而本申请提供的谐波抑制电路涉及的电感器可以是微带线，该本申请涉及的电容器可以集成于与谐波抑制电路 直接连接的器件上。从而可以进一步降低电路复杂度，降低成本。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明仅用于帮助理解本申请的方法及其核心思想。同时，本领域技术人员依据本申请的思想，基于本申请的具体实施方式及应用范围上做出的改变或变形之处，都属于本申请保护的范围。综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种适用于5G-NR射频功率放大器的谐波抑制电路，其特征在于，包括：
    并联连接的第一谐振器和第二谐振器；
    所述第一谐振器包括串联连接的第一电感器和第一电容器；
    所述第二谐振器包括串联连接的第二电感器和第二电容器；
    所述谐波抑制电路工作于第一频率；
    所述第一谐振器和所述第二谐波器中的至少一项谐振于所述第一频率；
    所述第一谐振器和第二谐振器并联谐振于第一频率的第一预设整数倍。
  2. 根据权利要求1所述的谐波抑制电路，其特征在于，所述第一电感器与所述第二电容器满足下式：
    Figure PCTCN2022078355-appb-100001
    和/或所述第二电感器与所述第二电容器满足下式：
    Figure PCTCN2022078355-appb-100002
    其中，f 1为所述第一预设频率，L 1为所述第一电感器，C 1为所述第一电容器，L 2为所述第二电感器，C 2为所述第二电容器。
  3. 根据权利要1所述的谐波抑制电路，其特征在于，所述第一电感器、所述第一电容器、所述第二电感器与所述第二电容器满足下式：
    Figure PCTCN2022078355-appb-100003
    其中，f 2为所述第一预设频率的第一预设整数倍，L 1为所述第一电感器，L 2为所述第二电感器，C 1为所述第一电容器，C 2为所述第二电容器。
  4. 根据权利要求1所述的谐波抑制电路，其特征在于，
    所述第一预设整数倍为2倍；
    所述第一预设频率为2.5GHz；
    所述第一电感器为0.2nH；
    所述第一电容器为2.5pF；
    所述第二电感器为0.28nH；
    所述第二电容器为13pF。
  5. 根据权利要求1所述的谐波抑制电路，其特征在于，所述第一电感器和所述第二电感器中的至少一个为微带线。
  6. 根据权利要求1所述的谐波抑制电路，其特征在于，所述第一电容器和所述第二电容器中的至少一个集成于与所述谐波抑制电路直接连接的元件上。
  7. 根据权利要求6所述的谐波抑制电路，其特征在于，所述谐波抑制电路的一端连接于射频功率放大器，另一端连接射频开关；
    所述第一电容器和所述第二电容器中的至少一个集成于所述射频开关和/或所述射频功率放大器。
  8. 一种功率放大器模组，其特征在于，包括：
    功率放大器；
    权利要求1-7中任意一项所述的谐波抑制电路，与所述功率放大器连接。
  9. 一种通信设备，其特征在于，包括：权利要求1-7中任意一项所述的谐波抑制电路和/或权利要求8所述的功率放大器模组。
  10. 一种通信系统，其特征在于，包括：权利要求1-7中任意一项所述的谐波抑制电路和/或权利要求8所述的功率放大器模组。
  11. 一种芯片，其特征在于，权利要求1-7中任意一项所述的谐波抑制 电路和/或权利要求8所述的功率放大器模组。
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