WO2023019655A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2023019655A1
WO2023019655A1 PCT/CN2021/116873 CN2021116873W WO2023019655A1 WO 2023019655 A1 WO2023019655 A1 WO 2023019655A1 CN 2021116873 W CN2021116873 W CN 2021116873W WO 2023019655 A1 WO2023019655 A1 WO 2023019655A1
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Prior art keywords
metal
metal layer
test
layer
dummy
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PCT/CN2021/116873
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English (en)
French (fr)
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李宗翰
刘志拯
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长鑫存储技术有限公司
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Priority to US17/651,574 priority Critical patent/US20230048600A1/en
Publication of WO2023019655A1 publication Critical patent/WO2023019655A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor structure and a manufacturing method thereof.
  • test unit is usually formed in the manufacturing process for performing the resistance test of the through hole.
  • test unit is located on the periphery of the device, and there are no other graphics around it, which may easily cause deformation of the through hole, making it difficult for the test results to reflect the actual resistance of the through hole inside the device.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure provided by the embodiment of the present application includes:
  • an insulating layer located between the first metal layer and the second metal layer, for isolating the first metal layer and the second metal layer;
  • test via hole penetrating through the insulating layer and connecting the first metal layer and the second metal layer through the conductive material in the test via hole;
  • At least one pair of dummy via holes penetrates through the insulating layer and connects any one of the first metal layer or the second metal layer.
  • the method for manufacturing a semiconductor structure includes:
  • a second metal layer is formed on the insulating layer, the test via and the dummy via, wherein the test via connects the first metal layer and the second metal layer, and the dummy via
  • the hole is connected to any one of the first metal layer or the second metal layer.
  • FIG. 1 is a first schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a semiconductor structure with a test via
  • FIG. 3 is a second schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a first metal layer in a semiconductor structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the positions of the first metal layer, test vias and dummy vias in a semiconductor structure provided by an embodiment of the present application;
  • FIG. 6 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application.
  • FIG. 7 is a third schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • Fig. 8 is a schematic diagram of forming a test through hole in an embodiment
  • FIG. 9 is a schematic diagram of forming a semiconductor structure in an embodiment
  • FIG. 10 is a schematic diagram 4 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a cross-sectional view of locations of test vias and dummy vias in a semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure 100 includes:
  • the first metal layer 120 is located on the surface of the semiconductor substrate 110;
  • the second metal layer 130 is located above the surface of the first metal layer 120;
  • an insulating layer 140 located between the first metal layer 120 and the second metal layer 120, for isolating the first metal layer 120 and the second metal layer 130;
  • testing via 150 penetrating through the insulating layer 140 and connecting the first metal layer 120 and the second metal layer 130 through the conductive material in the testing via 150 ;
  • At least one pair of dummy via holes 160 penetrate through the insulating layer 140 and connect to any one of the first metal layer 120 or the second metal layer 130 .
  • the above-mentioned semiconductor structure may be a test structure located around the semiconductor device for testing, or called a test unit.
  • the semiconductor structure can be formed synchronously with the semiconductor device during the process of manufacturing various semiconductor devices (such as memories and chips) using the wafer. Since the semiconductor structure and the semiconductor device are separated from each other, the performance of the semiconductor device is not affected.
  • the semiconductor structure can be used for testing during the manufacturing process of the semiconductor device, so as to realize the process monitoring of the semiconductor device.
  • the region where the semiconductor structure is located can be cut off, and only the semiconductor device is kept and the semiconductor device is processed. Packaged separately.
  • the above semiconductor structure can also be retained and packaged together with the semiconductor device, so as to facilitate product testing.
  • first metal layer and second metal layer are metal layers formed synchronously with different metal layers in the semiconductor device, and both the first metal layer and the second metal layer may have patterns formed by etching, for example, linear or mesh shape.
  • the first metal layer and the second metal layer are isolated from each other by an insulating layer, and the insulating layer may be made of insulating materials such as silicon oxide or silicon nitride.
  • the first metal layer and the second metal layer may be connected to each other through a through hole, and the through hole penetrates through the insulating layer.
  • the test via hole is connected to the first metal layer and the second metal layer, so that the first metal layer and the second metal layer can be electrically connected through the test via hole; the dummy via hole only connects the first metal layer or the second metal layer. Any layer in the layer, so as to support and balance the stress.
  • a dummy via has a structure similar to that of a test via and penetrates through an insulating layer.
  • the dummy via hole may also contain conductive materials such as metal, but it does not have the function of connecting the first metal layer and the second metal layer. That is to say, the dummy via may only connect to the first metal layer or only connect to the second metal layer.
  • the dummy vias can be used to support the entire semiconductor structure.
  • the position distribution of the dummy vias and the test vias can be centrally symmetric or axially symmetric, thereby making the semiconductor structure more stable.
  • the dummy vias may be distributed around the test vias to support the test vias and reduce test inaccuracies caused by deformation of the test vias.
  • the dummy through holes can improve the distribution of exposure energy in the area of the through holes, improve the process window and the shape of the through holes, and at the same time, a single through hole is easily deformed in the subsequent process, and setting at least one pair of dummy through holes can avoid the subsequent process. Deformation of the through hole.
  • the semiconductor structure in the embodiment of the present application has a more stable structure, which is not easy to be deformed during the manufacturing process, thus improving the performance of the semiconductor structure.
  • the accuracy and test efficiency of the test using the semiconductor structure are improved.
  • the first metal layer includes: a plurality of underlying metal lines distributed in parallel along a first direction;
  • the second metal layer includes: a plurality of top-layer metal lines distributed in parallel along a second direction; wherein the second direction is perpendicular to the first direction.
  • the first metal layer may be a linear metal wire, and may include a plurality of metal wires distributed side by side. Since the first metal layer is a metal layer close to the surface of the substrate, these metal lines may be referred to as bottom metal lines.
  • the plurality of underlying metal lines can all be distributed in parallel along the first direction, and the first direction can be any direction parallel to the surface of the substrate, which can be implemented in an actual manufacturing process.
  • the second metal layer can be a plurality of metal lines distributed in parallel with a structure similar to that of the first metal layer. Compared with the first metal layer, the second metal layer is far away from the substrate surface, so it can be called the top metal layer. Wire.
  • the plurality of top-layer metal lines are parallel distributed along the second direction. The second direction can be perpendicular to the first direction, which can make the structure more stable.
  • the test via hole is located at an overlapping position of one of the bottom metal lines and one of the top metal lines.
  • the metal lines of the first metal layer and the second metal layer are perpendicular to each other, therefore, the bottom metal lines of the first metal layer and the top metal lines of the second metal layer respectively have overlapping positions. These overlapping positions are located on the same straight line in the direction perpendicular to the substrate surface, therefore, the above-mentioned test via holes can be formed at these overlapping positions, so as to realize the connection between the first metal layer and the second metal layer.
  • the bottom metal line connected by the test via has two test terminals, and the top metal line connected by the test via has two test terminals;
  • the test terminal is used for performing a resistance test on the test via hole through a Kelvin four-wire detection method.
  • test vias connect a top-layer metal line and a bottom-layer metal line perpendicular to each other, and the two metal lines respectively have two test terminals, a total of four test terminals can be provided.
  • Kelvin four-wire detection method is also called four-terminal detection, or four-point probe method. This method can eliminate the impedance of wiring and contact resistance by separating the electrodes of current and voltage, so as to realize accurate resistance testing.
  • the metal wires connected to the above at least four through holes can be used to connect different detection terminals respectively, so as to realize four-wire detection. Compared with the method of single-point test, the detection accuracy can be improved.
  • the at least one pair of dummy vias 160 includes a pair of dummy vias 160 connected to the same top layer metal line 131 as the testing via 150 .
  • the dummy via hole is set at the position of the top metal line connected by the test via hole, so as to play a supporting role, reduce the probability of deformation of the top layer metal line, and further reduce the inaccurate test caused by the deformation of the test via hole Condition.
  • the at least one pair of dummy vias 160 includes at least two pairs of dummy vias 160 connected to the top layer metal lines 131 that are different from the test vias 150
  • the at least A pair of dummy vias 160 includes at least two pairs of dummy vias 160 connected to different underlying metal lines 121 with the test vias 150 .
  • multiple pairs of dummy vias can be arranged around the test vias, including not only the dummy vias connected to the same top layer metal line with the test vias, but also multiple pairs of dummy vias connected to the test vias. Dummy vias for different top and bottom metal lines.
  • the plurality of dummy through holes can make the semiconductor structure more stable and reduce the influence of deformation.
  • the dummy via hole can improve the regional exposure energy distribution of the via hole, and improve the process window and the morphology of the via hole.
  • At least two of the plurality of underlying metal lines 121 include at least two metal line segments 122 arranged at intervals, and two adjacent metal line segments Between 122 is a spacer 123 .
  • a part of the bottom metal line can be set as a plurality of spaced metal line segments, and there is a spacer between every two adjacent metal line segments.
  • These underlying metal lines do not have a connection function, but only have the function of simulating the structure in the semiconductor device. Therefore, these underlying metal lines do not need to be connected to test vias, nor do they need to have external test terminals.
  • the underlying metal wire connected to the test via hole does not have such a structure, but is a complete metal wire, and has an externally connected test terminal 124 as shown in FIG. 4 .
  • the above-mentioned underlying metal lines with spacers may be located adjacent to the complete underlying metal lines, or at other positions in the interval.
  • projections of at least three top-layer metal lines on the semiconductor substrate are located within projections of the spacers on the semiconductor substrate.
  • the above-mentioned underlying metal line composed of a plurality of metal line segments has at least three spacers, so that multiple dummy via holes can be conveniently provided.
  • the top of the dummy via 160 is connected to the top layer metal line (not shown in the figure), and the bottom of the dummy via 160 is connected to the spacer 123 .
  • the overlapping position of part of the top-layer metal lines and the bottom-layer metal lines is located in the interval area of the bottom-layer metal lines.
  • One end of the dummy via hole is connected to the top-layer metal line, and the other end may be connected to the spacer region, so as not to conduct the first metal layer and the second metal layer.
  • the distribution patterns of the test vias and the at least one pair of dummy vias are axisymmetric or centrosymmetric.
  • the dummy through hole and the test through hole together form a symmetrical structure, which can make the semiconductor structure have a balanced and stable structure, which can be used for repeated tests and is not easy to be damaged.
  • the dummy vias form a first axisymmetric distribution with the centerline of the semiconductor structure as an axis, and the distances from the dummy vias in the first axisymmetric distribution to the center of the semiconductor structure may be different.
  • the test through-holes can be located on the above-mentioned central axis, and if there are multiple test through-holes, they can also be symmetrically distributed around the above-mentioned central line. The distances between the dummy vias and the test vias can be the same or different.
  • the test vias and the dummy vias form a first centrosymmetric distribution centered on the center of the semiconductor structure, and the distances from the dummy vias in the first centrosymmetric distribution to the center of the semiconductor structure are the same.
  • the center of the semiconductor structure is the center of symmetry. If there is only one test through hole, it may be located at the center of symmetry; if there are multiple test through holes, the test through hole may be centrally symmetrical about the center of symmetry.
  • the dummy via hole is filled with conductive material.
  • the dummy vias can be manufactured synchronously with the test vias, using the same process flow. Therefore, the dummy via may have a structure exactly the same as that of the test via, that is, a structure filled with conductive material. Since the dummy via hole is located in the spacer region of the bottom metal line, it will not conduct the bottom metal line. In this way, on the one hand, the manufacturing process can be saved, on the other hand, the regional exposure energy distribution of the through hole can be improved, and the process window and the shape of the through hole can be improved.
  • the dummy via holes may also be filled with insulating materials, such as organic materials, oxides and the like. In this way, the effect of reducing the electrical interference between the through holes can be achieved.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor structure, as shown in FIG. 6 , including:
  • Step S101 forming a first metal layer on the surface of the semiconductor substrate
  • Step S102 covering the first metal layer with an insulating layer
  • Step S103 forming a test via hole and at least one pair of dummy via holes penetrating through the insulating layer;
  • Step S104 filling conductive material in the test via hole and the dummy via hole
  • Step S105 forming a second metal layer on the insulating layer, the test via hole and the dummy via hole, wherein the test via hole connects the first metal layer and the second metal layer, so The dummy via is connected to any one of the first metal layer or the second metal layer.
  • the manufacturing process of the semiconductor structure is carried out synchronously during the manufacturing process of the semiconductor device product.
  • the above-mentioned first metal layer, second metal layer and insulating layer are all formed synchronously with each layer in the semiconductor device.
  • test vias and dummy vias are also carried out synchronously with the process of forming vias in the semiconductor device.
  • an insulating layer (not shown) is formed on the first metal layer 120
  • multiple targets The test via hole 150 and the dummy via hole 160 are formed synchronously, and then the subsequent second metal layer 130 and other related processes are performed. Compared with the way shown in FIG.
  • only one via hole 801 is formed on the first metal layer 120, which can make the whole structure more stable, and can improve the regional exposure energy distribution of the via hole, and improve the process window and via hole At the same time, a single through hole is easily deformed in the subsequent process, and at least one pair of dummy through holes can be provided to avoid the deformation of the through hole in the subsequent process.
  • the forming the first metal layer on the surface of the semiconductor substrate includes:
  • the forming a second metal layer on the insulating layer, the test via hole and the dummy via hole includes:
  • a plurality of top-layer metal lines distributed in parallel along a second direction are formed on the insulating layer, the test via hole and the dummy via hole; wherein the second direction is perpendicular to the first direction.
  • a metal layer may be formed on the surface of the semiconductor substrate first, and then a plurality of metal lines are formed by patterned etching.
  • an insulating material can be deposited thereon to form an insulating layer.
  • At least two of the plurality of underlying metal lines include at least two metal line segments arranged at intervals, and a spacer exists between adjacent two of the metal line segments.
  • part of the metal lines can be removed by etching to form spacers, so that these bottom metal lines form a plurality of spaced metal line segments.
  • the top of the dummy via is connected to the top layer metal line, and the bottom of the dummy via is connected to the spacer.
  • the dummy vias can be formed synchronously with the test vias, and the top layer metal lines can be connected with the dummy vias.
  • the dummy via When the dummy via is connected to the position of the first metal layer, because it is located in the spacer, it will not be connected to the bottom metal line, so it has no test function and will not cause electrical interference to the test via, but it can serve as a support function to stabilize the semiconductor structure.
  • projections of at least three top-layer metal lines on the semiconductor substrate are located within projections of the spacers on the semiconductor substrate.
  • each layer of metal is connected through through holes.
  • the traditional ISO Test -key Isolation Test-key, isolation test unit
  • the test structure of the via hole includes a bottom metal line 901 , a top layer metal line 902 and a test via hole 903 located at the overlapping position of the two metal lines and connecting the two metal lines.
  • the through hole of this structure is easily affected by the surrounding isolation layer, resulting in unstable photolithography process, and there is no other pattern structure around the single test through hole, which is easy to cause test problems in the subsequent process of planarizing the metal layer.
  • the via is distorted and cannot be tested.
  • the resistance value of a single test via hole has a high probability of error, which cannot accurately reflect the resistance value of the actual via hole in the device.
  • the first metal layer 1010 includes a plurality of bottom metal lines 1011
  • the second metal layer 1020 includes a plurality of top layer metal lines 1021 .
  • a test via 1030 is provided, and the test via 1030 communicates with the bottom metal line 1011 and the top metal line 1021 .
  • the bottom metal wire 1011 and the top metal wire 1021 respectively connected to the test via 1030 are respectively connected through the test pads 1012 and 1022, so that the test pad 1012 and 1022 can be used to test the resistance of the test via 1030 by the Kelvin test method.
  • dummy via holes 1040 may also be provided. As shown in FIG. 11 , the dummy via 1040 is connected to the second metal layer 1020 and penetrates through the insulating layer 1050 between the first metal layer 1010 and the second metal layer 1020 , but is not connected to the first metal layer 1010 .
  • the underlying metal line of the first metal layer may have a plurality of disconnected and distributed metal line segments, and the disconnected part has a spacer. In this way, when the dummy via hole is connected to the position of the first metal layer, it touches the spacer region but does not touch the metal line, so that the first metal layer will not be conducted.
  • the dummy via 1040 and other vias can be used to form a stable and symmetrical structure, reducing the possibility of deformation of the test via. Therefore, the dummy through hole 1040 does not need to be conductive, and the dummy through hole 1040 can be filled with an insulating material, as shown in FIG. 11 .
  • the above-mentioned dummy vias can be formed at the same time as the test vias, and the dummy vias are filled with metal materials, but since the dummy vias are not connected to the underlying metal lines of the first metal layer, they will not conduct a first metal layer and a second metal layer.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure provided by the embodiments of the present application adopts at least one pair of dummy vias arranged at different positions around the test vias, which can play a supporting role on the one hand and reduce the number of test vias in the manufacturing process.
  • Possibility of hole deformation; on the other hand, the dummy through hole can improve the regional exposure energy distribution of the through hole, improve the process window and the shape of the through hole, and at the same time, a single through hole is easily deformed in the subsequent process. After the through hole, the deformation of the through hole in the subsequent process can be avoided.

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Abstract

本申请实施例公开了一种半导体结构及其制造方法。该半导体结构包括：半导体衬底；第一金属层，位于所述半导体衬底表面；第二金属层，位于所述第一金属层表面的上方；绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；测试通孔，贯穿所述绝缘层并通过所述测试通孔中的导电材料连接所述第一金属层和所述第二金属层；至少一对虚设通孔，贯穿所述绝缘层并连接所述第一金属层或所述第二金属层中的任意一层。

Description

半导体结构及其制造方法
相关申请的交叉引用
本申请基于申请号为202110935828.6、申请日为2021年08月16日、申请名称为“半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体结构及其制造方法。
背景技术
对于存储器、芯片等半导体器件，通常在半导体衬底上采用多层结构来实现。半导体衬底表面的各层电性连接通过金属线来实现，而不同层的金属线则通过通孔连接。通孔的阻值是影响连接性能的重要参数，因此，通常在制造过程中形成测试单元(Test-key)用于进行通孔的电阻测试。
然而测试单元位于器件外围，周围没有其他图形，容易造成通孔变形，导致测试结果难以反映器件内部通孔的实际阻值。
发明内容
本申请实施例提供一种半导体结构及其制造方法。
第一方面，本申请实施例提供的半导体结构，包括：
半导体衬底；
第一金属层，位于所述半导体衬底表面；
第二金属层，位于所述第一金属层表面的上方；
绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；
测试通孔，贯穿所述绝缘层并通过所述测试通孔中的导电材料连接所述第一金属层和所述第二金属层；
至少一对虚设通孔，贯穿所述绝缘层并连接所述第一金属层或所述第二金属层中的任意一层。
第二方面，本申请实施例提供的半导体结构的制造方法，包括：
在半导体衬底表面形成第一金属层；
在所述第一金属层上形成绝缘层；
形成贯穿所述绝缘层的测试通孔和至少一对虚设通孔；
在所述测试通孔和所述虚设通孔中填充导电材料；
在所述绝缘层、所述测试通孔和所述虚设通孔上形成第二金属层，其中，所述测试通孔连接所述第一金属层和所述第二金属层，所述虚设通孔连接所述第一金属层或所述第二金属层中的任意一层。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例提供的一种半导体结构的示意图一；
图2为具有一个测试通孔的半导体结构的示意图；
图3为本申请实施例提供的一种半导体结构的示意图二；
图4为本申请实施例提供的一种半导体结构中第一金属层的示意图；
图5为本申请实施例提供的一种半导体结构中第一金属层及测试通孔和虚设通孔位置的示意图；
图6为本申请实施例提供的一种半导体结构的制造方法的流程图；
图7为本申请实施例提供的一种半导体结构的示意图三；
图8为一实施例中形成一个测试通孔的示意图；
图9为一实施例中形成一个半导体结构的示意图；
图10为本申请实施例提供的一种半导体结构的示意图四；
图11为本申请实施例提供的一种半导体结构中测试通孔和虚设通孔所在位置的剖面图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本申请实施例提供一种半导体结构，如图1所示，该半导体结构100包括：
半导体衬底110；
第一金属层120，位于所述半导体衬底110表面；
第二金属层130，位于所述第一金属层120表面的上方；
绝缘层140，位于所述第一金属层120和所述第二金属层120之间，用于隔离所述第一金属层120和第二金属层130；
测试通孔150，贯穿所述绝缘层140并通过所述测试通孔150中的导电材料连接所述第一金属层120和所述第二金属层130；
至少一对虚设通孔160，贯穿所述绝缘层140并连接所述第一金属层120或所述第二金属层130中的任意一层。
在本申请实施例中，上述半导体结构可以为位于半导体器件周围的用于进行测试的 测试结构，或称为测试单元。该半导体结构可以在利用晶圆制造各种半导体器件(如存储器、芯片)等的过程中，与半导体器件同步形成。由于该半导体结构与半导体器件相互分离，因此不影响半导体器件的性能。
该半导体结构可以在半导体器件的制造过程中用于进行测试，从而实现半导体器件的制程监控，在完成半导体器件的制造时，可以切割掉上述半导体结构所在的区域，仅保留半导体器件并对半导体器件分别进行封装。当然，也可以将上述半导体结构保留，并与半导体器件封装在一起，从而便于对产品进行测试。
上述第一金属层与第二金属层为与半导体器件中不同金属层同步形成的金属层，第一金属层与第二金属层均可以具有通过刻蚀等方式形成的图形，例如，线形或者网状。第一金属层与第二金属层之间通过绝缘层相互隔离，绝缘层可以为氧化硅或者氮化硅等绝缘材料制成。
第一金属层与第二金属层之间可以通过通孔相互连接，通孔贯穿绝缘层。其中，测试通孔连接到第一金属层与第二金属层，使得第一金属层与第二金属层通过测试通孔能够实现电连接；虚设通孔则仅连通第一金属层或第二金属层中的任意一层，从而起到支撑和平衡应力的作用。
在本申请实施例中，虚设通孔(Dummy via)是具有与测试通孔有类似结构，贯穿绝缘层的通孔。虚设通孔中也可以包含金属等导电材料，但其并不具有连通第一金属层和第二金属层的作用。也就是说，虚设通孔可以仅连接第一金属层或者仅连接第二金属层。
虚设通孔可以用于支撑整个半导体结构，例如，虚设通孔与测试通孔的位置分布可以呈现中心对称或者轴对称，从而使得半导体结构更加稳定。或者，虚设通孔可以分布与测试通孔的周围，起到支撑测试通孔的作用，减少测试通孔变形导致的测试不准确。此外，虚设通孔能够改善通孔的区域曝光能量分布，改善工艺窗口和通孔的形貌，同时单个通孔在后续工艺过程中容易变形，设置至少一对虚设通孔后能够避免后续工艺过程中通孔的变形。
如此，相比于如图2所示的半导体结构200中仅设置一个测试通孔201的结构，本申请实施例中的半导体结构具有更加稳定的结构，不容易在制造过程中产生变形，因而提升了利用该半导体结构进行测试的准确性和测试效率。
在一些实施例中，所述第一金属层包括：沿第一方向平行分布的多条底层金属线；
所述第二金属层包括：沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
在本申请实施例中，第一金属层可以为线形的金属线，并且可以包括并排分布的多条金属线。由于第一金属层为靠近衬底表面的金属层，因此，这些金属线可以称为底层金属线。这里，多条底层金属线可以均沿第一方向平行分布，第一方向可以为平行于衬底表面的任意方向，可以以实际制造过程中便于实现的方式为准。
在本申请实施例，第二金属层可以为与第一金属层结构类似的多条平行分布的金属线，相对于第一金属层，第二金属层远离衬底表面，因此可以称为顶层金属线。多条顶层金属线沿着第二方向平行分布。第二方向可以与第一方向相互垂直，这样可以使结构 更加稳定。
在一些实施例中，所述测试通孔位于一条所述底层金属线与一条所述顶层金属线的交叠位置。
上述第一金属层与第二金属层的金属线相互垂直，因此，第一金属层的各底层金属线与第二金属层的各顶层金属线分别具有交叠的位置。这些交叠的位置在垂直于衬底表面的方向上位于同一直线，因此，可以在这些交叠位置形成上述测试通孔，从而实现第一金属层与第二金属层的连接。
在一些实施例中，所述测试通孔连接的所述底层金属线具有两个测试端，所述测试通孔连接的所述顶层金属线具有两个测试端；
所述测试端用于通过开尔文四线检测法对所述测试通孔进行电阻测试。
由于测试通孔连接了相互垂直的一条顶层金属线和一条底层金属线，两条金属线分别具有两个测试端，总共可以提供四个测试端。
开尔文四线检测法又称为四端子检测，或者四点探针法。该方法通过分离电流和电压的电极，可以消除布线和接触电阻的阻抗，从而实现精准地电阻测试。在本申请实施例中，可以利用上述至少四个通孔所连接的金属线分别连接不同的检测端，从而实现四线检测，相比于单点测试的方法，可以提升检测的准确性。
在一些实施例中，如图3所示，所述至少一对虚设通孔160中包括一对虚设通孔160与所述测试通孔150连接同一条所述顶层金属线131。
在形成顶层金属线时，如果顶层金属线发生了变形，则容易导致测试通孔变形，从而影响测试结果。在本申请实施例中，将虚设通孔设置在测试通孔连接的顶层金属线的位置，从而起到支撑作用，减少顶层金属线变形的概率，进而减少测试通孔变形导致的测试不准确的情况。
在一些实施例中，如图3所示，所述至少一对虚设通孔160中包括至少两对虚设通孔160与所述测试通孔150连接不同的所述顶层金属线131，所述至少一对虚设通孔160中包括至少两对虚设通孔160与所述测试通孔150连接不同的所述底层金属线121。
在本申请实施例中，可以在测试通孔的周围设置多个成对的虚设通孔，其中不仅包括与测试通孔连接同一顶层金属线的虚设通孔，还包括多对与测试通孔连接不同顶层金属线和底层金属线的虚设通孔。这样，多个虚设通孔可以使得半导体结构更加稳定，减少变形的影响。并且，虚设通孔能够改善通孔的区域曝光能量分布，改善工艺窗口和通孔的形貌。
在一些实施例中，如图4所示，多条所述底层金属线121中的至少两条所述底层金属线121包括至少两条间隔设置的金属线段122，相邻两条所述金属线段122之间为间隔区123。
考虑到虚设通孔仅连接顶层金属线或者底层金属线，因此，可以将底层金属线中的一部分设置为间隔的多个金属线段，每相邻的两条金属线段之间具有间隔区。
这些底层金属线不具有连接功能，仅具有模拟半导体器件中结构的功能，因此，这些底层金属线不需要连接测试通孔，也不需要具有外接的测试端。
需要说明的是，与测试通孔连接的底层金属线不具有这种结构，而是完整整条的金 属线，并且具有如图4所示的外接的测试端124。上述具有间隔区的底层金属线可以位于该完整的底层金属线的相邻位置，或者间隔的其他位置。
在一些实施例中，至少三条所述顶层金属线在所述半导体衬底上的投影部分位于所述间隔区在所述半导体衬底上的投影内。
因此，至少三条顶层金属线与这些底层金属线在交叠位置处时不能够通过通孔连通。也就是说，上述由多个金属线段组成的底层金属线至少具有三个间隔区，从而可以便于设置多个虚设通孔。
在一些实施例中，如图5所示，所述虚设通孔160顶端与所述顶层金属线(图中未示出)连接，且所述虚设通孔160底端与所述间隔区123连接。
这样，部分顶层金属线与底层金属线的交叠位置处在该底层金属线的间隔区内。虚设通孔的一端连接到顶层金属线，另一端则可以连接至上述间隔区，从而不会导通第一金属层和第二金属层。
在一些实施例中，所述测试通孔与所述至少一对虚设通孔的分布图形呈轴对称或中心对称。
虚设通孔与测试通孔共同构成对称结构，可以使得半导体结构具有平衡稳定的结构，能够用于进行反复测试，不易损坏。
在一些实施例中，虚设通孔构成以半导体结构中线为轴的第一轴对称分布，第一轴对称分布的各虚设通孔到半导体结构中心的距离可不相同。测试通孔可位于上述中轴线上，若测试通孔有多个，也可以以上述中线为中心对称分布。各虚设通孔与测试通孔之间的距离可以相同也可以不同。
在一些实施例中，测试通孔与虚设通孔构成以半导体结构中心为中心的第一中心对称分布，第一中心对称分布的虚设通孔到半导体结构中心的距离相同。半导体结构的中心即为对称中心。若测试通孔仅有一个，可以位于该对称中心，若测试通孔有多个，则测试通孔可以以该对称中心成中心对称。
在一些实施例中，所述虚设通孔中填充有导电材料。
在本申请实施例中，虚设通孔可以与测试通孔同步进行制造，采用相同的工艺流程。因此，虚设通孔可以具有与测试通孔完全一致的结构，即填充导电材料的结构。由于虚设通孔位于底层金属线的间隔区内，因此不会导通底层金属线。这样，一方面可以节省制造流程，另一方面能够改善通孔的区域曝光能量分布，改善工艺窗口和通孔的形貌。
在另一些实施例中，虚设通孔中也可以填充绝缘材料，例如有机材料、氧化物等等。这样，可以起到减少通孔之间的电性干扰的作用。
本申请实施例还提供一种半导体结构的制造方法，如图6所示，包括：
步骤S101、在半导体衬底表面形成第一金属层；
步骤S102、在所述第一金属层上覆盖绝缘层；
步骤S103、形成贯穿所述绝缘层的测试通孔和至少一对虚设通孔；
步骤S104、在所述测试通孔和所述虚设通孔中填充导电材料；
步骤S105、在所述绝缘层、所述测试通孔和所述虚设通孔上形成第二金属层，其中，所述测试通孔连接所述第一金属层和所述第二金属层，所述虚设通孔连接所述第一 金属层或所述第二金属层中的任意一层。
由于上述半导体结构可以为位于半导体器件周围的用于进行测试的测试结构，因此，该半导体结构的制造过程是在制造半导体器件产品的过程中同步进行的。上述第一金属层、第二金属层以及绝缘层均与半导体器件中的各层对应同步形成。
上述测试通孔和虚设通孔也与半导体器件中形成通孔的过程同步进行，如图7所示，在第一金属层120上形成绝缘层(图中未示出)后，在多个目标位置同步形成测试通孔150和虚设通孔160，然后再进行后续第二金属层130等的相关制程。相比于如图8所示的，在第一金属层120上仅形成一个通孔801的方式，可以使得整个结构更加稳定，且能够改善通孔的区域曝光能量分布，改善工艺窗口和通孔的形貌，同时单个通孔在后续工艺过程中容易变形，设置至少一对虚设通孔后能够避免后续工艺过程中通孔的变形。
在一些实施例中，所述在半导体衬底表面形成第一金属层，包括：
在所述半导体衬底表面形成沿第一方向平行分布的多条底层金属线；
所述在所述绝缘层、所述测试通孔和所述虚设通孔上形成第二金属层，包括：
在所述绝缘层、所述测试通孔和所述虚设通孔上形成多条沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
这里，可以先在半导体衬底表面形成一层金属层，然后通过图形化刻蚀的方式形成多条金属线。
形成第一金属层后，可以在上面沉积绝缘材料，形成绝缘层。
在一些实施例中，多条所述底层金属线中的至少两条所述底层金属线包括至少两条间隔设置的金属线段，相邻两条所述金属线段之间为间隔区。
在形成上述底层金属线后，可以通过刻蚀的方法去除部分金属线的部分区域，形成间隔区，使得这些底层金属线形成多条间隔的金属线段。
在一些实施例中，所述虚设通孔顶端与所述顶层金属线连接，且所述虚设通孔底端与所述间隔区连接。
这样，虚设通孔可以与测试通孔同步形成，并且顶层金属线可以与虚设通孔连接。虚设通孔连接至第一金属层的位置时由于位于间隔区内，因此不会与底层金属线连接，从而不具有测试功能，也不会对测试通孔产生电性干扰，但可以起到支撑作用，稳定半导体结构。
在一些实施例中，至少三条所述顶层金属线在所述半导体衬底上的投影部分位于所述间隔区在所述半导体衬底上的投影内。
这样，这些顶层金属线与带有间隔区的底层金属线不存在金属交叠的位置，虚设通孔连接在间隔区，因而不会连接底层金属线。
本申请实施例还提供如下示例：
对于MOS(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)器件等的后段工艺(BEOL，Back end of Line)各层金属都是通过通孔进行连接，传统的ISO Test-key(Isolation Test-key，隔离测试单元)一般测试单个通孔的阻值。
如图9所示，通孔的测试结构包括一条底层金属线901，一条顶层金属线902和位于这两条金属线的交叠位置，并连通这两条金属线的测试通孔903。这种结构的通孔容易受到周围隔离层的影响，导致光刻工艺不稳定，并且单个的测试通孔的周围没有其他图形结构，后续对金属层进行平坦化处理等的工艺过程中容易造成测试通孔变形，无法进行测试。此外，单个的测试通孔的阻值出现误差的概率高，不能准确反映器件中的实际通孔的阻值。
本申请实施例中，如图10所示，第一金属层1010包括多条底层金属线1011，第二金属层1020包括多条顶层金属线1021。在其中一条底层金属线与一条顶层金属线相交的交叠位置处，设置测试通孔1030，测试通孔1030连通底层金属线1011和顶层金属线1021。此外，第一金属层1010与第二金属层1020之间具有绝缘层(图中未示出)。
分别与测试通孔1030连接的底层金属线1011和顶层金属线1021分别通过测试焊盘1012和1022连接，这样可以利用测试焊盘1012和1022对测试通孔1030通过开尔文测试法对进行电阻测试。
此外，为了使整个半导体结构稳定，还可以设置虚设通孔1040。如图11所示，虚设通孔1040与第二金属层1020连接，贯穿第一金属层1010与第二金属层1020之间的绝缘层1050，但不与第一金属层1010连接。在本申请实施例中，第一金属层的底层金属线中可以具有多条断开的分布的金属线段，并且断开的部分具有间隔区。这样，虚设通孔连接至第一金属层的位置时接触到间隔区而不会接触金属线，从而不会导通第一金属层。
虚设通孔1040与其他通孔可以用于形成稳定对称的结构，减少测试通孔变形的可能。因此，虚设通孔1040无需具有导电性，虚设通孔1040中可以填充绝缘材料，如图11所示。当然，为了便于简化制造工艺，上述虚设通孔可以和测试通孔同时形成，虚设通孔中填充金属材料，但由于虚设通孔不与第一金属层的底层金属线连接，因此不会导通第一金属层和第二金属层。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅 仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请实施例提供了一种半导体结构及其制造方法。通过本申请实施例提供的技术方案，本申请实施例提供的半导体结构，采用至少一对虚设通孔设置在测试通孔周围的不同位置，一方面能够起到支撑作用，减少制造过程中测试通孔变形的可能性；另一方面，虚设通孔能够改善通孔的区域曝光能量分布，改善工艺窗口和通孔的形貌，同时单个通孔在后续工艺过程中容易变形，设置至少一对虚设通孔后能够避免后续工艺过程中通孔的变形。

Claims (16)

  1. 一种半导体结构，包括：
    半导体衬底；
    第一金属层，位于所述半导体衬底表面；
    第二金属层，位于所述第一金属层表面的上方；
    绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；
    测试通孔，贯穿所述绝缘层并通过所述测试通孔中的导电材料连接所述第一金属层和所述第二金属层；
    至少一对虚设通孔，贯穿所述绝缘层并连接所述第一金属层或所述第二金属层中的任意一层。
  2. 根据权利要求1所述的半导体结构，其中，所述第一金属层包括：沿第一方向平行分布的多条底层金属线；
    所述第二金属层包括：沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
  3. 根据权利要求2所述的半导体结构，其中，所述测试通孔位于一条所述底层金属线与一条所述顶层金属线的交叠位置。
  4. 根据权利要求3所述的半导体结构，其中，所述测试通孔连接的所述底层金属线具有两个测试端，所述测试通孔连接的所述顶层金属线具有两个测试端；
    所述测试端用于通过开尔文四线检测法对所述测试通孔进行电阻测试。
  5. 根据权利要求3所述的半导体结构，其中，所述至少一对虚设通孔中包括一对虚设通孔与所述测试通孔连接同一条所述顶层金属线。
  6. 根据权利要求2所述的半导体结构，其中，所述至少一对虚设通孔中包括至少两对所述虚设通孔与所述测试通孔连接不同的所述顶层金属线，所述至少一对虚设通孔中包括至少两对所述虚设通孔与所述测试通孔连接不同的所述底层金属线。
  7. 根据权利要求6所述的半导体结构，其中，多条所述底层金属线中的至少两条所述底层金属线包括至少两条间隔设置的金属线段，相邻两条所述金属线段之间为间隔区。
  8. 根据权利要求7所述的半导体结构，其中，至少三条所述顶层金属线在所述半导体衬底上的投影部分位于所述间隔区在所述半导体衬底上的投影内。
  9. 根据权利要求7所述的半导体结构，其中，所述虚设通孔顶端与所述顶层金属线连接，且所述虚设通孔底端与所述间隔区连接。
  10. 根据权利要求1至7任一所述的半导体结构，其中，所述测试通孔与所述至少一对虚设通孔的分布图形呈轴对称或中心对称。
  11. 根据权利要求1至7任一所述的半导体结构，其中，所述虚设通孔中填充有导电材料。
  12. 一种半导体结构的制造方法，包括：
    在半导体衬底表面形成第一金属层；
    在所述第一金属层上形成绝缘层；
    形成贯穿所述绝缘层的测试通孔和至少一对虚设通孔；
    在所述测试通孔和所述虚设通孔中填充导电材料；
    在所述绝缘层、所述测试通孔和所述虚设通孔上形成第二金属层，其中，所述测试通孔连接所述第一金属层和所述第二金属层，所述虚设通孔连接所述第一金属层或所述第二金属层中的任意一层。
  13. 根据权利要求12所述的方法，其中，所述在半导体衬底表面形成第一金属层，包括：
    在所述半导体衬底表面形成沿第一方向平行分布的多条底层金属线；
    所述在所述绝缘层、所述测试通孔和所述虚设通孔上形成第二金属层，包括：
    在所述绝缘层、所述测试通孔和所述虚设通孔上形成多条沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
  14. 根据权利要求13所述的方法，其中，多条所述底层金属线中的至少两条所述底层金属线包括至少两条间隔设置的金属线段，相邻两条所述金属线段之间为间隔区。
  15. 根据权利要求14所述的方法，其中，所述虚设通孔顶端与所述顶层金属线连接，且所述虚设通孔底端与所述间隔区连接。
  16. 根据权利要求15所述的方法，其中，至少三条所述顶层金属线在所述半导体衬底上的投影部分位于所述间隔区在所述半导体衬底上的投影内。
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