WO2022257587A1 - 数据处理方法、toe硬件及计算机可读存储介质 - Google Patents

数据处理方法、toe硬件及计算机可读存储介质 Download PDF

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WO2022257587A1
WO2022257587A1 PCT/CN2022/086150 CN2022086150W WO2022257587A1 WO 2022257587 A1 WO2022257587 A1 WO 2022257587A1 CN 2022086150 W CN2022086150 W CN 2022086150W WO 2022257587 A1 WO2022257587 A1 WO 2022257587A1
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information
data
sent
configuration information
cpu
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English (en)
French (fr)
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陈峰峰
熊先奎
张启明
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ZTE Corp
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ZTE Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
    • H04L69/162—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields involving adaptations of sockets based mechanisms

Definitions

  • the present application relates to but not limited to the technical field of network transmission, and in particular relates to a data processing method, TOE hardware and a computer-readable storage medium.
  • TCP Transmission Control Protocol
  • CPU Central Processing Unit
  • the Socket interface of the socket is fully compatible with the application layer, and the data interaction between the TOE hardware and the CPU can be realized through the Socket interface
  • the running space of the TCP link processing is controlled by the TOE hardware. It is provided by the double data rate (Double Data Rate, DDR) memory and the random access memory (Random Access Memory, RAM) inside the TOE hardware.
  • DDR Double Data Rate
  • RAM Random Access Memory
  • Embodiments of the present application provide a data processing method, TOE hardware, and a computer-readable storage medium.
  • the embodiment of the present application provides a data processing method, which is applied to TOE hardware, and the TOE hardware communicates with the central processing unit CPU, and the data processing method includes: acquiring the memory address information sent by the CPU and The configuration information of the transmission control protocol TCP link to be sent, wherein the memory address information represents the storage location of the data to be sent in the shared memory, and the data to be sent is obtained and written by the CPU from the TCP link to be sent To the shared memory, the shared memory is the memory shared by the TOE hardware and the CPU; obtain the data to be sent according to the memory address information, and perform TOE unloading according to the configuration information and the data to be sent ; Send the TCP packet obtained through TOE offloading to the transmission network.
  • the embodiment of the present application provides a data processing method, which is applied to TOE hardware, and the TOE hardware is communicatively connected to the CPU.
  • the data processing method includes: obtaining a TCP message from the transmission network, by The TCP message is carried out TOE unloading to obtain the TCP link to be received; the configuration information and the data to be received of the TCP link to be received are obtained, and the data to be received is written into the shared memory, wherein the shared memory is the TOE hardware memory shared with the CPU; obtaining memory address information, sending the memory address information and the configuration information to the CPU, so that the CPU obtains the data to be received according to the memory address information, and according to The configuration information receives the data to be received, wherein the memory address information represents a storage location of the data to be received in the shared memory.
  • the embodiment of the present application provides a TOE hardware, including: a memory, a processor, and a computer program stored on the memory and operable on the processor, when the processor executes the computer program, the following
  • a TOE hardware including: a memory, a processor, and a computer program stored on the memory and operable on the processor, when the processor executes the computer program, the following
  • the data processing method described in any one of the embodiments, or to implement the data processing method described in any one of the embodiments in the second aspect are examples of the data processing method described in any one of the embodiments, or to implement the data processing method described in any one of the embodiments in the second aspect.
  • the embodiments of the present application further provide a computer-readable storage medium, storing computer-executable instructions, the computer-executable instructions being used to execute the data processing method described in any one embodiment of the first aspect , or execute the data processing method as described in the embodiment of the second aspect.
  • Fig. 1 is a flow chart of steps of a data processing method provided by an embodiment of the present application
  • FIG. 2 is a flow chart of steps for obtaining index information provided by another embodiment of the present application.
  • FIG. 3 is a flow chart of steps for generating second index information provided by another embodiment of the present application.
  • FIG. 4 is a flow chart of steps for generating second index information provided by another embodiment of the present application.
  • FIG. 5 is a flow chart of TOE unloading steps provided by another embodiment of the present application.
  • FIG. 6 is a flow chart of steps of a data processing method provided in another embodiment of the present application.
  • FIG. 7 is a flow chart of steps for obtaining index information provided by another embodiment of the present application.
  • FIG. 8 is a flow chart of steps for obtaining second index information provided by another embodiment of the present application.
  • FIG. 9 is a flow chart of steps for obtaining second index information provided by another embodiment of the present application.
  • FIG. 10 is a flow chart of steps for sending memory address information and configuration information provided by another embodiment of the present application.
  • Fig. 11 is a schematic diagram of TOE hardware provided by another embodiment of the present application.
  • the application provides a data processing method, TOE hardware, and a computer-readable storage medium, wherein the data processing method is applied to the TOE hardware, and the TOE hardware communicates with the CPU, and the data processing method includes: obtaining the memory address information sent by the CPU and waiting Send the configuration information of the transmission control protocol TCP link, where the memory address information represents the storage location of the data to be sent in the shared memory, the data to be sent is obtained by the CPU from the TCP link to be sent and written to the shared memory, and the shared memory is TOE hardware
  • the memory shared with the CPU obtain the data to be sent according to the memory address information, perform TOE offloading according to the configuration information and the data to be sent; send the TCP message obtained through TOE offloading to the transmission network.
  • the running space for processing TCP links can be effectively increased, so that all data processing functions involved in the TCP protocol can be offloaded to TOE hardware.
  • Fig. 1 is the flow chart of the steps of the data processing method that an embodiment of the present application provides, and this data processing method is applied to TOE hardware, and TOE hardware is connected with CPU communication, and this data processing method includes but not limited to following steps:
  • Step S110 acquire the memory address information sent by the CPU and the configuration information of the transmission control protocol TCP link to be sent, wherein the memory address information represents the storage location of the data to be sent in the shared memory, and the data to be sent is obtained by the CPU from the TCP link to be sent And write to the shared memory, the shared memory is the memory shared by TOE hardware and CPU.
  • the CPU and the TOE hardware can communicate through the socket socket interface or the hardware descriptor queue; for example, communicate through the message (Message, msg) in the queue of the network interface card (Net Interface Card, NIC), Or realize socket interface compatibility between CPU and TOE hardware according to preset communication standards, so as to realize information interaction.
  • message Message, msg
  • Network interface card Net Interface Card, NIC
  • realize socket interface compatibility between CPU and TOE hardware according to preset communication standards so as to realize information interaction.
  • the data to be sent obtained by the CPU from the TCP connection to be sent can be written into the send buffer of the shared memory, and the send buffer can be in the form of a buffer queue, so the memory address information can be buffered in the shared memory to be sent.
  • the pointer information of the data buffer queue because the memory address information represents the storage location of the data to be sent in the shared memory, obtaining the memory address information can provide data support for the TOE hardware to obtain the data to be sent on the TCP link to be sent, this embodiment does not involve The improvement of the specific data acquisition method will not be repeated here.
  • obtaining the configuration information of the transmission control protocol TCP link to be sent can provide data support for realizing the function of the TCP protocol. It should be noted that the specific content of the configuration information of the transmission control protocol TCP link to be sent is within the knowledge of those skilled in the art It is well known that this embodiment is not limited.
  • the storage space is divided into internal memory and external memory, and the external memory includes DDR memory, etc.
  • the disadvantages are small storage space, high cost and low performance. Therefore, in the case of dealing with high concurrent data Insufficient storage space is likely to occur under the environment, affecting network performance.
  • the memory of the host server usually has a large storage space, such as random access memory (Random Access Memory, RAM), which can store buffer data far beyond the DDR memory. Therefore, using the host memory as a data buffer can Physically provide a large-capacity buffer space and provide a storage space basis for high-concurrency scenarios.
  • RAM Random Access Memory
  • memory generally includes volatile memory and nonvolatile memory, and the storage capacity of nonvolatile memory is usually larger than volatile memory, and common volatile memory includes dynamic random access memory (Dynamic Random Access Memory, DRAM), common non-volatile memory includes non-volatile dual in-line memory module (Non-Volatile Dual In-line Memory Module, NVDIMM), for TOE hardware, even
  • DRAM Dynamic Random Access Memory
  • NVDIMM Non-Volatile Dual In-line Memory Module
  • Step S120 acquire the data to be sent according to the memory address information, and perform TOE unloading according to the configuration information and the data to be sent.
  • the TOE hardware obtains the data to be sent from the shared memory according to the memory address information, performs TOE unloading according to the configuration information and the data to be sent, and transfers the function of processing the TCP protocol from the CPU to the TOE hardware, thereby effectively reducing the load on the CPU. load.
  • the data to be sent may be payload data of the TCP protocol, and specific content of the data to be sent is well known to those skilled in the art, and is not limited in this embodiment.
  • Step S130 sending the TCP message obtained through TOE offloading to the transmission network.
  • the TCP message is obtained through TOE offloading and sent to the transmission network, so that the processing function of the TCP protocol is transferred to the TOE hardware.
  • the shared memory can release the available storage Space, realize the reuse of the storage space in the shared memory, and improve the utilization rate of the space.
  • the embodiment of the present application does not limit the specific architecture of the TOE hardware, which may be Field Programmable Gate Array (Field Programmable Gate Array, FPGA) hardware, or Application Specific Integrated Circuit (ASIC) hardware. ).
  • step S110 in the embodiment shown in FIG. 1 the following steps are also included but not limited to.
  • Step S210 determine the link ID of the TCP link to be sent.
  • step S220 first index information is generated, and the first index information represents a mapping relationship between link identifiers and memory address information.
  • step S230 second index information is generated, and the second index information represents a mapping relationship between link identifiers and configuration information.
  • step S240 the index information of the TCP link to be sent is obtained by associating the first index information with the second index information.
  • the link identifier may be a unique identifier parameter of the TCP link to be sent, and those skilled in the art may be motivated to determine the link identifier based on data obtained from the CPU and shared memory, which is not limited in this embodiment.
  • step S230 in the embodiment shown in FIG. 2 also includes but is not limited to the following steps.
  • a configuration information record is generated in the configuration information record table.
  • the configuration information record includes configuration information, a configuration information record identifier and a link identifier, and the configuration information record table is preset and saved locally.
  • Step S320 obtaining second index information by associating configuration information records and link identifiers.
  • the configuration information record is generated in the local preset configuration information table, and the second index information obtained by associating the configuration information record with the link identifier can provide for implementing TOE offloading for the TCP link corresponding to the link identifier. data base.
  • the embodiment of the present application does not limit the local storage location of the configuration information record table in the TOE hardware, and may be stored in a double data rate (Double Data Rate, DDR) memory mounted on the TOE hardware. Not much to limit.
  • DDR Double Data Rate
  • the configuration information includes at least two different types of data structure information.
  • step S230 in the embodiment shown in FIG. 2 also includes but is not limited to the following steps.
  • Step S410 determining a data structure information record table corresponding to the data structure information, the data structure information record table is preset and saved locally for each type of data structure information.
  • Step S420 generating a data structure information record in the data structure information record table, where the data structure information record includes data structure information, a data structure information record identifier and a link identifier.
  • Step S430 associating the link identifier with all data structure information records to obtain second index information.
  • the data structure information includes the serial number, state machine, time stamp, timer, etc. corresponding to the sending and receiving of the TCP link to be sent.
  • the specific content of the data structure information is well known to those skilled in the art, and no restrictions are made here. .
  • corresponding data structure information recording tables are preset locally, and the data structure information recording table corresponding to the type of data structure information is determined Afterwards, the corresponding data structure information is stored in the corresponding data structure information recording table, so as to provide a data basis for implementing TOE offloading for the TCP link corresponding to the link identifier.
  • step S120 in the embodiment shown in FIG. 1 further includes but not limited to the following steps.
  • Step S510 when an uninstallation instruction carrying a target link identifier is received, determine target index information corresponding to the target link identifier.
  • Step S520 acquiring the target data to be sent from the shared memory according to the memory address information in the target index information.
  • Step S530 determine the target configuration according to the configuration information in the target index information.
  • Step S540 perform TOE offloading according to the target configuration and target data to be sent.
  • FIG. 6 is a flow chart of the steps of a data processing method provided by another embodiment of the present application.
  • the data processing method is applied to TOE hardware, and the TOE hardware is connected to the CPU in communication.
  • the data processing method includes but is not limited to The following steps.
  • step S610 the TCP message from the transmission network is obtained, and the TCP link to be received is obtained by performing TOE offload on the TCP message.
  • Step S620 acquiring the configuration information of the TCP link to be received and the data to be received, and writing the data to be received into the shared memory, wherein the shared memory is the memory shared by the TOE hardware and the CPU.
  • Step S630 obtain memory address information, and send the memory address information and configuration information to the CPU, so that the CPU obtains the data to be received according to the memory address information, and receives the data to be received according to the configuration information, wherein the memory address information indicates that the data to be received is in Shared memory storage location.
  • the TCP message from the transmission network is obtained
  • the TCP link to be received is obtained by performing TOE offloading on the TCP message
  • the configuration information and the data to be received of the TCP link to be received are obtained from the TCP link to be received
  • the Write the data to be received into the shared memory obtain the storage location information of the data to be received in the shared memory, that is, the memory address information, and send the memory address information and configuration information to the CPU, so that the CPU can obtain the data to be received according to the memory address information
  • Receive the data to be received according to the configuration information so that the function of processing the TCP protocol is transferred from the CPU to the TOE hardware, thereby effectively reducing the load on the CPU.
  • step S630 in the embodiment shown in FIG. 6 , the following steps are also included but not limited to.
  • Step S710 acquiring the connection identifier of the TCP connection to be received.
  • step S720 first index information is generated, and the first index information represents a mapping relationship between link identifiers and memory address information.
  • step S730 second index information is generated, and the second index information represents a mapping relationship between link identifiers and configuration information.
  • step S740 the index information of the TCP link to be received is obtained by associating the first index information with the second index information.
  • this embodiment can refer to the embodiment shown in Figure 2, the main difference is that the implementation direction of TOE offloading in this embodiment is different from the execution direction of TOE offloading in the embodiment shown in Figure 2 , this embodiment is used as the acquisition end of the TCP message, and the configuration information of the TCP link to be received and the memory address information of the TOE hardware storing the data to be received into the shared memory are sent to the CPU, so that the CPU performs the process according to the memory address information and configuration information.
  • the data receiving of the TCP link to be received is similar to the embodiment shown in FIG. 2 , and for the sake of simplicity, no further details are given here.
  • step S730 in the embodiment shown in FIG. 7 also includes but is not limited to the following steps.
  • a configuration information record is generated in the configuration information record table.
  • the configuration information record includes configuration information, a configuration information record identifier and a link identifier, and the configuration information record table is preset and saved locally.
  • step S820 the second index information is obtained by associating the configuration information record and the link identifier.
  • this embodiment can refer to the embodiment shown in Figure 3, the main difference is that the implementation direction of TOE offloading in this embodiment is different from the execution direction of TOE offloading in the embodiment shown in Figure 3 , this embodiment is used as the acquisition end of the TCP message, and the configuration information of the TCP link to be received and the memory address information of the TOE hardware storing the data to be received into the shared memory are sent to the CPU, so that the CPU performs the process according to the memory address information and configuration information.
  • the data receiving of the TCP link to be received is similar to the embodiment shown in FIG. 3 except that, for the sake of simplicity, no further details are given here.
  • the configuration information includes at least two different types of data structure information.
  • step S730 in the embodiment shown in FIG. 7 also includes but is not limited to the following steps.
  • Step S910 determining a data structure information record table corresponding to the data structure information, the data structure information record table is preset and stored locally for each type of data structure information.
  • Step S920 generating a data structure information record in the data structure information record table, where the data structure information record includes data structure information, a data structure information record identifier and a link identifier.
  • Step S930 associating the link identifier with all data structure information records to obtain second index information.
  • the technical solution and principle of this embodiment can refer to the embodiment shown in Figure 4, the main difference is that the implementation direction of TOE offloading in this embodiment is different from the execution direction of TOE offloading in the embodiment shown in Figure 4 , this embodiment is used as the acquisition end of the TCP message, and the configuration information of the TCP link to be received and the memory address information of the TOE hardware storing the data to be received into the shared memory are sent to the CPU, so that the CPU performs the process according to the memory address information and configuration information.
  • the data receiving of the TCP link to be received is similar to the embodiment shown in FIG. 4 , and for the sake of simplicity, no further details are given here.
  • step S630 in the embodiment shown in FIG. 6 also includes but is not limited to the following steps.
  • Step S1010 sending the memory address information to the CPU, so that the CPU acquires target data to be received from the shared memory according to the memory address information.
  • Step S1020 sending the configuration information to the CPU, so that the CPU determines the target configuration according to the configuration information, and performs data reception according to the target configuration and the data to be received.
  • the TOE hardware sends the memory address information to the CPU, so that the CPU obtains the target data to be received from the shared memory according to the memory address information, and sends the configuration information to the CPU, so that the CPU determines the target configuration according to the configuration information, and according to The target configuration and the data to be received are used for data reception, so that the process of TCP handshake and chain establishment is realized in the TOE hardware without the participation of the CPU, thereby effectively reducing the load on the CPU.
  • FIG. 11 is a schematic diagram of TOE hardware provided by another embodiment of the present application.
  • An embodiment of the present application also provides a TOE hardware 1100, the TOE hardware 1100 includes: a memory 1110, a processor 1120 and A computer program stored on the memory 1110 and executable on the processor 1120 .
  • the processor 1120 and the memory 1110 may be connected through a bus or in other ways.
  • the non-transitory software programs and instructions required to realize the data processing method of the above-mentioned embodiment are stored in the memory 1110, and when executed by the processor 1120, the data processing method applied to the TOE hardware 1100 in the above-mentioned embodiment is executed, for example, Carry out method step S110 to method step S130 in Fig. 1 described above, method step S210 to method step S240 in Fig. 2, method step S310 to method step S320 in Fig. 3, method step S410 to method step in Fig. 4 S430, method step S510 to method step S540 in FIG. 5 .
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • an embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor 1120 or a controller, for example, by Execution by a processor 1120 in the embodiment of the above-mentioned TOE hardware 1100 can make the above-mentioned processor 1120 execute the data processing method applied to the TOE hardware 1100 in the above-mentioned embodiment, for example, execute the method steps S110 to 1 in FIG. 1 described above.
  • computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .
  • Embodiments of the present application include a data processing method, TOE hardware, and a computer-readable storage medium, wherein the data processing method is applied to TOE hardware, and the TOE hardware is connected to a central processing unit CPU in communication, and the data processing method includes: obtaining The memory address information sent by the CPU and the configuration information of the transmission control protocol TCP link to be sent, wherein the memory address information represents the storage location of the data to be sent in the shared memory, and the data to be sent is sent by the CPU from the Obtain from the TCP link to be sent and write to the shared memory, the shared memory is the memory shared by the TOE hardware and the CPU; obtain the data to be sent according to the memory address information, and according to the configuration information performing TOE offloading with the data to be sent; and sending the TCP message obtained through TOE offloading to the transmission network.
  • the running space for processing TCP links can be effectively increased, so that all data processing functions involved in the TCP protocol can be offloaded to TOE hardware

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Abstract

一种数据处理方法、TOE硬件及计算机可读存储介质，其中，数据处理方法应用于TOE硬件，TOE硬件与中央处理器CPU通信连接，数据处理方法包括：获取CPU发送的内存地址信息和待发送传输控制协议TCP链接的配置信息，其中，内存地址信息表征待发送数据在共享内存的存储位置，待发送数据由CPU从待发送TCP链接中获取并写入至共享内存，共享内存为TOE硬件和CPU共享的内存(S110)；根据内存地址信息获取待发送数据，根据配置信息和待发送数据进行TOE卸载(S120)；将通过TOE卸载得到的TCP报文发送至传输网络(S130)。

Description

数据处理方法、TOE硬件及计算机可读存储介质
相关申请的交叉引用
本申请基于申请号为202110635842.4、申请日为2021年6月8日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及但不限于网络传输技术领域，尤其涉及一种数据处理方法、TOE硬件及计算机可读存储介质。
背景技术
随着网络技术的快速发展，百万兆以太网越来越普及，中央处理器(Central Processing Unit，CPU)实现的传输控制协议(Transmission Control Protocol，TCP)协议栈的开销越来越大，需要耗费大量的CPU资源和内存总线带宽，已经成为高性能网络服务的技术瓶颈，为了减轻CPU的压力，出现了传输控制协议卸载引擎((TCP Offload Engine，TOE,其中，传输控制协议(Transmission Control Protocol，TCP))技术，能够将协议栈的处理转移到TOE硬件实现，从而有效加速TCP协议的处理速度，释放CPU资源，降低处理时延。
在常见的TOE实现方案中，虽然实现了套接字Socket接口与应用层的完全兼容，能够使得TOE硬件与CPU之间通过Socket接口实现数据交互，但是，TCP链接处理的运行空间由TOE硬件挂载的双倍数据速率(Double Data Rate，DDR)存储器和TOE硬件内部的随机存取存储器(Random Access Memory，RAM)提供，当并发的TCP链接的数量较大，TOE硬件所需要的存储空间也随之增大，TOE硬件挂载的DDR存储器以及内部RAM无法满足巨大的存储需求，从而导致无法做到将TCP协议涉及的数据处理功能全部卸载到TOE硬件中实现。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供了一种数据处理方法、TOE硬件及计算机可读存储介质。
第一方面，本申请实施例提供了一种数据处理方法,应用于TOE硬件，所述TOE硬件与中央处理器CPU通信连接，所述数据处理方法包括：获取所述CPU发送的内存地址信息和待发送传输控制协议TCP链接的配置信息，其中，所述内存地址信息表征待发送数据在共享内存的存储位置，所述待发送数据由所述CPU从所述待发送TCP链接中获取并写入至所述共享内存，所述共享内存为所述TOE硬件和所述CPU共享的内存；根据所述内存地址信息获取所述待发送数据，根据所述配置信息和所述待发送数据进行TOE卸载；将通过TOE卸载得到的TCP报文发送至传输网络。
第二方面，本申请实施例提供了一种数据处理方法,应用于TOE硬件，所述TOE硬件与CPU通信连接，所述数据处理方法包括：获取来自于传输网络的TCP报文，通过对所述TCP报文进行TOE卸载得到待接收TCP链接；获取所述待接收TCP链接的配置信息和待接收数据， 将所述待接收数据写入共享内存，其中，所述共享内存为所述TOE硬件与所述CPU共享的内存；获取内存地址信息，将所述内存地址信息和所述配置信息发送至所述CPU，以使所述CPU根据所述内存地址信息获取所述待接收数据，并根据所述配置信息接收所述待接收数据，其中，所述内存地址信息表征所述待接收数据在所述共享内存的存储位置。
第三方面，本申请实施例提供了一种TOE硬件，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如第一方面任意一项实施例所述的数据处理方法，或实现第二方面任意一项实施例所述的数据处理方法。
第四方面，本申请实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行如第一方面任意一项实施例所述的数据处理方法，或执行如第二方面实施例所述的数据处理方法。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本申请一个实施例提供的数据处理方法的步骤流程图；
图2是本申请另一个实施例提供的得到索引信息的步骤流程图；
图3是本申请另一个实施例提供的生成第二索引信息的步骤流程图；
图4是本申请另一个实施例提供的生成第二索引信息的步骤流程图；
图5是本申请另一个实施例提供的TOE卸载的步骤流程图；
图6是本申请另一个实施例提供的数据处理方法的步骤流程图；
图7是本申请另一个实施例提供的得到索引信息的步骤流程图；
图8是本申请另一个实施例提供的得到第二索引信息的步骤流程图；
图9是本申请另一个实施例提供的得到第二索引信息的步骤流程图；
图10是本申请另一个实施例提供的发送内存地址信息和配置信息的步骤流程图；
图11是本申请另一个实施例提供的TOE硬件的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要说明的是，虽然在装置示意图中进行了功能模块划分，在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于装置中的模块划分，或流程图中的顺序执行所示出或描述的步骤。说明书、权利要求书或上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本申请提供了一种数据处理方法、TOE硬件及计算机可读存储介质，其中，数据处理方法应用于TOE硬件，TOE硬件与CPU通信连接，数据处理方法包括：获取CPU发送的内存地 址信息和待发送传输控制协议TCP链接的配置信息，其中，内存地址信息表征待发送数据在共享内存的存储位置，待发送数据由CPU从待发送TCP链接中获取并写入至共享内存，共享内存为TOE硬件和CPU共享的内存；根据内存地址信息获取待发送数据，根据配置信息和待发送数据进行TOE卸载；将通过TOE卸载得到的TCP报文发送至传输网络。根据本申请实施例提供的方案，能够有效增大处理TCP链接的运行空间，从而实现将TCP协议涉及的数据处理功能全部卸载到TOE硬件。
下面结合附图，对本申请实施例作进一步阐述。
参照图1，图1是本申请一个实施例提供的数据处理方法的步骤流程图，该数据处理方法应用于TOE硬件，TOE硬件与CPU通信连接，该数据处理方法包括但不限于有以下步骤：
步骤S110，获取CPU发送的内存地址信息和待发送传输控制协议TCP链接的配置信息，其中，内存地址信息表征待发送数据在共享内存的存储位置，待发送数据由CPU从待发送TCP链接中获取并写入至共享内存，共享内存为TOE硬件和CPU共享的内存。
需要说明的是，CPU和TOE硬件之间能够通过套接字socket接口或硬件描述符队列实现通信；例如通过网络接口卡(Net Interface Card，NIC)队列中的消息(Message，msg)进行通信，或者是根据预设的通信标准实现CPU和TOE硬件之间实现socket接口兼容，以实现信息的交互。
需要说明的是，CPU从待发送TCP链接中获取的待发送数据可以写入至共享内存的发送缓冲区，发送缓冲区可以采用缓冲队列的形式，因此内存地址信息可以是共享内存中缓冲有待发送数据的缓冲队列的指针信息，由于内存地址信息表征待发送数据在共享内存的存储位置，获取内存地址信息能够为TOE硬件获取待发送TCP链接的待发送数据做数据支撑，本实施例并不涉及具体的数据获取方式改进，在此不多作赘述。
可以理解的是，获取待发送传输控制协议TCP链接的配置信息能够为实现TCP协议功能提供数据支撑，需要说明的是，待发送传输控制协议TCP链接的配置信息的具体内容为本领域技术人员所熟知，本实施例不多作限定。
可以理解的是，对于主机服务器而言，存储空间分为内存和外存，外存包括DDR存储器等，其不足之处在于存储空间小、成本高和性能低，因此在应对高并发数据的情况下很容易出现存储空间不足的情况，影响网络性能。而主机服务器的内存通常具有较大的存储空间，例如随机存取存储器(Random Access Memory，RAM)，能够存储的缓冲数据量远超于DDR存储器，因此，利用主机内存作为数据缓冲区，能够在物理上提供大容量缓冲空间，为高并发场景提供存储空间基础。
本领域技术人员可以理解的是，内存通常包括易失性内存和非易失性内存，非易失性内存的存储容量通常大于易失性内存，常见的易失性内存包括动态随机存取存储器(Dynamic Random Access Memory，DRAM)，常见的非易失性内存包括非易失性双列直插式内存模块(Non-Volatile Dual In-line Memory Module，NVDIMM)，对于TOE硬件而言，即使是TCP链接的高并发场景，也是CPU发送数据和TOE硬件获取数据同步执行的过程，因此缓冲的数据并不需要永久性保存，基于此，在本实施例中既可以采用易失性内存，也可以采用非易失性内存，根据实际需求选取即可。
步骤S120，根据内存地址信息获取待发送数据，根据配置信息和待发送数据进行TOE卸载。
可以理解的是，TOE硬件根据内存地址信息从共享内存中获取待发送数据，根据配置信息和待发送数据进行TOE卸载，实现将处理TCP协议的功能从CPU转移至TOE硬件，从而有效减轻CPU的负荷。
需要说明的是，待发送数据可以是TCP协议的净荷数据，待发送数据的具体内容为本领域技术人员所熟知，本实施例不多作限定。
步骤S130，将通过TOE卸载得到的TCP报文发送至传输网络。
可以理解的是，通过TOE卸载得到TCP报文并发送至传输网络，实现将TCP协议的处理功能转移至TOE硬件。
需要说明的是，由于TCP报文是通过TOE硬件从共享内存中读取待发送数据，并根据待发送数据和配置信息执行TOE卸载得到，在完成TOE卸载之后，共享内存可以释放出可用的存储空间，实现共享内存中的存储空间的重复利用，提高空间的利用率。
需要说明的是，本申请实施例并不限制TOE硬件的具体架构，可以是现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)硬件，还可以是特殊应用集成电路(Application Specific Integrated Circuit，ASIC)。
另外，参照图2，在一实施例中，在图1所示实施例中的步骤S110之后，还包括但不限于有以下步骤。
步骤S210，确定待发送TCP链接的链接标识。
步骤S220，生成第一索引信息，第一索引信息表征链接标识与内存地址信息的映射关系。
步骤S230，生成第二索引信息，第二索引信息表征链接标识与配置信息的映射关系。
步骤S240，通过关联第一索引信息和第二索引信息得到待发送TCP链接的索引信息。
需要说明的是，链接标识可以是待发送TCP链接的唯一标识参数，本领域技术人员有动机根据从CPU以及共享内存中获取的数据中确定链接标识，本实施例对此不多作限定。
可以理解的是，针对TCP链接执行TOE卸载会生成对应的TCP报文，而TCP报文的内容组成为TCP链接的净荷数据以及TCP链接的配置信息，因此在获取来自CPU的内存地址信息以及待发送TCP链接的配置信息之后，需要确定待发送TCP链接的链接标识以及得到待发送TCP链接的链接标识、内存地址信息和配置信息之间的关联关系，即得到待发送TCP链接的索引信息，为实现TOE卸载提供数据基础。
另外，参照图3，在一实施例中，图2所示实施例中的步骤S230还包括但不限于有以下步骤。
步骤S310，在配置信息记录表中生成配置信息记录，配置信息记录包括配置信息、配置信息记录标识和链接标识，配置信息记录表预先设定并保存于本地。
步骤S320，通过关联配置信息记录和链接标识得到第二索引信息。
可以理解的是，在本地预先设定的配置信息表中生成配置信息记录，并通过关联配置信息记录和链接标识得到的第二索引信息能够为实现针对链接标识所对应的TCP链接进行TOE卸载提供数据基础。
需要说明的是，本申请实施例并不限制配置信息记录表在TOE硬件本地的存储位置，可以是存储在TOE硬件挂载的双倍数据速率(Double Data Rate，DDR)存储器中，本实施例不多作限定。
另外，在一实施例中，配置信息包括至少两种不同类型的数据结构信息，参照图4，图2 所示实施例中的步骤S230还包括但不限于有以下步骤。
步骤S410，确定与数据结构信息相对应的数据结构信息记录表，数据结构信息记录表针对每种数据结构信息预先设定并保存于本地。
步骤S420，在数据结构信息记录表中生成数据结构信息记录，数据结构信息记录包括数据结构信息、数据结构信息记录标识和链接标识。
步骤S430，将链接标识与全部的数据结构信息记录相关联，得到第二索引信息。
需要说明的是，数据结构信息包括待发送TCP链接对应的收发相关的序号、状态机、时间戳、定时器等，数据结构信息的具体内容为本领域技术人员所熟知，在此不多做限制。
可以理解的是，在本实施例中，根据不同类型的数据结构信息，在本地预先设定有分别对应的数据结构信息记录表，在确定与数据结构信息的类型相对应的数据结构信息记录表之后，将对应的数据结构信息存储至对应的数据结构信息记录表中，为实现针对链接标识所对应的TCP链接进行TOE卸载提供数据基础。
另外，参照图5，在一实施例中，图1所示实施例中的步骤S120还包括但不限于有以下步骤。
步骤S510，当接收到携带有目标链接标识的卸载指令，确定目标链接标识所对应的目标索引信息。
步骤S520，根据目标索引信息中的内存地址信息从共享内存中获取目标待发送数据。
步骤S530，根据目标索引信息中的配置信息确定目标配置。
步骤S540，根据目标配置和目标待发送数据进行TOE卸载。
可以理解的是，当接收到携带有目标链接标识的卸载指令，确定目标链接标识所对应的目标索引信息，即得到目标待发送TCP链接的链接标识、内存地址信息和配置信息之间的关联关系，根据目标索引信息中的内存地址信息从共享内存中获取目标待发送数据，根据目标索引信息中的配置信息确定目标配置，根据目标配置和目标待发送数据进行TOE卸载，从而实现将处理TCP协议的功能从CPU转移至TOE硬件，从而有效减轻CPU的负荷。
另外，参照图6，图6是本申请另一个实施例提供的数据处理方法的步骤流程图，该数据处理方法应用于TOE硬件，TOE硬件与CPU通信连接，该数据处理方法包括但不限于有以下步骤。
步骤S610，获取来自于传输网络的TCP报文，通过对TCP报文进行TOE卸载得到待接收TCP链接。
步骤S620，获取待接收TCP链接的配置信息和待接收数据，将待接收数据写入共享内存，其中，共享内存为TOE硬件与CPU共享的内存。
步骤S630，获取内存地址信息，将内存地址信息和配置信息发送至CPU，以使CPU根据内存地址信息获取待接收数据，并根据配置信息接收待接收数据，其中，内存地址信息表征待接收数据在共享内存的存储位置。
可以理解的是，获取来自于传输网络的TCP报文，通过对TCP报文进行TOE卸载得到待接收TCP链接，从待接收TCP链接中获取待接收TCP链接的配置信息和待接收数据，并将待接收数据写入共享内存，获取待接收数据在共享内存的存储位置信息，即内存地址信息，并将内存地址信息和配置信息发送至CPU，以使CPU根据内存地址信息获取待接收数据，并根据配置信息接收待接收数据，从而实现将处理TCP协议的功能从CPU转移至TOE硬件，从而 有效减轻CPU的负荷。
另外，参照图7，在一实施例中，在图6所示实施例中的步骤S630之后，还包括但不限于有以下步骤。
步骤S710，获取待接收TCP链接的链接标识。
步骤S720，生成第一索引信息，第一索引信息表征链接标识与内存地址信息的映射关系。
步骤S730，生成第二索引信息，第二索引信息表征链接标识与配置信息的映射关系。
步骤S740，通过关联第一索引信息和第二索引信息得到待接收TCP链接的索引信息。
需要说明的是，本实施例的技术方案和原理可以参考图2所示的实施例，主要区别在于本实施例实现TOE卸载的执行方向与图2所示的实施例的TOE卸载的执行方向不同，本实施例作为TCP报文的获取端，将待接收TCP链接的配置信息和TOE硬件将待接收数据存入共享内存的内存地址信息发送至CPU，以使CPU根据内存地址信息和配置信息进行待接收TCP链接的数据接收，除此以外与图2所示的实施例相近似，为了叙述简便，在此不多作赘述。
另外，参照图8，在一实施例中，图7所示实施例中的步骤S730还包括但不限于有以下步骤。
步骤S810，在配置信息记录表中生成配置信息记录，配置信息记录包括配置信息、配置信息记录标识和链接标识，配置信息记录表预先设定并保存于本地。
步骤S820，通过关联配置信息记录和链接标识得到第二索引信息。
需要说明的是，本实施例的技术方案和原理可以参考图3所示的实施例，主要区别在于本实施例实现TOE卸载的执行方向与图3所示的实施例的TOE卸载的执行方向不同，本实施例作为TCP报文的获取端，将待接收TCP链接的配置信息和TOE硬件将待接收数据存入共享内存的内存地址信息发送至CPU，以使CPU根据内存地址信息和配置信息进行待接收TCP链接的数据接收，除此以外与图3所示的实施例相近似，为了叙述简便，在此不多作赘述。
另外，在一实施例中，配置信息包括至少两种不同类型的数据结构信息，参照图9，图7所示实施例中的步骤S730还包括但不限于有以下步骤。
步骤S910，确定与数据结构信息相对应的数据结构信息记录表，数据结构信息记录表针对每种数据结构信息预先设定并保存于本地。
步骤S920，在数据结构信息记录表中生成数据结构信息记录，数据结构信息记录包括数据结构信息、数据结构信息记录标识和链接标识。
步骤S930，将链接标识与全部的数据结构信息记录相关联，得到第二索引信息。
需要说明的是，本实施例的技术方案和原理可以参考图4所示的实施例，主要区别在于本实施例实现TOE卸载的执行方向与图4所示的实施例的TOE卸载的执行方向不同，本实施例作为TCP报文的获取端，将待接收TCP链接的配置信息和TOE硬件将待接收数据存入共享内存的内存地址信息发送至CPU，以使CPU根据内存地址信息和配置信息进行待接收TCP链接的数据接收，除此以外与图4所示的实施例相近似，为了叙述简便，在此不多作赘述。
另外，参照图10，在一实施例中，图6所示实施例中的步骤S630还包括但不限于有以下步骤。
步骤S1010，将内存地址信息发送至CPU，以使CPU根据内存地址信息从共享内存中获取目标待接收数据。
步骤S1020，将配置信息发送至CPU，以使CPU根据配置信息确定目标配置，并根据目标 配置和待接收数据进行数据接收。
可以理解的是，TOE硬件将内存地址信息发送至CPU，使得CPU根据内存地址信息从共享内存中获取目标待接收数据，将配置信息发送至CPU，以使CPU根据配置信息确定目标配置，并根据目标配置和待接收数据进行数据接收，使得TCP握手建链的过程在TOE硬件实现，不需要CPU的参与，从而有效减轻CPU的负荷。
另外，参照图11，图11是本申请另一个实施例提供的TOE硬件的示意图，本申请的一个实施例还提供了一种TOE硬件1100，该TOE硬件1100包括：存储器1110、处理器1120及存储在存储器1110上并可在处理器1120上运行的计算机程序。
处理器1120和存储器1110可以通过总线或者其他方式连接。
实现上述实施例的数据处理方法所需的非暂态软件程序以及指令存储在存储器1110中，当被处理器1120执行时，执行上述实施例中的应用于TOE硬件1100的数据处理方法，例如，执行以上描述的图1中的方法步骤S110至方法步骤S130、图2中的方法步骤S210至方法步骤S240、图3中的方法步骤S310至方法步骤S320、图4中的方法步骤S410至方法步骤S430、图5中的方法步骤S510至方法步骤S540。
以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
此外，本申请的一个实施例还提供了一种计算机可读存储介质，该计算机可读存储介质存储有计算机可执行指令，该计算机可执行指令被一个处理器1120或控制器执行，例如，被上述TOE硬件1100实施例中的一个处理器1120执行，可使得上述处理器1120执行上述实施例中的应用于TOE硬件1100的数据处理方法，例如，执行以上描述的图1中的方法步骤S110至方法步骤S130、图2中的方法步骤S210至方法步骤S240、图3中的方法步骤S310至方法步骤S320、图4中的方法步骤S410至方法步骤S430、图5中的方法步骤S510至方法步骤S540。本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统可以被实施为软件、固件、硬件及其适当的组合。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本申请实施例包括一种数据处理方法、TOE硬件及计算机可读存储介质，其中，数据处理方法应用于TOE硬件，所述TOE硬件与中央处理器CPU通信连接，所述数据处理方法包括：获取所述CPU发送的内存地址信息和待发送传输控制协议TCP链接的配置信息，其中，所述内存地址信息表征待发送数据在共享内存的存储位置，所述待发送数据由所述CPU从所述待 发送TCP链接中获取并写入至所述共享内存，所述共享内存为所述TOE硬件和所述CPU共享的内存；根据所述内存地址信息获取所述待发送数据，根据所述配置信息和所述待发送数据进行TOE卸载；将通过TOE卸载得到的TCP报文发送至传输网络。根据本申请实施例提供的方案，能够有效增大处理TCP链接的运行空间，从而实现将TCP协议涉及的数据处理功能全部卸载到TOE硬件。
以上是对本申请的一些实施进行了具体说明，但本申请并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请范围的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (12)

  1. 一种数据处理方法，应用于传输控制协议卸载引擎TOE硬件，所述TOE硬件与中央处理器CPU通信连接，所述数据处理方法包括：
    获取所述CPU发送的内存地址信息和待发送传输控制协议TCP链接的配置信息，其中，所述内存地址信息表征待发送数据在共享内存的存储位置，所述待发送数据由所述CPU从所述待发送TCP链接中获取并写入至所述共享内存，所述共享内存为所述TOE硬件和所述CPU共享的内存；
    根据所述内存地址信息获取所述待发送数据，根据所述配置信息和所述待发送数据进行TOE卸载；
    将通过TOE卸载得到的TCP报文发送至传输网络。
  2. 根据权利要求1所述的方法，其中，在所述获取所述CPU发送的内存地址信息和待发送TCP链接的配置信息之后，所述方法还包括：
    确定所述待发送TCP链接的链接标识；
    生成第一索引信息，所述第一索引信息表征所述链接标识与所述内存地址信息的映射关系；
    生成第二索引信息，所述第二索引信息表征所述链接标识与所述配置信息的映射关系；
    通过关联所述第一索引信息和所述第二索引信息得到所述待发送TCP链接的索引信息。
  3. 根据权利要求2所述的方法，其中，所述生成第二索引信息，包括：
    在配置信息记录表中生成配置信息记录，所述配置信息记录包括所述配置信息、配置信息记录标识和所述链接标识，所述配置信息记录表预先设定并保存于本地；
    通过关联所述配置信息记录和所述链接标识得到所述第二索引信息。
  4. 根据权利要求2所述的方法，其中，所述配置信息包括至少两种不同类型的数据结构信息，所述生成第二索引信息，包括：
    确定与所述数据结构信息相对应的数据结构信息记录表，所述数据结构信息记录表针对每种所述数据结构信息预先设定并保存于本地；
    在所述数据结构信息记录表中生成数据结构信息记录，所述数据结构信息记录包括所述数据结构信息、数据结构信息记录标识和所述链接标识；
    将所述链接标识与全部的所述数据结构信息记录相关联，得到所述第二索引信息。
  5. 根据权利要求2所述的方法，其中，所述根据所述内存地址信息获取所述待发送数据，根据所述配置信息和所述待发送数据进行所述待发送TCP链接的TOE卸载，包括：
    当接收到携带有目标链接标识的卸载指令，确定所述目标链接标识所对应的目标索引信息；
    根据所述目标索引信息中的内存地址信息从所述共享内存中获取目标待发送数据；
    根据所述目标索引信息中的配置信息确定目标配置；
    根据所述目标配置和所述目标待发送数据进行TOE卸载。
  6. 一种数据处理方法，应用于TOE硬件，所述TOE硬件与CPU通信连接，所述数据处理方法包括：
    获取来自于传输网络的TCP报文，通过对所述TCP报文进行TOE卸载得到待接收TCP链 接；
    获取所述待接收TCP链接的配置信息和待接收数据，将所述待接收数据写入共享内存，其中，所述共享内存为所述TOE硬件与所述CPU共享的内存；
    获取内存地址信息，将所述内存地址信息和所述配置信息发送至所述CPU，以使所述CPU根据所述内存地址信息获取所述待接收数据，并根据所述配置信息接收所述待接收数据，其中，所述内存地址信息表征所述待接收数据在所述共享内存的存储位置。
  7. 根据权利要求6所述的方法，其中,在所述获取内存地址信息之后，所述方法还包括：
    获取所述待接收TCP链接的链接标识；
    生成第一索引信息，所述第一索引信息表征所述链接标识与所述内存地址信息的映射关系；
    生成第二索引信息，所述第二索引信息表征所述链接标识与所述配置信息的映射关系；
    通过关联所述第一索引信息和所述第二索引信息得到所述待接收TCP链接的索引信息。
  8. 根据权利要求7所述的方法，其中，所述生成第二索引信息，包括：
    在配置信息记录表中生成配置信息记录，所述配置信息记录包括所述配置信息、配置信息记录标识和所述链接标识，所述配置信息记录表预先设定并保存于本地；
    通过关联所述配置信息记录和所述链接标识得到所述第二索引信息。
  9. 根据权利要求7所述的方法，其中，所述配置信息包括至少两种不同类型的数据结构信息，所述生成第二索引信息，包括：
    确定与所述数据结构信息相对应的数据结构信息记录表，所述数据结构信息记录表针对每种所述数据结构信息预先设定并保存于本地；
    在所述数据结构信息记录表中生成数据结构信息记录，所述数据结构信息记录包括所述数据结构信息、数据结构信息记录标识和所述链接标识；
    将所述链接标识与全部的所述数据结构信息记录相关联，得到所述第二索引信息。
  10. 根据权利要求6所述的方法，其中，所述将所述内存地址信息和所述配置信息发送至所述CPU，以使所述CPU根据所述内存地址信息和所述配置信息进行所述待接收TCP链接的数据接收，包括：
    将所述内存地址信息发送至所述CPU，以使所述CPU根据所述内存地址信息从所述共享内存中获取目标待接收数据；
    将所述配置信息发送至所述CPU，以使所述CPU根据所述配置信息确定目标配置，并根据所述目标配置和所述待接收数据进行数据接收。
  11. 一种TOE硬件，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现如权利要求1至5中任意一项所述的数据处理方法，或者实现如权利要求6至10中任意一项所述的数据处理方法。
  12. 一种计算机可读存储介质，存储有计算机可执行指令，其中，所述计算机可执行指令用于执行如权利要求1至10中任意一项所述的数据处理方法。
PCT/CN2022/086150 2021-06-08 2022-04-11 数据处理方法、toe硬件及计算机可读存储介质 Ceased WO2022257587A1 (zh)

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