WO2022237419A1

WO2022237419A1 - Task execution method and apparatus, and storage medium

Info

Publication number: WO2022237419A1
Application number: PCT/CN2022/086072
Authority: WO
Inventors: 姜珊; 许凯程; 张晓谦; 孙忠刚
Original assignee: 中国第一汽车股份有限公司
Priority date: 2021-05-11
Filing date: 2022-04-11
Publication date: 2022-11-17
Also published as: CN113238842A

Abstract

The present application relates to the field of computer technologies, and discloses a task execution method and apparatus, and a storage medium. The method comprises: during execution of a periodic task, detecting whether there is non-volatile data being written; and in response to detecting that there is non-volatile data being written, executing a FLASH emulating EEPROM operation task within at least one remaining duration for executing the periodic task, each period corresponding to one remaining duration, each remaining duration being determined according to a duration for executing the periodic task and a preset duration in the corresponding period, and the preset duration being the period of the periodic task.

Description

Task execution method, device and storage medium

This application claims priority to a Chinese patent application with application number 202110513244.X filed with the China Patent Office on May 11, 2021, the entire contents of which are incorporated herein by reference.

technical field

The embodiments of the present application relate to the technical field of computers, for example, to a task execution method, device, and storage medium.

Background technique

In the vehicle real-time control system, the vehicle controller will write a large amount of non-volatile data during program operation. With the intelligent development of new energy vehicles, the amount of non-volatile data is gradually increasing, and the generation of non-volatile data always exists along with the life cycle of the entire electronic control unit (Electronic Control Unit, ECU). Therefore, how to store non-volatile data in real time becomes particularly important.

Electrically Erasable Programmable read-only memory (EEPROM) has the function of instant reading and writing, and the memory chip FLASH (that is, flash memory) does not have the function of instant reading and writing, so EEPROM is generally used to store non-volatile data. However, the storage space of EEPROM is limited, so FLASH is often used to simulate the read and write functions of EEPROM to store non-volatile data.

However, it takes a long time to execute the FLASH emulation EEPROM task. In order to avoid affecting the execution of other tasks, in the related art, the FLASH emulation EEPROM task is only executed during the power-off stage to realize writing of non-volatile data. In this way, the power-off phase will take too long.

Contents of the invention

The present application provides a task execution method, device and storage medium, which reduces the duration of the power-off phase by using the idle time of executing periodic tasks to execute FLASH simulation EEPROM tasks.

In the first aspect, the present application provides a task execution method, including: during the execution of the periodic task, detecting whether there is non-volatile data writing; Execute the FLASH simulation EEPROM operation task in at least one remaining period of time. Wherein, the cycle of the periodic task is a preset duration; each cycle corresponds to a remaining duration; each remaining duration is determined according to the duration of executing the periodic task and the preset duration in the corresponding cycle.

In a second aspect, the present application provides a task execution device, including: a detection module and an execution module;

The detection module is configured to detect whether non-volatile data is written during the execution of the periodic task by the execution module; the period of the periodic task is a preset duration;

The execution module is configured to respond to the detection module detecting that there is non-volatile data writing, and executes the FLASH simulation EEPROM operation task in at least one remaining period of executing the periodic task; each period corresponds to a remaining period; each remaining period It is determined according to the duration of executing the periodic task and the preset duration in the corresponding cycle.

In a third aspect, the present application provides a task execution device, including a memory, a processor, a bus, and a communication interface; the memory is configured to store instructions executed by a computer, and the processor and the memory are connected through a bus; when the task execution device is running, the processor executes The computer stored in the memory executes instructions, so that the task execution device executes the task execution method provided in the first aspect above.

In a fourth aspect, the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer executes the instructions, the computer executes the task execution method as provided in the first aspect.

In a fifth aspect, the present application provides a computer program product, the computer program product includes computer instructions, and when the computer instructions are run on a computer, the computer is made to execute the task execution method as provided in the first aspect.

It should be noted that all or part of the above computer instructions may be stored on a computer-readable storage medium. Wherein, the computer-readable storage medium may be packaged together with the processor of the task execution device, or may be separately packaged with the processor of the task execution device, which is not limited in this application.

For the descriptions of the second aspect, the third aspect, the fourth aspect and the fifth aspect in this application, reference may be made to the detailed description of the first aspect.

In this application, the names of the above-mentioned task performing apparatuses do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalent technologies.

Description of drawings

FIG. 1 is a schematic flowchart of a task execution method provided by an embodiment of the present application;

FIG. 2 is a schematic flowchart of another task execution method provided by the embodiment of the present application;

FIG. 3 is a schematic flowchart of another task execution method provided by the embodiment of the present application;

FIG. 4 is a schematic flowchart of another task execution method provided in the embodiment of the present application;

FIG. 5 is a schematic flowchart of another task execution method provided by the embodiment of the present application;

FIG. 6 is a schematic flowchart of another task execution method provided by the embodiment of the present application;

FIG. 7 is a schematic structural diagram of a task execution device provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another task execution device provided by an embodiment of the present application.

Detailed ways

The task execution method, device and storage medium provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations.

The terms "first" and "second" in the specification and drawings of the present application are used to distinguish different objects, or to distinguish different processes for the same object, rather than to describe a specific sequence of objects.

In addition, the terms "including" and "having" mentioned in the description of the present application and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include other unlisted steps or units, or may optionally also include Other steps or elements inherent to the process, method, product or apparatus are included.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

In the description of the present application, unless otherwise specified, the meaning of "plurality" refers to at least two.

In the vehicle real-time control system, the vehicle controller will write a large amount of non-volatile data during program operation. With the intelligent development of new energy vehicles, the amount of non-volatile data is gradually increasing, and the generation of non-volatile data always exists along with the life cycle of ECU. Therefore, how to store non-volatile data in real time becomes particularly important.

EEPROM has the function of reading and writing in real time, and FLASH does not have the function of reading and writing in real time, so EEPROM is generally used to store non-volatile data. However, the storage space of EEPROM is limited, so FLASH is often used to simulate the read and write functions of EEPROM to store non-volatile data.

The FLASH analog EEPROM in the related art can be implemented in two ways: synchronous and asynchronous. In the synchronous implementation mode, FLASH emulates EEPROM for a long time, and the emulation operation cannot be interrupted, which affects the execution of other tasks. In the process of asynchronous implementation, although the single running time of FLASH emulated EEPROM is short, the number of cycle scheduling is large, and when the amount of stored data is large, the overall running time is longer.

Due to the defects of the above two methods, currently only the FLASH simulation EEPROM task is performed in the power-off stage to realize the writing of non-volatile data. However, this would result in an excessively long power-down phase.

In view of the problems existing in the above-mentioned related technologies, the embodiment of the present application provides a task execution method, device and storage medium, by using the idle time of executing periodic tasks to execute FLASH simulation EEPROM tasks, so as to reduce the duration of the power-off phase.

The task execution method provided in the embodiment of the present application may be applicable to a task execution device. The task execution device may be a physical machine (such as a server), or a virtual machine (virtual machine, VM) deployed on the physical machine. A real-time operating system (Real Time Operating System, RTOS) is embedded in the task execution device, and the RTOS can be set to execute the periodic tasks involved in the embodiments of the present application.

It can be understood that, in the case where the task execution device is a server, the server may be one server, or may be a server cluster composed of multiple servers, which is not limited in this embodiment of the present application.

The task execution method provided by this application will be described in detail below.

Referring to Figure 1, the task execution method provided by the embodiment of the present application includes S101-S102:

S101. During the periodical task execution by the task execution device, detect whether non-volatile data is written.

Wherein, the period of the periodical task may be a preset duration determined artificially in advance.

During the execution of periodic tasks by the real-time operating system embedded in the task execution device, the non-volatile memory (Non Volatile Memory, NVM) scheduler in the real-time operating system can be set to control the FLASH to realize the simulation operation, and the writing of the NVM scheduler The interface is set up to receive write requests for non-volatile data. Therefore, optionally, in a possible implementation, the task execution device may determine whether the write interface of the NVM scheduler detects a write request, and if it is determined that the write interface detects a write request, determine whether there is a write request. Non-volatile data writes.

S102. The task execution device executes the FLASH simulation EEPROM operation task within at least one remaining period of execution of the periodic task when it detects that non-volatile data is written.

Wherein, each cycle corresponds to a remaining duration. Each remaining duration is determined according to the duration of executing the periodic task and the preset duration in the corresponding period.

In a possible implementation manner, the remaining duration may be determined according to a difference between a preset duration and a duration for executing a periodic task in a corresponding period. Exemplarily, when the task executing device executes the periodic task, the time interval between the first period and the second period is 10ms, that is, the preset duration in the embodiment of the present application is 10ms. In the first cycle, the period required by the task execution device to execute the periodic task is 5 ms, and in the second cycle, the time required by the task execution device to execute the periodic task is 7 ms. Then it can be determined that the remaining time in the first cycle is 5ms, that is, the time for executing the FLASH simulation EEPROM operation task in the first cycle is 5ms, and the remaining time in the second cycle is 3ms, that is, in the second cycle The duration of executing the FLASH simulation EEPROM operation task in the cycle is 3ms.

In another possible implementation, the remaining duration can also be determined based on the resources occupied by executing periodic tasks and the resources occupied by executing FLASH simulation EEPROM operation tasks, that is, the execution of periodic tasks and the execution of FLASH simulation EEPROM can be determined. The time during which the resources occupied by the operation tasks do not conflict is determined as the remaining time. Exemplarily, the FLASH simulation EEPROM operation task is implemented by program code in most cases, and the program code must be implemented by a single thread, and cannot be executed in parallel with the periodic task. However, when the FLASH simulation EEPROM operation task is implemented by hardware such as a chip, it does not conflict with the execution of periodic tasks. At this time, the FLASH simulation EEPROM operation task can be paralleled with the periodic task at the same time.

Optionally, in a possible implementation manner, the FLASH simulation EEPROM operation task may be executed within at least one remaining period of execution of the periodic task by setting the priorities of the periodic task and the FLASH simulation EEPROM operation task. For example, it can be determined that the priority of the periodic task is higher than that of the FLASH simulation EEPROM operation task, so that when the task execution device executes the task, it can execute the tasks in the order of priority. The periodic task can be executed preferentially, and the FLASH simulated EEPROM operation task is executed within at least one remaining period of execution of the periodic task. In this way, the execution of the FLASH simulated EEPROM operation task will not affect the execution of the periodic task.

Optionally, in a possible implementation manner, the FLASH simulation EEPROM operation task can be set to be triggered by an event set by the verification interface of the NVM scheduler, and the event trigger is used to trigger the execution of the FLASH simulation EEPROM operation task. When the task execution device detects that non-volatile data is written, it can call the verification interface to set an event trigger to trigger the execution of the FLASH simulation EEPROM operation task within at least one remaining time period.

In order to ensure that multiple FLASH simulation EEPROM operation tasks do not interfere with each other, the next FLASH simulation EEPROM operation subtask can be re-executed after a FLASH simulation EEPROM operation subtask is completed. Therefore, optionally, in a possible implementation, the task execution device can close the verification interface after calling the verification interface to set the event trigger, and then restart the verification after the FLASH simulation EEPROM operation task is completed. interface. In this way, if a FLASH simulation EEPROM operation task is being executed, because the verification interface is closed, the task execution device cannot call the verification interface to set an event trigger, and another FLASH simulation EEPROM operation task cannot be started.

Optionally, in a possible implementation manner, the verification interface may be a runtime environment/client-server (Run-time environment/Client-Server, RTE/C-S) interface.

It can be understood that, in practical applications, event triggering may also be set in other ways, which is not limited in this embodiment of the present application. Exemplarily, event triggering can also be implemented by modifying program codes in the real-time operating system.

Optionally, in order to ensure that multiple FLASH simulated EEPROM operation tasks do not interfere with each other, in a possible implementation, after the task execution device calls the verification interface to set the event trigger, it can also set the scheduling status of the NVM scheduler to Change to PENDING state. In the PENDING state, you can wait for the periodic tasks being executed to complete. After the periodic tasks are executed, change the scheduling state of the NVM scheduler to the execution (BUSY) state. The NVM scheduler cannot be rescheduled in the BUSY state and the PENDING state. For other FLASH simulation EEPROM operation tasks, after the current FLASH simulation EEPROM operation task is completed, the scheduling state is changed to the idle (IDLE) state, and other FLASH simulation EEPROM operation tasks can be rescheduled in the IDLE state.

In the task execution method provided in the embodiment of the present application, during the execution of periodic tasks, the tasks are not executed all the time. Instead, after the periodic tasks in one cycle are executed, the periodic tasks will not be executed until the next cycle node. Therefore, the technical solution provided by the embodiment of the present application can utilize the idle time during the periodical task implementation to execute the FLASH simulation EEPROM operation task. In this way, the FLASH simulated EEPROM can complete the writing operation of non-volatile data in real time, and it is not necessary to perform the FLASH simulated EEPROM operation task in the power-off stage. Therefore, compared with the task execution method in the related art, the technical solution provided by the present application can reduce the duration of the power-off phase.

As shown in Figure 2, the embodiment of the present application also provides a task execution method, including S201-S203:

S201. The task execution device determines that the priority of the periodic task is higher than that of the FLASH simulation EEPROM operation task.

S202. The task execution device detects whether non-volatile data is written during the execution of the periodic task.

S203. In the case of detecting that non-volatile data is written, the task execution device executes the FLASH simulation EEPROM operation task within at least one remaining duration according to the priority.

Optionally, as shown in Figure 3, this embodiment of the present application also provides a task execution method, including S301-S303:

S301. The task execution device determines that the FLASH simulation EEPROM operation task is triggered by a verification interface setting event of the NVM scheduler.

S302. The task execution device detects whether non-volatile data is written during the execution of the periodic task.

S303. When the task execution device detects that non-volatile data is written, it invokes the verification interface to set an event trigger, and triggers the execution of the FLASH simulation EEPROM operation task within at least one remaining duration.

Optionally, as shown in Figure 4, this embodiment of the present application also provides a task execution method, including S401-S405:

S401. The task execution device determines that the FLASH simulation EEPROM operation task is triggered by a verification interface setting event of the NVM scheduler.

S402. The task executing device detects whether non-volatile data is written during the execution of the periodic task.

S403. When the task execution device detects that non-volatile data is written, it invokes the verification interface to set an event trigger, and closes the verification interface.

S404. The task execution device executes the FLASH simulation EEPROM operation task within at least one remaining time period.

S405. The task execution device opens the verification interface after the FLASH simulation EEPROM operation task is executed.

Optionally, as shown in Figure 5, this embodiment of the present application also provides a task execution method, including S501-S505:

S501. The task execution device determines that the FLASH simulation EEPROM operation task is triggered by a verification interface setting event of the NVM scheduler.

S502. The task executing device detects whether non-volatile data is written during the execution of the periodic task.

S503. When the task execution device detects that non-volatile data is written, it invokes the verification interface to set an event trigger, and changes the scheduling state of the NVM scheduler to a waiting state.

S504. The task execution device executes the FLASH simulation EEPROM operation task within at least one remaining duration, and changes the scheduling state to the execution state during execution of the FLASH simulation EEPROM operation task.

S505. The task execution device changes the scheduling state to an idle state after the FLASH simulation EEPROM operation task is executed.

In order to more clearly illustrate the task execution method provided by the embodiment of the present application, referring to FIG. 6 , an embodiment will be used for a detailed description below. As shown in Figure 6, the task execution method provided by the embodiment of the present application includes S601-S604:

S601. Start the real-time operating system in the task execution device, and initialize the task.

S602. The task executing device executes periodic task A.

S603. The task executing device executes the periodic task B.

S604. The task executing device executes the periodic task C.

It can be understood that the task execution device can execute multiple periodic tasks at the same time. In practical applications, one of the multiple periodic tasks can be selected, and the FLASH simulation EEPROM operation task can be executed within at least one remaining duration of the periodic task. . Therefore, the embodiment of the present application does not limit the order of the above steps S602-S604, and may be executed in parallel.

Exemplarily, as shown in FIG. 6 , taking the execution of the FLASH simulation EEPROM operation task within at least one remaining duration of periodic task A as an example, the task execution device executes steps S6021-S6025 during execution of step S602.

S6021. Determine whether there is non-volatile data written.

If the task execution device determines that there is non-volatile data written, execute S6022; if the task execution device determines that no non-volatile data is written during the execution of periodic task A, only periodic task A needs to be executed.

S6022. Determine whether the NVM scheduler is in the IDLE state.

When the task execution device determines that the NVM scheduler is in the IDLE state, execute S6023; when the task execution device determines that the NVM scheduler is not in the IDLE state, but in the BUSY state or the PENDING state, re-execute after the first preset interval S6022.

Wherein, the first preset interval may be a time length determined artificially in advance, which is not limited in this embodiment of the present application.

S6023. Call the verification interface to set an event trigger, close the verification interface, and change the scheduling state to the PENDING state.

S6024. Execute the FLASH simulation EEPROM operation task within at least one remaining duration, and change the scheduling state to the BUSY state during the execution of the FLASH simulation EEPROM operation task.

S6025. After the execution of the FLASH simulation EEPROM operation task is completed, change the scheduling state to the IDLE state, and open the verification interface.

The embodiment of the present application only shows three periodic tasks as an example, and the embodiment of the present application does not limit the number of periodic tasks.

It can be understood that, in practical applications, during the execution of periodic task B or periodic task C by the task execution device, the processing process of the task execution device is the same as that of the execution device during the execution of periodic task A, you can refer to the aforementioned steps S6021-S6025 Relevant descriptions are not repeated in this embodiment of the present application.

It should be noted that, in practical applications, it takes a long time to execute the FLASH simulation EEPROM operation task, and often needs to use multiple remaining time periods. Therefore, a complete FLASH simulation EEPROM operation task can be executed by using the remaining duration of multiple continuous periodic tasks, and it can be executed according to the priority of the task during the implementation process.

As shown in FIG. 7 , the embodiment of the present application also provides a task execution device, which may include: a detection module 11 and an execution module 12 .

Wherein, the detection module 11 may execute S101 in the above method embodiment, and the execution module 12 may execute S102 in the above method embodiment.

Exemplarily, the detection module 11 is configured to detect whether non-volatile data is written during the execution module 12 executing the periodic task; the period of the periodic task is a preset duration;

The execution module 12 is configured to execute the FLASH simulation EEPROM operation task in at least one remaining duration of performing periodic tasks when the detection module 11 detects that non-volatile data is written; each cycle corresponds to a remaining duration; Each remaining duration is determined according to the duration of executing the periodic task and the preset duration in the corresponding cycle.

Optionally, in a possible implementation, the task execution device provided by the present application may further include: a determination module configured to determine that the priority of the periodic task is higher than that of the FLASH simulation EEPROM operation task;

The execution module 12 is configured to execute the FLASH simulation EEPROM operation task within at least one remaining duration according to the priority.

Optionally, in another possible implementation, the determination module is also configured to determine that the FLASH simulation EEPROM operation task is triggered by the verification interface setting event of the NVM scheduler; the event trigger is used to trigger the execution of the FLASH simulation EEPROM operation task;

The execution module 12 is configured to, when the detection module 11 detects that non-volatile data is written, call the verification interface to set an event trigger, and trigger the execution of the FLASH simulation EEPROM operation task within at least one remaining duration.

Optionally, in another possible implementation, the task execution device provided by the present application may also include a processing module, and the processing module is configured to close the verification interface after calling the verification interface to set an event trigger; the processing module also It is set to enable the verification interface after the FLASH simulation EEPROM operation task is completed.

Optionally, in another possible implementation,

The processing module is also configured to change the scheduling state of the NVM scheduling machine to a waiting state after calling the verification interface to set the event trigger;

The processing module is also configured to change the scheduling state to the execution state during the execution of the FLASH simulation EEPROM operation task;

The processing module is also configured to change the scheduling state to an idle state after the FLASH simulation EEPROM operation task is executed.

Optionally, in another possible implementation manner, the foregoing "verification interface" is an RTE/C-S interface.

Optionally, in another possible implementation, the detection module 11 is configured to: determine whether the write interface of the NVM scheduler detects a write request; if it is determined that the write interface detects a write request, determine There is non-volatile data written.

Optionally, the task performing device may further include a storage module configured to store program codes of the task performing device and the like.

As shown in Figure 8, the embodiment of the present application also provides a task execution device, including a memory 41, a processor 42, a bus 43, and a communication interface 44; 43 connection; when the task execution device is running, the processor 42 executes the computer-executed instructions stored in the memory 41, so that the task execution device executes any one of the task execution methods provided in the above-mentioned embodiments.

Optionally, the task execution device may further include a transceiver configured to perform the steps of sending and receiving data, signaling or information under the control of the processor of the task execution device, for example, receiving a write request.

Optionally, the task execution device may be a physical machine for implementing task execution, or may be a part of the physical machine, for example, may be a chip system in the physical machine. The chip system is configured to support the task execution device to implement the functions involved in any of the above task execution methods of the present application, for example, receive, send or process the data and/or information involved in the above task execution methods. The chip system includes a chip, and may also include other discrete devices or circuit structures.

In a specific implementation, as an embodiment, the processors 42 (42-1 and 42-2) may include at least one central processing unit (central processing unit, CPU), such as CPU0 and CPU1 shown in FIG. 8 . And as an embodiment, the task execution apparatus may include multiple processors 42, such as the processor 42-1 and the processor 42-2 shown in FIG. 8 . Each CPU in these processors 42 may be a single-core processor (single-CPU), or a multi-core processor (multi-CPU). Processor 42 herein may refer to at least one device, circuit, and/or processing core for processing data (eg, computer program instructions).

Memory 41 can be read-only memory 41 (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM) or other types that can store information and instructions Type of dynamic storage device, also can be electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), read-only disc (compact disc read-only memory, CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures and can be used by Any other medium accessed by a computer, but not limited to. The memory 41 may exist independently, and is connected to the processor 42 through the bus 43 . The memory 41 can also be integrated with the processor 42 .

In a specific implementation, the memory 41 is set to store the data in this application and the computer-executed instructions corresponding to executing the software program of this application. The processor 42 can perform various functions of the device by running or executing software programs stored in the memory 41 and calling data stored in the memory 41 .

Communication interface 44, using any device such as a transceiver, configured to communicate with other devices or communication networks, such as control systems, wireless access networks (radio access network, RAN), wireless local area networks (wireless local area networks, WLAN), etc. . The communication interface 44 may include a receiving unit to implement a receiving function, and a sending unit to implement a sending function.

The bus 43 may be an industry standard architecture (industry standard architecture, ISA) bus, a peripheral component interconnect (PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, etc. The bus 43 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 8 , but it does not mean that there is only one bus or one type of bus.

As an example, with reference to Figure 7, the processing module in the task execution device implements the same function as the processor in Figure 8, and the storage module in the task execution device implements the same function as the memory in Figure 8 .

For the explanation of relevant content in this embodiment, reference may be made to the foregoing method embodiment, and details are not repeated here.

Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and brevity of the description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be allocated according to needs It is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the working process of the above-described system, device, and unit, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

The embodiment of the present application also provides a computer-readable storage medium, where an instruction is stored in the computer-readable storage medium, and when the computer executes the instruction, the computer executes any one of the task execution methods provided in the foregoing embodiments.

Wherein, the computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (non-exhaustive list) of computer readable storage media include: electrical connection with at least one lead, portable computer disk, hard disk, RAM, ROM, erasable programmable read-only memory (erasable programmable read-only memory) only memory, EPROM), registers, hard disks, optical fibers, CD-ROMs, optical storage devices, magnetic storage devices, or any suitable combination of the above, or any other form of computer-readable storage media known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an application specific integrated circuit (ASIC). In the embodiments of the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, and the program may be used by or in combination with an instruction execution system, device or device.

Claims

A method for performing tasks, comprising:

During the execution of the periodic task, detect whether there is non-volatile data writing; the period of the periodic task is a preset duration;

In response to detecting that the non-volatile data is written, execute the FLASH simulation chargeable erasable programmable read-only memory EEPROM operation task within at least one remaining period of performing the periodic task; each cycle corresponds to a remaining period ; Each remaining duration is determined according to the duration of executing the periodic task and the preset duration in the corresponding period.
The task execution method according to claim 1, further comprising:

Determine that the priority of the periodic task is higher than the priority of the FLASH simulation EEPROM operation task;

The performing the FLASH simulation EEPROM operation task within at least one remaining period of executing the periodic task includes: executing the FLASH simulation EEPROM operation task within the at least one remaining period according to the priority.
The task execution method according to claim 1, further comprising:

It is determined that the FLASH simulation EEPROM operation task is triggered by the verification interface setting event of the non-volatile memory NVM scheduler; the event trigger is used to trigger execution of the FLASH simulation EEPROM operation task;

In response to detecting that the non-volatile data is written, performing a FLASH simulation EEPROM operation task within at least one remaining period of executing the periodic task includes;

In response to detecting that the non-volatile data is written, calling the verification interface to set the event trigger triggers execution of the FLASH simulation EEPROM operation task within the at least one remaining duration.
The task execution method according to claim 3, further comprising:

After the event trigger is set by calling the verification interface, closing the verification interface;

After the execution of the FLASH simulation EEPROM operation task is completed, the verification interface is opened.
The task execution method according to claim 3, further comprising:

After the event trigger is set by calling the verification interface, changing the scheduling state of the NVM scheduler to a waiting state;

During the execution of the FLASH simulation EEPROM operation task, the scheduling state of the NVM scheduler is changed to an execution state;

After the execution of the FLASH simulation EEPROM operation task is completed, the scheduling state of the NVM scheduling machine is changed to an idle state.
The task execution method according to any one of claims 3-5, wherein the verification interface is an operating environment/client-server RTE/C-S interface.
The task execution method according to claim 1, wherein said detecting whether non-volatile data is written includes:

Determine whether the write interface of the NVM scheduler detects a write request;

In response to determining that the write interface of the NVM scheduler detects the write request, it is determined that the non-volatile data is written.
A task performance device, comprising:

The detection module is configured to detect whether non-volatile data is written during the execution of the periodic task by the execution module; the period of the periodic task is a preset duration;

The execution module is configured to, in response to the detection module detecting that the non-volatile data is written, execute the FLASH simulation charged erasable programmable read-only memory during at least one remaining period of executing the periodic task EEPROM operation tasks; each cycle corresponds to a remaining duration; each remaining duration is determined according to the duration of executing the periodic task and the preset duration in the corresponding cycle.
A task execution device, comprising a memory, a processor, a bus, and a communication interface; the memory is configured to store instructions executed by a computer, and the processor is connected to the memory through the bus;

When the task execution device is running, the processor executes the computer-executed instructions stored in the memory, so that the task execution device executes the task execution method according to any one of claims 1-7.
A computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer executes the instructions, the computer executes the task execution method according to any one of claims 1-7 .