WO2022225698A2 - Superlattice, ferroic order thin films for use as high/negative-k dielectric - Google Patents

Abstract

Disclosed are HfO2-ZrO2 superlattice heterostructures such as a gate stack (24), stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto silicon (Si) transistors and scaled down to ∼20 Å, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ∼6.5 Å effective SiO2 thickness, which is even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself, and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, the disclosed gate stacks (24), which do not require such scavenging, provide substantially lower leakage current and no mobility degradation and demonstrate that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the sub-2 nm thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

Description

SUPERLA TTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC

Government Support

[0001] This invention was made with government support under Grant Number FA8650-19-2-7933 awarded by the Office of Naval Research. The government has certain rights in the invention.

Related Applications

[0002] This application claims the benefit of U.S. provisional patent application serial number 63/170,826, filed April 5, 2021, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0003] The present disclosure relates to semiconductor devices and in particular to semiconductor devices that comprise superlattice heterostructures.

Background

[0004] With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This need has led to the adoption of high- dielectric hafnium oxide (Flf02) in the gate stack, which remains as the material of choice to date. Moreover, with the two-dimensional scaling of silicon field-effect transistors reaching fundamental limits, new functional improvements to transistors, as well as novel computing paradigms and vertical device integration at the architecture level, are currently under intense study. Gate oxides play a critical role in this endeavor, as gate oxides are a common performance booster for all devices, including silicon, new channel materials with potential for higher performance, and even materials suitable for three-dimensional integrated transistors. Indeed, the gate oxide transition from silicon dioxide (S1O2) to high-k dielectric (DE) is considered a paradigm shift in computing technology. In this context, ferroelectric oxides offer new functionalities considered promising for energy- efficient electronics. The advent of atomic layer deposition (ALD)–grown ferroelectric-doped HfO2 has overcome much of the material compatibility issues that plague traditional perovskite-based ferroelectric materials. In addition, considering ferroic order persists down to a thickness of 1 nm in this system allows for integration of these oxides in the most aggressively scaled devices in which the state-of-the-art high-κ oxide thickness is less than 2 nm. [0005] In an advanced silicon transistor, the gate oxide is a combination of two distinct layers. The first is an interfacial SiO2 formed with a self-limiting process, resulting in ∼8.0-8.5 Å thickness. The next is the high-κ (HK) dielectric HfO2 layer that is typically ∼2 nm in thickness. Higher capacitance of this series combination is desirable to suppress short channel effects. The capacitance is conventionally represented by effective oxide thickness (EOT), where lower EOT represents higher

capacitance. Therefore, the EOT minimum value is limited by the interfacial SiO₂ thickness. Indeed, even integrating HfO₂ as the high-κ layer, the EOT is typically ∼9 Å. To go below this value, the semiconductor industry has implemented sophisticated scavenging techniques to reduce the SiO₂ thickness after the full gate stack is formed. Although this technique is very effective in scaling EOT, the thinner SiO2 results in undesirable leakage current and mobility degradation. Thus, what is needed is a new gate structure that provides the desired higher capacitance while limiting undesirable leakage current and mobility degradation. Summary [0006] With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This need has led to the adoption of high-κ dielectric hafnium oxide (HfO2) in the gate stack, which remains as the material of choice to date. The present disclosure relates to HfO₂-ZrO₂ (zirconium oxide) superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto silicon (Si) transistors and scaled down to ∼20 Å, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ∼6.5 Å effective SiO₂ thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO₂-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, the gate stacks according to the present disclosure, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. The present disclosure demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric- antiferroelectric order, stabilized in the sub-2 nm thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics. [0007] In another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein. [0008] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. Brief Description of the Drawing Figures [0009] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure. [0010] Figure 1A shows the phenomeno-logical model of negative capacitance in a mixed ferroic system, with Landau free energy landscapes for a ferroelectric (FE), antiferroelectric (AFE), and mixed FE-AFE system. [0011] Figure 1B shows engineering of ferroic phase competition in the HfO2-ZrO2 fluorite-structure system. [0012] Figure 1C depicts thin films of HfO2-ZrO2 that are grown using atomic layer deposition (ALD) in which the nanolaminate periodicity is dictated by the sequence of Hf:Zr (4:12) ALD cycles before the Hf-Zr superstructure is repeated various times.

[0013] Figure 1 D shows the underlying mixed ferroic order in these HfC - Zr02 heterostructures as established by high-resolution TEM.

[0014] Figure 1 E shows synchrotron in-plane grazing incidence diffraction demonstrating the presence of both the AFE T-phase (101) and FE O-phase (111) reflections the cf-lattice spacings of which are consistent with those extracted from TEM.

[0015] Figure 2A shows metal-insulator-metal (MIM) capacitance-voltage ( C-V) hysteresis loops for a mixed FE-AFE Flf02-Zr02 multilayer demonstrating higher capacitance compared against its AFE (Zr02) and FE (Zr: Hf02) counterparts of the same thickness.

[0016] Figure 2B shows the inverse capacitance versus thickness of the MIM Flf02-Zr02 multilayers up to five superlattice repeats (10 nm), with an extracted permittivity of 52, which is extremely large for Flf02-based oxides. [0017] Figure 2C shows MIM C-V hysteresis loops for Flf02-Zr02 multilayers of the same periodicity demonstrating an evolution from mixed- ferroic to FE-like hysteresis upon cooling slightly below room temperature. [0018] Figure 2D shows metal oxide semiconductor (MOS) accumulation C-V of Flf02-Zr02-Flf02 trilayer compared with AFE Zr02, FE Zr: Hf02, and high-K dielectric Hf02, all of the same thickness (20 A), indicating mixed- ferroic behavior is optimal for enhancing capacitance rather than purely FE or AFE behavior.

[0019] Figure 2E shows accumulation C-V of the Flf02-Zr02-Flf02 trilayer compared with bilayer and solid-solution films of the same thickness (ALD cycles) and composition (Hf:Zr cycles), with an inset showing a diagram of multilayer (Hf and Zr cations vertically separated) versus solid solution (Hf and Zr cations intermixed).

[0020] Figure 2F shows accumulation C-V curves for a 2 nm Hf02-Zr02- Hf02 trilayer grown on sub-nanometer S1O2 fit to effective oxide thickness (EOT) simulations.

[0021] Figure 3A shows Hf02-Zr02 multilayer and Zr-rich Hf:Zr02 solid solution films. [0022] Figure 3B shows MOS accumulation C-V of the HfC -ZrC -HfC trilayer (60% Zr) compared with solid solution films of the same thickness (2 nm) and composition (60% Zr).

[0023] Figure 3C shows MIM C-V hysteresis loops of the Flf02-Zr02 superlattice (60% Zr) compared with solid solution films of the same thickness (6 nm) and composition (60% Zr).

[0024] Figure 4A shows leakage-effective oxide thickness (J_G-EOT) scaling of the multilayer gate stacks benchmarked against reported high-k metal gate (FIKMG) literature. [0025] Figure 4B shows normalized mobility versus EOT scaling of the multilayer gate stacks benchmarked against reported FIKMG literature.

[0026] Figure 4C shows a graph showing g_m versus gate voltage (VG) for long-channel bulk transistors (LG = 1 _jum).

[0027] Figure 4D shows a transfer characteristic of a typical transistor. [0028] Figure 4E shows an output characteristic of a typical transistor.

[0029] Figure 4F shows device de-embedded and extrinsic transconductance.

[0030] Figure 5 is a cross-sectional view of an exemplary embodiment of a semiconductor device in the form of an advanced transistor that is accordance with the present disclosure.

[0031] Figure 6A shows the Flf02-Zr02 multilayer structure on S1O2- buffered silicon.

[0032] Figure 6B shows synchrotron X-ray-reflectometry (XRR) of thicker Flf02-Zr02 heterostructures repeated with the same periodicity as the thinner trilayer structure.

[0033] Figure 6C shows layer-resolved electron energy loss spectroscopy (EELS) of the 2 nm Hf02-Zr02-Hf02 trilayer, which again shows clear separation of Hf02-Zr02 layers following the expected 4 A-12 A-4 A Hf02- Zr02-Flf02 structure. [0034] Figure 6D illustrates angle-resolved X-ray photoelectron spectroscopy (XPS) of the 2 nm Hf02-Zr02-Hf02 trilayer and the extracted atomic composition.

[0035] Figure 7 A shows Hf02-Zr02 multilayer and Hf:Zr02 solid solution films. [0036] Figure 7B shows a comparison of MOS capacitor accumulation C-V characteristics in Hf02-Zr02 multilayers.

[0037] Figure 7C is a diagram showing a comparison of mixed-ferroic behavior in low-temperature treated MIM Flf02-Zr02 multilayers versus FE behavior in in the same multilayers annealed at high temperatures.

[0038] Figure 8A illustrates in-plane synchrotron grazing-incidence diffraction (GID) of a bare Flf02-Zr02-Flf02 trilayer indexed to the tetragonal/orthorhombic phases.

[0039] Figure 8B illustrates the two-dimensional reciprocal space map of a bare 2 nm Flf02-Zr02-Flf02 trilayer indexed to the tetragonal/orthorhombic phases by indexing integrated diffraction spectrum.

[0040] Figure 8C illustrates synchrotron X-ray absorption spectroscopy (XAS) of a bare 2 nm Flf02-Zr02-Flf02 trilayer at the Hf Mz (left) and Zr Lz,2 edges.

[0041] Figure 8D shows second harmonic generation (SFIG) mapped across a bare 2 nm Flf02-Zr02-Flf02 trilayer.

[0042] Figure 8E shows mixed ferroic order in Flf02-Zr02 heterostructures is established by high-resolution TEM along with graphs of intensity versus distance.

[0043] Figure 8F shows additional mixed ferroic order in Flf02-Zr02 heterostructures is established by high-resolution TEM along with graphs of intensity versus distance. Figure 9A is a graphic indicating transition from mixed tetragonal-orthorhombic phase to predominately orthorhombic structure as a function of temperature.

[0044] Figure 9B shows crystal field splitting for fluorite-structure polymorphs; the symmetry-induced e-splitting provides a spectroscopic signature for the polar O-phase.

[0045] Figure 9C shows hard and soft synchrotron X-ray spectroscopy measured at beamline 4-ID-D of the Advanced Photon Source.

[0046] Figure 9D shows simulated oxygen -edge XAS spectra for the respective O-phase and T-phase; the XAS provides spectroscopic signatures to distinguish between the O-phase and T-phase, which are difficult to resolve from GID. [0047] Figure 9E shows prototypical C-V behavior for mixed antiferroelectric-ferroelectric and ferroelectric films in MIM capacitor structures. [0048] Figure 9F shows temperature-dependent C-V for thicker HfO2-ZrO2 multilayers of the same periodicity demonstrating an evolution from mixed- ferroic to ferroelectric-like hysteresis upon cooling slightly below room temperature. [0049] Figure 10A illustrates zoomed-out and zoomed-in cross-sectional TEM images of HfO2-ZrO2 multilayer structure along with a graph of intensity versus position. [0050] Figure 10B shows C-V measurements of HfO2 thickness series. [0051] Figure 10C shows Q-V measurements of HfO2 thickness series. [0052] Figure 10D shows C-V measurements of Al₂O₃ thickness series. [0053] Figure 10E shows Q-V measurements of Al2O3 thickness series. [0054] Figure 10F shows the consistency in the SiL Q-V relation extracted from the C-V data from both the HfO₂ and Al₂O₃ thickness series. [0055] Figure 11A shows split C-V curves obtained for multilayer HfO₂- ZrO2 gate stacks (repeated 1 and 3 times). [0056] Figure 11B shows ID -VG transfer characteristics for LG = 1µm bulk transistors at V_DS = 50 mV for multiple devices per sample. [0057] Figure 11C shows g_m-V_G transfer characteristics for L_G = 1µm bulk transistors at V_DS = 50 mV for multiple devices per sample. [0058] Figure 11D shows a series resistance extraction from 1/V_ov method for V_ov = V_gs − V_t = 0.3 V to 0.5 V for L_G = 1µm. [0059] Figure 11E shows extracted mobility as a function of inversion sheet charge density; the effective mobility was taken to be the average maximum mobility across all measured devices. [0060] Figure 11F shows a transfer I_D-V_G data set fit to a constant mobility model based on the extracted effectively mobility in Figure 11E. [0061] Figure 11G shows a transfer g_m data set fit to a constant mobility model based on the extracted effectively mobility in Figure 11E. [0062] Figure 12A shows threshold voltage extraction by linear extrapolation for various channel lengths. [0063] Figure 12B shows source/drain series resistance extracted using the 1/V_ov method. [0064] Figure 12C shows source/drain series resistance extracted using the line resistance method. [0065] Figure 12D shows measured and extracted transconductance versus V_G for V_DS = 0.9 V to 1.1 V, assuming R_s = R_d = 250 Ω-µm for L_G = 90 nm. [0066] Figure 12E shows measured (left) and extracted (right) output conductance versus VG for VDS = 0.9 V to 1.1 V, assuming Rs = Rd = 250 Ω-µm for L_G = 90 nm. [0067] Figure 13A is a diagram of a de-embedding procedure for extracting corrected admittance parameters by decoupling parasitic shunt capacitance and series resistance and inductance. [0068] Figure 13B depicts a small-signal model of the transistor of the present disclosure. [0069] Figure 13C shows de-embedded as a function of squared

frequency at different DC V_GS bias points extrapolated to the zero frequency limit to extract the RF g_m. [0070] Figure 14A shows a metal oxide semiconductor of the 20 Å HfO₂- ZrO₂-HfO₂ mixed ferroic trilayer sample on lightly doped Si (10¹⁵ cm⁻³). [0071] Figure 14B shows accumulation C-V curves for the 2 nm HfO2- ZrO₂-HfO₂ trilayer grown on sub-nanometer SiO₂ fit to effective oxide thickness (EOT) simulations. [0072] Figure 14C shows the applied voltage pulse, the measured current response, and the integrated charge as a function of time for 2 nm HfO₂-ZrO₂- HfO₂ trilayer in MOS capacitors. [0073] Figure 14D shows the maximum charge, the residual charge, and their difference derived from the charge vs. time curve for each of the voltage pulses. [0074] Figure 14E shows the reversible charge of the MOS layer compared with the extracted charge of the Si charge layer plus SiO2 interlayer (SiL) derived electrically. [0075] Figure 14F is a scatter plot of reported ferroelectric-dielectric systems demonstrating negative capacitance at the capacitor level via capacitance or charge enhancement.

Detailed Description

[0076] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0077] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0078] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0079] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0082] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

[0083] With the two-dimensional scaling of silicon field-effect transistors reaching fundamental limits, new functional improvements to transistors, as well as novel computing paradigms and vertical device integration at the architecture level, are currently under intense study. Gate oxides play a critical role in this endeavor, as gate oxides are a common performance booster for all devices, including silicon, new channel materials with potential for higher performance, and even materials suitable for three-dimensional integrated transistors. Indeed, the gate oxide transition from silicon dioxide (S1O2) to high-K dielectric (DE) is considered a paradigm shift in computing technology. In this context, ferroelectric oxides offer new functionalities considered promising for energy-efficient electronics. The advent of atomic layer deposition (ALD)-grown ferroelectric-doped hafnium oxide (Hf02) has overcome much of the material compatibility issues that plague traditional perovskite-based ferroelectric materials. In addition, considering ferroic order persists down to a thickness of 1 nm in this system allows for integration of these oxides in the most aggressively scaled devices in which the state-of- the-art high-K oxide thickness is less than 2 nm.

[0084] In an advanced silicon transistor, the gate oxide is a combination of two distinct layers. The first is an interfacial S1O2 formed with a self-limiting process, resulting in ~8.0-8.5 A thickness. The next is the high-k (HK) dielectric Hf02 layer that is typically ~2 nm in thickness. Higher capacitance of this series combination is desirable to suppress short channel effects. The capacitance is conventionally represented by effective oxide thickness (EOT),

where lower EOT represents higher capacitance. Therefore, the EOT minimum value is limited by the interfacial SiO2 thickness. Indeed, even integrating HfO2 as the high-κ layer, the EOT is typically ∼9 Å. To go below this value, the semiconductor industry has implemented sophisticated scavenging techniques to reduce the SiO2 thickness after the full gate stack is formed. Although this technique is very effective in scaling EOT, the thinner SiO₂ results in undesirable leakage and mobility degradation. [0085] Disclosed is an ultrathin HfO₂-ZrO₂ (zirconium oxide) superlattice gate stack that exploits mixed ferroelectric-antiferroelectric (FE-AFE) order, as shown in Figures 1A and 1B. The films as disclosed demonstrate mixed ferroic order down to 2 nm thickness—the same thickness of high-κ oxide used in advanced transistors. Moreover, when integrated with silicon, the films show an overall EOT of <6.5 Å, despite the fact that both transmission electron microscopy (TEM) and electrical characterization reveal 8.0-8.5 Å interfacial SiO₂ thickness, as is typically expected. In at least some embodiments the oxide layer has an effective thickness between 5.5 Å and 6.5 Å. The larger capacitance than its constituent layers is a signature of the charge boost stemming from the negative capacitance effect, possible in materials with ferroic order. The EOT shows a clear dependence on the specific sequence and layering, underlying atomic-level control of the gate oxide behavior. The fact that sub-8 Å EOT is achieved without any interfacial SiO₂ scavenging results in substantially lower leakage current for the same EOT compared with benchmarks established by major semiconductor industries. In addition, no mobility degradation is observed as EOT is scaled with these HfO₂-ZrO₂ ferroic gate stacks. Furthermore, large ON current (>1 mA/µm) obtained in L_G = 90 nm transistors indicate that there is no adverse effect on the carrier velocity. Therefore, ultrathin HfO2-ZrO2 multilayers exploiting ferroic order provide a new pathway toward energy- efficient gate stacks for advanced transistors. [0086] Figures 1A to 1E illustrate the atomic-scale design of negative capacitance in ultrathin hafnium oxide–zirconium oxide (HfO2-ZrO2). Figure 1A shows the phenomeno-logical model of negative capacitance in a mixed ferroic system, with Landau free energy landscapes for a ferroelectric, antiferroelectric, and mixed FE-AFE system. Mixed FE-AFE phase competition should suppress polarization and enhance electric susceptibility via proximity to a phase boundary, flatten the energy landscape, and provide for desirable traits for negative capacitance stabilization. The stable energy minimum of the composite free energy landscape, corresponding to the negative curvature regime of the ferroelectric energy landscape, is highlighted. [0087] Figure 1B shows engineering of ferroic phase competition in the HfO₂-ZrO₂ fluorite-structure system. Beyond the conventionally studied tuning parameters—composition, electric field, temperature—are introduced dimensional confinement via superlattice layering to tailor ferroic phase competition at the atomic-scale. [0088] Thin films of HfO2-ZrO2 are grown using ALD in which the nanolaminate periodicity is dictated by the sequence of Hf:Zr (4:12) ALD cycles before the Hf-Zr superstructure is repeated various times (Figure 1C). After top metal deposition, the entire gate stack undergoes a low-temperature post-metal anneal (200 °C, 60 s, N2), which does not interfere with the HfO₂-ZrO₂ multilayer structure, as various characterization techniques— synchrotron x-ray reflectivity (XRR), layer-resolved electron energy loss spectroscopy (EELS), and angle-resolved X-ray photoelectric spectroscopy (XPS)—confirm the expected Hf 4 Å to Zr 12 Å periodicity (see also Figures 6A to 6D). The underlying mixed ferroic order in these HfO₂-ZrO₂ heterostructures is established by high-resolution TEM (Figure 1D; see also Figures 8E and 8F) and in-plane grazing incidence diffraction (Figure 1E; see also Figures 8A and 8B). Both techniques indicate the presence of the tetragonal (P42/nmc, T−) and orthorhombic (Pca21, O−) phase, which correspond to antiferroelectric and ferroelectric order in fluorite-structure films, respectively. Synchrotron X-ray spectroscopy and optical spectroscopy further confirm the presence of inversion symmetry breaking in the 2 nm HfO₂-ZrO₂- HfO2 superlattice heterostructure (see also Figures 8C and 8D). [0089] Figure 1C shows the HfO2-ZrO2 fluorite-structure multilayer on silicon (Si), in which the heterostructures maintain distinct layers (i.e., not solid solution alloys) based on EELS, x-ray reflectivity (XRR), and depth-resolved XPS. The role of the layering on the underlying ferroic order and capacitance is studied by electrical measurements as a function of annealing temperature and HfO2-ZrO2 stacking structure (see also Figures 7A to 7C). [0090] Figure 1 D shows a high-resolution transmission electron microscopy image of the atomic-scale HfC -ZrC -HfC trilayer (top) and extracted cf-lattice spacings (bottom) corresponding to the tetragonal (P42/nmc, left) and orthorhombic (Pca2i, right) crystal structures corresponding the fluorite-structure AFE and FE phases, respectively.

[0091] Figure 1 E shows synchrotron in-plane grazing incidence diffraction demonstrating the presence of both the AFE T-phase (101) and FE O-phase (111) reflections the cf-lattice spacings of which are consistent with those extracted from TEM. Detailed indexing to higher-order reflections for structural identification of the ferroic phases is provided by wide-angle synchrotron diffraction (see also Figure 8A). Further evidence of inversion symmetry breaking is provided by second harmonic generation and synchrotron linear dichroism (see also Figures 8C and 8D).

[0092] Mixed-ferroic atomic-scale Flf02-Zr02 multilayers designed considering FE-AFE order can tune the free energy landscape in a similar manner to the FE-DE model systems originally studied for negative capacitance stabilization (Figure 1A). From the energy landscape picture within a Landau formalism, the competition between the negative curvature (negative capacitance) of the FE and the positive curvature (positive capacitance) of the AFE can flatten the overall energy landscape, thereby substantially increasing the susceptibility. To confirm the higher susceptibility in the mixed AFE-FE system directly, capacitance-voltage ( C-V) hysteresis loops were performed in metal-insulator-metal (MIM) capacitor structures on thicker films with the same superlattice periodicity (Figure 2A). Besides features indicative of mixed FE-AFE order, the total capacitance for the superlattice is larger than both conventional AFE Zr02 and FE Zr:Hf02 of the same thickness (Figure 2A), demonstrating enhanced susceptibility. To quantify the permittivity, capacitance measurements were performed across the superlattice thickness series. These measurements yield an extracted permittivity of ~52 (Figure 2B), which is larger than both FE orthorhombic Zr:Hf02 and AFE tetragonal Zr02 values.

[0093] Figures 2A to 2F illustrate enhanced capacitance in ultrathin Hf02- Zr02 mixed-ferroic heterostructures. Figure 2A shows MIM capacitance- voltage ( C-V) hysteresis loops for a mixed FE-AFE Hf02-Zr02 multilayer demonstrating higher capacitance compared against its AFE (ZrC ) and FE (Zr: Hf02) counterparts of the same thickness.

[0094] Figure 2B shows the inverse capacitance versus thickness of the MIM Flf02-Zr02 multilayers up to five superlattice repeats (10 nm), with an extracted permittivity of 52, which is extremely large for Flf02-based oxides. [0095] To further understand the ferroic evolution in these Flf02-Zr02 superlattices, low temperature measurements were performed where enhanced FE phase stabilization is expected. Indeed, temperature-dependent C-V loops for thicker Flf02-Zr02 multilayers demonstrate an evolution from mixed-ferroic to FE-like hysteresis upon cooling slightly below room temperature (~240 K, Figure 2C), consistent with temperature-dependent X-ray spectroscopy indicating transition from mixed tetragonal-orthorhombic phase to predominately orthorhombic structure at similar temperatures (see also Figures 9A to 9F). The capacitance decrease upon cooling as the system moves away from the highly susceptible mixed ferroic phase is consistent with previous work on negative capacitance in FE-DE systems, which establishes the energy landscape link between enhanced capacitance and susceptibility near phase transitions. Notably, the intertwined FE-AFE phases within the superlattice and resulting enhancement in susceptibility from the competition of FE and AFE phases is conceptually similar to negative stiffness composites of ferroelastics within a metal matrix, that is, the mechanical analog to negative capacitance.

[0096] Figure 2C shows MIM C-V hysteresis loops for Flf02-Zr02 multilayers of the same periodicity demonstrating an evolution from mixed- ferroic to FE-like hysteresis upon cooling slightly below room temperature.

The proximity to the temperature-dependent phase transition (see also Figures 9A to 9F) suggests the Flf02-Zr02 heterostructures lies near the maximum electric susceptibility position, ideal for negative capacitance stabilization.

[0097] Next, the superlattices were grown on Si substrates in metal-oxide- semiconductor (MOS) capacitor structures. A self-limiting chemical oxide S1O2 was grown first, resulting in -8.0-8.5 thickness, following the standard practice in advanced Si devices. Next, a 20-cycle thick multilayer was grown with ALD following the same stacking as before, that is, Hf:Zr: Hf 4: 12:4. Accumulation C-V curves of the superlattice stack result in significantly larger capacitance in comparison with other conventional stacks — DE HfC , AFE Zr02, FE Zr:Hf02 — of the same 20 A thickness (Figure 2D). Furthermore, the Hf:Zr: Hf 4:12:4 trilayer demonstrates enhanced capacitance compared with a bilayer (Hf:Zr 8:12) and solid solution (Hf:Zr [2:3]4) of the same thickness and Hf:Zr composition (Figure 2E). Notably, the composition in the films as disclosed is close to the point at which several previous reports have discussed a possible morphotropic phase boundary (MPB) in thicker Flf02-Zr02 solid solution films. Indeed, the origin of MPB lies in the flattening of the energy landscape. From this context, the negative curvature of the FE compensating the positive curvature of AFE is similar to obtaining MPB in these thin films. Flowever, a critical distinction is the fact that, unlike the thicker films, MPB is not solely determined by volume fraction of the constituents. Rather, the overall flattening of the energy landscape is determined by stacking. For example, compared with solid solutions at the typically reported Zr-rich “MPB”-like compositions, the Flf02-Zr02-Flf02 trilayer demonstrates larger capacitance (Figures 3A, 3B, and 3C). This indicates the enhanced capacitance in Flf02-Zr02 films is not simply driven by doping but instead can be tuned by the configuration of the multilayer structure (see also Figures 7 A to 7C). Overall, these capacitor studies suggest that the exact stacking sequence plays a crucial role in stabilizing the FE-AFE phase competition that leads to enhanced capacitance, akin to previous reports in perovskite-based FE-DE superlattices.

[0098] Figure 2D shows metal oxide semiconductor (MOS) accumulation C-V of Flf02-Zr02-Flf02 trilayer compared with AFE Zr02, FE Zr:hlf02, and high-K dielectric Hf02, all of the same thickness (20 A), indicating mixed- ferroic behavior is optimal for enhancing capacitance rather than purely FE or AFE behavior.

[0099] Figure 2E shows accumulation C-V of the Flf02-Zr02-Flf02 trilayer compared with bilayer and solid-solution films of the same thickness (ALD cycles) and composition (Hf:Zr cycles), with an inset showing a diagram of multilayer (Hf and Zr cations vertically separated) versus solid solution (Hf and Zr cations intermixed). These results suggest that the capacitance enhancement in multilayer films is not simply driven by Hf:Zr composition but instead by the atomic-scale stacking (see also Figures 3A to 3C and 7A to 7C).

[00100] Figure 3A to 3C illustrate solid solutions versus superlattice structure: the role of ALD period and Zr-content. Figure 3A shows FlfC -ZrC multilayer and Zr-rich Hf:Zr02 solid solution films. With shorter ALD periods, the mixed FE-AFE multilayer structure transitions towards a Hf:Zr02 solid- solution with AFE-like behavior. In the solid solution state, the loss of the mixed ferroic order yields diminished capacitance due to the lack of mixed- ferroic-induced capacitance enhancement.

[00101] Figure 3B shows MOS accumulation C-V of the Hf02-Zr02-Hf02 trilayer (60% Zr) compared with solid solution films of the same thickness (2 nm) and composition (60% Zr), as well as solid solution films of the same thickness and higher Zr-com position (67%-100% Zr).

[00102] Figure 3C shows MIM C-V hysteresis loops of the Hf02-Zr02 superlattice (60% Zr) compared with solid solution films of the same thickness (6 nm) and composition (60% Zr), as well as solid solution films of the same thickness and higher Zr-com position (67%-100% Zr). The Hf:Zr02 solid solution films with higher Zr content (60%-75%) are around the range attributed to the morphotropic phase boundary in thicker Hf:Zr02 alloys. These results indicate the capacitance enhancement in multilayer films is not simply driven by Zr-content but instead by the atomic-scale stacking, as the solid solution films with sub-atomic superlattice period do not demonstrate the same mixed ferroic behavior and enhanced capacitance as the superlattices. [00103] To quantify the observed capacitance, EOT simulations of MOS capacitors were performed using the industry standard model Synopsys simulation platform. The Hf:Zr:Hf 4:12:4 trilayer stacks vary between 6.5 A and 7.0 A EOT (Figure 2F), consistent over many measured capacitors. Notably, this EOT is smaller than the expected thickness of the interfacial S1O2 layer (8.0-8.5 A), as mentioned previously. To investigate further, high-resolution TEM was performed on the disclosed gate stacks (see also Figures 10A to 10F), which illustrates the S1O2 thickness is indeed ~8.5 A. To supplement this physical characterization, electrical characterization of the interfacial layer was implemented next via standard inverse capacitance vs. thickness analysis of conventional dielectric Hf02 and aluminum oxide (AI2O3) thickness series grown on the same S1O2 (see also Figures 10A to 10F). All thermal processing is kept exactly the same as the superlattice gate stack. The extracted Flf02 and AI2O3 permittivity — 19 and 9, respectively — is consistent with the typical dielectric phases of these two materials. Therefore, one can reliably extract the S1O2 layer thickness, yielding 8 A (see also Figures 10A to 10F), consistent with the high-resolution TEM results, similar to previously studies established by the semiconductor industry. Moreover, the consistent interlayer thickness extracted from both material systems indicates that neither Hf nor aluminum (Al) encroaches into the interfacial S1O2, which would reduce its thickness and/or increase its permittivity. So considering the interfacial layer thickness as 8 A, the Hf:Zr: Hf 4:12:4 gate stack demonstrates an overall EOT 1.0-1.5 A lower than the constituent S1O2 thickness. In other words, capacitance enhancement is observed in this 20 A mixed ferroic gate oxide integrated on Si. Therefore, the mixed FE-AFE order not only improves the permittivity of the multilayer stack itself but also couples to the S1O2 in MOS capacitor structures, yielding improved overall capacitance.

[00104] Figure 2F shows accumulation C-V curves for a 2 nm FlfC -ZrC - Hf02 trilayer grown on sub-nanometer S1O2 fit to effective oxide thickness (EOT) simulations; the inset shows externally verified MOS accumulation C-V of the same trilayer stack, demonstrating 6.5 A EOT. The 2 nm trilayer on top of the S1O2 demonstrates lower EOT than the thickness of the S1O2 interlayer alone, carefully extracted via physical (8.5 A) and electrical (8.0 A) methodologies (see also Figures 10Ato 10F), providing evidence of capacitance enhancement. Furthermore, these 2 nm ferroic gate stacks demonstrate amplified charge from pulsed current-voltage ( l-V) measurements relative to the S1O2 interlayer (see also Figures 14A to 14F). Notably, this 2 nm Flf02-Zr02 multilayer on sub-nanometer S1O2 provides the most scaled demonstration of charge and capacitance enhancement at the capacitor-level (see also Figures 14A to 14F).

[00105] The practical implication of this capacitance enhancement can be clearly seen in Figure 4A, which shows leakage current vs. EOT behavior.

The leakage current is measured at VG - V = -1 V, where V® is the flatband voltage of the semiconductor. All other data points on this plot are taken from reported industrial gate stacks. The leakage current for the 4:12:4 stack is substantially lower at the same EOT. Note that below 9 A, the other gate stacks need sophisticated scavenging techniques to reduce the thickness of the interfacial S1O2. On the other hand, the structure of the present disclosure can reach ~6.5 A without any scavenging. This indicates that the leakage current for the stacks as disclosed is lower. Notably, the scavenging the interfacial S1O2 leads to a loss of mobility due to increase in remote phonon scattering. As it has been shown, the mobility drops off with a slope of 20 cm²/V-s per every angstrom of scavenged S1O2. To test how mobility is affected by the superlattice gate stack, long channel bulk transistors were fabricated with two different repeats of the superlattice, together with another sample that has thick (60 A) Hf02 as the gate stack. To extract mobility, a careful fitting of the measured C-V from the transistor structures is performed. In addition, series resistance is modeled from the data and de-embedded to reveal the intrinsic behavior. Next, the mobility is extracted using the peak transconductance method (see also Figures 13A to 13C). The mobility was found to remain essentially the same for all three stacks despite the difference in materials and EOT (from 2 nm EOT for Hf02 down to <8 A for the superlattice gate stack). First, this shows that there is no fundamental change in electron transport due to the use of the superlattice gate stack compared with standard Flf02. In addition, it shows that there is no penalty in mobility even below an EOT of 9 A, where conventional gate stacks show a degradation due to the need of scavenging. Because the absolute value of mobility depends on the specific processing technique, mobility numbers have been normalized in Figure 4B. This clearly shows the flat behavior for the superlattice gate stack compared with the falling of trend for conventional gate stacks due to scavenging in the low EOT range.

[00106] Figures 4A to 4F illustrate device performance benefits utilizing ultrathin mixed-ferroic Flf02-Zr02 gate stacks. Figure 4A shows leakage- effective oxide thickness (J_G-EOT) scaling of the multilayer gate stacks (stars) benchmarked against reported high-k metal gate (FIKMG) literature, including interlayer-scavenged 2 nm Flf02 (triangles, circles, squares), high-k doped Hf02 (diamonds), and Si02/poly-Si (negative sloped thin line). The leakage is the lowest reported for a 6.5-7.0 Å EOT MOS capacitor on silicon, due to the EOT reduction without requiring interlayer SiO2 thickness reduction. [00107] Figure 4B shows normalized mobility versus EOT scaling of the multilayer gate stacks (stars) benchmarked against reported HKMG literature, including interlayer-scavenged 2 nm HfO2 (triangles, circles, squares, diamonds) and hybrid silicate-scavenged interlayer (area between positive sloped thin lines), with an inset showing SiO₂ interlayer thickness versus EOT scaling comparing the 7.0 Å EOT HfO2-ZrO2-HfO2 trilayer against notable HKMG literature, which employ interlayer scavenging to reduce EOT. For EOT scaling in conventional HKMG systems, the SiO₂ interlayer has to be reduced to lower EOT, which leads to degraded mobility. In this case, enhanced capacitance in HfO2-ZrO2 multilayers achieves scaled EOT without having to thin the SiO₂ interlayer; therefore, mobility is not degraded. The inset scatter plot highlights the underlying reason for the enhanced leakage- EOT and mobility-EOT behavior in the ultrathin trilayer gate stacks: low EOT without reduced SiO₂ interlayer thickness. [00108] To examine how the capacitance enhancement behaves at high frequency, radio frequency measurements were performed on the same long channel (LG = 1 µm) devices (see also Figures 12A to 12F). This allows one to extract device parameters up to ∼800 MHz for the disclosed devices (close to the cut-off frequency). Of particular interest is the transconductance (g_m), which is proportional to the product of capacitance and electron velocity (mobility). From Y-parameter measurements one can find alternating current (AC) transconductance as Re(Y₂₁) = g_m + af², where f is the frequency (Methods). This yields an AC transconductance as a function of applied gate voltage (V_G). This dependence is plotted together with direct current (DC) transconductance (∂I_D/∂V_G from DC I_D-V_G; Figure 4C). The DC and AC transconductances are similar with the AC transconductance being roughly 15% larger at the peak value. The hypothesis is that this slightly large AC transconductance results from the fact that certain interface traps, which affect the DC behavior, cannot respond at frequencies larger than 100 MHz, leading to better gate control. More importantly, these results show that the capacitance enhancement is not limited to low frequencies. [00109] Figure 4C is a graph showing g_m versus gate voltage (V_G) for long- channel bulk transistors (L_G = 1 µm) obtained from both direct current (DC) (derivative of I_D-V_G) and radio frequency (Re[Y₂₁]) measurements at V_DS = 1 V; the inset shows de-embedded Re[Y21] (open circles) as a function of squared frequency at different DC V_GS bias points extrapolated to the zero frequency limit (dotted lines) to extract the RF g_m (see also Figures 13A to 13C). The high-frequency measurements help suppress defect contributions that would otherwise dampen the intrinsic g_m. [00110] Finally, to test the ON current capability, a LG = 90 nm device was fabricated on a SOI transistor with 18 nm SOI thickness and the superlattice gate stack. The transfer and output characteristic of a typical transistor are shown in Figures 4D and 4E. Note that the threshold voltage of this device is 0.55 V, which is consistent with the work function of tungsten used as the gate metal. Because of this, the transistors have been driven up to 1.6 V gate voltage so that an overdrive voltage (V_ov = V_G − V_T ) of ∼1 V can be applied. It is found that at a drain voltage (V_D ) and V_ov of 1 V, the drain current exceeds 1 mA/µm. In addition, as shown in Figure 4F, the measured extrinsic transconductance is ∼1.1 µS/µm, which gives an intrinsic transconductance of ∼1.75 µS/µm (see also Figures 14A to 14F). These values of ON current and transconductance are substantially larger than a conventional 90 nm transistor and result from the large capacitance provided by the superlattice gate stack and the fact that the low EOT resulting from the stack does not affect the electron transport adversely. [00111] Figures 4D, 4E, and 4F show DC I-V transfer characteristics (I_D -V_G), DC output characteristics (I_D -V_D), and DC transconductance (g_m-V_G), respectively, for short-channel (L_G = 90 nm) silicon-on-insulator (SOI) transistors. Notably, the maximum on-current and g_m at V_DS = 1 V exceeds 1 µA/µm and 1 mS/µm. Direct current mobility and transconductance values are carefully extracted after de-embedding the series resistance from double- swept I-V measurements (see also Figures 11A to 11F and Figures 12A to 12F, respectively). [00112] With the superlattice gate stack demonstrated in integrated Si devices, we return to the capacitance enhancement observed in this gate stack. As previously discussed, the mixed FE-AFE order facilitates a flatter energy landscape where the negative curvature of the FE phase is compensated by the positive curvature of the AFE phase. Notably, when the mixed ferroic oxide is grown on an S1O2 interlayer, it can lead to similar compensation again. As observed in the thicker FE-AFE superlattice MIM capacitors, some hysteresis still remains, which manifests at large voltages, indicative of a negative curvature regime still persisting in the superlattices. The interfacial DE S1O2 can flatten out that energy landscape even further, thus leading to enhanced capacitance. This is similar to the negative capacitance and resultant capacitance enhancement observed in FE-DE series combinations. To supplement the C-V evidence of capacitance enhancement (Figure 2F), pulsed electrical measurements of the superlattice gate stack MOS capacitors, which can quantify the amount of stored charge as a function of voltage, demonstrate larger stored charge than if just interfacial S1O2 was sitting on top of Si, providing further evidence of negative capacitance in the gate stack (see also Figures 14A to 14F). Note that previous studies have shown that negative capacitance stabilization is favored under states of high susceptibility. As disclosed, the competing ferroic order in Flf02-Zr02 multilayers substantially increases its susceptibility and is thus expected to facilitate negative capacitance behavior when placed on top of the interfacial Si02.

[00113] Capacitance enhancement has been demonstrated in single crystalline, perovskite-structure ferroelectric-dielectric superlattices by many groups. The present disclosure demonstrates that the same enhancement is possible in Flf02-Zr02 fluorite-structure superlattices exhibiting mixed ferroelectric-antiferroelectric order in films as thin as just ~2 nm. The ability to control ferroic order in such ultrathin films is of critical importance for advanced electronic devices, considering previous studies have shown that negative capacitance can be stabilized under states of high susceptibility. Furthermore, the present disclosure establishes the critical role of atomic- layer stacking, as opposed to conventional doping techniques, in controlling the ferroic phase space and permittivity of fluorite-structure oxides down to ultrathin limits, leveraging its unique size effects and rich antiferroelectric- ferroelectric polymorphs. When this mixed phase Flf02-Zr02 multilayer is integrated on Si, the gate stack exhibits a capacitance enhancement, lowering the EOT below the thickness of S1O2 itself, which would not be possible with a conventional dielectric. Notably, the lowest EOT achieved (6.5 A) for the gate stack and interfacial S1O2 together is lower than that used in the most advanced Si transistors today. Therefore, the present disclosure demonstrates that harnessing atomic-scale layering in ultrathin Hf02-Zr02 ferroic gate oxides presents a promising materials design platform for future Si transistors beyond conventional high-k dielectrics that has enabled the semiconductor industry over the past two decades.

[00114] Figure 5 is a cross-sectional view of an exemplary embodiment of a semiconductor device 10 in the form of an advanced transistor that is in accordance with the present disclosure. In this exemplary embodiment, the semiconductor device 10 has a semiconductor substrate 12 having a source region 14, a channel region 16 spaced from the source region 14, and a drain region 18 spaced from both the source region 14 and the channel region 16 with a source contact 20 disposed over the source region 14, a drain contact 22 disposed over the drain region 18, and a gate stack 24. The gate stack 24 includes an oxide layer 26 disposed over the channel region 16, a periodic sequence of (Hf02-Zr02)xN material layers 28 disposed over the oxide layer 26, wherein N is a natural counting number, and a gate contact 30 disposed over the periodic sequence of (Hf02-Zr02)xN material layers 28.

METHODS

Gate Stack

[00115] Gate oxide. Thin films of Hf02-Zr02 were grown by ALD in a Fiji Ultratech/Cambridge Nanotech tool (University of California, Berkeley) at 270 °C, in which tetrakis (ethylmethylamino) hafnium and tetrakis (ethylmethylamino) zirconium precursors are heated to 75 °C and water vapor is used as the oxidant. For metal-ferroelectric-insulator-semiconductor capacitor structures, sub-nanometer chemically grown S1O2 on lightly doped Si (10¹⁵ cm^-3) was prepared by the standard clean (SC-1) solution (5:1:1 H2q:H2q2:NH4qH at 80 °C for 10 minutes) after the Si wafer was cleaned in Piranha (120 °C for 10 minutes) to remove organics and hydrogen flouride (HF) (50:1 H20:HF at room temperature for 30 s) to remove any native oxide. Subsequently, HfC -ZrC multilayers are deposited at 270 °C by ALD. After ALD deposition, post-deposition annealing was performed at 175 °C (20 min, forming gas N2/H2 background) to help cure the Si02-oxide interface. For confirmation and reproducibility, Hf02-Zr02 multilayers of the same ALD cycling were also deposited at MIT Lincoln Laboratory; after ALD deposition, post-deposition annealing was performed at 250 °C (1 min, N2 background). [00116] Gate metal. For capacitors as embodied in the present disclosure, the first layer of the gate metal, titanium nitride (TiN), is deposited by ALD (250 °C, 20 cycles, 15 A) in N2 and H2 plasma. Subsequently, tungsten (W) is deposited by sputtering (room temperature, 60 nm). For MIT Lincoln Laboratory capacitors, the gate metal, TiN, is deposited by physical vapor deposition (room temperature).

[00117] Annealing. The entire gate stack undergoes a low-temperature post-metal anneal (200 °C, 1 min, N2) to cure interface defects. This low temperature does not interfere with the Hf02-Zr02 multilayer structure, as confirmed by various characterization techniques (Figures 6A to 6D) and maintains the mixed ferroic behavior, as high-temperature annealing would induce purely ferroelectric behavior (Figures 7 A to 7C). X-ray diffraction and TEM confirm the presence of crystalline ultrathin films despite the low deposition temperature, afforded by the low crystallization temperature of Zr02. In fact, non-post-annealed ALD-grown Zr02 has previously demonstrated crystallization into the ferroelectric orthorhombic phase on Si. [00118] Figures 6A to 6D illustrate an atomic-scale multilayer structure. Figure 6A shows the Hf02-Zr02 multilayer structure on Si02-buffered silicon. [00119] Figure 6B shows synchrotron XRR of thicker Hf02-Zr02 heterostructures (left) repeated with the same periodicity as the thinner trilayer structure; and the XRR fitting (right) demonstrates the presence of well- separated Hf02-Zr02 layers, that is, not a solid-solution, for three different multilayer repeats of fixed periodicity.

[00120] Figure 6C shows layer-resolved EELS of the 2 nm Hf02-Zr02-Hf02 trilayer, which again shows clear separation of Hf02-Zr02 layers following the expected 4 A-12 A-4 A Hf02-Zr02-Hf02 structure.

[00121] Figure 6D illustrates angle-resolved XPS of the 2 nm HfC -ZrC - Hf02 trilayer (left) and the extracted atomic composition (right); the presence of increasing Zr-content as the grazing angle increases is expected from the multilayer structure.

[00122] Figures 7A to 7C illustrates solid solutions versus superlattice structure: role of annealing temperature. Figure 7A shows FlfC -ZrC multilayer and Hf:Zr02 solid solution films. Under a high-temperature anneal, the multilayer structure transitions towards a Hf:Zr02 solid-solution-like structure demonstrating more FE-like behavior. In the solid solution state, the loss of the mixed ferroic order yields diminished capacitance due to the lack of both the higher-permittivity AFE phase and the mixed-ferroic-induced capacitance enhancement.

[00123] Figure 7B shows a comparison of MOS capacitor accumulation C-V characteristics in FlfC^-ZrC multilayers, where the heterostructure was repeated (top center) 1 time, (bottom left) 2 times, or (bottom right) 3 times, under both low-temperature and high-temperature anneals.

[00124] Figure 7C is a diagram showing a comparison of mixed-ferroic behavior in low-temperature treated MIM FlfC -ZrC multilayers versus FE behavior in in the same multilayers annealed at high temperatures, where the heterostructure was repeated (top center) 3 times, (bottom left) 4 times, or (bottom right) 5 times. In all instances, the high-temperature anneal (>500 °C) results in diminished accumulation capacitance compared with the low- temperature anneals, as the multilayered mixed-ferroic films presumably transition to more FE-like solid-solution alloys.

Device Fabrication

[00125] MOS and MIM capacitors. For MOS capacitor structures, after gate stack deposition, top electrodes are defined by photolithography and dry etching. For bare structures (structural studies), the top metal is removed by chemical etching to expose the gate oxide surface. For MIM capacitors, W is deposited by sputtering (room temperature, 30 nm) on a lightly doped Si substrate as the bottom metal electrode. After ferroic film deposition by ALD, 60 nm of W is deposited by sputtering. The top electrodes are then defined by photolithography and dry etching.

[00126] Bulk transistors. The n-type bulk transistors were fabricated by a non-self-aligned gate-last process on bulk silicon wafers (10¹⁷ cm^-3) with local oxidation of silicon as device isolation technique. First, a 10 nm of S1O2 thermal oxide and a 30 nm of low-pressure chemical vapor deposition silicon nitride (Si3N4) were grown on the Si substrates. After the active region was defined by photolithography and Si₃N₄/SiO₂ etching, the dry oxidation was performed to form the local oxidation of silicon isolation. Next, the source/drain regions were defined by photolithography and ion implantation with an ion dose of 3×10¹⁵ ions/cm². The dopants were then activated by rapid thermal anneal at 900 °C for 7 min in N₂ ambient. The gate stacks with the sub-nanometer chemically grown SiO2, 2 nm HfO2-ZrO2 heterostructure, and 100 nm of sputtered W gate were then deposited. After the gate fingers (from 500 nm to 50 µm) were patterned by photolithography and etched by inductively coupled plasma metal etching, the 400 nm thick interlayer dielectric SiO2 was then deposited using plasma-enhanced chemical vapor deposition. Last, after the contact hole opening, the Ti/TiN contact metal was deposited by sputtering, defined by photolithography, and then etched by inductively coupled plasma metal etching. [00127] Short-channel SOI transistors. The n-type short-channel transistors were fabricated by a non–self-aligned gate-last process on SOI substrates with a gate length (L_G) down to 90 nm. First, the device layer was thinned down to 20 nm and the active regions were defined by photolithography with expose regions etched slightly into the buried oxide. The hydrogen silsequioxane negative resist were written by e-beam lithography as a hard mask for the ion implantation with a dose of 5×10¹⁵ ions/cm². The dopant activation was conducted in an rapid thermal anneal at 900 °C for 15 seconds in N2 ambient. The gate stacks with the sub-nanometer chemically grown SiO2, 2 nm HfO2-ZrO2 heterostructure, 1.5 nm of plasma-enhanced ALD TiN, and 100 nm of sputtered W were sequentially deposited. The gate region (250 nm) was then patterned by photolithography. Like the backend process for the bulk transistors, a 400 nm of interlayer dielectric and a sputtered Ti/TiN contact metal were deposited and defined by photolithography and inductively coupled plasma etching. Microscopy [00128] Transmission electron microscopy. Electron microscopy was performed at the National Center for Electron Microscopy facility of the Molecular Foundry at Lawrence Berkeley National Laboratory. The high- resolution bright field TEM images of HfO2-ZrO2 thin films were performed by FEI ThemIS 60-300 microscope with image aberration corrector operated at 300 kV (Figure 1D; Figures 8E and 8F). To prepare cross-sectional TEM samples of HfO2-ZrO2 thin films, mechanical polishing was employed by using an Allied High Tech Multiprep at a 0.5° wedge to thin down the total thickness of samples down to 10 µm. Later, argon (Ar) ion milling of the Gatan Precision Ion Milling System was utilized to make an electron-transparent sample, starting from 4 keV down to 200 eV as final cleaning energy. The local interplanar d-spacing in HfO2-ZrO2 thin films was measured by DigitalMicrograph software using line profile with integration width. The SiO₂ interlayer thickness in wide field-of-view was measured by the same method. [00129] Figures 8A to 8F illustrates ferroic phase insights from structural characterization. Figures 8E and 8F are TEM micrographs showing additional cross-sectional evidence of T-phase and O-phase, respectively, in which the extracted T-(101) lattice spacing (∼2.95 Å) and O-(111) lattice spacing (∼3.08 Å) is consistent with that extracted from IP-GiD. [00130] Optical microscopy. Second harmonic generation (SHG) measurements (Figure 8D) were performed with a Ti:sapphire femtosecond laser (Tsunami, Spectra Physics, λ ∼ 800 nm, frequency ∼ 80 MHz). The linearly polarized femtosecond laser beam was focused through 50X objective lens (NA ∼ 0.42) which results in a focal spot size of 2 µm. The generated SHG signal was collected through the same objective lens and separated from the fundamental beam by the harmonic separator. After passing through the optical bandpass filter, the SHG signals were registered to the photon multiplier tube without a polarizer. The fundamental beam was mechanically chopped, and the signal collected by the photon multiplier tube was filtered by a lock-in amplifier to reduce the background noise. For SHG spatial mapping, a two-axis piezo stage was utilized and the coordinate was synchronized with the photon multiplier tube signal. The SHG intensity was obtained by averaging the mapping signals across a 100 µm × 100 µm sample area. [00131] Figure 8D shows SHG mapped across a bare 2 nm HfO₂-ZrO₂-HfO₂ trilayer; the presence of SHG intensity demonstrates the inversion symmetry breaking present in these ultrathin ferroic films. X-Ray Characterization [00132] X-ray reflectivity. Synchrotron X-ray reflectivity—performed at Sector 33-BM-C beamline of the Advanced Photon Source, Argonne National Laboratory and at Beamline 2-1 of the Stanford Synchrotron Radiation Lightsource, SLAC National Accelerator Laboratory—confirmed the thickness of HfO₂-ZrO₂ heterostructures (Figure 6B). The overall thickness of the HfO₂- ZrO₂ heterostructures is consistent with the growth rate (∼1 Å/cycle) of ALD- grown Zr:HfO₂. Furthermore, the presence of irregularly spaced fringes in the thicker HfO2-ZrO2 heterostructures suggests the presence of well-separated HfO2-ZrO2 layers, that is, not a solid solution. This is confirmed by XRR fitting (Figure 6B) performed with the python package GenX50, which considers factors such as density, roughness, and thickness. [00133] Grazing incidence diffraction: in-plane. Synchrotron in-plane grazing-incidence diffraction (GID) (Figure 1E and Figure 8A) was performed at Sector 33-ID-D beamline of the Advanced Photon Source, Argonne National Laboratory. A Pilatus 100K Area Detector collected diffraction flux from the in-plane grazing incidence geometry; the region of interest on the Pilatus detector was set long in the vertical direction to amplify the relevant diffracted flux. In-plane GID fixed the out-of-plane grazing angle (δ = 0.9°) while the detector was swept in-plane (ν spanned 8°-50°); the corrected Bragg angle (2θ) over which the data is plotted and indexed is determined from the relationship cos 2θ = cosν · cos δ set by the geometry of the experimental setup. The X-ray source was fixed at 16 keV (λ = 0.775 Å). In-plane geometry allows for sampling of multiple lattice planes and finer-width reflections to enable clear indexing to the ferroelectric orthorhombic (Pca2₁) and antiferroelectric tetragonal (P42/nmc) fluorite structure in HfO2-ZrO2 heterostructures. The presence of many reflections from the in-plane GID spectra allow for clear distinction from other nonpolar fluorite-structure polymorphs (Figure 1E; Figure 8A). Such diffraction spectra would be otherwise prohibited in typical out-of-plane geometry due to the lack of vertical diffraction planes and the large linewidth inherent to nanometer-thick films; only a few large-linewidth reflections are present in previous out-of-plane GID scans of 1 nm Zr:HfO2. [00134] Figure 8A illustrates in-plane synchrotron GID of a bare HfO2-ZrO2- HfO2 trilayer indexed to the tetragonal/orthorhombic phases (left); a zoom-in of in-plane GID around orthorhombic (111) peak and tetragonal (101) peaks, confirming the presence of mixed ferroic order in the HfO2-ZrO2-HfO2 trilayer (center); and differentiation of the two peaks by performing detailed indexing of the entire spectrum, which largely indexed to the orthorhombic phase (right). Lattice parameters corresponding to the orthorhombic phase, determined from the {200} family of reflections, are self-consistently checked against the (111) lattice spacing as well as other higher-order reflections present at higher angles. As seen in the table in Figure 8A, the extracted lattice parameters correspond well to extracted Bragg d-spacing. [00135] Two-dimensional diffraction. Two-dimensional reciprocal space maps (Figures 8B and 8C) were measured at Beamline 11-3 of the Stanford Synchrotron Radiation Lightsource, SLAC National Accelerator Laboratory. Rayonix MX225 CCD area detector collected diffraction flux in gazing incidence (<0.20°) geometry; the X-ray source (50 microns vertical x 150 microns horizontal beam size) was fixed at 12.7 keV. The sample-detector work distance was set to 80 mm to enable detection of a wide region of reciprocal space (Q-range 0.2 Å⁻¹ to 5 Å⁻¹) at the expense of real space resolution (d-spacing or θ). The two-dimensional diffraction scans, in which a wide portion of the entire reciprocal space was collected simultaneously rather than at discrete regions in Qx-Qy space, were averaged over data collection time and for repeated scans. These measurement features, in tandem with the high X-ray flux afforded by the synchrotron source, enabled sufficient diffraction signal detection and contrast in films just one nanometer in thickness. Data analysis was performed by Nika, an Igor Pro package for correction, calibration, and reduction of two-dimensional areal maps into one- dimensional data. Two-dimensional reciprocal space maps on bare HfO2-ZrO2 heterostructures confirm the presence of crystalline ultrathin films despite the low deposition temperature, afforded by the low crystallization temperature of ZrO2 on Si. [00136] Figure 8B illustrates the two-dimensional reciprocal space map of a bare 2 nm HfO₂-ZrO₂-HfO₂ trilayer indexed to the tetragonal/orthorhombic phases by indexing integrated diffraction spectrum. The lack of fully polycrystalline rings demonstrates that these 2 nm HfC -ZrC -HfC trilayers are highly-oriented, consistent with TEM imaging.

[00137] Figure 8C illustrates synchrotron X-ray absorption spectroscopy (XAS) of a bare 2 nm Hf02-Zr02-Hf02 trilayer at the Hf Mz (left) and Zr Lz,2 edges (center): the presence of linear dichroism (orbital polarization) provides further evidence of symmetry-breaking in these oriented thin films.

[00138] Ferroic phase identification from diffraction. For fluorite- structure thin films, the main phases to consider are the dielectric monoclinic (P2i/c), antiferroelectric tetragonal (P42/nmc), and ferroelectric orthorhombic phases (Pca2i). Various diffraction reflections from the wide-angle in-plane grazing incidence diffraction spectra enable indexing to the orthorhombic Pca2i phase. Lattice parameters (a, b, c), determined via Bragg’s law from the c/200 family of reflections, are self-consistently checked against the (111) lattice spacing as well as other higher-order reflections

present in the in-plane diffraction spectra (Figure 8A). For example, the lattice parameters extracted from the {200} peaks were a = 5.36 A, b = 5.23 A, and c = 5.47 A. This corresponds to a c/211 lattice spacing of 2.209 A, which agrees well with the lattice spacing (2.205 A) obtained from Bragg’s law based on the peak position (Figure 8A).

[00139] The monoclinic phase was ruled out due to a lack of two {111} peaks in the diffraction spectra and the (111) peak being significantly offset from its expected peak position in the monoclinic phase. With regard to the indexing of tetragonal (101) peak, it is always reported that the tetragonal (101) reflection has a smaller cf-spacing in thicker Hf02-based films and is therefore expected to be present at a higher angle compared with the orthorhombic (111) reflection, which is the case in the indexed diffraction spectra (Figure 8A). In terms of extracting the phase fraction of the tetragonal and orthorhombic phases, while Rietveld refinement has been applied to grazing incidence x-ray diffraction of thick (10 nm) Zr:Hf0255 to determine the orthorhombic phase fraction, that methodology cannot be applied in the ultrathin regime, as the films are highly oriented, as opposed to fully polycrystalline (Figure 8B), which is a requirement to apply Rietveld refinement. [00140] X-ray absorption spectroscopy. Hard and soft synchrotron X-ray spectroscopy (Figure 9C) was measured at beamline 4-ID-D of the Advanced Photon Source, Argonne National Laboratory and Beamline 4.0.2. of the Advanced Light Source, Lawrence Berkeley National Laboratory, respectively. Spectroscopy measurements were taken at the oxygen K-edge (520-550 eV), zirconium M_3,2-edge (325-355 eV), hafnium M₃-edge (2090-2150 eV), and zirconium L_3,2-edge (2200-2350 eV). X-rays were incident at 20° off grazing. An X-ray absorption spectroscopy (XAS) (X-ray linear dichroism) was obtained from the average (difference) of horizontal and vertical linearly polarized X-rays. To eliminate systematic artifacts in the signal that drift with time, spectra measured at ALS were captured with the order of polarization rotation reversed (e.g., horizontal, vertical, vertical, and horizontal) in successive scans, in which an elliptically polarizing undulator tuned the polarization and photon energy of the synchrotron X-ray source. Spectra measured at Advanced Light Source were recorded under total electron yield mode from room temperature down to 100 K. Spectra measured at Advanced Photon Source were recorded under various modes: total electron yield, fluorescence yield, and reflectivity. [00141] Figures 9A to 9F illustrate ferroic phase insights: proximity to temperature-dependent phase transition. Figure 9C shows temperature- dependent XAS at the oxygen K-edge for a 2 nm HfO2-ZrO2-HfO2 bare film demonstrating clearer spectroscopic signatures of the ferroelectric O-phase emerge slightly below room temperature. [00142] Ferroic phase identification from spectroscopy. X-ray spectroscopy provides various signatures to distinguish the competing ferroelectric orthorhombic (Pca2₁) and antiferroelectric tetragonal (P4₂/nmc) phases. Simulated XAS spectra at the oxygen K-edge (Figure 9D) for ZrO₂ in the various fluorite-structure polymorphs (orthorhombic Pca21 and tetragonal P42/nmc) were computed through the Materials Project open-source database for XAS spectrum. The T-phase (P4₂/nmc) nonpolar distortion (D_4h, fourfold prismatic symmetry) from regular tetrahedral (T_d, full tetrahedral symmetry) fluorite-structure symmetry does not split the degenerate e-bands

, as confirmed by experiment and the aforementioned XAS simulations. Meanwhile, the O-phase (Pca21) polar rhombic pyramidal distortion (C2_v, twofold pyramidal symmetry) does split the e-manifold based on crystal field symmetry, providing a spectroscopic means to distinguish the T-phase and O-phase. The additional spectroscopic feature present between the main e-absorption and t2- absorption features due to orthorhombic symmetry-lowering distortion is illustrated by its crystal field diagram (Figure 9B). This provides a spectroscopic fingerprint for phase identification beyond diffraction, which can often be ambiguous due to the nearly identical T-phase and O-phase lattice parameters. For the 2 nm HfO2-ZrO2-HfO2 trilayer, the experimental O K-edge XAS spectra demonstrates tetrahedral and rhombic splitting features closely matching the polar O-phase (Pca21) emerge slightly below room temperature, indicative of the mixed tetragonal- orthorhombic to orthorhombic phase transition upon cooling. This temperature-dependent tetragonal-orthorhombic structural evolution is expected for fluorite-structure thin films and is consistent with temperature- dependent capacitance measurements (Figures 9E and 9F). [00143] Figure 9B shows crystal field splitting for fluorite-structure polymorphs; the symmetry-induced e-splitting provides a spectroscopic signature for the polar O-phase. [00144] Figure 9C shows hard and soft synchrotron X-ray spectroscopy measured at beamline 4-ID-D of the Advanced Photon Source. [00145] Figure 9D shows simulated oxygen K-edge XAS spectra for the respective O-phase and T-phase; the XAS provides spectroscopic signatures to distinguish between the O-phase and T-phase, which are difficult to resolve from GID. [00146] Figure 9E shows prototypical C-V behavior for mixed antiferroelectric-ferroelectric (shoulder-like features in addition to the characteristic butterfly-like shape) and ferroelectric films (just butterfly-like) in MIM capacitor structures. [00147] Figure 9F shows temperature-dependent C-V for thicker HfO₂-ZrO₂ multilayers of the same periodicity (in a MIM capacitor structure) demonstrating an evolution from mixed-ferroic to ferroelectric-like hysteresis upon cooling slightly below room temperature. Thinner HfO₂-ZrO₂ multilayers films suffer from leakage-limitations, preventing such hysteretic C-V measurements. The thicker Hf02-Zr02 multilayers of the same periodicity — annealed at the same low-temperature condition to maintain the multilayer structure — demonstrate a similar mixed ferroic to ferroelectric phase transition slightly below room temperature as the thinner 2 nm multilayer (Figure 9C). [00148] X-ray photoelectron spectroscopy. Angle-resolved photoelectron spectroscopy was performed using a Phi Versaprobe III at the Stanford Nano Shared Facilities (Figure 6D). A monochromated aluminum source was used to give a photon energy of 1486.6 eV. Data were fit and analyzed using CasaXPS. Angle-dependent XPS at various incident grazing angles enabled depth-resolved composition analysis to help confirm the Flf02-Zr02 multilayer structure.

Dielectric Measurements

[00149] Metal-oxide-semiconductor capacitance. Capacitance-voltage ( C-V) measurements were performed using a commercial Semiconductor Device Analyzer (Agilent B1500) with a multi-frequency capacitance measuring unit. Nineteen-micron Wtips (d.c.P-FITR 154-001, FormFactor) made electrical contact within a commercial probe station (Cascade Microtech); voltage was applied to the W top electrode, and the lightly doped Si bottom electrode was grounded. To eliminate contributions from series and parasitic resistances, frequency-dependent C-V measurements were performed. In particular, C-V data were analyzed at two frequencies (100-500 kFIz regime) to allow for the extraction of accurate frequency- independent C-V via a three-element circuit model consisting of the capacitor and the parasitic series and parallel resistors. The frequency-independent capacitance is given by

where C_/ and D,· refer to the measured capacitance in parallel mode (C_p-R_p) and dissipation values at frequency f,. The dissipation factor is given by D = -cot Q, where Q is the phase. To maximize the accuracy of this method, it is important that the dissipation factors are small («1) at the frequencies chosen; therefore, high frequencies were selected. [00150] Permittivity extraction The permittivity of Al2O3 and HfO2 dielectric layers was extracted from thickness-dependent MOS C-V measurements on lightly doped p substrates (Figures 10A to 10F). In the accumulation region of the MOS C-V measurements, the MOS capacitor can be modeled as three capacitors (Al2O3 or HfO2 dielectric layer, SiO2 interlayer, and Si space charge layer) in series using the following equation,

where ^ is the thickness ^^^^ ^_^ of the high-κ (Al2O3 or HfO2) layer, ^_^^^^ is the physical SiO2 thickness, and tCL is the charge layer thickness in silicon. The physical SiO₂ thickness is constant across all of the thickness series (Al₂O₃ and HfO2 single layers). Additionally, the capacitance values were extracted at various values of fixed charge (Q = −1 to −2 µC/cm²), which ensures that the charge- layer thickness is constant across all thicknesses and in the accumulation region. Therefore, from Equation 2, the inverse capacitance at a fixed charge as a function of film thickness should result in a line, and the permittivity can be extracted from the slope. This yielded extracted permittivities of 9 and 19 for the Al₂O₃ and HfO₂ thickness series, respectively, as expected for these systems. Note that for the HfO2 thickness series, thicknesses of 6 nm and higher were used to ensure HfO2 stabilizes in the dielectric monoclinic phase (κ ∼ 18). [00151] Similarly, the permittivity of the HfO₂-ZrO₂ heterostructures was extracted from thickness-dependent MIM C-V measurements (Figure 2B). The inverse capacitance is a linear function of the film thickness, and the permittivity can be extracted from the slope. [00152] Electrical interlayer thickness extraction. The thickness of the SiO2 interlayer was determined not only by TEM (Figure 10A) but also electrically via C-V measurements of both dielectric HfO2 and Al2O3 thickness series on SiO₂-buffered Si (Figure 10F). From Equation 2, the inverse capacitance at a fixed charge as a function of dielectric thickness should result in a line, and the capacitance-equivalent thickness (CET) of the SiO2 interlayer and Si charge layer can be extracted from the y-intercept. By extracting the CET at different charge values, the Q-V relation of the SiO2 interlayer and Si charge layer can be calculated through the following equation,

where ^_^^ is the flatband voltage (Figures 10B and 10D). To confirm this methodology, another method for determining the Q-V relation of the SiO2 interlayer and Si charge layer was extracted from the Q-V relations of both the dielectric HfO₂ and Al₂O₃ thickness series. At a fixed charge, the corresponding voltage values of each thickness were fit to a line, and the y- intercept corresponds to the voltage value for the SiO2 interlayer and Si charge layer Q-V relation. As expected, both methods lead to the same extracted Q-V relation (Figures 10C and 10E), corresponding to 8 Å EOT (Figure 10F)—close to the SiO2 physical thickness of 8.5 Å obtained via TEM (Figure 10A)—based on simulated technology computer-aided design (TCAD) Q-V relations of different SiO₂ thicknesses on lightly doped Si. [00153] Figures 10A to 10F illustrate SiO2 interlayer thickness. Figure 10A illustrates zoomed-out (left) and zoomed-in (center) cross-sectional TEM images of HfO₂-ZrO₂ multilayer structure; and a physics SiO₂ thickness of 8.5 Å is extracted from a intensity line scan (right) taken from a vertical cut of the cross-sectional TEM image. Note that the intensity of the interface between SiO₂ and the Si substrate is determined based on the oxygen content and not purely the intensity linescan, due to their similar intensity. [00154] Figures 10B and 10D show C-V measurements of HfO2 and Al2O3 thickness series, respectively, in MOS capacitor structures (left), extracted inverse capacitance versus thickness at various values of charge (center), and extracted Q-V relation Si charge layer and SiO2 interlayer (SiL) (right), which fits to technology computer-aided design simulations for 8.0 Å SiO2; and the SiL Q-V relation was found by integrating the extracted capacitance equivalent thickness of SiL versus charge (right, inset). This electrical interlayer thickness (8.0 A) is consistent with the physical thickness as determined by TEM (8.5 A).

[00155] Figures 10C and 10E show Q-V curves of HfC and AI2O3 thickness series, respectively, obtained from integrating MOS C-V measurements (top left), extracted voltage vs. thickness at various values of charge (top right), and extracted Q-V relation of SiL (bottom center); and the SiL Q-V relation is consistent with the Q-V relation extracted from the C-V data (right, inset). [00156] Figure 10F shows the consistency in the SiL Q-V relation extracted from the C-V data from both the Hf02 and AI2O3 thickness series, which fits to an S1O2 interlayer thickness of 8.0 A.

[00157] Hysteretic C-V measurements. Capacitance-voltage ( C-V) measurements on MIM capacitors were performed using a commercial Semiconductor Device Analyzer (Agilent B1500) with a multi-frequency capacitance measuring unit. Nineteen-micron Wtips (d.c.P-HTR 154-001, FormFactor) made electrical contact within a commercial probe station (Cascade Microtech); voltage was applied to the W top electrode and the W bottom electrode was grounded.

Electrical Characterization

[00158] Benchmarking to HKMG literature In Figure 4A, the leakage- effective oxide thickness (JG-EOT) scaling of negative capacitance multilayer gate stack benchmarked against reported high-k metal gate (HKMG) literature includes references taken from interlayer-scavenged 2 nm Hf02 (triangles, circles, squares), high-k doped Hf02 (diamonds), and Si02/poly-Si (negative sloped thin line)). In Figure 4B, the normalized mobility versus EOT scaling of the negative capacitance multilayer gate stack benchmarked against reported HKMG literature includes references taken from interlayer-scavenged 2 nm Hf02 (triangles, circles, squares, diamonds) and hybrid silicate-scavenged interlayer (area between positive sloped thin lines). In the Figure 4B inset, the S1O2 interlayer thickness versus EOT scaling scatter plot considers the 7.0 A EOT Hf02-Zr02-Hf02 trilayer to HKMG references that employ interlayer scavenging to reduce EOT.

[00159] Transistor transfer and output characteristics. Transistor l_d-V_g and I_d-V_d characterization of short-channel and long-channel transistors were performed using a commercial Semiconductor Device Analyzer (Agilent B1500). Nineteen-micron W tips (d.c.P-HTR 154-001, FormFactor) made electrical contact within a commercial probe station (Cascade Microtech); voltage was applied to the gate and drain contacts, while the source and Si substrate were grounded. [00160] Mobility extraction. The low-field transistor mobility is calculated based on the channel resistance (R_ch) and inversion sheet charge density (Q_inv), which are extracted respectively from transfer characteristics (I_D − V_GS) and from the gate-to-channel capacitance-voltage (C_gc − V_GS) measurements. Given the the device aspect ratio of channel length (L) and channel width (W), then

First, the channel resistance is extracted at 50 mV drain-to-source bias (V_DS) by subtracting the parasitic resistance (R_p) from the measured drain-to-source resistance (R_DS).

where R_p is ascribed to the resistance of the source and the drain contacts and the n+ extension regions that are extrinsic to the channel region. When the overdrive voltage (V_ov = V_GS − V_t, where V_t is the threshold voltage) is sufficiently large, Rch is known to be inversely proportional to Vov according to Equation 4. Therefore, R_p can be extracted using a linear extrapolation of the R_DS − 1/V_ov relationship (Figure 11D), which is derived from the I_D −V_GS from which the threshold voltage (V_t) can be characterized with the maximum-g_m method. Secondly, the C_gc − V_GS of a large (W = L = 50 µm) device (Figure 11A) is integrated and normalized to the channel area (A = 2500 µm²) to estimate the inversion charge.

The large device dimensions minimizes the parasitic capacitance contribution to ensure C_gc is representative of the inversion electron responses. Finally, the foregoing characterizations are combined to obtain the effective mobility using Equation 4 (Figure 11E). [00161] Figures 11A to 11G illustrate mobility extraction. Figure 11A shows split C-V curves obtained for multilayer HfO₂-ZrO₂ gate stacks (repeated 1 and 3 times, that is, HZHx1 and HZHx3) and 60 Å HfO₂ dielectric control (Hf-60) from L_G = 50 µm bulk transistors at 10 kHz. These C-V curves were fit to EOT simulations of 7.5 Å, 10.6 Å, and 18 Å for HZHx1, HZHx3, and Hf-60, respectively. From the off-state accumulation C-V, a doping level of Na = 2 x 10¹⁷ cm⁻³ was extracted; and from the slope of the inversion C-V, the interface trap density was found to be D_it = 3 x 10¹² eV⁻¹ cm⁻². [00162] Figures 11B and 11C show I_D -V_G and g_m-V_G (transfer characteristics, respectively, for L_G = 1µm bulk transistors at V_DS = 50 mV for multiple devices per sample. [00163] Figure 11D shows a series resistance extraction from 1/V_ov method for V_ov = V_gs − V_t = 0.3 V to 0.5 V for L_G = 1µm. The threshold voltage was extracted from the maximum g_m method. [00164] Figure 11E shows extracted mobility as a function of inversion sheet charge density; the effective mobility was taken to be the average maximum mobility across all measured devices. [00165] Figures 11F and 11G show transfer I_D-V_G and g_m data, respectively, fit to a constant mobility model based on the extracted effectively mobility in Figure 11E. All data shown are taken for LG = 1 µm bulk transistors, and a summary of the EOT-mobility trend from the various samples is provided in Figures 4A to 4F. [00166] Transconductance extraction. The measured transconductance (g_m = ∂I_D /∂V_GS ) and the output conductance (g_ds = ∂I_D /∂V_DS ) are affected by the series resistance on the source (RS) and the drain sides (RD), as they reduce the voltage drops on the channel region.

where V_GSi and V_DSi are the gate-to-source and the drain-to-source voltages intrinsic to the channel, respectively. R_S ≈ R_D ≈ R_p/2 because the transistor is symmetric. [00167] R_p can be extracted from the R_DS − 1/V_ov relationships as discussed in the “Mobility extraction” section (Figure 12B). Besides, devices with different gate length (L_g) series are fabricated on the SOI wafer, which enables another extraction method with R_SD − L_g relations. At low V_D and a given V_ov, Q_inv and µ_eff are unchanged across different gate lengths (L_g) if the short-channel effect is not significant, making R_ch proportional to the channel length. Such conditions are confirmed by the consistency of Vt across measured L_g (Figure 12A). Therefore, the L_g offset and the R_p can be found at the intersect of the linear relations of the R_SD − L_g with different V_ov (Figure 12C). The two R_p extraction methods yield consistent results. [00168] Figures 12A to 12E illustrate transconductance extraction. Figure 12A shows threshold voltage extraction by linear extrapolation for various channel lengths; all channel lengths give nearly constant V_T (∼0.42 V), satisfying the assumption for the line resistance method. [00169] Figure 12B shows source/drain series resistance extracted using the 1/V_ov method; by performing a linear interpolation of the total resistance for V_ov = 0.5 V to 0.6 V, the extracted series resistance is ∼500 Ω-µm. [00170] Figure 12C shows source/drain series resistance extracted using the line resistance method; the trend is considered down to L_G = 90 nm, which intersects at ∼500-600 Ω-µm and which is consistent with the 1/Vov method, with an L_G offset of ∼50 nm. [00171] The following equation is solved to extract the intrinsic g_mi = ∂I_D/∂V_GSi and g_dsi = ∂I_D/∂V_DSi without the degradation due to R_S and R_D.

where g_m and g_ds are measured, and R_S ≈ R_D ≈ R_p/2 from the foregoing discussed characterizations. Using this methodology, the intrinsic g_mi and intrinsic g_dsi are extracted (Figure 4F; Figures 12D and 12E). [00172] Figures 12D and 12E show measured (left) and extracted (right) transconductance and showing output conductance, respectively, versus V_G for V_DS = 0.9 V to 1.1 V, assuming R_s = R_d = 250 Ω-µm for L_G = 90 nm. The de-embedding of intrinsic g_m and g_ds from extrinsic G_m and G_ds is described in the methods section. All data shown were measured on SOI short-channel transistors integrating the 2 nm HfO2-ZrO2-HfO2 ferroic gate stack. [00173] Radio frequency measurements. Scattering-parameters (S parameters) for L_G = 1 µm bulk transistors (henceforth referred to as the device under test, DUT) at various DC biases as well as open and short structures (Figure 13A) are measured using a Keysight E8361C Network Analyzer in conjunction with a Keysight 4155C Semiconductor Parameter Analyzer. The devices were measured using low contact resistance Infinity Series probes. To calibrate the measurement setup, a line-reflect-reflect- match calibration was performed with a Cascade Microtech Impedance Standard. Following calibration, S-parameters were measured for each of the DUT, open, and short structures. These measured S-parameters were converted to admittance parameters (Y-parameters), Y_DUT, Y_open, and Y_short. To remove the effects of parasitic shunt parasitic pad capacitance and series pad resistance and inductance of the DUT, the following de-embedding process was followed. First, to decouple the effect of shunt parasitic capacitances, the Y parameters of the open structure (Y_open) are subtracted from the Y parameters of the DUT and short structure and then are converted to impedance parameters (Z parameters):

Next, to decouple the effect of series pad resistance and inductance of DUT, Z2 is subtracted from Z1, and the resulting difference is converted back to admittance parameters, Y_corr:

Y_corr represents the de-embedded admittance parameters of the DUT. This de-embedding procedure is schematically represented in Figure 13A. [00174] Figures 13A to 13C illustrate RF device characterization. Figure 13A is a diagram of a de-embedding procedure for extracting corrected admittance parameters (Y_corr) by decoupling parasitic shunt capacitance and series resistance and inductance by measuring scattering parameters for the device under test (DUT) as well as open and short structures. [00175] To extract the total gate capacitance (C_gg) and transconductance (g_m) from the de-embedded admittance parameters, a small-signal model of the transistor was assumed (Figure 13B). Under this small-signal model, the Y-parameters can be written in terms model parameters and frequency (assuming

The transconductance (g_m) can therefore be extracted at a fixed DC bias via the following relation (Figure 4C; Figure 12C).

[00176] Figure 13B shows a small-signal model for a transistor used to extract transconductance (g_m) and total gate capacitance (C_gg = C_gs + C_gd). [00177] Figure 13C shows de-embedded ^^[^_^^] ^^^ (open circles) as a function of squared frequency at different DC V_GS bias points extrapolated to the zero frequency limit (dotted lines) to extract the RF g_m. All data shown were extracted from bulk transistors (L_G = 1 µm) integrating the 2 nm HfO2-ZrO2- HfO₂ ferroic gate stack. [00178] Charge boost measurements. Pulsed charge-voltage measurements (Figures 14A to 14F) were conducted on p- Si/SiO2/HfO2-ZrO2 (2 nm)/TiN/W capacitor structures to extract the energy landscape of the ferroic HfO₂-ZrO₂ heterostructure. The capacitor structures were connected to an Agilent 81150A Pulse Function Arbitrary Noise Generator, and the current and voltage were measured through an InfiniiVision DSOX3024A oscilloscope with a 50 Ω and 1 MΩ input impedance, respectively. Short voltage pulses (500 ns) with increasing amplitudes were applied to the capacitor (Figure 14C). From the integration of the measured discharging current, a charge vs. voltage relationship was extracted (Figure 14D). The voltage was calculated by max(V − IR), where V is the applied voltage pulse, I is the measured current, and R is a combination of the oscilloscope resistance (50 Ω) and parasitic resistances associated with the setup and lightly doped substrate (220 Ω). Fast voltage pulses were applied in order to minimize charge injection into the ferroelectric-dielectric interface, which could mask the observation of the negative capacitance regime. Additionally, short voltage pulses help prevent electrical breakdown of the SiO₂ layer. To determine the P-E_F relation of the 2 nm HfO2-ZrO2 heterostructure, the electric field across the ferroic HfO2-ZrO2 heterostructure was calculated by subtracting the voltage across the series capacitance of the SiO₂ interlayer and Si charge layer (V_D) at a fixed charge value,

where t is the thickness of the HfO2-ZrO2 heterostructure. The Q-V relation of the series capacitance of the SiO₂ interlayer and Si charge layer was determined via thickness-dependent C-V measurements of Al2O3 and HfO2 (Figures 10A to 10F; Electrical interlayer thickness extraction), which corresponded to 8 Å SiO₂ on lightly doped Si. The charge boost due to negative capacitance was calculated by integrating the difference between the Q-V relations of the 2 nm HfO2-ZrO2 heterostructure and the series combination of the SiO2 interlayer and the Si charge layer (Figure 14E). [00179] Figures 14A to 14F illustrate capacitance and charge enhancement. Figure 14C shows the applied voltage pulse (top), the measured current response (center), and the integrated charge (bottom) as a function of time for 2 nm HfO₂-ZrO₂-HfO₂ trilayer in MOS capacitors. [00180] Figure 14D shows the maximum charge Q_max, the residual charge Q_res, and their difference, Q_rev, derived from the charge vs. time curve for each of the voltage pulses. [00181] Figure 14E shows the reversible charge of the MOS layer (top) compared with the extracted charge of the Si charge layer plus SiO2 interlayer (SiL) derived electrically (see Figure 7F). The charge boost (bottom) present in the total MOS structure (SiL plus HZH capacitors) compared with just the SiL is a signature of negative capacitance, as previously demonstrated in metal-ferroelectric-insulator-metal structures. [00182] Figure 14A shows a MOS of the 20 Å HfO₂-ZrO₂-HfO₂ mixed ferroic trilayer sample on lightly doped Si (10¹⁵ cm⁻³) considered for the following accumulation C-V and pulsed I-V measurements. [00183] Figure 14B shows accumulation C-V curves for the 2 nm HfO₂- ZrO₂-HfO₂ trilayer grown on sub-nanometer SiO₂ fit to effective oxide thickness (EOT) simulations, and the inset shows externally verified MOS accumulation C-V of the same trilayer stack, demonstrating 6.5 Å EOT. The 2 nm trilayer on top of SiO₂ demonstrates lower EOT than the thickness of SiO2 interlayer alone, carefully extracted via physical (8.5 Å) and electrical (8.0 Å) methodologies (see Figures 10A to 10F), providing evidence of capacitance enhancement. [00184] Figure 14F is a scatter plot of reported ferroelectric-dielectric systems demonstrating negative capacitance at the capacitor level via capacitance ( C-V measurements) or charge (pulsed l-V measurements) enhancement. The plot considers fluorite-structure bilayers (red), perovskite- structure bilayers (blue, BL), and perovskite-structure superlattices (blue, SL). Employing the sub-nanometer S1O2 interlayer and 2 nm Flf02-Zr02 multilayer on silicon (black, star) as disclosed provides the most scaled demonstration of negative capacitance, as supported by enhanced capacitance from C-V measurements (Figure 14B) and amplified charge from pulsed l-V measurements (Figure 14E) relative to the S1O2 dielectric interlayer.

Modeling

[00185] Landau phenomenology of antiferroelectric-ferroelectric system. The qualitative energy landscape for a mixed ferroelectric- antiferroelectric material (Figure 1A) was calculated by assuming a series combination of antiferroelectric and ferroelectric layers connected to a voltage source t/_s. The energy landscape potentials were calculated via the Landau- Ginzburg-Devonshire formalism (without strain coupling):

For the antiferroelectric layer, the energy landscape assumes two sublattices (Pa, P_b) with spontaneous, antiparallel dipoles. To express the AFE energy landscape in terms of total polarization, a change of variables was performed (P = P_a + P_b, A = P_a - P_b). The antiferroelectric profile therefore becomes,

The system is also constrained by electrical boundary conditions at the antiferroelectric/ferroelectric interface ^_^^_^^^ + ^_^^^ = ^_^^_^^ + ^_^^ and that the voltage across both layers must sum up to ^_^^^_^ = ^_^^^_^^ + ^_^^^^_^^^^. With these constraints, the combined energy profile is given by

To further simplify this expression, note that the last term represents the electrostatic energy arising from polarization mismatch at the AFE-FE interface. In general, such mismatch is quite costly, resulting in nearly uniform polarization across all layers. Therefore, the approximation (P_AFE = P_FE = P ) is applied, which sets the last term to 0. Furthermore, to express U as just a function of P, another constraint can be generated by noting that in equilibrium, ∇U_A = 0, resulting in the constraint,

This constraint allows for the determination of A for any value of P, which allows one to determine U as a function of P (Figure 1A). [00186] Technology computer-aided design simulations. The measured C-V curves are calibrated to Sentuarus Technology computer-aided design simulations device simulator, which solves the electrostatics, electron and hole transports, and the quantum confinement effect self-consistently. The MOS capacitors with 1 × 10¹⁵ cm⁻³ p-type substrate doping and L = 50 µm planar MOSFETs with 2 × 10¹⁷ cm⁻³ p-type substrate doping are simulated with finite-element method. The EOT and the metal work function (φm) are the only two parameters that are fit to the MOS capacitor measurement results, yet the slope of the accumulation capacitance can be successfully captured by the model (Figure 2F; Figures 10A to 10F). Similarly, both components (gate-to-channel and gate-to-body) of the MOSFET split C-V are captured by the TCAD model with appropriate EOT, φm, and an Si/SiO2 interface state density of 2 × 10¹² cm⁻²eV⁻¹ (Figure 11A). Atomic-Scale HfO₂-ZrO₂ Mixed-Ferroic Heterostructure [00187] Thickness limits and atomic-scale heterostructures. Recent perspectives on HfO2-based ferroelectricity for device applications posed the technological challenges stemming from thickness limit concerns of HfO2- based ferroelectricity, and thereby, negative capacitance. The use of short- period superlattices, that is, nanolaminates, is common in the high-κ field to enhance permittivity; in particular, rutile-structure titanium oxide (TiO2) is often paired with fluorite-structure HfO₂ and/or ZrO₂ in dynamic random-access memory (DRAM) capacitors. Recently, fluorite-structure nanolaminates were employed to tune the ferroelectric behavior of HfO2-ZrO2 films. However, all previous works have studied nanolaminates with thick periodicity, going as thin as 10 ALD cycles (∼1.1 nm) per superlattice sub-layer. The method of the present disclosure scales down to a much thinner thickness limit while still maintaining physical separation of the individual layers (Figures 6A to 6D). The reasoning behind using a short-period superlattice structure to scale down the ferroic behavior of HfO₂-ZrO₂ rather than simply thinning down a solid solution stems from the notorious thickness-dependent ferroelectric behavior in Zr:HfO2 at fixed composition. In the present disclosure, the use of nanolaminated structures can help provide thickness-independent scaling of ferroic order, as has been previously demonstrated to overcome the upper thickness limit of HfO2-based ferroelectricity. The persistence of high capacitance for these 2 nm films is notable considering other high-κ dielectric systems suffer from significant permittivity degradation in the thin film (sub-10 nm) regime, particularly TiO2-based and strontium titanium oxide (SrTiO₃)-based oxides. Sustaining the mixed ferroic order underlying negative capacitance to the 2 nm regime is extremely relevant for advanced technology nodes, which budget only ∼2 nm for the oxide layer. [00188] Iso-structural polycrystalline multilayer. Previous attempts to heterostructure ferroelectric Zr:HfO2 with dielectric Al2O3 failed to demonstrate capacitance enhancement, which was attributed to the fixed charges at the ferroelectric-dielectric interface. These charges can screen the ferroelectric polarization, pushing the stable point of the energy well to one of the minimum points, and thereby preventing stabilization of negative capacitance regime via depolarization fields from the dielectric. In the present disclosure the use of iso-structural HfO2-ZrO2 to serve as both the nonpolar (antiferroelectric) and polar (ferroelectric) layers, and leveraging the high (low) onset crystallization temperature of HfO₂ (ZrO₂) on Si, enables interfaces with diminished defects, allowing for the polar layer to experience the depolarization fields and stabilize in the “forbidden” negative charge regime. Regarding the polycrystalline nature of the ultrathin multilayers, it has been experimentally and theoretically established that negative capacitance can be stabilized in the presence of ferroelectric domains. [00189] It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein. [00190] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

Claims What is claimed is: 1. A gate stack (24) comprising: ^ an oxide layer (26) disposed over a semiconductor substrate (12); and ^ a periodic sequence of (HfO₂–ZrO₂)xN material layers (28) disposed over the oxide layer (26), wherein N is a natural counting number.

2. The gate stack (24) of claim 1 wherein the oxide layer (26) comprises silicon dioxide.

3. The gate stack (24) of claim 2 wherein the oxide layer (26) is between 8 Å and 8.5 Å in thickness.

4. The gate stack (24) of claim 2 wherein the oxide layer (26) has an effective thickness between 5.5 Å and 6.5 Å.

5. The gate stack (24) of claim 1 further comprising a metal layer disposed over the periodic sequence of (HfO₂–ZrO₂)xN material layers (28).

6. The gate stack (24) of claim 5 further comprising the metal layer disposed over the oxide layer (26) in a metal-oxide-metal capacitor configuration.

7. A method of fabricating a gate stack (24) comprising: ^ disposing an oxide layer (26) over a semiconductor substrate (12); and ^ disposing a periodic sequence of (HfO2–ZrO2)xN material layers (28) over the oxide layer (26), wherein N is a natural counting number.

8. The method of fabricating the gate stack (24) of claim 7 wherein disposing the oxide layer (26) over the semiconductor substrate (12) is achieved through atomic layer deposition.

9. The method of fabricating the gate stack (24) claim 8 wherein disposing the periodic sequence of (Hf02-Zr02)xN material layers (28) over the oxide layer (26) is achieved through atomic layer deposition.

10. The method of fabricating the gate stack (24) of claim 6 wherein the oxide layer (26) comprises silicon dioxide.

11. The method of fabricating the gate stack (24) of claim 10 wherein the oxide layer (26) is between 8 A and 8.5 A in thickness.

12. The method of fabricating the gate stack (24) of claim 10 wherein the oxide layer (26) has an effective thickness between 5.5 A and 6.5 A.

13. The method of fabricating the gate stack (24) of claim 6 further comprising disposing the metal layer over the periodic sequence of (HfC - Zr02)xN material layers (28).

14. A semiconductor device (10) comprising:

• a semiconductor substrate (12) having a source region (14), a channel region (16) spaced from the source region (14), and a drain region (18) spaced from both the source region (14) and channel region (16);

• a source contact (20) disposed over the source region (14);

• a drain contact (22) disposed over the drain region (18); and

• a gate stack (24) comprising:

• an oxide layer (26) disposed over the channel region (16);

• a periodic sequence of (Hf02-Zr02)xN material layers (28) disposed over the oxide layer (26), wherein N is a natural counting number; and

• a gate contact (30) disposed over the periodic sequence of (Hf02-Zr02)xN material layers (28).

15. The semiconductor device (10) of claim 14 wherein the semiconductor substrate (12) comprises silicon.

16. The semiconductor device (10) of claim 14 wherein the oxide layer (26) comprises silicon dioxide.

17. The semiconductor device (10) of claim 16 wherein the oxide layer is between 8 A and 8.5 A in thickness.

18. The semiconductor device (10) of claim 16 wherein the oxide layer has an effective thickness between 5.5 A and 6.5 A.

19. The semiconductor device (10) of claim 14 wherein the source contact (20), the drain contact (22), and the gate contact (30) comprise metal.

20. The semiconductor device (10) of claim 14 having an intrinsic transconductance of between 1.7 mb/mίti and 1.8 mb/mίti.