WO2022188034A1 - 一种时延参数的检验方法和装置 - Google Patents

一种时延参数的检验方法和装置 Download PDF

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WO2022188034A1
WO2022188034A1 PCT/CN2021/079794 CN2021079794W WO2022188034A1 WO 2022188034 A1 WO2022188034 A1 WO 2022188034A1 CN 2021079794 W CN2021079794 W CN 2021079794W WO 2022188034 A1 WO2022188034 A1 WO 2022188034A1
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parameters
delay
module
packet
message
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PCT/CN2021/079794
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English (en)
French (fr)
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肖聪
许辛达
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华为技术有限公司
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Priority to PCT/CN2021/079794 priority Critical patent/WO2022188034A1/zh
Priority to CN202180089633.2A priority patent/CN116685854A/zh
Publication of WO2022188034A1 publication Critical patent/WO2022188034A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits

Definitions

  • the present application relates to the field of chip testing, and in particular, to a method and device for checking time delay parameters of an ESL model.
  • the packet transmission delay in the switch is a key indicator for testing the performance of the switch. That is, with the rapid development of communication services, the switch chip delay performance indicator is becoming more and more important. For switch chips, large-scale and complex chip designs are common, and chip designers need to evaluate and master chip latency performance indicators at any time during the chip development process. During this process, once the chip's delay performance index does not meet the chip design specifications, the chip designer must adjust the chip architecture as soon as possible to ensure that the chip's delay performance index meets the design specifications, so as to ensure competition when the chip is finally cast. force.
  • ESL Electronic System Level
  • the ESL model uses the C ⁇ C++ high-level language to model the chip, and its code complexity and scale are much smaller than that of the RTL code, which can effectively support chip performance evaluation including delay evaluation.
  • the ESL model is just a model, not the same as the RTL code; in order to ensure the accuracy of the delay evaluation of the ESL model, it is necessary to back-mark all the parameters related to the delay in the RTL circuit to the ESL chip model, so as to ensure the ESL chip model. Evaluate the accuracy and validity of the latency performance metrics.
  • the realization method of back-marking the delay parameters in the RTL circuit to the ESL chip model is to rely on the chip designer to sample the delay parameters of the RTL circuit.
  • code developers can obtain delay parameters in RTL circuits by reading RTL codes. Due to differences in understanding of RTL codes by different developers, or omissions in understanding RTL codes, there may be large errors in the obtained RTL delay parameters, and then As a result, the accuracy of back-marking the delay parameters in the RTL circuit to the ESL chip model is not high.
  • the data error of the packet transmission delay estimated by the ESL model after inverting the delay parameters in the above method can reach 1 microsecond ( ⁇ s). More than 0.4 ⁇ s, so it still does not meet the requirements of high precision and low delay.
  • the present application provides a method and device for verifying delay parameters, which are used to detect whether the obtained ESL circuit delay parameters are accurate, and improve the accuracy of evaluating the message transmission delay by using the ESL model. Specifically, the application discloses the following technical solutions:
  • the present application provides a method for verifying a delay parameter.
  • the method can be applied to a network device.
  • the network device can be a server or a functional module integrated on the server.
  • the method includes:
  • the first set of parameters includes delay parameters for message transmission in at least one module of the RTL circuit of the buffer transfer level;
  • the second set of parameters includes The delay parameter of the at least one module that is counted when the message is transmitted in the electronic system-level design ESL model;
  • the ESL model delay parameters are calibrated, and the calibrated parameters are used to evaluate the packet delay, thereby avoiding the need for developers to sample RTL.
  • This method improves the accuracy of using the ESL model to evaluate the message transmission delay, meets the requirements of high precision and low delay, and ensures the competitiveness of chip project development.
  • the method also splits the end-to-end delay data into numerous small-granularity delay indicators, that is, the transmission delay parameters corresponding to each module, and evaluates the delay data in each small-granularity delay parameter index. Make the evaluation results more refined and accurate.
  • the at least one module includes a first module
  • the acquiring the first set of parameters includes: acquiring the message from the time that reaches the first module The time difference between the point in time at the input interface and the point in time when the output interface is reached.
  • the method before acquiring the first set of parameters, further includes: judging whether the data transmitted by the packet in the RTL circuit chip is real data , and if so, obtain the first set of parameters.
  • judging whether the data transmitted by the message in the RTL circuit chip is real data includes: judging whether the message of the message starts from the message Whether the indicator carried in the beginning part is "1".
  • the obtaining the first set of parameters includes: obtaining a weighted average of delay parameters of the N packets transmitted in the same module.
  • the weighted average of N packets is calculated as the delay parameter of the RTL circuit, which is more accurate than obtaining the first set of parameters through a single packet.
  • the obtaining the first set of parameters includes: obtaining the first set of parameters from the chip delay accuracy verification table CLAT, and the CLAT
  • the table includes delay parameters transmitted by each of the at least one module.
  • the obtaining the second set of parameters includes: obtaining at least the packet in the ESL model based on ESL modeling and ESL simulation technology Delay parameter for a module transmission.
  • the present application also provides a device for checking a delay parameter, the device comprising:
  • an acquisition unit configured to acquire a first set of parameters and a second set of parameters, where the first set of parameters includes a delay parameter for message transmission in at least one module of the RTL circuit of the buffer transfer level, and the second set of parameters Including the delay parameter of the at least one module that is counted when the message is transmitted in the electronic system-level design ESL model;
  • a processing unit configured to check that when the first set of parameters does not match the second set of parameters, determine that there is an error in the second set of parameters, and calibrate the second set of parameters to obtain a third set of parameters, and using the third set of parameters to evaluate the packet transmission delay.
  • the at least one module includes a first module
  • the obtaining unit is further configured to obtain the input of the message from reaching the first module The time difference between the point in time of the interface and the point in time when the output interface is reached.
  • the processing unit is further configured to determine that the packet is in the RTL before the acquisition unit acquires the first set of parameters Whether the data transmitted in the circuit chip is real data, and if so, obtain the first set of parameters.
  • processing unit is further configured to determine that the data is real data when the indication flag carried in the message start part of the message is "1".
  • the obtaining unit is further configured to obtain a weighted average of delay parameters of the N packets transmitted in the same module.
  • the storage unit further includes a storage unit configured to store a chip delay accuracy verification table CLAT, where the CLAT table includes the at least delay parameters transmitted by each module in one module; the obtaining unit is further configured to obtain the first set of parameters from the CLAT of the storage unit.
  • CLAT chip delay accuracy verification table
  • the obtaining unit is further configured to obtain at least one module of the message in the ESL model based on ESL modeling and ESL simulation technology Delay parameter for transmission.
  • the present application also provides a detection device, the detection device includes at least one processor and an interface circuit, wherein the interface circuit is used to provide instructions and/or data for the at least one processor;
  • the at least one processor is configured to execute the instructions to implement the foregoing first aspect and the methods in various implementation manners of the first aspect.
  • the apparatus further includes a memory for storing the instructions and/or data.
  • the at least one processor and the interface circuit may be integrated into one processing chip or chip circuit.
  • the detection apparatus is a network device, and the network device includes but is not limited to a server and a controller.
  • the present application also provides a computer-readable storage medium, in which instructions are stored, so that when the instructions are executed on a computer or a processor, the instructions can be used to execute the foregoing first aspect and each of the first aspects. method in an implementation.
  • the present application also provides a computer program product, the computer program product includes computer instructions, when the instructions are executed by a computer or a processor, the aforementioned first aspect and the methods in various implementation manners of the first aspect can be implemented.
  • the present application further provides a server, including the foregoing second aspect and the apparatus in various implementation manners of the second aspect, or including the foregoing apparatus in the third aspect, for implementing the foregoing first aspect and the third aspect.
  • a server including the foregoing second aspect and the apparatus in various implementation manners of the second aspect, or including the foregoing apparatus in the third aspect, for implementing the foregoing first aspect and the third aspect.
  • methods in various implementations.
  • beneficial effects corresponding to the technical solutions of the various implementation manners of the second aspect to the fifth aspect are the same as the beneficial effects of the foregoing first aspect and various implementation manners of the first aspect.
  • beneficial effects in various implementation manners of the first aspect will not be repeated.
  • FIG. 1 is an architectural diagram of a wireless communication system according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an RTL circuit chip model provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for verifying time delay parameters provided by an embodiment of the present application
  • FIG. 5 is a schematic structural diagram of an apparatus for checking a delay parameter provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a detection apparatus provided by an embodiment of the present application.
  • the technical solution of the present application can be applied to a detection device, and the detection device can be used to evaluate the transmission delay of a chip in a chip testing stage of a switch or router.
  • the detection device is integrated into a third-party device as a functional module, such as an Android application package (APK), and the third-party device includes but is not limited to network devices such as servers and controllers.
  • API Android application package
  • the switch or router is a device in a wireless communication system, for example, in a wireless local area network (Wireless Local Area Network, WLAN), as shown in FIG. 1, including at least one server, switch, base station (Node B or eNB) and terminal equipment, etc.
  • the terminal equipment includes user equipment (user equipment, UE), smart phone, smart screen TV (TV), notebook computer, tablet computer, personal computer (personal computer, PC), personal digital assistant (personal digital assistant, PDA), Foldable terminals, wearable devices with wireless communication functions (such as smart watches or bracelets), etc.
  • the switch or router may also be applied in other communication systems, such as a wired transmission system, and the present embodiment does not limit the chip structure and composition of the switch or router.
  • ESL Electronic System Level
  • Common simulators include functional simulation, performance simulation, and instruction simulation.
  • ESL is a set of methodologies that can develop, optimize and verify complex system on chip (SoC) architectures and embedded software in a tightly coupled manner, and it can provide a verification basis for downstream register transfer level (RTL) implementations.
  • SoC system on chip
  • RTL register transfer level
  • ESL uses high-level languages such as C/C++ to simulate hardware behavior through software models, provides various levels of software simulation platforms for SoC systems, and provides a runnable verification environment for SoC system architecture verification and embedded software development. Effectively Support the iterative development of SoC systems.
  • RTL Register Transfer Level
  • EDA Electronic Design Automation
  • First-in, first-out (LIFO) and last-in-first-out (FIFO) are two methods of measuring transmission delay.
  • the FIFO method refers to the time interval between when the last bit (bit) of the frame enters the switch port and when the first bit of the frame is forwarded from the switch port. This time interval is the time required for the switch to perform entry lookup, buffer scheduling, and forwarding after the switch has completely received the packet.
  • the FIFO method refers to the time interval between the first bit of the frame entering the device port and the first bit of the frame being forwarded from the device port. In cut-through mode, the forwarding starts as soon as the packet header reaches the switch, and the packet is not cached. This method can more accurately measure any storage or storage encountered by the packet/packet as it passes through the switch. Therefore, in this embodiment, the FIFO method is used to obtain the packet transmission delay.
  • An embodiment of the present application provides a method for checking time delay parameters, which is used to improve the accuracy of sampling parameters of an ESL chip model.
  • the method includes three stages, namely: a sampling stage, a comparison stage, and a calibration stage. The implementation process of these three stages is described below.
  • This embodiment takes the execution body as an example of a detection device.
  • the detection device needs to obtain two sets of parameters.
  • the first set of parameters is the delay parameters of the RTL circuit
  • the second set of parameters is obtained by using the ESL model. delay parameter.
  • this embodiment provides a schematic structural diagram of an RTL circuit chip model.
  • the RTL circuit chip shown in FIG. 2 includes 3 blocks, which are marked as block 0, block 1 and block 2, among which "0", "1” ” and “2” are the identifiers of blocks, and the identifiers of each block are different.
  • the circuit chip may also include other more or less modules, which is not limited in this embodiment.
  • each block contains at least one input interface and an output interface. For example, set the input interface of block 0 as a and the output interface as b; the input interface of block 1 as b and the output interface as c; block 2 The input interface is c, and the output interface is d.
  • the delay By marking the input/output interface of each block, it is convenient to record the delay (latency) of the message or data transmission in each block.
  • the above method for obtaining the delay parameters of the RTL circuit includes:
  • Step 101 Acquire a first set of parameters, where the first set of parameters includes delay parameters of at least one packet transmitted in at least one module of the RTL circuit.
  • the delay parameters of the RTL circuit when sampling the delay parameters of the RTL circuit, it is first necessary to judge whether the transmission of the (one or more) packets in the RTL circuit chip meets the preset conditions, and when the preset conditions are met, obtain the current packet transmission Delay parameter of at least one block of time statistics. If the preset conditions are not met, the sampling fails this time, and re-sampling is required.
  • the judging whether a preset condition is met includes: detecting whether the received message data is real data. If “Yes”, it is determined that the message transmission satisfies the preset condition; if the judgment result is "No", it is determined that the preset condition is not met. For example, taking the received packet as the first packet as an example, determine whether the indicator carried in the start-of-packet (sop) of the first packet is "1"; if it is "1" 1", it is determined that the data transmitted in the first packet is real data, that is, the preset condition is met; if the sop indication is marked as "0", the transmitted data is not real data, that is, the preset condition is not met.
  • the detection device when receiving the first packet, the detection device also acquires the first signal at the same time.
  • the signal flag (flag) of the first signal is valid (valid), for example, it is indicated as "1" in the signal flag of the first signal.
  • the first signal and/or the first message may be transmitted on the interface bus, and will pass through at least one block during transmission.
  • the chip circuit in order to indicate that the real message is transmitted through the chip interface, the chip circuit usually transmits a 1bit (bit) valid signal on the interface bus to detect whether there is a valid message transmission at the current moment. This process may be referred to as "valid signal flagging". If the content carried in the preset field in the signal is "1”, it means that the signal is valid, and the data on the interface bus is valid data at this time; if the content indicated in the signal mark is "0", it means that the signal is valid Invalid, that is, the data message from the RTL circuit chip has not been received, and thus the first set of parameters cannot be obtained.
  • valid signal flagging If the content carried in the preset field in the signal is "1”, it means that the signal is valid, and the data on the interface bus is valid data at this time; if the content indicated in the signal mark is "0”, it means that the signal is valid Invalid, that is, the data message from the RTL circuit chip has not been received, and thus the first set of parameters cannot be obtained.
  • the judging whether the data transmitted in the first message is real data can be determined by the sop indication mark.
  • each bus-width unit may also be called a packet fragmentation unit, and each packet fragmentation unit is used to transmit real and effective data.
  • the FIFO method is followed to count the delay, and only the moment of the first fragment (sop mark) of the packet is obtained.
  • the transmission delay of the first packet passing through block 0 can be expressed as latency_ab
  • the sampling point of input interface a can be expressed by start point
  • the sampling point of output interface b can be expressed by end point
  • ⁇ t(latency_ab) t(end Point)-t(start Point)
  • the transmission delay of the first packet in block 1 is latency_bc
  • the transmission delay in block 2 is latency_cd.
  • the delay parameters of each block in the RTL circuit chip model are represented by the "Chip Latency Accuracy Verification Table” (Chip Latency Accuracy Verification Table, CLAT table for short), as shown in Table 1 below.
  • LatencyName is a transmission delay name, which is unique within the same module.
  • start point is the starting position of the transmission delay sampling point, which can be used for the valid signal mark of the chip interface bus; end point is the end position of the transmission delay sampling point, which can be used for the valid signal mark of the chip interface bus.
  • the above-mentioned CLAT table may be preconfigured and stored in the detection device.
  • the parameters in the above CLAT table can be freely set by the chip developer, that is, which delay parameters need to be collected and compared, and the setting process of the above parameters in this embodiment is not limited.
  • the detection device uses the interface signal monitoring function provided by the EDA technology to add the input/output interface signal of each block to the EDA verification environment.
  • the input interface sends the first packet, and then samples the timestamp of the sampling point position of the first packet transmitted in each block in the EDA verification environment.
  • the first group of parameters is obtained as the delay parameter ⁇ t (latency_ab, the delay between ab interfaces) of block 0; for module block 1, Obtaining the first group of parameters is the delay parameter ⁇ t of block 1 (latency_bc, the delay between bc interfaces); module block 2, obtaining the first group of parameters is the delay parameter ⁇ t of block 2 (latency_cd, between cd interfaces delay); for the chip circuit module composed of modules block 0, block 1 and block 2, the acquired first group of parameters includes delay parameters ⁇ t(latency_ab), ⁇ t(latency_bc) and ⁇ t(latency_cd).
  • the first set of parameters may also be a weighted average of delay parameters of N packets acquired by the detection device and transmitted in the same module, where N is a positive integer and N ⁇ 2.
  • sample data ie, transmission delay parameters
  • the group of data is averaged to obtain the corresponding first group of parameters.
  • each packet in the first packet set is transmitted to block 0 respectively, and when the above preset conditions are met, the input/output interface of each packet in block 0 is obtained. , and then calculate the delay parameters of each packet in block 0, corresponding to the five packets 64B, 256B, 1518B, 4096B, and 9600B of the first packet set, and obtain five delay parameters, which are ⁇ t1, ⁇ t2, ⁇ t3, ⁇ t4 and ⁇ t5; calculate the weighted average ( ⁇ t average) from ⁇ t1 to ⁇ t5, and obtain the first set of parameters for block 0 as ⁇ t average.
  • the first set of parameters for each block is calculated using the same weighted average method.
  • the acquired first set of parameters includes 3 ⁇ t averages. For example, ⁇ t0 average, ⁇ t1 average, and ⁇ t2 average correspond to block 0, block 1, and block 2, respectively.
  • This method defines a standard circuit delay parameter sampling method by multiplexing the EDA verification monitor (the interface signal monitoring function provided by EDA technology): that is, adding the valid signal and the sop signal of the input/output interface of each block to the EDA verification
  • the EDA verification monitor the interface signal monitoring function provided by EDA technology
  • sampling will be performed according to the changes of the valid signal and the sop signal on the input interface, and the packet will be obtained at the corresponding input/output interface. Therefore, the delay parameters of the RTL circuit of each block can be accurately counted, which provides a basis for the subsequent parameter comparison stage.
  • Step 102 Obtain a second set of parameters by using the ESL model, where the second set of parameters includes delay parameters of at least one module counted by the ESL model.
  • the process of acquiring the second set of parameters is similar to the aforementioned step 101, and also uses each block as a unit to acquire the transmission delay of a packet in each block in the ESL model, or acquire multiple packets of different lengths The weighted average of the delays transmitted in the same block.
  • the transmission of the first message or the first message set ⁇ 64Byte, 256B, 1518B, 4096B, 9600B ⁇ in the second set of parameters is the same as the message transmitted by the interface bus in the aforementioned RTL circuit chip model.
  • the process of acquiring the transmission delay parameters of the model will not be described in detail.
  • both the aforementioned first set of parameters and the second set of parameters may be recorded in the CLAT table, and the obtained statistical results are shown in Table 2.
  • the method further includes: storing the above Table 2 in the storage unit of the detection device.
  • the calculated first and second sets of parameters of block 0 are 10 and 10, and the unit is (microsecond ⁇ s); the first and second sets of parameters of block 1 are divided into are 8 and 8; the first set of parameters and the second set of parameters of block 2 are 12 and 10.
  • the second set of parameters is the first packet in the ESL model
  • the transmission delay of the block 0 obtained in , for example, denoted as ⁇ t'(latency_ab). Compare whether ⁇ t(latency_ab) and ⁇ t'(latency_ab) are the same, or whether the difference between them is within the allowable range.
  • the detected RTL circuit module contains 3 blocks, compare whether the first set of parameters and the second set of parameters corresponding to each block are the same, or whether the delay difference of each set of parameters is within the allowable range. within.
  • the detection device uses the second set of parameters to evaluate the packet transmission delay, that is, to evaluate the chip transmission delay performance index using the delay parameters counted by the ESL model, and an accurate evaluation result can be obtained.
  • the first group of parameters ⁇ t(latency_ab) 10
  • the tester will call the timestamp corresponding to the input/output interface of the module if he wants to detect the transmission delay of the module, and then calculate the first group above. parameters and the second set of parameters.
  • the method further includes:
  • a possible implementation manner is to use the first set of parameters as an input for calibrating ESL model parameters, and modify the statistical delay parameters of the ESL model (ie, the second set of parameters) to obtain the third set of parameters. wherein the third set of parameters matches the first set of parameters.
  • the ESL model delay parameters are calibrated, and the calibrated parameters are used to evaluate the packet delay, thereby avoiding the need for developers to sample RTL.
  • This method improves the accuracy of using the ESL model to evaluate the message transmission delay, meets the requirements of high precision and low delay, and ensures the competitiveness of chip project development.
  • the method process of this embodiment can be shown in FIG. 4 .
  • the method includes three partial processes.
  • Part 1 is "delay parameter collection", which is the preparation stage of the method.
  • Delay Parameter Collection related functions are realized by developing a self-delay evaluation form, such as a CLAT table.
  • CLAT self-delay evaluation form
  • the chip developer confirms the content of the relevant delay parameters, as well as the name of the input interface and output interface of each block marked in the RTL circuit.
  • the second part is the “delay parameter sampling” process, which corresponds to the "1. Sampling stage” in the previous embodiment.
  • the delay parameter sampling includes: RTL circuit delay parameter sampling (first set of parameters) and sampling of ESL model delay parameters (second set of parameters).
  • the sampling of the delay parameters of the RTL circuit can be determined by recording the start position (start point) and end position (end point) of the interface sampling point of each block in the CLAT sheet, and adding the signal of each interface sampling point to the
  • the ESL model delay parameter records the interface signal information in the CLAT table, for example, finds the corresponding interface modeling feature in the ESL model, and obtains the time delay of any block in the ESL model based on ESL modeling and ESL simulation technology Extended parameter data.
  • the third part is "time delay parameter comparison and calibration", and this process corresponds to "second, comparison stage” and “third, calibration stage” in the foregoing embodiment.
  • the process of Part 3 "Delay parameter comparison and calibration” the specific values of the delay parameters of the RTL circuit and the delay parameters of the ESL model are compared based on the CLAT table. If the two sets of parameters are the same or match, it indicates that the ESL model The delay parameter is accurate; otherwise, it is determined that the delay parameter of the ESL model is inaccurate.
  • the delay parameter of the ESL model is calibrated.
  • the delay parameter of the RTL circuit is used as the input to calibrate the ESL model, the delay parameter of the ESL model is corrected to obtain the corrected delay parameter, and then the corrected delay parameter is used to evaluate the message transmission delay.
  • the embodiment of the present application adopts the C language high-order ESL model delay parameter to realize the message delay evaluation. At this time, it is necessary to Using the delay parameters of the RTL circuit to calibrate the delay parameters of the ESL model with errors, the corrected ESL delay parameters are obtained.
  • This method solves the problem of insufficient accuracy of the switch chip delay evaluation, quickly marks the RTL circuit parameters that affect the chip delay into the ESL model, evaluates whether the ESL model delay parameters are accurate through the high-precision chip ESL model, and evaluates whether the delay parameters of the ESL model are accurate.
  • the error of the ESL model delay parameters is corrected, and finally the packet transmission delay is evaluated by the corrected ESL model delay parameters, and accurate delay results are obtained.
  • This method improves the efficiency and accuracy of aligning the ESL model delay parameters.
  • the end-to-end delay data is also divided into many small-granularity delay indicators, that is, the transmission delay parameter corresponding to each block, and the time is evaluated in each small-granularity delay parameter index. Extending the data, making the evaluation results more refined and accurate.
  • this method can provide not only the end-to-end transmission delay data of the chip, but also the transmission delay parameter data of any length (the length is less than the end-to-end delay of the chip) according to the needs of the chip developer. It provides convenience for chip developers to evaluate the delay indicators of different modules and subsystems inside the chip.
  • FIG. 5 is a schematic structural diagram of an apparatus for checking a delay parameter according to an embodiment of the present application.
  • the device may be the aforementioned detection device, or a third-party device, where the third-party device includes the functions of the detection device, and can implement the method for verifying the delay parameter in the foregoing embodiment.
  • the apparatus may include: an acquisition unit 501 and a processing unit 502 .
  • the apparatus may further include other units or modules such as a storage unit (the storage unit is not shown in FIG. 5 ), which is not limited in this embodiment.
  • the obtaining unit 501 is configured to obtain a first set of parameters and a second set of parameters, where the first set of parameters includes delay parameters of packets transmitted in at least one module of the RTL circuit, and the second set of parameters includes all The delay parameter of the at least one module that is counted when the message is transmitted in the ESL model, and the detected RTL circuit and the ESL circuit are pre-divided into at least one module (block), and each module includes a signal input interface and output interface.
  • the processing unit 502 is configured to check that when the first set of parameters does not match the second set of parameters, determine that there is an error in the second set of parameters, and calibrate the second set of parameters to obtain a third set of parameters , and use the third set of parameters to evaluate the packet transmission delay.
  • the obtaining unit 501 is further configured to obtain the time point when the message reaches the input interface of the first module. The time difference from the point in time when the output interface is reached.
  • the obtaining unit 501 is further configured to obtain the first set of parameters by multiplexing the EDA verification monitor, or adopting the interface signal monitoring function provided by the EDA technology.
  • the processing unit 502 is further configured to, before the obtaining unit 501 obtains the first set of parameters, determine whether the data transmitted by the message in the RTL circuit chip is not. is the real data, and if so, obtain the first set of parameters.
  • the obtaining unit 501 is further configured to obtain the weighted average of the delay parameters of the N packets transmitted in the same module.
  • the storage unit is configured to store a CLAT table, where the CLAT table includes a delay parameter transmitted by each module in the at least one module.
  • the obtaining unit 501 is further configured to obtain the first set of parameters from the CLAT stored in the storage unit.
  • the CLAT table further stores the second group of parameters and a comparison result after comparing the first group of parameters with the second group of parameters.
  • the obtaining unit 501 is further configured to obtain a delay parameter of the packet transmission in at least one module in the ESL model based on ESL modeling and ESL simulation technology.
  • the device combines EDA verification technology and ESL model technology to quickly mark the RTL circuit parameters into the ESL model, ensuring that accurate delay data can be obtained at any time during the chip development process, and improving the efficiency of obtaining chip transmission delay parameters.
  • an embodiment of the present application further provides a detection device, which may be a chip circuit, or may also be a functional module integrated in a third-party device, such as an APK package.
  • the detection device may further include the aforementioned time delay parameter verification device.
  • FIG. 6 shows a schematic structural diagram of the detection device, including: at least one processor 110 and an interface circuit 120, wherein at least one processor 110 and the interface circuit 120 are coupled through a bus.
  • processor 110 and the interface circuit 120 are coupled through a bus.
  • other modules or units such as the memory 130 and at least one pin may also be included.
  • At least one processor 110 is the control center of the chip circuit, and can be used to complete the method for checking the delay parameter in the foregoing embodiments, and the like.
  • At least one processor 110 may be composed of an integrated circuit (Integrated Circuit, IC), for example, may be composed of a single packaged IC, or may be composed of a plurality of packaged ICs connected with the same function or different functions.
  • the processor may include a central processing unit (central processing unit, CPU) or a digital signal processor (digital signal processor, DSP) or the like.
  • At least one processor 110 may further include a hardware chip, and the hardware chip may be a logic circuit, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or its combination.
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general-purpose array logic (generic array logic, GAL) or any combination thereof.
  • CPLD complex programmable logic device
  • FPGA field-programmable gate array
  • GAL general-purpose array logic
  • the memory 130 is used for storing and exchanging various types of data or signals, including the first message, the first message set, the first group of parameters, the second group of parameters or the CLAT table, and the like.
  • computer programs or codes may be stored in the memory 130 .
  • the memory 130 may include volatile memory (volatile memory), such as random access memory (RAM); may also include non-volatile memory (non-volatile memory), such as flash memory (flash memory) memory), hard sisk drive (HDD) or solid-state drive (Solid-State Drive, SSD), the memory 130 may also include a combination of the above-mentioned types of memory.
  • volatile memory such as random access memory (RAM)
  • non-volatile memory such as flash memory (flash memory) memory), hard sisk drive (HDD) or solid-state drive (Solid-State Drive, SSD
  • flash memory flash memory
  • HDD hard sisk drive
  • SSD solid-state drive
  • the memory 130 may be used as a storage medium, integrated in at least one processor 110, or configured outside the processor, which is not limited in this embodiment.
  • the memory 130 is used for storing the first group of parameters, the second group of parameters, the received message, and the CLAT table and other information.
  • the interface circuit 120 may use any transceiver-like device.
  • the interface circuit 120 is connected to the RTL circuit chip, and is used to obtain the delay parameter of the RTL circuit, that is, the aforementioned first group of parameters.
  • the interface circuit 120 is further configured to obtain the delay parameter of at least one module of the ESL model statistics, that is, the aforementioned second set of parameters.
  • interface circuit 120 is also used to communicate with other internal or external devices, such as Ethernet, WLAN, and the like.
  • the third-party device may further include a mobile communication module, a wireless communication module, and the like.
  • the mobile communication module includes: a module with wireless communication function such as 2G/3G/4G/5G communication.
  • filters, switches, power amplifiers, low noise amplifiers (LNAs), etc. may also be included.
  • the wireless communication module can provide wireless communication solutions including WLAN, Bluetooth (BT), global navigation satellite system (GNSS), etc. applied on the server or the controller.
  • the above-mentioned detection device may also include other more or less components, and the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the structures thereof. And the components shown in FIG. 6 can be implemented in hardware, software, firmware or any combination thereof.
  • the functions of the acquisition unit 501 and the processing unit 502 can be implemented by at least one processor 110 and the interface circuit 120 , and the functions of the storage unit can be implemented by the memory 130 .
  • an embodiment of the present application also provides a wireless communication system.
  • the system includes at least one server, a switch, a UE, and an eNB.
  • the structure of each device in the system may be the same as that shown in FIG. 6 , or may be different.
  • At least one processor 110 uses the interface circuit 120 to obtain the first set of parameters and the second parameter, and the first set of parameters includes a message in at least one module of the RTL circuit Delay parameters of transmission, the second group of parameters includes delay parameters of the at least one module that are counted when the packet is transmitted in the ESL model.
  • at least one processor 110 is further configured to determine whether the first set of parameters matches the second set of parameters, and if not, determine that there is an error in the second set of parameters, and determine whether the second set of parameters is in error. Perform calibration to obtain a third group of parameters, and use the third group of parameters to perform the evaluation of the message transmission delay.
  • this method improves the accuracy of using the ESL model to evaluate the message transmission delay, and at the same time meets the requirements of high precision and low delay, and ensures the competitiveness of chip project development.
  • the present application also provides a computer program product comprising one or more computer program instructions.
  • a computer loads and executes the computer program instructions, all or part of the processes or functions described in the various embodiments described above occur.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer program instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transferred from a network node, computer, server or data
  • the center transmits to another node by wire or wireless.

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Abstract

一种时延参数的检验方法和装置，方法包括：获取第一组参数和第二组参数，第一组参数包括报文在暂存器转移层次RTL电路的至少一个模块中传输的时延参数，第二组参数包括报文在电子系统级设计ESL模型传输时统计的至少一个模块的时延参数；检验如果第一组参数与第二组参数不相匹配，则确定第二组参数存在误差，对第二组参数进行校准得到第三组参数，以及利用第三组参数进行报文传输时延的评估工作，从而可避免开发人员采样RTL时延参数带来的误差，本方法提高了利用ESL模型评估报文传输时延的精确度，同时满足高精度、低时延的要求。

Description

一种时延参数的检验方法和装置 技术领域
本申请涉及芯片测试领域，尤其是涉及一种ESL模型的时延参数的检验方法和装置。
背景技术
报文在交换机中的传输时延是测试交换机性能的一个关键指标，即随着通信业务的飞速发展，交换机芯片时延性能指标也越来越重要。对于交换机芯片而言，大规模和大复杂度芯片设计是普遍存在，芯片设计者需要在芯片开发过程中随时评估和掌握芯片时延性能指标。在此过程中，一旦芯片的时延性能指标不符合芯片设计规格时，芯片设计者就要尽快地调整芯片架构，以便保证芯片时延性能指标符合设计规格，从而保证芯片最终投片时的竞争力。
对于交换机芯片设计者而言，在芯片开发过程中报文传输时延的评估方法包括以下两种：一种是通过电子设计自动化(Electronics Design Automation，EDA)验证的方式进行评估；另一种是通过电子系统级设计(Electronic System Level，ESL)芯片模型方式进行评估。其中，对于大规模和高复杂度的交换机芯片的设计而言，一般芯片设计者会使用ESL芯片模型替代真实的暂存器转移层次(Register Transfer Level，RTL)进行时延评估。
ESL模型使用了C\C++高级语言对芯片进行建模，其代码复杂度和规模要远小于RTL代码，进而能够高效支撑包括时延评估在内的芯片性能评估工作。但ESL模型只是模型，不等同于RTL代码；为了保证ESL模型评估的时延精准度，需要把RTL电路中与时延相关联的参数全部反标到ESL芯片模型中，这样才能保证ESL芯片模型评估的时延性能指标的准确性和有效性。
当前，将RTL电路中的时延参数反标到ESL芯片模型的实现手段是，依赖芯片设计人员对RTL电路进行时延参数采样。例如代码开发者通过阅读RTL代码来获得RTL电路中时延参数，由于不同开发人员对RTL代码理解差异，或者对RTL代码理解疏漏等因素都可能导致获得的RTL时延参数存在较大误差，进而导致将RTL电路中的时延参数反标到ESL芯片模型时精确度不高。在实际项目测试中，通过上述方式反标时延参数后的ESL模型评估的报文传输时延数据误差能达到1微秒(μs)，而业界对于交换机的整体时延性能指标的要求是不超过0.4μs，因此仍然不满足高精度、低时延的要求。
发明内容
本申请提供了一种时延参数的校验方法和装置，用于检测获得的ESL电路时延参数的是否准确，提高利用ESL模型评估报文传输时延的精确度。具体地，本申请公开了以下技术方案：
第一方面，本申请提供了一种时延参数的校验方法，该方法可应用于一种网络设备，该网络设备可以是服务器或集成在服务器上的功能模块，所述方法包括：
获取第一组参数，以及获取第二组参数，其中，所述第一组参数包括报文在暂存器转移层次RTL电路的至少一个模块中传输的时延参数；所述第二组参数包括所述报文在电子 系统级设计ESL模型传输时统计的所述至少一个模块的时延参数；
检验如果所述第一组参数与所述第二组参数不相匹配，则确定所述第二组参数存在误差，对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
本方面提供的方法，当检测出获得的ESL模型时延参数存在误差时，对该ESL模型时延参数进行校准，并利用校准后参数进行报文时延评估，从而避免了开发人员采样RTL时延参数带来的误差，本方法提高了利用ESL模型评估报文传输时延的精确度，同时满足高精度、低时延的要求，保证芯片项目开发的竞争力。
另外，本方法还将端到端的时延数据拆分成众多小粒度的时延指标，即每个模块对应的传输时延参数，在每一个小粒度延时参数指标中来评估时延数据，使得评估结果更精细和更准确。
结合第一方面，在第一方面的一种可能的实现方式中，所述至少一个模块包括第一模块，所述获取第一组参数包括：获取所述报文从达到所述第一模块的输入接口的时间点与达到输出接口的时间点之间的时间差。
结合第一方面，在第一方面的另一种可能的实现方式中，所述获取第一组参数之前，还包括：判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，如果是，则获取所述第一组参数。
结合第一方面，在第一方面的又一种可能的实现方式中，判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，包括：判断所述报文的报文起始部分所携带的指示标记是否为“1”。
结合第一方面，在第一方面的又一种可能的实现方式中，当所述报文为第一报文集，所述第一报文集中包括N个不同长度的报文，N≥2，且N为正整数，则所述获取第一组参数，包括：获取所述N个报文在同一模块传输的时延参数的加权平均值。本实现方式，计算N个报文的加权平均值作为RTL电路时延参数，相比于通过单一报文得到第一组参数而言，精度更高。
结合第一方面，在第一方面的又一种可能的实现方式中，所述获取第一组参数，包括：从芯片延时精准度验证表CLAT中获取所述第一组参数，所述CLAT表中包括所述至少一个模块中的每个模块传输的时延参数。
结合第一方面，在第一方面的又一种可能的实现方式中，所述获取第二组参数，包括：基于ESL建模和ESL仿真技术获取所述报文在所述ESL模型中的至少一个模块传输的时延参数。
第二方面，本申请还提供了一种时延参数的检验装置，所述装置包括：
获取单元，用于获取第一组参数和第二组参数，所述第一组参数包括报文在暂存器转移层次RTL电路的至少一个模块中传输的时延参数，所述第二组参数包括所述报文在电子系统级设计ESL模型传输时统计的所述至少一个模块的时延参数；
处理单元，用于检验在所述第一组参数与所述第二组参数不相匹配时，确定所述第二组参数存在误差，对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
结合第二方面，在第二方面的一种可能的实现方式中，所述至少一个模块包括第一模 块，所述获取单元，还用于获取所述报文从达到所述第一模块的输入接口的时间点与达到输出接口的时间点之间的时间差。
结合第二方面，在第二方面的另一种可能的实现方式中，所述处理单元，还用于在所述获取单元获取所述第一组参数之前，判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，如果是，则获取所述第一组参数。
进一步地，所述处理单元，还用于当所述报文的报文起始部分所携带的指示标记为“1”时，确定所述数据为真实数据。
结合第二方面，在第二方面的又一种可能的实现方式中，当所述报文为第一报文集，所述第一报文集中包括N个不同长度的报文，N≥2，且N为正整数，所述获取单元，还用于获取所述N个报文在同一模块传输的时延参数的加权平均值。
结合第二方面，在第二方面的又一种可能的实现方式中，还包括存储单元，所述存储单元，用于存储芯片延时精准度验证表CLAT，所述CLAT表中包括所述至少一个模块中的每个模块传输的时延参数；所述获取单元，还用于从所述存储单元的所述CLAT中获取所述第一组参数。
结合第二方面，在第二方面的又一种可能的实现方式中，所述获取单元，还用于基于ESL建模和ESL仿真技术获取所述报文在所述ESL模型中的至少一个模块传输的时延参数。
第三方面，本申请还提供了一种检测装置，该检测装置包括至少一个处理器和接口电路，其中，所述接口电路，用于为所述至少一个处理器提供指令和/或数据；所述至少一个处理器，用于执行所述指令，以实现前述第一方面及第一方面各种实现方式中的方法。
此外，所述装置中还包括存储器，所述存储器用于存储所述指令，和/或，数据。
可选的，所述至少一个处理器和所述接口电路可以集成在一个处理芯片或者芯片电路中。
可选的，所述检测装置为一种网络设备，所述网络设备包括但不限于服务器、控制器。
第四方面，本申请还提供了一种计算机可读存储介质，该存储介质中存储有指令，使得当指令在计算机或处理器上运行时，可以用于执行前述第一方面以及第一方面各种实现方式中的方法。
另外，本申请还提供了一种计算机程序产品，该计算机程序产品包括计算机指令，当该指令被计算机或处理器执行时，可实现前述第一方面以及第一方面各种实现方式中的方法。
第五方面，本申请还提供了一种服务器，包括前述第二方面以及第二方面各种实现方式中的装置，或者，包括前述第三方面中的装置，用于实现前述第一方面以及第一方面各种实现方式中的方法。
需要说明的是，上述第二方面至第五方面的各种实现方式的技术方案所对应的有益效果与前述第一方面以及第一方面的各种实现方式的有益效果相同，具体参见上述第一方面以及第一方面的各种实现方式中的有益效果描述，不再赘述。
附图说明
图1为本申请实施例提供的一种无线通信系统的架构图；
图2为本申请实施例提供的一种RTL电路芯片模型的结构示意图；
图3为本申请实施例提供的一种时延参数校验方法的流程图；
图4为本申请实施例提供的另一种时延参数校验方法的流程图；
图5为本申请实施例提供的一种时延参数的校验装置的结构示意图；
图6为本申请实施例提供的一种检测装置的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请实施例中的技术方案，下面结合附图对本申请实施例中的技术方案进行的说明。在对本申请实施例的技术方案说明之前，首先，对本申请技术方案的应用场景进行说明。
本申请的技术方案可应用于一种检测装置，该检测装置可用于在交换机或路由器的芯片测试阶段对芯片的传输时延进行评估。所述检测装置作为一个功能模块，比如一个安卓应用程序包(Android application package，APK)集成在第三方设备中，所述第三方设备包括但不限于服务器和控制器等网络设备。
其中，所述交换机或路由器为无线通信系统中的设备，比如在一无线局域网(Wireless Local Area Network，WLAN)中，如图1所示，包括至少一个服务器、交换机、基站(Node B或eNB)和终端设备等。所述终端设备包括用户设备(user equipment，UE)、智能手机、智慧屏电视(TV)、笔记本电脑、平板电脑、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)，可折叠终端、具备无线通讯功能的可穿戴设备(例如智能手表或手环)等。
此外，所述交换机或路由器还可以应用在其他通信系统中，比如有线传输系统等，本实施例对交换机或路由器的芯片结构和组成不予限制。
下面介绍芯片测试过程中可能使用的术语。
(1)电子系统级设计(Electronic System Level，ESL)，ESL是一种芯片仿真器的设计方法，常见仿真器有功能仿真、性能仿真、指令仿真，业界也有很多仿真器的设计平台和工具，比如：Coware、Carbon、Mentor等。ESL是一套能够以紧耦合方式开发、优化和验证复杂片上系统(system on chip，SoC)架构和嵌入式软件的方法论，它能够提供下游寄存器传输级(RTL)实现的验证基础。此外，ESL利用C/C++等高级语言通过软件模型来模拟硬件行为，为SoC系统提供各种级别的软件模拟平台，为SoC系统架构验证和嵌入式软件开发提供一种可运行的验证环境，有效支撑SoC系统的迭代开发。
(2)暂存器转移层次(Register Transfer Level，RTL)，又可以指“寄存器转换级电路”。在集成电路设计中，RTL用于描述同步数字电路操作的抽象级。
(3)电子设计自动化(Electronics Design Automation，EDA)，EDA技术是以计算机为工具，设计者在EDA软件平台上，融合应用电子技术、计算机技术、信息处理及智能化技术的最新成果，进行电子产品的自动设计。EDA技术的出现，极大地提高了电路设计的效率和可操作性。
(4)LIFO和FIFO。根据报文转发特性，可以包含以下报文转发时延类型：
先进先出(last bit in first bit out，LIFO)和后进先出(first bit in first bit out，FIFO)是两种测量传输时延的方法。其中，FIFO方法是指帧的最后一个比特(bit)进入交换机端口，到帧的第一个bit从所述交换机端口转发之间的时间间隔。这段时间间隔是交换机完全接收到报文后，进行表项查找，缓存(buffer)调度，再转发所需要的时间。
FIFO方法是指帧的第一个bit进入设备端口，到帧的第一个bit从设备端口转发之间的时间间隔。在直通转发(cut-through)模式方式下，只要报文头到达交换机即开始转发，报文不被缓存，这种方法能够更精确地测量数据包/报文经过交换机时遇到的任何存储或处理时间，因此本实施例中采用FIFO方法来获取报文传输时延。
下面对本申请的技术方案进行详细地说明。
本申请实施例提供了一种时延参数的检验方法，用于提高ESL芯片模型采样参数的精确度，该方法包括三个阶段，分别是：采样阶段、比较阶段和校准阶段。下面对这三个阶段的实施过程进行说明。
一、采样阶段
本实施例以执行主体为一种检测装置举例，在“一、采样阶段”，该检测装置需要获取两组参数，第一组参数为RTL电路时延参数，第二组参数为利用ESL模型获得的时延参数。首先，介绍获取第一组参数，即RTL电路时延参数的过程。
参见图2，为本实施例提供了一种RTL电路芯片模型的结构示意图，该结构示意图中将诸多复杂的电路结构简化为一个个模块(block)。本实施例对每个模块所包含的电路结构也不予限制，图2所示的RTL电路芯片内包含3个block，分别标记为block 0、block 1和block 2，其中“0”、“1”、“2”为block的标识，且每个block的标识都不同。此外，电路芯片中还可以包含其他更多或者更少的模块，本实施例对此不予限制。
在RTL电路芯片模型中，每个block包含至少一个输入接口和输出接口，比如，设置block 0的输入接口为a，输出接口为b；block 1的输入接口为b，输出接口为c；block 2的输入接口为c，输出接口为d，通过将每个block的输入/输出接口做标记，便于记录报文或数据在每个block中传输的时延(latency)。具体地，当第一报文传输经过任意一个block时，在该block中的传输时延可表征为：第一报文的报文头从到达该block的输入接口的时间点与到达输出接口的时间点之间的时间差Δt，即：传输时延＝到达输出接口的时间点–到达输入接口的时间点。
参见图3，上述获取RTL电路时延参数的方法，包括：
步骤101：获取第一组参数，所述第一组参数包括至少一个报文在RTL电路的至少一个模块中传输的时延参数。
具体地，在对RTL电路的时延参数进行采样时，首先需要判断(一个或多个)报文在RTL电路芯片内传输是否满足预设条件，当满足预设条件时，获取当前报文传输时统计的至少一个block的时延参数。如果不满足所述预设条件，则此次采样失败，需要重新采样。
其中，所述判断是否满足预设条件，包括：检测接收的报文数据是否是真实数据。如果“是”，则确定该报文传输满足所述预设条件；如果判断结果为“否”，则确定不满足所述预设条件。例如，以接收的报文是第一报文举例，判断该第一报文的报文起始部分(start-of-packet，sop)中所携带的指示标记是否为“1”；如果为“1”，则确定第一报文中传输的数据是真是数据，即满足所述预设条件；如果sop指示标记为“0”，则传输的不是真实数据，即不满足所述预设条件。
另外，检测装置在接收到所述第一报文时，还同时获取第一信号。其中，所述第一信号的信号标记(flag)为有效的(valid)，例如在第一信号的信号标记中指示为“1”。其中，所述第一信号和/或所述第一报文可在接口总线上传输，并且传输时会经过至少一个block。
在芯片电路逻辑中，为了表示真实报文传输通过芯片接口，芯片电路通常会在接口总线上传输一个1bit(比特)的有效(valid)信号，用于检测当前时刻是否存在有效的报文传输，该过程可称为“valid信号标记”。如果该信号中的预设字段中所携带的内容为“1”，则表示该信号为有效，此时接口总线上的数据是有效数据；如果信号标记中指示内容为“0”，则表示信号无效，即未接收到来自RTL电路芯片的数据报文，进而无法获得第一组参数。
此外，所述判断所述第一报文中传输的数据是否是真实数据，可通过sop指示标记来确定，由于接口总线是存在位宽(bus-width)限制的，所以对于长度较长的报文而言传输时需要将其切割成多个bus-width单元，其中每一个bus-width单元又可称为报文分片单元，每个报文分片单元上用于传输真实有效的数据。在“采样阶段”，遵循FIFO方法统计时延，仅获取报文起始部分分片(sop标记)的时刻。
比如以block 0为例，第一报文经过block 0的传输时延可表示为latency_ab，输入接口a采样点可通过start point表示，输出接口b采样点通过end point表示，则Δt(latency_ab)＝t(end Point)-t(start Point)。类似的，第一报文在block 1中的传输时延为latency_bc，在block 2中的传输时延为latency_cd。
可选的，将RTL电路芯片模型中每个block的时延参数通过“芯片延时精准度验证表”(Chip Latency Accuracy Verification Table，简称CLAT表)来表示，如下表1所示。
表1、CLAT表
Figure PCTCN2021079794-appb-000001
在表1中，block表示模块，LatencyName为传输时延名称，该名称在同一模块内具有唯一性。start point为传输时延采样点的起始位置，可用于芯片接口总线的valid信号标记；end point为传输时延采样点的结束位置，可用于芯片接口总线的valid信号标记。
应理解，上述CLAT表可预先配置并存储在检测装置中。另外，需要说明的是，上述CLAT表中的参数可由芯片开发者决定自由设置，即决定哪些时延参数需要被采集和比较，本实施例上述参数的设置过程不做限制。
在“一、采样阶段”，检测装置利用EDA技术提供的接口信号监测功能，将每个block的输入/输出接口信添加到EDA验证环境中，在最开始时向RTL电路芯片中的block 0的输入接口发送第一报文，然后在EDA验证环境中采样该第一报文在每个block中传输的采样点位置的时间戳。
具体地，在上述步骤101中以每个block为单位，对于模块block 0，获取所述第一组参数为block 0的时延参数Δt(latency_ab，ab接口间时延)；对于模块block 1，获取所述第一组参数为block 1的时延参数Δt(latency_bc，bc接口间时延)；模块block 2，获取所述第一组参数为block 2的时延参数Δt(latency_cd，cd接口间时延)；对于模块block 0、block 1和block 2组成的芯片电路模块，获取的所述第一组参数包括时延参数Δt(latency_ab)、 Δt(latency_bc)和Δt(latency_cd)。
可选的，为了提高采样的精确度，所述第一组参数还可以是检测装置获取的N个报文在同一模块传输的时延参数的加权平均值，N为正整数且N≥2。比如在一种报文采样方式中，芯片电路向接口总线传输第一报文集，所述第一报文集中包括N个标准长度的报文，比如，N＝5，且这5个报文的标准长度分别是：64Byte、256Byte、1518Byte、4096Byte、9600Byte等。针对每一个长度的报文在RTL电路模型中获得采样数据(即传输的时延参数)，然后将这组数据计算平均值从而得到对应的第一组参数。
例如，以block 0为例，将第一报文集中的每个报文分别传输至block 0中，且在满足上述预设条件的情况下，获取每个报文在block 0的输入/输出接口的时间戳，然后计算出每个报文在block 0的时延参数，对应于前述第一报文集的5个报文64B、256B、1518B、4096B、9600B，获得5个时延参数，分别是Δt1、Δt2、Δt3、Δt4和Δt5；计算从Δt1至Δt5的加权平均值(Δt平均)，得到关于block 0的所述第一组参数为Δt平均。同理地，对于block 1和block 2而言，计算每个block的第一组参数，也采用相同的求加权平均值的方法获得。对于包含3个block的RTL电路芯片模型，则获取的所述第一组参数中包括3个Δt平均。比如Δt0平均、Δt1平均、Δt2平均，分别对应于block 0、block 1和block 2。
本方法，通过复用EDA验证monitor(EDA技术提供的接口信号监测功能)，定义了标准的电路时延参数采样方法：即将每个block的输入/输出接口的valid信号和sop信号添加到EDA验证环境中，在芯片最开始的模块的输入接口处输入一个或多个报文，EDA验证环境中将根据输入接口上的valid信号以及sop信号变化进行采样，获得报文在对应输入/输出接口所处的时间戳，从而可以精准统计出每个block的RTL电路时延参数，为后续参数比较阶段提供依据。
步骤102：利用ESL模型获取第二组参数，所述第二组参数包括ESL模型统计的至少一个模块的时延参数。
其中，第二组参数的获取过程与前述步骤101相类似，也是以每个block为单位，获取一个报文在ESL模型中的每个block的传输时延，或者获取多个不同长度的报文在同一个block传输的时延的加权平均值。
应理解，在第二组参数中传输第一报文或第一报文集{64Byte、256B、1518B、4096B、9600B}与前述RTL电路芯片模型中接口总线传输的报文相同，本实施例对ESL模型的传输时延参数的获取过程不详细赘述。
可选的，对于前述第一组参数和第二组参数都可以记录在CLAT表中，得到统计结果如表2所示。以及，可选的，方法还包括：将上述表2存储在所述检测装置的存储单元中。
表2、CLAT表
Figure PCTCN2021079794-appb-000002
在一示例中，参见表2，计算的block 0的第一组参数和第二组参数分是10和10，单 位是(微秒μs)；block 1的第一组参数和第二组参数分是8和8；block 2的第一组参数和第二组参数分是12和10。
二、比较阶段
103：判断所述第一组参数和所述第二组参数是否相匹配，即判断所述RTL电路时延参数与所述ESL模型统计的时延参数是否相同。
具体地，以每个block为单位进行比较，如果前述第一组参数为第一报文经过block 0传输的时延Δt(latency_ab)，则第二组参数为所述第一报文在ESL模型中获取的该block 0的传输时延，比如记为Δt’(latency_ab)。比较Δt(latency_ab)和Δt’(latency_ab)是否相同，或者二者之差是否在允许的范围之内。
同理地，如果检测的RTL电路模块中包含3个block，则分别比较每个block对应的第一组参数和第二组参数是否相同，或者每一组参数的时延之差是否在允许范围之内。
104：如果否，即第一组参数和第二组参数不相匹配或不相同，则确定所述第二组参数(ESL模型统计的时延参数)存在误差。
105：如果是，即第一组参数和第二组参数相匹配或相同，则确定所述第二组参数不存在误差。然后，检测装置利用该第二组参数进行报文传输时延的评估工作，即利用该ESL模型统计的时延参数进行芯片传输时延性能指标评估，能得到准确的评估结果。
例如，前述表2统计的两组参数中，对于block 0而言，第一组参数Δt(latency_ab)＝10，第二组参数Δt’(latency_ab)＝10，即Δt(latency_ab)＝Δt’(latency_ab)，则确定所述第二组参数Δt’(latency_ab)采样准确。
同理地，对于block 1而言，第一组参数Δt(latency_bc)＝8，第二组参数Δt’(latency_bc)＝8，即Δt(latency_bc)＝Δt’(latency_bc)，则确定所述第二组参数Δt’(latency_ab)采样准确。对于block 2而言，第一组参数Δt(latency_cd)＝12，第二组参数Δt’(latency_cd)＝10，即Δt(latency_cd)＞Δt’(latency_cd)，则确定所述第二组参数Δt’(latency_cd)采样值不准确。
另外，对于整个包含3个block的ESL电路模型而言，如果这3个block中有一个或者一个以上的比较结果是“不相匹配”，则对于整个ESL电路而言，确定该第二组参数的采样结果不准确。换句话说，只有所有block比较的采样结果都是“准确”时，整个(overall)ESL电路模型的采样结果才准确。
需要说明的是，在上述表1或表2所统计的数据中，测试人员想要检测哪一个模块的传输时延就调用该模块输入/输出接口对应的时间戳，进而计算得到上述第一组参数和第二组参数。
三、校准阶段
在上述步骤103中判断出所述第二组参数存在误差时，衔接上述步骤104之后，所述方法还包括：
106：对所述第二组参数进行校准得到第三组参数，并利用所述第三组参数进行报文传输时延的评估工作。
一种可能的实现方式是，将所述第一组参数作为校准ESL模型参数的输入，修正ESL模型统计的时延参数(即所述第二组参数)，得到所述第三组参数。其中所述第三组参数与所述第一组参数相匹配。
本实施例的方法，当检测出采样的ESL模型时延参数存在误差时，对该ESL模型时 延参数进行校准，并利用校准后参数进行报文时延评估，从而避免了开发人员采样RTL时延参数带来的误差，本方法提高了利用ESL模型评估报文传输时延的精确度，同时满足高精度、低时延的要求，保证芯片项目开发的竞争力。
可选的，本实施例的方法流程可通过图4示出，参见图4，该方法包括3个部分流程，第①部分为“时延参数收集”，该流程为方法的准备阶段。具体地，在第①部分“时延参数收集”过程中，通过开发自有时延评估表单，比如CLAT表来实现相关功能。通过CLAT表单，芯片开发者确认相关的时延参数内容，以及其在RTL电路中标记每个block的输入接口和输出接口的名称。
第②部分为“时延参数采样”流程，对应于前述实施例的“一、采样阶段”，在第②部分“时延参数采样”过程中，时延参数采样包括：RTL电路时延参数采样(第一组参数)和ESL模型时延参数的采样(第二组参数)。
其中，RTL电路时延参数的采样可通过CLAT表单中记录每个block的接口采样点的起始位置(start point)和结束位置(end point)来确定，将每一个接口采样点的信号加入到EDA验证环境monitor组件中得到所述RTL电路时延参数。例如任一block的RTL电路传输时延Δt(latency)＝t(end point)-t(start point)。另外，所述ESL模型时延参数则通过CLAT表中记录接口信号的信息，比如在ESL模型中找到对应的接口建模特性，基于ESL建模和ESL仿真技术获取ESL模型中任一block的时延参数数据。
第③部分为“时延参数比对和校准”，该流程对应于前述实施例的“二、比较阶段”和“三、校准阶段”。在第③部分“时延参数比对和校准”过程中，基于CLAT表对RTL电路时延参数和ESL模型时延参数的具体数值进行比较，如果两组参数相同或相匹配，则表明ESL模型时延参数准确；否则，确定该ESL模型时延参数不准确。
进一步地，如果比较确定ESL模型统计的时延参数不准确，则对该ESL模型时延参数进行校准。例如，将RTL电路时延参数作为校准ESL模型的输入，修正ESL模型时延参数得到修正后的时延参数，然后利用该修正后的时延参数做报文传输时延的评估工作。
需要说明的是，如果采用RTL电路时延参数对报文传输时延进行评估，则对于大规模的业务复杂的芯片而言是无法实现的，因为实现成本和代价极高，所以为了在大规模芯片中去度量时延，并且避免RTL电路时延参数评估报文带来的高成本，进而本申请实施例采用C语言的高阶ESL模型时延参数来实现报文时延评估，此时需要利用RTL电路时延参数对有误差的ESL模型时延参数进行校准，得到修正的ESL时延参数。
本方法解决了交换机芯片时延评估精准度不足的问题，将影响芯片时延的RTL电路参数快速标记到ESL模型中，通过高精度的芯片ESL模型评估ESL模型时延参数是否准确，并对有误差的ESL模型时延参数进行修正，最后通过修正后的ESL模型时延参数评估报文传输时延，得到精准的时延结果，本方法提高了对齐ESL模型时延参数的效率和精准度。
另外，本实施例中，还将端到端的时延数据拆分成众多小粒度的时延指标，即每个block对应的传输时延参数，在每一个小粒度延时参数指标中来评估时延数据，使得评估结果更精细和更准确。
需要说明的是，本方法可根据芯片开发者的需要，不仅可提供芯片端到端的传输时延数据，还可以提供任意长度(该长度小于芯片端到端时延)的传输时延参数数据，为芯片开发者评估芯片内部不同模块、不同子系统的时延指标提供便捷。
下面介绍与上述方法实施例对应的装置实施例。
图5为本申请实施例提供的一种时延参数的校验装置的结构示意图。所述装置可以是前述的检测装置，或者是一种第三方设备，该第三方设备包含所述检测装置的功能，可以实现前述实施例中的时延参数的校验方法。
具体地，如图5所示，该装置可以包括：获取单元501和处理单元502。此外，所述装置还可以包括存储单元(该存储单元在图5中未示出)等其他的单元或模块，本实施例对此不予限制。
其中，获取单元501，用于获取第一组参数和第二组参数，所述第一组参数包括报文在RTL电路的至少一个模块中传输的时延参数，所述第二组参数包括所述报文在ESL模型传输时统计的所述至少一个模块的时延参数，且被检测的RTL电路和ESL电路预先被划分为至少一个模块(block)，每个模块包括信号的输入接口和输出接口。
处理单元502，用于检验在所述第一组参数与所述第二组参数不相匹配时，确定所述第二组参数存在误差，对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
可选的，在一种具体的实施方式中，如果所述至少一个模块包括第一模块，则获取单元501，还用于获取所述报文从达到所述第一模块的输入接口的时间点与达到输出接口的时间点之间的时间差。
进一步地，获取单元501，还用于通过复用EDA验证监控器，或者采用EDA技术提供的接口信号监测功能获取所述第一组参数。
可选的，在另一种具体的实施方式中，处理单元502，还用于在获取单元501获取所述第一组参数之前，判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，如果是，则获取所述第一组参数。
进一步地，当判断所述报文的报文起始部分(sop)所携带的指示标记为“1”时，确定该报文中传输的数据为真实数据。
可选的，在又一种具体的实施方式中，当所述报文为第一报文集，所述第一报文集中包括N个不同长度的报文，N≥2，且N为正整数，获取单元501，还用于获取所述N个报文在同一模块传输的时延参数的加权平均值。
可选的，在又一种具体的实施方式中，所述存储单元用于存储CLAT表，所述CLAT表中包括所述至少一个模块中的每个模块传输的时延参数。获取单元501，还用于从所述存储单元存储的所述CLAT中获取所述第一组参数。
可选的，所述CLAT表中还存储所述第二组参数，以及第一组参数与第二组参数比较后的比较结果。
可选的，在又一种具体的实施方式中，获取单元501，还用于基于ESL建模和ESL仿真技术获取所述报文在所述ESL模型中的至少一个模块传输的时延参数。
本装置结合EDA验证技术和ESL模型技术，快速地将RTL电路参数标记到ESL模型中，保证芯片开发过程中可随时获取精准时延数据，提升了获取芯片传输延时参数的效率。
另外，在一种硬件实现中，本申请实施例还提供了一种检测装置，该检测装置可用是一种芯片电路，或者还可以是集成在第三方设备的功能模块，比如APK包。此外，所述检测装置还可以包含前述的时延参数的校验装置。
图6示出了该检测装置的结构示意图，包括：至少一个处理器110和接口电路120，其中，至少一个处理器110和接口电路120通过总线耦合。此外，可选的，还可以包括存储器130、至少一个管脚等其他模块或单元。
其中，至少一个处理器110为芯片电路的控制中心，可用于完成前述实施例中的时延参数的校验方法等。
进一步地，至少一个处理器110可以由集成电路(Integrated Circuit，IC)组成，例如可以由单颗封装的IC所组成，也可以由连接多颗相同功能或不同功能的封装IC而组成。举例来说，处理器可以包括中央处理器(central processing unit，CPU)或数字信号处理器(digital signal processor，DSP)等。
此外，至少一个处理器110还可以包括硬件芯片，所述该硬件芯片可以是一种逻辑电路，专用集成电路(application specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。
存储器130用于存储和交换各类数据或信号，包括第一报文、第一报文集、第一组参数、第二组参数或CLAT表等。此外，存储器130中可以存储有计算机程序或代码。
具体地，存储器130可以包括易失性存储器(volatile memory)，例如随机存取内存(random access memory，RAM)；还可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard sisk drive，HDD)或固态硬盘(Solid-State Drive，SSD)，存储器130还可以包括上述种类的存储器的组合。
可选的，存储器130既可以作为存储介质，集成在至少一个处理器110中，还可以被配置在处理器之外，本实施例对此不予限制。
其中，所述存储器130用于存储第一组参数、第二组参数、接收的报文，以及CLAT表等信息。
接口电路120，包括至少一个输入接口和输出接口，可使用任何收发器一类的装置。比如所述接口电路120与RTL电路芯片相连接，用于获取所述RTL电路时延参数，即前述第一组参数。此外，接口电路120还用于获取ESL模型统计的至少一个模块的时延参数，即前述第二组参数。
应理解，接口电路120还用于与内部或外部其它设备通信，如以太网，WLAN等。
此外，上述检测装置作为第三方设备，比如服务器、控制器时，所述第三方设备中还可以包括移动通信模块、无线通信模块等。所述移动通信模块包括：具有无线通信功能的比如2G/3G/4G/5G通信的模块。此外，还可以包括滤波器、开关、功率放大器、低噪声放大器(low noise amplifier，LNA)等。此外，所述无线通信模块可以提供应用在服务器或控制器上的包括WLAN，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)等无线通信的解决方案。
应理解，上述检测装置中还可以包括其他更多或更少的部件，本申请实施例示意的结构并不构成对其结构的具体限定。并且图6所示的部件可以以硬件，软件、固件或者其任意组合的方式来实现。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。例如，在前述 图5所示的装置中，获取单元501和处理单元502的功能可以通过至少一个处理器110和接口电路120来实现，所述存储单元的功能可以由存储器130实现。
此外，本申请实施例还提供了一种无线通信系统，如图1所示，该系统包括至少一个服务器、交换机、UE和eNB。其中，该系统中的各个设备的结构可以与图6所示结构相同，也可以不相同。
当采用图6所示的结构时，至少一个处理器110利用接口电路120获取所述第一组参数和所述第二参数，所述第一组参数包括报文在RTL电路的至少一个模块中传输的时延参数，所述第二组参数包括所述报文在ESL模型传输时统计的所述至少一个模块的时延参数。另外，至少一个处理器110还用于判断所述第一组参数与所述第二组参数是否相匹配，如果否，则确定所述第二组参数存在误差，并对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
本系统中提供的系统，当检测出采样的ESL模型时延参数存在误差时，对该ESL模型时延参数进行校准，并利用校准后参数进行报文时延评估，从而避免了开发人员采样RTL时延参数带来的误差，本方法提高了利用ESL模型评估报文传输时延的精确度，同时满足高精度、低时延的要求，保证芯片项目开发的竞争力。
另外，本申请还提供一种计算机程序产品，所述计算机程序产品包括一个或多个计算机程序指令。在计算机加载和执行所述计算机程序指令时，全部或部分地产生按照上述各个实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络或者其他可编程装置。
所述计算机程序指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网络节点、计算机、服务器或数据中心通过有线或无线方式向另一个节点进行传输。
此外，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
以上所述的本申请实施方式并不构成对本申请保护范围的限定。

Claims (16)

  1. 一种时延参数的检验方法，其特征在于，所述方法包括：
    获取第一组参数，所述第一组参数包括报文在暂存器转移层次RTL电路的至少一个模块中传输的时延参数；
    获取第二组参数，所述第二组参数包括所述报文在电子系统级设计ESL模型传输时统计的所述至少一个模块的时延参数；
    检验如果所述第一组参数与所述第二组参数不相匹配，则确定所述第二组参数存在误差，对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
  2. 根据权利要求1所述的方法，其特征在于，所述至少一个模块包括第一模块，所述获取第一组参数，包括：
    获取所述报文从达到所述第一模块的输入接口的时间点与到达输出接口的时间点之间的时间差。
  3. 根据权利要求1或2所述的方法，其特征在于，所述获取第一组参数之前，还包括：
    判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，如果是，则获取所述第一组参数。
  4. 根据权利要求3所述的方法，其特征在于，判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，包括：
    判断所述报文的报文起始部分所携带的指示标记是否为“1”。
  5. 根据权利要求1-4任意一项所述的方法，其特征在于，当所述报文为第一报文集，所述第一报文集中包括N个不同长度的报文，N≥2，且N为正整数，则所述获取第一组参数，包括：
    获取所述N个报文在同一模块传输的时延参数的加权平均值。
  6. 根据权利要求1-5任意一项所述的方法，其特征在于，所述获取第一组参数，包括：
    从芯片延时精准度验证表CLAT中获取所述第一组参数，所述CLAT表中包括所述至少一个模块中的每个模块传输的时延参数。
  7. 根据权利要求1-6任意一项所述的方法，其特征在于，所述获取第二组参数，包括：
    基于ESL建模和ESL仿真技术获取所述报文在所述ESL模型中的至少一个模块传输的时延参数。
  8. 一种时延参数的检验装置，其特征在于，所述装置包括：
    获取单元，用于获取第一组参数和第二组参数，所述第一组参数包括报文在暂存器转移层次RTL电路的至少一个模块中传输的时延参数，所述第二组参数包括所述报文在电子系统级设计ESL模型传输时统计的所述至少一个模块的时延参数；
    处理单元，用于检验在所述第一组参数与所述第二组参数不相匹配时，确定所述第二组参数存在误差，对所述第二组参数进行校准得到第三组参数，以及利用所述第三组参数进行报文传输时延的评估工作。
  9. 根据权利要求8所述的装置，其特征在于，所述至少一个模块包括第一模块，
    所述获取单元，还用于获取所述报文从达到所述第一模块的输入接口的时间点与达到输出接口的时间点之间的时间差。
  10. 根据权利要求8或9所述的装置，其特征在于，
    所述处理单元，还用于在所述获取单元获取所述第一组参数之前，判断所述报文在所述RTL电路芯片内传输的数据是否是真实数据，如果是，则获取所述第一组参数。
  11. 根据权利要求10所述的装置，其特征在于，
    所述处理单元，还用于当所述报文的报文起始部分所携带的指示标记为“1”时，确定所述数据为真实数据。
  12. 根据权利要求8-11任意一项所述的装置，其特征在于，当所述报文为第一报文集，所述第一报文集中包括N个不同长度的报文，N≥2，且N为正整数，
    所述获取单元，还用于获取所述N个报文在同一模块传输的时延参数的加权平均值。
  13. 根据权利要求8-12任意一项所述的装置，其特征在于，还包括存储单元，
    所述存储单元，用于存储芯片延时精准度验证表CLAT，所述CLAT表中包括所述至少一个模块中的每个模块传输的时延参数；
    所述获取单元，还用于从所述存储单元的所述CLAT中获取所述第一组参数。
  14. 根据权利要求8-13任意一项所述的装置，其特征在于，
    所述获取单元，还用于基于ESL建模和ESL仿真技术获取所述报文在所述ESL模型中的至少一个模块传输的时延参数。
  15. 一种检测装置，其特征在于，包括：至少一个处理器和接口电路，
    所述接口电路，用于为所述至少一个处理器提供指令和/或数据；
    所述至少一个处理器，用于执行所述指令，以实现如权利要求1至7中任一项所述的方法。
  16. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序指令，当所述计算机程序指令被运行时，实现如权利要求1至7中任一项所述的方法。
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