WO2022172622A1

WO2022172622A1 - Light detection device and light detection system

Info

Publication number: WO2022172622A1
Application number: PCT/JP2021/047983
Authority: WO
Inventors: 俊輔酒詰
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-02-15
Filing date: 2021-12-23
Publication date: 2022-08-18
Also published as: JP2022124396A

Abstract

This light detection device comprises: a clock signal generation unit that comprises a reference oscillation circuit for carrying out an oscillation operation and that generates a clock signal having a prescribed frequency by carrying out a phase synchronization operation; a first timing detection unit that comprises a first light reception unit for generating a first pulse signal corresponding to a light reception result of a first light reception element, a first counter for generating a first code by carrying out a count operation on the basis of the clock signal, a first oscillation circuit for generating a first multiphase clock signal by carrying out an oscillation operation on the basis of the first pulse signal, and a first latch unit for, on the basis of the first pulse signal, latching the first code and a second code corresponding to the first multiphase clock signal, and that detects a first light reception timing at the first light reception unit; and a correction processing unit that carries out first correction processing according to the frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.

Description

Photodetector and photodetection system

The present disclosure relates to a photodetection device and a photodetection system that detect light.

The TOF (Time Of Flight) method is often used when measuring the distance to the measurement target. In this TOF method, light is emitted and reflected light reflected by the object to be measured is detected. In the TOF method, the distance to the measurement object is measured by measuring the time difference between the timing at which the light is emitted and the timing at which the reflected light is detected. For example, Patent Literature 1 discloses a sensor that uses a delay line to improve the accuracy of distance measurement.

JP 2019-49430 A

In the photodetector, it is desired to improve the detection accuracy, and further improvement of the detection accuracy is expected.

It is desirable to provide a photodetector and a photodetection system that can improve detection accuracy.

A photodetector according to an embodiment of the present disclosure includes a clock signal generator, a first light receiver, a first timing detector, and a correction processor. The clock signal generation unit has a reference oscillation circuit that performs an oscillation operation, and is configured to generate a clock signal with a predetermined frequency by performing a phase synchronization operation. The first light receiving section has a first light receiving element and is configured to generate a first pulse signal according to the light receiving result of the first light receiving element. The first timing detection unit includes a first counter that generates a first code by performing a counting operation based on a clock signal, and a first multiplicity by performing an oscillation operation based on a first pulse signal. A first oscillation circuit for generating a phase clock signal, and a first latch for latching a first code based on the first pulse signal and a second code according to the first multiphase clock signal. and configured to detect the first light receiving timing in the first light receiving section. The correction processing unit is configured to perform a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.

A photodetection system according to an embodiment of the present disclosure includes a light emitter and a photodetector. The light emitter is configured to emit light. The light detection section is configured to detect light reflected by the detection target, among the light emitted from the light emission section. The photodetector includes a clock signal generator, a first light receiver, a first timing detector, and a correction processor. The clock signal generation unit has a reference oscillation circuit that performs an oscillation operation, and is configured to generate a clock signal with a predetermined frequency by performing a phase synchronization operation. The first light receiving section has a first light receiving element and is configured to generate a first pulse signal according to the light receiving result of the first light receiving element. The first timing detection unit includes a first counter that generates a first code by performing a counting operation based on a clock signal, and a first multiplicity by performing an oscillation operation based on a first pulse signal. A first oscillation circuit for generating a phase clock signal, and a first latch for latching a first code based on the first pulse signal and a second code according to the first multiphase clock signal. and configured to detect the first light receiving timing in the first light receiving section. The correction processing unit is configured to perform a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.

1 is a block diagram showing a configuration example of a photodetection system according to an embodiment of the present disclosure; FIG. 2 is a block diagram showing a configuration example of a clock signal generation unit shown in FIG. 1; FIG. 3 is a circuit diagram showing a configuration example of an oscillation circuit shown in FIG. 2; FIG. 2 is a circuit diagram showing a configuration example of a light receiving unit shown in FIG. 1; FIG. 3 is a circuit diagram showing another configuration example of the light receiving unit shown in FIG. 1; FIG. 3 is a block diagram showing a configuration example of a timing detection unit according to the first embodiment; FIG. 6 is a circuit diagram showing a configuration example of an oscillation circuit shown in FIG. 5; FIG. 6 is a timing waveform diagram showing an operation example of the frequency divider shown in FIG. 5; FIG. FIG. 2 is an explanatory diagram showing a mounting example of a photodetector shown in FIG. 1; FIG. 3 is an explanatory diagram showing another implementation example of the photodetector shown in FIG. 1; FIG. 2 is an explanatory diagram showing a mounting example of a light receiving unit shown in FIG. 1; 6 is an explanatory diagram showing one operation state of the timing detection unit shown in FIG. 5; FIG. 6 is a timing waveform diagram showing an operation example of the timing detection unit shown in FIG. 5; FIG. 6 is an explanatory diagram showing one characteristic example of the timing detection unit shown in FIG. 5; FIG. 6 is an explanatory diagram showing another characteristic example of the timing detection unit shown in FIG. 5; FIG. 6 is an explanatory diagram showing another characteristic example of the timing detection unit shown in FIG. 5; FIG. 6 is a flow chart showing an operation example of a timing detection unit and a correction processing unit shown in FIG. 5; 6 is an explanatory diagram showing another operating state of the timing detection unit shown in FIG. 5; FIG. 6 is a timing waveform diagram showing another operation example of the timing detection section shown in FIG. 5; FIG. 9 is a flow chart showing an operation example of a timing detection unit and a correction processing unit according to a modification of the first embodiment; FIG. 11 is a block diagram showing a configuration example of a timing detection unit according to a second embodiment; FIG. 20 is a circuit diagram showing a configuration example of the oscillation circuit shown in FIG. 19; FIG. FIG. 20 is a flow chart showing an operation example of a timing detection unit and a correction processing unit shown in FIG. 19; FIG. FIG. 20 is another flowchart showing an operation example of the timing detection unit and the correction processing unit shown in FIG. 19; FIG. FIG. 11 is a circuit diagram showing a configuration example of an oscillator circuit according to a modification of the second embodiment; FIG. 11 is a flow chart showing an operation example of a timing detection unit and a correction processing unit according to a modification of the second embodiment; FIG. FIG. 11 is another flowchart showing an operation example of the timing detection section and the correction processing section according to the modification of the second embodiment; FIG. FIG. 11 is a block diagram showing a configuration example of a multiphase clock signal generator according to a third embodiment; 25 is a timing waveform diagram showing an operation example of the timing detection unit shown in FIG. 24; FIG. FIG. 12 is a block diagram showing a configuration example of a clock signal generator according to a modification of the third embodiment; FIG. FIG. 11 is a block diagram showing a configuration example of a timing detection unit according to a fourth embodiment; FIG. FIG. 28 is an explanatory diagram showing one operation state of the timing detection unit shown in FIG. 27; FIG. 30 is a timing waveform diagram showing an operation example of the timing detection unit shown in FIG. 28; 28 is an explanatory diagram showing another operating state of the timing detection unit shown in FIG. 27; FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Application example

<1. First Embodiment>
[Configuration example]
FIG. 1 shows a configuration example of a photodetection system (photodetection system 1) according to an embodiment. The light detection system 1 is a ToF sensor, and is configured to emit light and detect reflected light reflected by the object to be measured OBJ. Note that a photodetector according to an embodiment of the present disclosure is embodied by the present embodiment, and thus will be described together. The photodetection system 1 includes a photodetector 10 , a light emitter 8 and an optical member 9 .

The light detection section 10 is configured to drive the light emission section 8 to irradiate the light emission section 8 with light and to detect reflected light reflected by the measurement object OBJ.

The light emitting section 8 is configured to emit a light pulse L0 toward the object to be measured OBJ by being driven by the light detecting section 10 . The light emitting unit 8 has a light source that emits infrared light, for example. This light source is configured using, for example, a laser light source or an LED (Light Emitting Diode).

The optical member 9 is configured to guide the light pulse L0 emitted from the light emitting section 8 to the object to be measured OBJ and to guide part of the light (light pulse L0R) to the light detection section 10. A half mirror, for example, can be used as the optical member 9 .

The light pulse L0 emitted from the light detection system 1 in this way is reflected by the measurement object OBJ. Then, the light pulse (reflected light pulse L1) reflected by the object to be measured OBJ enters the photodetection section 10 of the photodetection system 1 . The photodetector 10 detects this reflected light pulse L1.

The light detection unit 10 includes a clock signal generation unit 20, a control signal generation unit 12, a drive unit 13, a pixel array 14, a TDC (Time to Digital Converter) unit 30, a correction processing unit 16, and a histogram generation unit. 17 , a distance calculator 18 and a transmitter 19 .

The clock signal generator 20 is configured to generate the clock signal CLK based on the reference clock signal REFCLK.

FIG. 2 shows a configuration example of the clock signal generation unit 20. As shown in FIG. The clock signal generator 20 has a phase comparator circuit 21 , a charge pump 22 , a loop filter 23 , an oscillator circuit 24 and a frequency divider circuit 25 .

The phase comparison circuit 21 is configured to compare the phase of the reference clock signal REFCLK and the phase of the clock signal DIVCLK supplied from the frequency dividing circuit 25 . The phase comparison circuit 21 is configured using, for example, a so-called phase frequency comparison circuit (PFD: Phase Frequency Detector).

The charge pump 22 is configured to flow current into the loop filter 23 or sink current from the loop filter 23 based on the comparison result in the phase comparator circuit 21 . Loop filter 23 is configured to generate a control voltage Vctrl for oscillator circuit 24 .

The oscillation circuit 24 is a voltage-controlled oscillator, and is configured to generate a clock signal CLK having a frequency corresponding to the control voltage Vctrl by performing an oscillation operation.

FIG. 3 shows a configuration example of the oscillation circuit 24. As shown in FIG. The oscillation circuit 24 is a ring oscillator and has a plurality of inverters IV (four inverters IV1 to IV4 in this example) and a transistor MN1. The transistor MN1 is an N-type MOS (Metal Oxide Semiconductor) transistor. Although four inverters IV1 to IV4 are provided in this example, the present invention is not limited to this, and for example, five or more inverters may be provided.

The inverters IV1 to IV4 are connected in this order. Specifically, the input terminal of the inverter IV1 is connected to the output terminal of the inverter IV4, and the output terminal is connected to the input terminal of the inverter IV2. The input terminal of inverter IV2 is connected to the output terminal of inverter IV1, and the output terminal is connected to the input terminal of inverter IV3. The input terminal of inverter IV3 is connected to the output terminal of inverter IV2, and the output terminal is connected to the input terminal of inverter IV4. The input terminal of inverter IV4 is connected to the output terminal of inverter IV3, and the output terminal is connected to the input terminal of IV1. Inverter IV4 outputs clock signal CLK. The ground terminals of inverters IV1-IV4 are connected to the drain of transistor MN1.

The control voltage Vctrl is supplied to the gate of the transistor MN1, the drain is connected to the ground terminals of the inverters IV1 to IV4, and the source is grounded.

With this configuration, the oscillation circuit 24 generates the clock signal CLK having a frequency corresponding to the delay times of the inverters IV1 to IV4. The delay times of the inverters IV1-IV4 change according to the control voltage Vctrl. For example, when the control voltage Vctrl is high, the current flowing through the transistor MN1 increases, so the current flowing through the inverters IV1-IV4 increases and the delay time of the inverters IV1-IV4 decreases. Therefore, the frequency of the clock signal CLK is increased. Also, when the control voltage Vctrl is low, the current flowing through the transistor MN1 decreases, so the current flowing through the inverters IV1 to IV4 decreases, and the delay time of the inverters IV1 to IV4 increases. Therefore, the frequency of clock signal CLK is lowered. Thus, the oscillation circuit 24 generates the clock signal CLK having a frequency corresponding to the control voltage Vctrl.

The frequency dividing circuit 25 (FIG. 2) is configured to generate a clock signal DIVCLK having a frequency that is 1/N times the frequency of the clock signal CLK by performing a frequency dividing operation based on the clock signal CLK.

The phase comparator circuit 21, charge pump 22, loop filter 23, oscillator circuit 24, and frequency divider circuit 25 constitute a phase locked loop. The clock signal DIVCLK is synchronized with the reference clock signal REFCLK by the phase synchronization circuit performing the phase synchronization operation. As a result, the phase synchronization circuit generates a clock signal CLK having a frequency that is N times the frequency of the reference clock signal REFCLK.

As shown in FIG. 1, the clock signal generator 20 supplies the clock signal CLK thus generated to the control signal generator 12, the driver 13, and the TDC unit 30. Also, the clock signal generator 20 supplies the control voltage Vctrl to the TDC section 30 .

The control signal generator 12 ( FIG. 1 ) is configured to generate various control signals used in the photodetector 10 . For example, the control signal generation unit 12 generates a signal STR that instructs the light emission operation of the light emission unit 8 . The photodetector 10 has two operation modes M (operation modes MA and MB). The operation mode MA is a mode in which the photodetection system 1 performs ranging operation. The operation mode MB is a mode in which the photodetection system 1 performs calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34 (described later) of the TDC section 30, as will be described later. The control signal generator 12 generates various control signals according to these operation modes M. FIG. The control signal generator 12 operates in synchronization with the clock signal CLK.

The driving unit 13 is configured to drive the light emitting unit 8 so that the light emitting unit 8 emits the light pulse L0 based on the signal STR. The driving section 13 operates in synchronization with the clock signal CLK.

The pixel array 14 has a plurality of light receiving portions P arranged in a matrix. The light receiving unit P is configured to detect light and generate a pulse signal PLS having pulses corresponding to the detected light. The plurality of light receiving portions P includes light receiving portions PR. This light receiving portion PR detects the light pulse L0R guided by the optical member 9 . The light-receiving portions P other than the light-receiving portion PR among the plurality of light-receiving portions P detect the reflected light pulse L1 reflected by the object to be measured OBJ.

4A shows a configuration example of the light receiving section P. FIG. The light receiving section P has a plurality (four in this example) of light receiving circuits DET1 and an OR circuit OR1.

The light receiving circuit DET1 has a photodiode PD, a resistive element R1, and an inverter IVP.

The photodiode PD is a photoelectric conversion element that converts light into charge. The photodiode PD has an anode supplied with the power supply voltage VSS and a cathode connected to the node N1. A single photon avalanche diode (SPAD), for example, can be used as the photodiode PD.

A power supply voltage VDD is supplied to one end of the resistance element R1, and the other end is connected to the node N1.

Inverter IVP outputs a low level when the voltage at node N1 is higher than the logic threshold, and outputs a high level when the voltage at node N1 is lower than the logic threshold, thereby generating pulse signal PLS1. configured as

With this configuration, in the light receiving circuit DET1, when the photodiode PD detects light, avalanche amplification occurs and the voltage at the node N1 drops. When the voltage at node N1 becomes lower than the logic threshold of inverter IVP, pulse signal PLS1 changes from low level to high level. Thereafter, a current flows through the node N1 through the resistance element R1, thereby increasing the voltage of the node N1. Then, when the voltage at the node N1 becomes higher than the logic threshold of the inverter IVP, the pulse signal PLS1 changes from high level to low level. In this manner, the light receiving circuit DET1 generates a pulse signal PLS1 having pulses corresponding to the detected light.

The logical sum circuit OR1 is configured to generate the pulse signal PLS by calculating the logical sum based on the pulse signals PLS1 output from the four light receiving circuits DET1.

Although four light receiving circuits DET1 are provided in this example, the present invention is not limited to this. Three or less light receiving circuits DET1 may be provided, or five or more light receiving circuits DET1 may be provided. Thus, in the light receiving portion P, the light receiving sensitivity of the light receiving portion P can be increased by providing the plurality of light receiving pixels DET1.

4B shows another configuration example of the light receiving section P. FIG. In this example, the light receiving section P has a plurality of (four in this example) light receiving circuits DET2. The light receiving circuit DET2 has a photodiode PD, a transistor MP1, an inverter IVP, and a control circuit CKT1.

The transistor MP1 is a P-type MOS transistor having a gate connected to the output terminal of the control circuit CKT1, a source supplied with the power supply voltage VDD, and a drain connected to the node N1.

The control circuit CKT1 is configured to control the operation of the transistor MP1 based on the pulse signal PLS1. Specifically, the control circuit CKT1 sets the voltage of the gate of the transistor MP1 to low level after the pulse signal PLS1 changes from low level to high level, and sets the voltage of the transistor MP1 to low level after the pulse signal PLS1 changes from high level to low level. The gate voltage is set to a high level.

With this configuration, in the photodetector circuit DET2, the voltage at the node N1 drops when the photodiode PD detects light. Then, when the voltage at the node N1 becomes lower than the logic threshold of the inverter IVP, the pulse signal PLS1 changes from low level to high level. The control circuit CKT1 makes the voltage of the gate of the transistor MP1 low after this change in the pulse signal PLS1. As a result, the transistor MP1 is turned on, and current flows through the transistor MP1 to the node N1, thereby increasing the voltage of the node N1. Then, when the voltage at the node N1 becomes higher than the logic threshold of the inverter IVP, the pulse signal PLS1 changes from high level to low level. The control circuit CKT1 makes the voltage of the gate of the transistor MP1 high after this change in the pulse signal PLS1. This turns off the transistor MP1. In this manner, the light receiving circuit DET2 generates the pulse signal PLS1 having pulses corresponding to the detected light.

In this example, the OR circuit OR1 is provided, but the present invention is not limited to this. For example, a selector for sequentially selecting one of the pulse signals PLS1 generated by the four light receiving circuits DET1 is provided. may

The TDC section 30 (FIG. 1) is configured to detect light reception timing in each of the plurality of light receiving sections P based on the pulse signal PLS supplied from each of the plurality of light receiving sections P in the pixel array 14 . The TDC section 30 has a plurality of timing detection sections 31 . The multiple timing detection units 31 are provided corresponding to the multiple light receiving units P in the pixel array 14 .

FIG. 5 shows a configuration example of the timing detection section 31 in the TDC section 30. As shown in FIG. In addition to the TDC section 30, FIG. 5 also depicts a clock signal generation section 20, a control signal generation section 12, a drive section 13, a correction processing section 16, and a histogram generation section 17. FIG. In FIG. 5, thick lines indicate wirings that transmit multi-bit signals.

Each of the plurality of timing detection units 31 is configured to detect light reception timing in the corresponding light receiving unit P based on the pulse signal PLS generated by the corresponding light receiving unit P. The timing detection unit 31 includes an AND circuit 32, a selector 33, an oscillation circuit 34, a flip-flop (F/F) 35, an inverter 36, a selector 37, an inverter 38, a selector 41, a counter 42, and , a flip-flop section (F/F section) 43 , an output section 44 , a frequency dividing section 45 , a flip-flop section 46 and a correction section 47 .

The logical product circuit 32 is configured to obtain the logical product of the pulse signal PLS and the output signal of the inverter 38 .

The selector 33 is configured to select one of the signal STR and the output signal of the AND circuit 32 based on the control signal from the control signal generator 12 and output the selected signal. Specifically, based on the control signal from the control signal generator 12, the selector 33 selects the output signal of the AND circuit 32 in the operation mode MA, and selects the signal STR in the operation mode MB. there is

The oscillation circuit 34 is a voltage-controlled oscillation circuit, and similarly to the oscillation circuit 24 of the clock signal generation unit 20, performs an oscillation operation to generate a multiphase clock signal CLKM having a frequency corresponding to the control voltage Vctrl. configured to In this example, multiphase clock signal CLKM includes four clock signals CLK0, CLK90, CLK180 and CLK270. Further, the oscillation circuit 34 can perform an oscillation operation or stop the oscillation operation based on the signal EN.

FIG. 6 shows a configuration example of the oscillation circuit 34. As shown in FIG. The oscillator circuit 34 has the same configuration as the oscillator circuit 24 of the clock signal generator 20 (FIG. 3). Specifically, the oscillation circuit 34 has four inverters IV11 to IV14 and a transistor MN11. Inverters IV11-IV14 correspond to inverters IV1-IV4 in oscillation circuit 24, and transistor MN11 corresponds to transistor MN1 in oscillation circuit . Inverters IV11-IV14 are connected in this order. Inverter IV11 outputs clock signal CLK0, inverter IV14 outputs clock signal CLK90, inverter IV13 outputs clock signal CLK180, and inverter IV12 outputs clock signal CLK270. The inverters IV11 to IV14 can operate or stop operating based on the signal EN. Specifically, the inverters IV11 to IV14 operate when the signal EN is at high level, and stop operating when the signal EN is at low level. As a result, the oscillator circuit 34 oscillates when the signal EN is at high level, and stops oscillating when the signal EN is at low level.

Thus, the configuration of the oscillation circuit 34 (FIG. 6) is similar to the configuration of the oscillation circuit 24 (FIG. 3). Also, as shown in FIG. 5, the

oscillation circuits

34 and 24 perform oscillation operations based on the same control voltage Vctrl. Therefore, the oscillation frequency of the oscillation circuit 34 is expected to be substantially the same as the oscillation frequency of the oscillation circuit 24 . In other words, the frequency of the multiphase clock signal CLKM generated by the oscillation circuit 34 is expected to be the same as the frequency of the clock signal CLK generated by the oscillation circuit 24 .

The flip-flop 35 (FIG. 5) is configured to latch the signal EN based on the rising edge of the clock signal CLK.

The inverter 36 is configured to invert the signal STR and output the inverted signal.

The selector 37 is configured to select one of the output signal of the flip-flop 35 and the output signal of the inverter 36 based on the control signal from the control signal generator 12 and output the selected signal as the signal STP. be done. Specifically, based on the control signal from the control signal generator 12, the selector 37 selects the output signal of the flip-flop 35 in the operation mode MA, and selects the output signal of the inverter 36 in the operation mode MB. It's becoming

Inverter 38 is configured to invert signal STP and output the inverted signal.
The inverter 38 includes a delay circuit, and outputs a signal after a predetermined delay time has elapsed from the transition timing of the signal STP.

The selector 41 selects one of the clock signal CLK generated by the oscillator circuit 24 and the clock signal CLK0 generated by the oscillator circuit 34 based on the control signal from the control signal generator 12, and outputs the selected signal. configured to Specifically, based on the control signal from the control signal generator 12, the selector 41 selects the clock signal CLK in the operation mode MA, and selects the clock signal CLK0 in the operation mode MB.

The counter 42 is configured to generate a count code CDC1 by performing a counting operation based on the rising edge of the output signal of the selector 41. Counter 42 starts a counting operation based on signal STR. The counter 42 outputs a multi-bit count code CDC1.

The flip-flop unit 43 is configured to latch the count code CDC1 supplied from the counter 42 based on the rising edge of the signal STP. The flip-flop section 43 then supplies the count code CDC indicating the latch result to the output section 44 and the histogram generation section 17 .

The output unit 44 is configured to supply the count code CDC to the correction processing unit 16 via the bus wiring BUS1 based on the control signal from the control signal generation unit 12. Each of the output units 44 in the plurality of timing detection units 31 sequentially supplies the count code CDC to the correction processing unit 16 via the bus wiring BUS1 based on the control signal from the control signal generation unit 12. there is

The frequency dividing unit 45 is configured to generate the count code CDF1 by frequency-dividing each of the clock signals CLK0, CLK90, CLK180, and CLK270 included in the multiphase clock signal CLKM by two.

FIG. 7 shows an operation example of the frequency divider 45. (A) to (D) show the waveforms of the clock signals CLK0, CLK270, CLK180 and CLK90, and (E) to (H) show the waveforms of the clock signals CLK0, CLK270, CLK180 and CLK90. Waveforms of signals CDF0, CDF45, CDF90 and CDF135 representing code CDF1 are shown.

The frequency dividing unit 45 performs a toggle operation at the rising edge of the clock signal CLK0 to generate the signal CDF0 (FIGS. 7A and 7E), and performs a toggle operation at the rising edge of the clock signal CLK270 to generate the signal CDF0. CDF135 is generated (FIGS. 7(B) and (H)), and a signal CDF90 is generated by performing a toggle operation at the rising edge of the clock signal CLK180 (FIGS. 7(C) and (G)). A signal CDF45 is generated by performing a toggle operation at the rising edge (FIGS. 7(D) and (F)).

As a result, the count code CDF1 (signals CDF, CDF45, CDF90, CDF135) is "1000" during the period from timing t1 to t2, "1100" for the period from timing t2 to t3, and "1100" for the period from timing t3 to t4. is "1110" in the period from timing t4 to t5, "1111" in the period from timing t5 to t6, "0111" in the period from timing t5 to t6, "0011" in the period from timing t6 to t7, and timing t7 to t8. , and is "0000" during the period from timing t8 to t9. In this way, the count code CDF1 ((E) to (H) in FIG. 7) is changed four times in a period corresponding to one cycle of the multiphase clock signal CLKM ((A) to (D) in FIG. 7). It has become.

The flip-flop unit 46 is configured to latch the count code CDF1 supplied from the frequency dividing unit 45 based on the rising edge of the signal STP. The flip-flop section 46 then supplies the count code CDF indicating the latch result to the correction section 47 and the histogram generation section 17 .

The correction unit 47 is configured to perform correction processing on the count code CDF and supply the corrected count code CDF to the histogram generation unit 17 . Based on the control signal from the control signal generator 12, each of the correction units 47 in the plurality of timing detectors 31 receives the correction parameter CAL1 supplied via the bus line BUS2. Then, the correction unit 47 performs correction processing on the count code CDF based on this correction parameter CAL1.

The correction processing unit 16 (FIGS. 1 and 5) is configured to perform calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34 in the operation mode M2. The correction processing section 16 has a calculation section 16A and a storage section 16B. Based on the count code CDC supplied from the timing detection unit 31 in the TDC unit 30 via the bus wiring BUS1, the calculation unit 16A performs correction according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34. It is configured to calculate a parameter CAL1. The storage unit 16B is configured to store correction parameters CAL1 for each of the plurality of timing detection units 31. FIG. The correction processing section 16 supplies the correction parameter CAL1 to the timing detection section 31 in the TDC section 30 via the bus wiring BUS2.

The histogram generation unit 17 (FIG. 1) is configured to generate a histogram of the time-of-flight Ttof of the light pulse detected by the light receiving unit P based on the light receiving timing of the light receiving unit P. Specifically, the histogram generation unit 17 calculates the flight time Ttof of the light pulse detected by the light receiving unit P based on the light receiving timing of the light receiving unit P. FIG. The light detection system 1 emits the light pulse L0 a plurality of times, so that the histogram generator 17 accumulates the data of the flight time Ttof for each of the plurality of light receiving portions P. FIG. The histogram generation unit 17 generates a histogram of the flight times Ttof for each of the plurality of light receiving units P based on the accumulated data of the flight times Ttof. Then, the histogram generator 17 identifies the flight time Ttof with the highest frequency based on the histogram of the flight times Ttof for the light receiving portion P, and determines the flight time Ttof as the flight time Ttof of the light receiving portion P. It's like

The distance calculation unit 18 is configured to generate the distance image PIC by calculating the distance value based on the data of the time-of-flight Ttof for each of the plurality of light receiving units P.

The transmission unit 19 is configured to transmit the image data of the distance image PIC.

Next, mounting of the photodetector 10 in the photodetection system 1 will be described. The photodetector 10 may be formed on one semiconductor substrate, or may be formed on a plurality of semiconductor substrates, for example.

FIG. 8 shows a mounting example of the photodetector 10 formed on one semiconductor substrate 111 . In this example, the light-receiving pixels P are arranged side by side in the region 112 of the semiconductor substrate 111 , and the timing detection section 31 is arranged side by side in the region 113 of the semiconductor substrate 111 . A clock signal generator 20 , a control signal generator 12 , a driver 13 , a correction processor 16 , a histogram generator 17 , a distance calculator 18 and a transmitter 19 are also arranged on this semiconductor substrate 111 .

9 and 10 show a mounting example of the photodetector 10 formed on two

semiconductor substrates

101 and 102 . The semiconductor substrate 101 is arranged on the light receiving surface S side of the photodetector 10 , and the semiconductor substrate 102 is arranged on the side opposite to the light receiving surface S side of the photodetector 10 .

Semiconductor substrates

101 and 102 are overlaid on each other. The wiring of the semiconductor substrate 101 and the wiring of the semiconductor substrate 102 are connected by the wiring 103 . For the wiring 103, metal bonding such as Cu--Cu bonding and bump bonding can be used. The photodetection unit U is arranged over these two

semiconductor substrates

101 and 102, for example.

As shown in FIG. 10, the light receiving portion P is arranged over two

semiconductor substrates

101 and 102 in this example. Specifically, photodiode PD is arranged on semiconductor substrate 101 , and resistor element R 1 , inverter IVP, and OR circuit OR 1 are arranged on semiconductor substrate 102 . The cathode of photodiode PD is connected via wiring 103 to the other end of resistive element R1 and the input terminal of inverter IV1. In this example, the modification is applied to the light receiving portion P shown in FIG. 4A, but the modification may be applied to the light receiving portion P shown in FIG. 4B.

As shown in FIG. 9, the four photodiodes PD in the light receiving portion P are arranged in a certain region on the semiconductor substrate 101. In FIG. The timing detection unit 31 that operates based on the pulse signal PLS generated by the light receiving unit P is arranged in a region of the semiconductor substrate 102 corresponding to the region where the four photodiodes PD are arranged. Clock signal generator 20 , control signal generator 12 , driver 13 , correction processor 16 , histogram generator 17 , distance calculator 18 , and transmitter 19 are arranged on semiconductor substrate 102 .

Here, the clock signal generator 20 corresponds to a specific example of the "clock signal generator" in the present disclosure. The oscillator circuit 24 corresponds to a specific example of the "reference oscillator circuit" in the present disclosure. The clock signal CLK corresponds to a specific example of "clock signal" in the present disclosure. The light receiving section P corresponds to a specific example of the "first light receiving section" in the present disclosure. The photodiode PD corresponds to a specific example of "first light receiving element" in the present disclosure. The pulse signal PLS corresponds to a specific example of "first pulse signal" in the present disclosure. The timing detector 31 corresponds to a specific example of "first timing detector" in the present disclosure. The counter 42 corresponds to a specific example of "first counter" in the present disclosure. The count code CDC1 corresponds to a specific example of "first code" in the present disclosure. The oscillator circuit 34 corresponds to a specific example of the "first oscillator circuit" in the present disclosure. The multiphase clock signal CLKM corresponds to a specific example of "first multiphase clock signal" in the present disclosure. The flip-

flop units

43 and 46 correspond to a specific example of the "first latch unit" in the present disclosure. The correction processing unit 16 corresponds to a specific example of "correction processing unit" in the present disclosure. The control voltage Vctrl corresponds to a specific example of "control voltage" in the present disclosure. The corrector 47 corresponds to a specific example of the "corrector" in the present disclosure. Operation mode MA corresponds to a specific example of "first operation mode" in the present disclosure. The operation mode MB corresponds to a specific example of "second operation mode" in the present disclosure. The correction parameter CAL1 corresponds to a specific example of "frequency ratio" in the present disclosure. The histogram generation unit 17 corresponds to a specific example of the "processing unit" in the present disclosure.

[Operation and action]
Next, the operation and effect of the photodetection system 1 of this embodiment will be described.

(Outline of overall operation)
First, with reference to FIG. 1, an overview of the overall operation of the photodetection system 1 will be described. The clock signal generator 20 generates the clock signal CLK based on the reference clock signal REFCLK. The control signal generation unit 12 generates a signal STR that instructs the light emission operation of the light emission unit 8 . The control signal generator 12 generates various control signals according to the operation mode M (operation modes MA and MB). The driving unit 13 drives the light emitting unit 8 so that the light emitting unit 8 emits the light pulse L0 based on the signal STR. The light emitting unit 8 emits a light pulse L0 toward the object to be measured OBJ. The optical member 9 guides the light pulse L0 emitted from the light emitting unit 8 to the object to be measured OBJ and guides part of the light (light pulse L0R) to the light detection unit 10 . Each of the plurality of light receiving portions P of the pixel array 14 detects light to generate a pulse signal PLS having pulses corresponding to the detected light. The light receiving part PR detects the light pulse L0R guided by the optical member 9 . The light-receiving portions P other than the light-receiving portion PR among the plurality of light-receiving portions P detect the reflected light pulse L1 reflected by the object to be measured OBJ. The TDC section 30 detects the light reception timing of each of the plurality of light receiving sections P based on the pulse signal PLS supplied from each of the plurality of light receiving sections P in the pixel array 14 . The correction processing unit 16 performs calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34 in the operation mode M2. The histogram generation unit 17 generates a histogram of the flight time Ttof of the light pulse detected by the light receiving unit P based on the light receiving timing of the light receiving unit P. FIG. The distance calculation unit 18 calculates a distance value based on the data of the time-of-flight Ttof for each of the plurality of light receiving units P, thereby generating the distance image PIC. The transmission unit 19 transmits the image data of the distance image PIC.

(detailed operation)
Next, detailed operation of the photodetection system 1 will be described. The photodetection system 1 has operating modes MA and MB. In operation mode MA, the photodetection system 1 performs ranging operation. In the operation mode MB, the photodetection system 1 performs calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34 . This operation will be described in detail below.

(Operation mode MA)
FIG. 11 shows an example of the operating state of the TDC section 30 in the operating mode MA. In FIG. 11, the

selectors

33, 37 and 41 are shown using switches representing their operating states.

In the operation mode MA, the selectors 33 of the plurality of timing detectors 31 select the output signal of the AND circuit 32 based on the control signal from the control signal generator 12, and use this signal as the signal EN. It is supplied to the oscillation circuit 34 and the flip-flop 35 . The selector 37 selects the output signal of the flip-flop 35 based on the control signal from the control signal generator 12, and supplies this signal to the flip-

flop units

43 and 46 and the inverter 38 as the signal STP. The selector 41 selects the clock signal CLK generated by the oscillation circuit 24 of the clock signal generator 20 based on the control signal from the control signal generator 12 and supplies the clock signal CLK to the counter 42 .

Next, among the plurality of light receiving portions P in the pixel array 14, the light receiving portion P (light receiving portion PR) that detects the light pulse L0R guided by the optical member 9 and the reflected light pulse L1 reflected by the measurement object OBJ Focusing on the light receiving portion P (light receiving portion PA) that detects , the operation of the photodetection system 1 in the operation mode MA will be described.

FIG. 12 shows an operation example of the photodetection system 1 in the operation mode MA, where (A) shows the waveform of the signal STR, (B) shows the waveform of the clock signal CLK, and (C) to ( I) shows the waveform of the signal in the timing detection section 31 (timing detection section 31R) that operates based on the pulse signal PLS (pulse signal PLSR) generated by the light receiving section PR, and (J) to (P) show the waveform of the signal in the light receiving section PA. 3 shows waveforms of signals in the timing detector 31 (timing detector 31A) that operates based on the pulse signal PLS (pulse signal PLSA) generated by .

FIG. 12(C) shows the count code CDC1 (count code CDC1R) in the timing detection section 31R, (D) shows the waveform of the pulse signal PLSR supplied to the timing detection section 31R, and (E) shows the timing detection section 31R. (F) shows the waveform of the signal STP (signal STPR) in the timing detection section 31R, and (G) shows the waveform of the signal EN (signal ENR) in the timing detection section 31R. (H) indicates the count code CDC (count code CDCR) in the timing detector 31R, and (I) indicates the count code CDF (count code CDFR) in the timing detector 31R.

12(J) shows the count code CDC1 (count code CDC1A) in the timing detection section 31A, (K) shows the waveform of the pulse signal PLSA supplied to the timing detection section 31A, and (L) shows the timing detection section 31A. (M) shows the waveform of the signal STP (signal STPA) in the timing detection section 31A, (N) shows the waveform of the signal EN (signal ENA) in the timing detection section 31A, and (N) the count code CDF1 (count code CDF1A) in the timing detection section 31A. (O) indicates the count code CDC (count code CDCA) in the timing detection section 31A, and (P) indicates the count code CDF (count code CDFA) in the timing detection section 31A.

At timing t11, the control signal generator 12 changes the signal STR from low level to high level in response to the rising edge of the clock signal CLK ((A) and (B) in FIG. 12). As a result, the counter 42 of the timing detector 31R starts a counting operation based on the rising edge of the clock signal CLK, and the count code CDC1R begins to increment (FIG. 12(C)). Similarly, the counter 42 of the timing detector 31A starts a counting operation based on the rising edge of the clock signal CLK, and the count code CDC1A starts increasing ((J) in FIG. 12).

Further, based on this change in the control signal STR, the driving section 13 drives the light emitting section 8, and the light emitting section 8 emits the light pulse L0. The optical member 9 guides the light pulse L0 emitted from the light emitting unit 8 to the object to be measured OBJ, and guides part of the light (light pulse L0R) to the light receiving unit PR of the light detection unit 10 . The light receiving part PR generates a pulse signal PLSR by detecting this light pulse L0R. As a result, at timing t12, the pulse signal PLSR changes from low level to high level ((D) in FIG. 12). After that, the timing detection section 31R corresponding to this light receiving section PR operates based on this pulse signal PLSR.

At this timing t12, the signal STPR is at low level ((F) in FIG. 12), so the output signal of the AND circuit 32 of the timing detector 31R changes from low level to high level based on this pulse signal PLSR. do. As a result, the signal ENR changes from low level to high level (FIG. 12(E)).

Based on this change in signal ENR, the oscillation circuit 34 of the timing detector 31R starts oscillating and starts generating multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK27). The frequency divider 45 generates a count code CDF1R based on this multiphase clock signal CLKM (FIG. 12(G)). This count code CDF1R changes four times while the count code CDC1R changes once. That is, by using the count code CDF1R, the light receiving timing can be detected with higher accuracy. In other words, count code CDC1R is a coarse code and count code CDF1R is a fine code. Thus, in the timing detection section 31R, the count code CDC1R (coarse code) is generated based on the clock signal CLK generated by the oscillation circuit 24 of the clock signal generation section 20, and generated by the oscillation circuit 34 of the timing detection section 31R. Count code CDF1R (fine code) is generated based on multiphase clock signal CLKM.

Next, at timing t13, the control signal generator 12 changes the signal STR from high level to low level in response to the rising edge of the clock signal CLK ((A) and (B) in FIG. 12).

Also, at this timing t13, the flip-flop 35 of the timing detection section 31R latches the signal ENR based on the rising edge of the clock signal CLK. As a result, the signal STPR changes from low level to high level at this timing t13 ((F) in FIG. 12).

Based on this change in the signal STPR, the flip-flop section 43 of the timing detection section 31R latches the count code CDC1R to generate the count code CDCR ((C), (H) in FIG. 12). In this example, the code value "0" of the count code CDC1R is latched. Based on this latch result, the count code CDCR becomes "0" at timing t15 in this example.

Similarly, based on this change in signal STPR, the flip-flop section 46 of the timing detection section 31R latches the count code CDF1R to generate the count code CDFR (FIGS. 12(G) and (I)). In this example, the code value "1111" of the count code CDF1R is latched. Based on this latch result, the count code CDFR becomes "4" at timing t15 in this example.

When the signal STPR changes from low level to high level in this manner, the output signal of the AND circuit 32 of the timing detection section 31R changes from high level to low level. As a result, at timing t14, the signal ENR changes from high level to low level ((E) in FIG. 12). As a result, the oscillation circuit 34 of the timing detector 31R stops oscillating, and updating of the count code CDF1R stops ((G) in FIG. 12).

Then, at timing t15, the flip-flop 35 of the timing detection section 31R latches the signal ENR based on the rising edge of the clock signal CLK. As a result, the signal STPR changes from high level to low level at this timing t15 ((F) in FIG. 12).

Then, in this example, at timing t16, the pulse signal PLSR changes from high level to low level (FIG. 12(D)).

After that, after a while, the light receiving part PA detects the reflected light pulse L1 reflected by the object to be measured OBJ to generate the pulse signal PLSA. As a result, at timing t22, the pulse signal PLSA changes from low level to high level ((K) in FIG. 12). After that, the timing detection section 31A corresponding to this light receiving section PA operates based on this pulse signal PLSA.

At this timing t22, the signal STPA is at low level ((M) in FIG. 12), so the output signal of the AND circuit 32 of the timing detector 31A changes from low level to high level based on this pulse signal PLSA. do. As a result, the signal ENA changes from low level to high level ((L) in FIG. 12).

Based on this change in signal ENA, the oscillation circuit 34 of the timing detector 31A starts oscillating and starts generating multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK27). The frequency divider 45 generates the count code CDF1A based on this multiphase clock signal CLKM (FIG. 12(N)). This count code CDF1A changes four times while the count code CDC1A changes once. Thus, in the timing detection section 31A, the count code CDC1A (course code) is generated based on the clock signal CLK generated by the oscillation circuit 24 of the clock signal generation section 20, and generated by the oscillation circuit 34 of the timing detection section 31A. Count code CDF1A (fine code) is generated based on multiphase clock signal CLKM.

Next, at timing t23, the flip-flop 35 of the timing detection section 31A latches the signal ENA based on the rising edge of the clock signal CLK. As a result, the signal STPA changes from low level to high level at this timing t23 ((M) in FIG. 12).

Based on this change in signal STPA, the flip-flop section 43 of the timing detection section 31A latches the count code CDC1A to generate the count code CDCA ((J) and (O) in FIG. 12). In this example, the code value "21" of the count code CDC1A is latched. Based on this latch result, the count code CDCA becomes "21" at timing t25 in this example.

Similarly, based on this change in signal STPA, the flip-flop section 46 of the timing detection section 31A latches the count code CDF1A to generate the count code CDFA ((N), (P) in FIG. 12). In this example, the code value "1110" of the count code CDF1A is latched. Based on this latch result, the count code CDFA becomes "3" at timing t25 in this example.

When the signal STPA changes from low level to high level in this manner, the output signal of the AND circuit 32 of the timing detection section 31A changes from high level to low level. As a result, at timing t24, the signal ENA changes from high level to low level ((L) in FIG. 12). As a result, the oscillation circuit 34 of the timing detector 31A stops oscillating, and the update of the count code CDF1A stops ((N) in FIG. 12).

Then, at timing t25, the flip-flop 35 of the timing detection section 31A latches the signal ENA based on the rising edge of the clock signal CLK. As a result, the signal STPA changes from high level to low level at this timing t25 ((M) in FIG. 12).

Then, in this example, at timing t26, the pulse signal PLSA changes from high level to low level ((K) in FIG. 12).

Thus, in this example, the timing detector 31R generates the count code CDCR (code value "0") and the count code CDFR (code value "4"), and the timing detector 31A generates the count code CDCA (code value "4"). code value "21") and count code CDFA (code value "3").

As shown in FIG. 12, the time between the timing t12 when the light receiving unit PR detects the pulse signal PLSR and the timing t22 when the light receiving unit PA detects the pulse signal PLSA is the time of the light pulse detected by the light receiving unit PA. Time of flight Ttof.

The TDC section 30 supplies the count codes CDCR, CDFR and the count codes CDCA, CDFA to the histogram generating section 17 . The histogram generator 17 first calculates the flight time Ttof using the following formula.
Ttof = (CDCA×W-(W-(CDFA-1)))-(CDCR×W-(W-(CDFR-1)))
= (CDCA - CDCR) x W + (CDFA - CDFR)
Here, the flight time Ttof is the time based on the count value based on the count code CDF (fine code). W is the ratio between the update period of the count code CDC1 (coarse code) and the update period of the count code CDF1 (fine code), and is "4" in the example of FIG. That is, since the count code CDF1 changes four times while the count code CDC1 changes once, W is "4". In this example, the code value of count code CDCR is "0", the code value of count code CDFR is "4", the code value of count code CDCA is "21", and the code value of count code CDFA is Since it is "3", the flight time Ttof is "83".

The light detection system 1 emits the light pulse L0 multiple times, so that the histogram generation unit 17 accumulates the data of the flight time Ttof for each of the multiple light receiving units P. The histogram generation unit 17 generates a histogram of the flight times Ttof for each of the plurality of light receiving units P based on the accumulated data of the flight times Ttof. Then, the histogram generator 17 identifies the flight time Ttof with the highest frequency based on the histogram of the flight times Ttof at the light receiving portion P, and determines the flight time Ttof as the flight time Ttof of the light receiving portion P.

Then, the distance calculation unit 18 generates the distance image PIC by calculating the distance value based on the data of the time-of-flight Ttof for each of the plurality of light receiving units P.

(Operation mode MB)
As described above, the configuration of the oscillator circuit 34 (FIG. 6) is similar to the configuration of the oscillator circuit 24 (FIG. 3). Also, as shown in FIG. 5, the

oscillation circuits

However, as shown in FIG. 5, the TDC section 30 has a plurality of timing detection sections 31, so that the plurality of oscillation circuits 34 in the plurality of timing detection sections 31 are replaced by the oscillation circuit of the clock signal generation section 20. 24 is difficult. If the position of the oscillator circuit 34 is far from the position of the oscillator circuit 24 , a difference may occur between the oscillation frequency of the oscillator circuit 34 and the oscillation frequency of the oscillator circuit 24 . That is, for example, when the oscillation circuit 34 and the oscillation circuit 24 are separated from each other, the power supply voltage supplied to the oscillation circuit 34 and the power supply voltage supplied to the oscillation circuit 24 may vary due to, for example, a power supply voltage drop in the power supply line. There may be differences between Also, if the oscillator circuit 34 and the oscillator circuit 24 are separated from each other, for example, there is a possibility that a temperature difference occurs between the temperature at the position of the oscillator circuit 34 and the temperature at the position of the oscillator circuit 24 . Further, when the oscillator circuit 34 and the oscillator circuit 24 are separated from each other, there is a possibility that the characteristics of the elements constituting the oscillator circuit 34 and the characteristics of the elements constituting the oscillator circuit 24 are different. . In such a case, a difference may occur between the oscillation frequency of the oscillation circuit 34 and the oscillation frequency of the oscillation circuit 24 .

As described above, when there is a difference between the oscillation frequency of the oscillation circuit 34 and the oscillation frequency of the oscillation circuit 24, the linearity of the conversion characteristic for converting time into the count code in the timing detection section 31 is lowered. put away.

FIG. 13 shows an example of conversion characteristics when the oscillation frequency of the oscillation circuit 34 is the same as the oscillation frequency of the oscillation circuit 24. FIG. In the timing detector 31, a count code CDC (coarse code) is generated based on the clock signal CLK generated by the oscillator circuit 24, and a count code CDF (fine code) is generated based on the multiphase clock signal CLKM generated by the oscillator circuit 34. is generated. When the oscillation frequency of oscillation circuit 34 is the same as the oscillation frequency of oscillation circuit 24, the slope of the conversion characteristic of count code CDC and the slope of the conversion characteristic of count code CDF are equal to each other, as shown in FIG. can do. As a result, the timing detection section 31 can realize the ideal conversion characteristics indicated by the dashed line.

14A shows an example of conversion characteristics when the oscillation frequency of the oscillation circuit 34 is lower than the oscillation frequency of the oscillation circuit 24. FIG. FIG. 14B shows an example of conversion characteristics when the oscillation frequency of the oscillation circuit 34 is higher than the oscillation frequency of the oscillation circuit 24. FIG.

When the oscillation frequency of oscillation circuit 34 is lower than the oscillation frequency of oscillation circuit 24, the slope of the conversion characteristic of count code CDF is smaller than the slope of the conversion characteristic of count code CDC, as shown in FIG. 14A. . When the oscillation frequency of oscillation circuit 34 is higher than the oscillation frequency of oscillation circuit 24, the slope of the conversion characteristic of count code CDF is higher than the slope of the conversion characteristic of count code CDC, as shown in FIG. 14B. growing. As a result, the conversion characteristics of the timing detection unit 31 deviate from the ideal conversion characteristics indicated by the dashed line, resulting in reduced linearity.

Therefore, the photodetection system 1 performs calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34 in the operation mode MB. Thereby, even when there is a difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 34, the conversion characteristic of the timing detection section 31 can be improved.

FIG. 15 shows an example of calibration in the photodetection system 1. FIG. In this example, the photodetection system 1 performs calibration when the power is turned on.

When the light detection system 1 is powered on, the control signal generator 12 sets the operation mode M to the operation mode MB (step S101). Specifically, the control signal generator 12 sets the operating states of the

selectors

33 , 37 , 41 of the plurality of timing detectors 31 .

FIG. 16 shows an example of the operating state of the TDC section 30 in the operating mode MB. In the operation mode MB, each selector 33 of the plurality of timing detectors 31 selects the signal STR based on the control signal from the control signal generator 12, and uses this signal as the signal EN to operate the oscillation circuit 34 and the flip-flop. 35. The selector 37 selects the output signal of the inverter 36 based on the control signal from the control signal generator 12 and supplies this signal to the flip-

flop units

43 and 46 and the inverter 38 as the signal STP. The selector 41 selects the clock signal CLK0 generated by the oscillation circuit 34 based on the control signal from the control signal generator 12 and supplies the clock signal CLK0 to the counter 42 .

Next, the photodetection system 1 performs a count operation in a plurality of timing detection units 31 to obtain a count code CDC (step S102). Focusing on one of the plurality of timing detection units 31 in the TDC unit 30, the operation of the photodetection system 1 in the operation mode MB will be described below.

FIG. 17 shows an operation example of the photodetection system 1 in the operation mode MB when the oscillation frequency of the oscillation circuit 34 of the timing detection section 31 is lower than the oscillation frequency of the oscillation circuit 24 of the clock signal generation section 20. , (A) shows the waveform of signal STR, (B) shows the waveform of clock signal CLK, (C) shows the waveform of signal EN, (D) shows the waveform of clock signal CLK0, and (E ) indicates the count code CDC1, (F) indicates the waveform of the signal STP, and (G) indicates the count code CDC.

At timing t31, the control signal generator 12 changes the signal STR from low level to high level in response to the rising edge of the clock signal CLK ((A) and (B) in FIG. 17).

The signal EN changes from low level to high level according to this change in signal STR (FIG. 17(C)). Based on this change in signal EN, oscillation circuit 34 starts oscillating and starts generating multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK270).

As a result, the counter 42 starts a counting operation based on the rising edge of the clock signal CLK0, and the count code CDC1 begins to increment (FIG. 17(E)). In this example, the oscillation frequency of the oscillation circuit 34 of the timing detection section 31 is lower than the oscillation frequency of the oscillation circuit 24 of the clock signal generation section 20, so the frequency of the clock signal CLK0 is lower than the frequency of the clock signal CLK. The counter 42 performs a count operation based on such a clock signal CLK0.

After timing t31, the control signal generator 12 counts the pulses of the clock signal CLK. At the timing t32 when the count value reaches the predetermined value CNT, the control signal generator 12 changes the signal STR from high level to low level in response to the rising edge of the clock signal CLK (FIG. 17(A), ( B)). In this example, the predetermined value CNT is set to "1024".

At timing t32, the signal EN changes from high level to low level according to this change in signal STR (FIG. 17(C)). As a result, the oscillation circuit 34 stops oscillating (FIG. 17(D)), and updating of the count code CDC1 stops (FIG. 17(E)).

In addition, the signal STP changes from low level to high level at timing t32 according to this change in signal STR ((F) in FIG. 17). Based on this change in the signal STP, the flip-flop unit 43 latches the count code CDC1 to generate the count code CDC (FIGS. 17(E) and (G)). In this example, the code value "987" of the count code CDC1 is latched. Based on this latch result, the count code CDC becomes "987" at timing t33 in this example. That is, the time length of the period from timing t31 to t32 is represented by "1024" when the clock signal CLK generated by the oscillation circuit 24 is used as a reference, and is represented by "987" when the clock signal CLK0 generated by the oscillation circuit 34 is used as a reference. expressed. In other words, the oscillation frequency of the oscillation circuit 34 is “987/1024” of the oscillation frequency of the oscillation circuit 24 .

Thus, the photodetection system 1 obtains the count code CDC in each of the multiple timing detection units 31 . Based on the control signal from the control signal generator 12, the output units 44 of the plurality of timing detectors 31 sequentially supply the count code CDC to the correction processor 16 via the bus wiring BUS1.

Next, the correction processing unit 16 calculates a correction parameter CAL1 based on the count code CDC and the predetermined value CNT, and stores this correction parameter CAL1 (step S103). Specifically, the calculation unit 16A of the correction processing unit 16 calculates the correction parameter CAL1 using the following formula.
CAL1=CNT/CDC
For example, in the example of FIG. 17, the predetermined value CNT is "1024" and the count code CDC is "987", so the correction parameter CAL1 is "1024/987". The calculation unit 16A calculates correction parameters CAL1 based on the count codes CDC supplied from the plurality of timing detection units 31, respectively. Then, the storage unit 16B stores the correction parameter CAL1 for each of the plurality of timing detection units 31. FIG.

Next, the photodetection system 1 sets the correction parameter CAL1 in the correction units 47 in the plurality of timing detection units 31 (step S104). Specifically, the correction processing unit 16 supplies the plurality of correction parameters CAL1 stored in the storage unit 16B to the correction units 47 of the plurality of timing detection units 31 via the bus wiring BUS2. Each correction unit 47 sets the correction parameter CAL1 so that the count code CDF can be corrected by multiplying the count code CDF by the correction parameter CAL1.

In this example, the correction unit 47 performs correction by multiplying the code value of the count code CDF by the value "1024/987" of the correction parameter CAL1 in the operation mode MA. That is, in this example, since the oscillation frequency of the oscillation circuit 34 is "987/1024" of the oscillation frequency of the oscillation circuit 24 of the clock signal generation unit 20, the count code CDF is also the desired value of "987/1024". "become. Therefore, the correction unit 47 multiplies the code value of the count code CDF by the value "1024/987" of the correction parameter CAL1 to correct the count code CDF. Thereby, the influence of the frequency difference between the oscillation frequency of oscillation circuit 24 and the oscillation frequency of oscillation circuit 34 on count code CDF can be reduced.

Then, the control signal generator 12 sets the operation mode M to the operation mode MA (step S105). Specifically, the control signal generator 12 sets the operating states of the

selectors

33, 37, and 41 of the plurality of timing detectors 31 as shown in FIG.

Then, the photodetection system 1 starts a distance measurement operation, for example, as shown in FIG. 12 (step S106).

This is the end of this process.

Thus, the photodetection system 1 is provided with the clock signal generation section 20, the timing detection section 31, and the correction processing section 16. The clock signal generation unit 20 has an oscillation circuit 24 that performs an oscillation operation, and generates a clock signal CLK having a predetermined frequency by performing a phase synchronization operation. The timing detection unit 31 includes a counter 42 that generates a first code (count code CDC1) by performing a count operation based on the clock signal CLK, and a multiphase clock signal by performing an oscillation operation based on the pulse signal PLS. An oscillation circuit 34 that generates CLKM, and a flip-flop that latches a first code (count code CDC1) based on pulse signal PLS and a second code (count code CDF1) corresponding to multiphase clock signal CLKM. 43 and 46, and detects the light receiving timing in the light receiving portion P. FIG. The correction processing unit 16 performs correction processing according to the frequency difference between the frequency of the clock signal CLK and the frequency of the multiphase clock signal CLKM. As a result, in the photodetection system 1, for example, when there is a difference between the frequency of the clock signal CLK and the frequency of the multiphase clock signal CLKM, the conversion characteristics of the timing detection section 31 can be enhanced. Accuracy can be improved.

Also, in the photodetection system 1, the timing detection section 31 has a correction section 47 that corrects the second code (count code CDF) latched by the flip-flop section 46. FIG. In the second operation mode (operation mode MB), the correction processing unit 16 calculates the frequency ratio (correction parameter CAL1) between the clock signal CLK and the multiphase clock signal CLKM. Then, in the first operation mode (operation mode MA), the correction unit 47 corrects the second code (count code CDF) latched by the flip-flop unit 46 using the frequency ratio (correction parameter CAL1). I made it As a result, in the photodetection system 1, for example, when there is a difference between the frequency of the clock signal CLK and the frequency of the multiphase clock signal CLKM, the conversion characteristics of the timing detection section 31 can be enhanced. Accuracy can be improved.

[effect]
As described above, the present embodiment includes the clock signal generation section, the timing detection section, and the correction processing section. The clock signal generation unit has an oscillation circuit that performs an oscillation operation, and generates a clock signal with a predetermined frequency by performing a phase synchronization operation. The timing detection unit includes a counter that generates a first code by performing a counting operation based on a clock signal, an oscillation circuit that generates a multiphase clock signal by performing an oscillation operation based on a pulse signal, and a pulse signal. , a flip-flop section for latching a first code and a second code corresponding to a multiphase clock signal is provided, and the light receiving timing of the light receiving section is detected. The correction processing unit performs correction processing according to the frequency difference between the frequencies of the clock signals and the frequencies of the multiphase clock signals. Thereby, detection accuracy can be improved.

In this embodiment, the timing detection section 31 has the correction section 47 that corrects the second code (count code CDF) latched by the flip-flop section 46 . In the second operation mode, the correction processing unit calculates the frequency ratio of the clock signal and the multiphase clock signal, and in the first operation mode, the correction unit converts the second code latched by the flip-flop unit to Correction is made using the frequency ratio. Thereby, detection accuracy can be improved.

[Modification 1]
In the above embodiment, as shown in FIG. 15, the operation mode M is set to the operation mode MB when the power of the photodetection system 1 is turned on, but the present invention is not limited to this. Alternatively, for example, as shown in FIG. 18, the operation mode M may be periodically set to the operation mode MB while the photodetection system 1 is performing the ranging operation. In this example, the control signal generator 12 checks whether a predetermined period of time has elapsed while the photodetection system 1 is performing the ranging operation (step S117). If the predetermined time has not yet passed ("N" in step S117), the process of step S117 is repeated until the predetermined time has passed. If the predetermined time has passed ("Y" in step S117), the distance measuring operation is stopped (step S118), and the process returns to step S101. In this example, the operation mode M is periodically set to the operation mode MB, but the operation mode is not limited to this, and the operation mode M can be set to the operation mode MB at any timing. As a result, for example, when the photodetection system 1 operates for a long time, or when the temperature or power supply voltage fluctuates, the conversion characteristics of the timing detection section 31 can be enhanced.

<2. Second Embodiment>
Next, a photodetection system 2 according to a second embodiment will be described. This embodiment differs from the first embodiment in the method of calibration. That is, although the count code CDF is corrected in the first embodiment, the oscillation frequency itself is adjusted in the present embodiment. The same reference numerals are assigned to substantially the same components as those of the photodetection system 1 according to the first embodiment, and description thereof will be omitted as appropriate.

The photodetection system 2 includes a photodetection section 50 in the same manner as the photodetection system 1 (FIG. 1) according to the first embodiment. The photodetection section 50 includes a TDC section 60 and a correction processing section 56 .

Similar to the TDC unit 30 according to the first embodiment, the TDC unit 60, based on the pulse signal PLS supplied from each of the plurality of light receiving units P in the pixel array 14, detects the It is configured to detect light reception timing. The TDC section 60 has a plurality of timing detection sections 61 .

FIG. 19 shows a configuration example of the timing detection section 61 in the TDC section 60. As shown in FIG. The timing detection unit 61 includes an AND circuit 32, a selector 33, an oscillation circuit 64, a flip-flop (F/F) 35, an inverter 36, a selector 37, an inverter 38, a selector 41, a counter 42 and , a flip-flop section 43 , an output section 44 , a frequency dividing section 45 and a flip-flop section 46 . That is, the timing detection section 61 is obtained by replacing the oscillation circuit 34 in the timing detection section 31 (FIG. 5) according to the above embodiment with the oscillation circuit 64 and eliminating the correction section 47 .

The oscillation circuit 64 is configured to generate a multiphase clock signal CLKM having a frequency corresponding to the control voltage Vctrl by performing an oscillation operation. Oscillating circuit 64 oscillates or stops oscillating based on signal EN. Further, the oscillation circuit 64 can adjust the oscillation frequency based on the correction parameter CAL2.

FIG. 20 shows a configuration example of the oscillation circuit 64. In FIG. The oscillation circuit 64 has a transistor MN12 and an adjustment section 65 .

The transistor MN12 is an N-type MOS transistor. Transistor MN12 includes a plurality of transistors. The drains of these transistors are connected to the ground terminals of inverters IV1-IV4, and the sources are grounded. A control voltage Vctrl or a ground voltage is selectively supplied to the respective gates of these transistors.

The adjustment unit 65 is configured to set the number of transistors that supply the control voltage Vctrl, among the plurality of transistors included in the transistor MN12, based on the correction parameter CAL2. The adjusting section 65 selectively supplies the control voltage Vctrl or the ground voltage to each gate of the plurality of transistors included in the transistor MN12.

With this configuration, in the oscillation circuit 64, for example, when the value indicated by the correction parameter CAL2 is large, the adjusting section 65 increases the number of transistors that supply the control voltage Vctrl. In this case, the current flowing through the transistor MN12 increases, so the current flowing through the inverters IV1 to IV4 increases, and the frequency of the multiphase clock signal CLKM increases. Further, for example, when the value indicated by the correction parameter CAL2 is small, the adjusting section 65 reduces the number of transistors that supply the control voltage Vctrl. In this case, since the current flowing through transistor MN12 is reduced, the current flowing through inverters IV1-IV4 is reduced, and the frequency of multiphase clock signal CLKM is lowered. Thus, the oscillation circuit 64 can adjust the oscillation frequency based on the correction parameter CAL2.

The correction processing unit 56 (FIG. 19) is configured to perform calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 64 in the operation mode M2. The correction processing section 56 has a calculation section 56A and a storage section 56B. Based on the count code CDC supplied from the timing detection section 61 in the TDC section 60 via the bus wiring BUS1, the calculation section 56A performs correction according to the frequency difference between the oscillation frequencies of the

oscillation circuits

24 and 34. It is configured to calculate a parameter CAL2. The storage unit 56B is configured to store correction parameters CAL2 for each of the plurality of timing detection units 61. FIG. The correction processing unit 56 supplies the correction parameter CAL2 to the timing detection unit 61 in the TDC unit 60 via the bus wiring BUS2.

Here, the timing detection unit 61 corresponds to a specific example of the "first timing detection unit" in the present disclosure. The oscillator circuit 64 corresponds to a specific example of the "first oscillator circuit" in the present disclosure. The correction processing unit 56 corresponds to a specific example of "correction processing unit" in the present disclosure. The adjuster 65 corresponds to a specific example of "adjuster" in the present disclosure.

The photodetection system 2 performs calibration according to the frequency difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 64 in the operation mode MB. Thereby, even if there is a difference between the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 64, the conversion characteristic of the timing detection section 61 can be improved.

FIGS. 21A and 21B represent an example of calibration in the photodetection system 2. FIG. In this example, the photodetection system 2 performs calibration when power is turned on.

When the light detection system 2 is powered on, the control signal generator 12 sets the operation mode M to the operation mode MB (step S201). Specifically, the control signal generator 12 sets the operation states of the

selectors

33 , 37 and 41 of the plurality of timing detectors 61 . The operating states of the

selectors

33, 37 and 41 are the same as in the case of the first embodiment (FIG. 16). Further, the control signal generator 12 sets the setting of the adjuster 65 of the oscillation circuit 64 to the initial state. Accordingly, the adjustment unit 65 supplies the control voltage Vctrl to a predetermined number of transistors among the plurality of transistors included in the transistor MN12. Also, the value of the correction parameter CAL2 is set to a value corresponding to this initial state.

Next, the photodetection system 2 performs a count operation in each of the plurality of timing detection units 61 to obtain a count code CDC (step S202). This operation is the same as in the case of the first embodiment (FIG. 17). Based on the control signal from the control signal generator 12, the output units 44 of the plurality of timing detectors 61 sequentially supply the count code CDC to the correction processor 56 via the bus wiring BUS1.

The arithmetic unit 56A of the correction processing unit 56 performs the processing of steps S203 to S210 based on the count codes CDC supplied from the plurality of timing detection units 61 respectively.

Operation unit 56A calculates correction parameter CAL1 based on count code CDC and predetermined value CNT (step S203). Specifically, the calculation unit 56A calculates the correction parameter CAL1 using the following equation, similarly to the calculation unit 16A according to the first embodiment.
CAL1=CNT/CDC

Next, the calculation unit 56A confirms whether or not it is the first calculation for the timing detection unit 61 (step S204). If it is the first calculation ("Y" in step S204), the process proceeds to step S206.

If it is not the first calculation ("N" in step S204), the calculation unit 56A checks whether the magnitude relationship between the count code CDC and the predetermined value CNT has changed (step S205). If the magnitude relationship has changed ("Y" in step S205), the process proceeds to step S211.

If the magnitude relationship has not changed ("N" in step S205), the correction parameters CAL1 and CAL2 are stored as the previous correction parameters (step S206).

Next, the calculation unit 56A confirms whether the value of the count code CDC is greater than the predetermined value CNT (step S207).

If the value of the count code CDC is greater than the predetermined value CNT ("Y" in step S207), the calculation unit 56A updates the value of the correction parameter CAL2 by decrementing it (step S208). That is, when the value of the count code CDC is greater than the predetermined value CNT, the oscillation frequency of the oscillation circuit 64 is higher than the oscillation frequency of the oscillation circuit 24. , by decrementing the value of the correction parameter CAL2.

If the value of the count code CDC is smaller than the predetermined value CNT ("N" in step S207), the calculation unit 56A updates the value of the correction parameter CAL2 by incrementing it (step S209). That is, when the value of the count code CDC is smaller than the predetermined value CNT, the oscillation frequency of the oscillation circuit 64 is lower than the oscillation frequency of the oscillation circuit 24. , by incrementing the value of the correction parameter CAL2.

Next, the storage unit 56B stores the updated correction parameter CAL2 (step S210).

Next, the photodetection system 2 sets the correction parameter CAL2 in the adjustment units 65 of the plurality of timing detection units 61 (step S211). Specifically, the correction processing unit 56 supplies the plurality of correction parameters CAL2 stored in the storage unit 56B to the adjustment units 65 of the plurality of timing detection units 61 via the bus wiring BUS2. Each adjustment unit 65 sets the number of transistors that supply the control voltage Vctrl among the plurality of transistors included in the transistor MN12 based on the correction parameter CAL2. Thereby, the oscillation frequency of the oscillation circuit 64 is adjusted based on the correction parameter CAL2.

Then, the process returns to step S202.

In step S205, if the magnitude relationship between the count code CDC and the predetermined value CNT has changed ("Y" in step S205), the calculation unit 56A determines whether the correction parameter CAL1 is closer to "1" than the previous correction parameter CAL1. Confirm whether or not (step S212). If the correction parameter CAL1 is closer to "1" than the previous correction parameter CAL1 ("Y" in step S212), the storage unit 56B stores the correction parameter CAL2 (step S213). If the correction parameter CAL1 is not closer to "1" than the previous correction parameter CAL1 ("N" in step S212), the storage unit 56B stores the previous correction parameter CAL2 (step S214).

Next, the photodetection system 2 sets the correction parameter CAL2 in the adjustment units 65 of the plurality of timing detection units 61 (step S215). Specifically, the correction processing unit 56 supplies the correction parameter CAL2 stored in the storage unit 56B to the adjustment unit 65 of the timing detection unit 61 via the bus wiring BUS2. Based on this correction parameter CAL2, the adjustment unit 65 sets the number of transistors that supply the control voltage Vctrl among the plurality of transistors included in the transistor MN12. Thereby, the oscillation frequency of the oscillation circuit 64 is adjusted based on the correction parameter CAL2.

Then, the control signal generator 12 sets the operation mode M to the operation mode MA (step S216). Specifically, the control signal generator 12 sets the operation states of the

selectors

33, 37 and 41 are the same as in the case of the first embodiment (FIG. 11).

Then, the photodetection system 2 starts ranging operation (step S217).

This is the end of this process.

Thus, in the photodetection system 2, the oscillation circuit 64 has the adjustment section 65 that adjusts the oscillation frequency. Then, in the second operation mode (operation mode MB), the correction processing unit 56 adjusts the frequency of the multiphase clock signal CLKM to the frequency of the clock signal CLK based on the frequency of the clock signal CLK and the frequency of the multiphase clock signal CLKM. The operation of the adjustment unit 65 is controlled so as to approach . As a result, in the photodetection system 2, for example, when there is a difference between the frequency of the clock signal CLK and the frequency of the multiphase clock signal CLKM, the conversion characteristics of the timing detection section 61 can be enhanced. Accuracy can be improved.

As described above, in the present embodiment, the oscillation circuit has an adjustment section that adjusts the oscillation frequency. Then, in the second operation mode, the correction processing unit operates the adjustment unit based on the frequency of the clock signal and the frequency of the multiphase clock signal so that the frequency of the multiphase clock signal approaches the frequency of the clock signal. made to control. Thereby, detection accuracy can be improved.

[Modification 2-1]
In the above embodiment, the oscillation frequency of the oscillation circuit 64 is adjusted by setting the number of transistors supplying the control voltage Vctrl among the plurality of transistors included in the transistor MN12 based on the correction parameter CAL2. , but not limited to. Alternatively, for example, as shown in FIG. 22, the oscillation frequency of the oscillation circuit 64 may be adjusted by adjusting the voltage of the control signal Vctrl. The oscillation circuit 64 has a switch SW, an adjustment section 66, and a capacitive element C1.

A control voltage Vctrl is supplied to one end of the switch SW, and the other end is connected to the gate of the transistor MN11. The switch SW is controlled by the control signal generator 12, for example.

The adjustment unit 66 is configured to generate the voltage ΔV, which is the voltage correction amount of the control voltage Vctrl, based on the correction parameter CAL2. The adjustment section 66 has a DAC (Digital to Analog Converter) 66A. This DAC 66A is configured to generate a voltage ΔV.

One end of the capacitive element C1 is connected to the transistor MN11, and the other end is supplied with the voltage ΔV.

With this configuration, the oscillation frequency of the oscillation circuit 64 can be adjusted by turning off the switch SW. When the switch SW is turned off, the voltage of the gate of the transistor MN11 is maintained at the control voltage Vctrl. Then, the adjustment unit 66 generates the voltage ΔV based on the correction parameter CAL2, so that the voltage of the gate of the transistor MN11 changes from the control voltage Vctrl by this voltage ΔV. Thus, the oscillation circuit 64 can adjust the oscillation frequency based on the correction parameter CAL2.

[Modification 2-2]
In the above embodiment, as shown in FIGS. 21A and 21B, the operation mode M is set to the operation mode MB when the power of the photodetection system 2 is turned on, but the present invention is not limited to this. Alternatively, for example, as shown in FIGS. 23A and 23B, the operation mode M may be periodically set to the operation mode MB while the photodetection system 2 is performing the ranging operation. In this example, the control signal generator 12 checks whether a predetermined period of time has elapsed while the photodetection system 2 is performing the ranging operation (step S228). If the predetermined time has not yet passed ("N" in step S228), the process of step S228 is repeated until the predetermined time has passed. If the predetermined time has passed ("Y" in step S2287), the distance measuring operation is stopped (step S229), and the process returns to step S201. In this example, the operation mode M is periodically set to the operation mode MB, but the operation mode is not limited to this, and the operation mode M can be set to the operation mode MB at any timing. As a result, for example, when the photodetection system 2 operates for a long time, or when the temperature or power supply voltage fluctuates, the conversion characteristics of the timing detector 61 can be enhanced.

[Other Modifications]
Moreover, you may combine these modifications.

<3. Third Embodiment>
Next, a photodetection system 3 according to a third embodiment will be described. This embodiment is configured to adjust the phase of the clock signal CLK in the photodetection system 2 according to the second embodiment. The same reference numerals are assigned to substantially the same components as those of the photodetection system 2 according to the second embodiment, and description thereof will be omitted as appropriate.

The photodetection system 3 includes a photodetection section 70, like the photodetection system 1 (FIG. 1) according to the first embodiment. The photodetector 70 has a multiphase clock signal generator 71 , a selector 73 , and a control signal generator 72 .

The multiphase clock signal generator 71 is configured to generate multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK270).

FIG. 24 shows a configuration example of the multiphase clock signal generator 71. In FIG. The multiphase clock signal generation section 71 has an oscillation circuit 64 , an inverter 36 , a counter 42 , a flip-flop section 43 and an output section 44 .

The oscillation circuit 64 is configured to generate a multiphase clock signal CLKM having a frequency corresponding to the control voltage Vctrl by performing an oscillation operation. Oscillation circuit 64 performs an oscillation operation or stops an oscillation operation based on signal STR. The oscillation circuit 64 can adjust the oscillation frequency based on the correction parameter CAL2.

The counter 42 is configured to generate the count code CDC1 by performing a counting operation based on the rising edge of the clock signal CLK0. Counter 42 starts a counting operation based on signal STR. The counter 42 outputs a multi-bit count code CDC1.

The flip-flop unit 43 is configured to latch the count code CDC1 supplied from the counter 42 based on the rising edge of the signal STP. Then, the flip-flop section 43 supplies the count code CDC indicating the latch result to the output section 44 .

The output unit 44 is configured to supply the count code CDC to the correction processing unit 56 via the bus wiring BUS1 based on the control signal from the control signal generation unit 12.

With this configuration, the multiphase clock signal generation section 71 can adjust the oscillation frequency of the oscillation circuit 64 in the same manner as the timing detection section 61 according to the second embodiment.

The selector 73 (FIG. 24) selects one of the clock signals CLK0, CLK90, CLK180, and CLK270 included in the multiphase clock signal CLKM generated by the multiphase clock signal generation unit 71 based on the signal NSEL, The selected clock signal is configured to be supplied to the driving section 13 as the clock signal NCLK.

The control signal generator 72 is configured to generate various control signals used in the photodetector 70 . In this example, the control signal generator 72 generates the signal NSEL and the signal STR2. In this example, the driving section 13 drives the light emitting section 8 so that the light emitting section 8 emits the light pulse L0 based on the signal STR2.

Here, the multiphase clock signal generator 71 corresponds to a specific example of the "multiphase clock signal generator" in the present disclosure. The oscillator circuit 64 corresponds to a specific example of the "third oscillator circuit" in the present disclosure. Clock signal CLKM corresponds to a specific example of "third multiphase clock signal" in the present disclosure. The selector 73 corresponds to a specific example of "selector" in the present disclosure. The control signal generator 72 corresponds to a specific example of the "control signal generator" in the present disclosure. The flip-flop 13A corresponds to a specific example of "sampling circuit" in the present disclosure.

As in the case of the photodetection system 2 according to the second embodiment (FIGS. 21A and 21B), the photodetection system 3 has the oscillation frequency of the oscillation circuit 24 and the oscillation frequency of the oscillation circuit 64 in the operation mode MB. Perform calibration according to the difference. Thereby, the photodetection system 3 adjusts the oscillation frequency of the oscillation circuit 64 in the multiphase clock signal generator 71 and the plurality of timing detectors 61 .

Then, the photodetection system 3 performs ranging operation in the operation mode MA. The selector 73 selects one of the clock signals CLK0, CLK90, CLK180, and CLK270 included in the multiphase clock signal CLKM generated by the multiphase clock signal generation unit 71, and supplies the selected clock signal to the drive unit 13. do. The flip-flop 13A of the driving section 13 generates the signal TRG by latching the signal STR2 at the rising edge of the clock signal NCLK. As a result, the driving section 13 drives the light emitting section 8 at timing according to the output signal of the selector 73 .

FIG. 25 shows an operation example of the multiphase clock signal generator 71, the control signal generator 72, the selector 73, and the driver 13 in the operation mode MA. The waveform of the clock signal CLK to be generated is shown, (B) shows the waveform of the signal STR, (C) shows the waveform of the signal STR2, and (D) to (G) are generated by the multiphase clock signal generator 71. Waveforms of multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, and CLK270) are shown, (H) shows the waveform of signal NSEL, (I) shows the waveform of clock signal NCLK, and (J) shows the driving section. 13 shows the waveform of the signal TRG generated by the flip-flop 13A at 13. FIG.

At timing t41, the control signal generator 72 changes the signal STR2 from low level to high level based on the rising edge of the clock signal CLK ((A) and (C) in FIG. 25). At timing t41, the control signal generator 72 also generates a signal NSEL (“2”) that instructs the selector 73 to select the clock signal CLK180 based on the rising edge of the clock signal CLK (FIG. 25). (H)).

Next, at timing t42 after a period of time corresponding to, for example, one cycle or more of the clock signal CLK has elapsed from this timing t41, the control signal generator 72 changes the signal STR from low level to high level based on the rising edge of the clock signal CLK. (FIG. 25(B)). As a result, the oscillation circuit 64 of the multiphase clock signal generator 71 starts oscillating and starts to generate the multiphase clock signal CLKM ((D) to (G) in FIG. 25). Selector 73 selects clock signal CLK180 based on signal NSEL and outputs this signal as clock signal NCLK (FIG. 25(I)).

At timing t43, the flip-flop 13A of the driving section 13 changes the signal TRG from low level to high level by latching the signal STR2 at the rising edge of the clock signal NCLK ((J) in FIG. 25). Then, at timing t44 after a period of time corresponding to, for example, two cycles or more of the clock signal CLK has elapsed from timing t42, the control signal generator 72 changes the signal STR2 from high level to low level based on the rising edge of the clock signal CLK. (Fig. 25(C)). At subsequent timing t45, the flip-flop 13A of the driving section 13 changes the signal TRG from high level to low level by latching the signal STR2 at the rising edge of the clock signal NCLK (FIG. 25(J)). The driving section 13 drives the light emitting section 8 based on this signal TRG.

Then, at timing t46 after a period of time corresponding to, for example, two cycles or more of the clock signal CLK has elapsed from the timing t44, the control signal generator 72 changes the signal STR from high level to low level based on the rising edge of the clock signal CLK. (Fig. 25(B)). As a result, the oscillation circuit 64 of the multiphase clock signal generator 71 stops oscillating and stops generating the multiphase clock signal CLKM ((D) to (G) in FIG. 25).

Thus, in the photodetection system 3, the multiphase clock signal generator 71 generates the multiphase clock signal CLKM, and the selector 73 selects the clock signals CLK0, CLK90, CLK180, and CLK270 included in the multiphase clock signal CLKM. Since one of them is selected and the selected clock signal is supplied to the driving section 13, the light emission timing of the light emitting section 8 can be adjusted.

As described above, in the present embodiment, the multiphase clock signal generator generates the multiphase clock signals, and the selector 73 selects one of the clock signals included in the multiphase clock signals, Since the clock signal is supplied to the driving section, the light emission timing of the light emitting section can be adjusted.

[Modification 3-1]
In the above embodiment, the selector 73 selects one of the clock signals CLK0, CLK90, CLK180, and CLK270 included in the multiphase clock signal CLKM generated by the multiphase clock signal generator 71, but is limited to this. not to be Alternatively, instead of providing the multiphase clock signal generator 71, for example, as shown in FIG. One of a plurality of clock signals included in this multiphase clock signal may be selected. The oscillator circuit 84 has four inverters IV1 to IV4, for example, like the oscillator circuit 24 (FIG. 3) according to the third embodiment. In the oscillator circuit 84, these four inverters IV output multi-phase clock signals as in the oscillator circuit 34 (FIG. 6).

[Modification 3-2]
Each modification of the second embodiment may be applied to the photodetection system 3 according to the embodiment.

<4. Fourth Embodiment>
Next, a photodetection system 4 according to a fourth embodiment will be described. In this embodiment, the configuration of the timing detector 31 according to the first embodiment is somewhat simplified. The same reference numerals are assigned to substantially the same components as those of the photodetection system 1 according to the first embodiment, and description thereof will be omitted as appropriate.

The photodetection system 4 includes a photodetection section 90 in the same manner as the photodetection system 1 (FIG. 1) according to the first embodiment. The photodetector section 90 has a pixel array 114 and a TDC section 130 .

The pixel array 114 has a plurality of light receiving portions P arranged in a matrix. The light receiving unit P is configured to detect light and generate a pulse signal PLS having pulses corresponding to the detected light. The light-receiving part P is configured so as to be able to generate a pulse signal PLS with a narrow pulse width in this example.

Similar to the TDC unit 30 according to the first embodiment, the TDC unit 130, based on the pulse signal PLS supplied from each of the plurality of light receiving units P in the pixel array 14, detects the It is configured to detect light reception timing. The TDC section 130 has a plurality of timing detection sections 131 .

FIG. 27 shows a configuration example of the timing detection section 131 in the TDC section 130. As shown in FIG.

The timing detection section 131 includes an SR latch 132, a selector 133, an oscillation circuit 34, a selector 135, an inverter 136, a selector 41, a counter 42, a flip-flop section (F/F section) 43, and an output section. 44 , a frequency dividing section 45 , a flip-flop section 46 and a correcting section 47 .

The SR latch 132 is configured to be set by the pulse signal PLS and reset by the clock signal CLK.

The selector 133 is configured to select one of the signal STR and the output signal of the SR latch 132 based on the control signal from the control signal generator 12 and output the selected signal as the signal EN. Specifically, based on the control signal from the control signal generator 12, the selector 133 selects the output signal of the SR latch 132 in the operation mode MA, and selects the signal STR in the operation mode MB. .

The selector 135 is configured to select one of the signal EN and the signal STR based on the control signal from the control signal generator 12 and output the selected signal. Specifically, based on the control signal from the control signal generator 12, the selector 135 selects the signal EN in the operation mode MA, and selects the signal STR in the operation mode MB.

The inverter 136 is configured to invert the output signal of the selector 135 and output the inverted signal as the signal STP.

FIG. 28 shows an example of the operating state of the TDC section 130 in the operating mode MA. In operation mode MA, each selector 133 of a plurality of timing detectors 131 selects the output signal of SR latch 132 based on the control signal from control signal generator 12, and oscillates this signal as signal EN. It feeds circuit 34 and selector 135 . The selector 135 selects the signal EN based on the control signal from the control signal generator 12 and supplies the signal EN to the inverter 136 . The selector 41 selects the clock signal CLK generated by the oscillation circuit 24 of the clock signal generator 20 based on the control signal from the control signal generator 12 and supplies the clock signal CLK to the counter 42 .

Next, among the plurality of light receiving portions P in the pixel array 114, the light receiving portion P (light receiving portion PR) that detects the light pulse L0R guided by the optical member 9 and the reflected light pulse L1 reflected by the measurement object OBJ Focusing on the light receiving portion P (light receiving portion PA) that detects , the operation of the light detection system 4 in the operation mode MA will be described.

FIG. 29 shows an operation example of the photodetection system 4 in the operation mode MA, where (A) shows the waveform of the signal STR, (B) shows the waveform of the clock signal CLK, and (C) to ( I) shows the waveform of the signal in the timing detection unit 131 (timing detection unit 131R) that operates based on the pulse signal PLS (pulse signal PLSR) generated by the light receiving unit PR. 1 shows waveforms of signals in the timing detector 131 (timing detector 131A) that operates based on the pulse signal PLS (pulse signal PLSA) generated by .

29(C) shows the count code CDC1 (count code CDC1R) in the timing detection section 131R, (D) shows the waveform of the pulse signal PLSR supplied to the timing detection section 131R, and (E) shows the timing detection section 131R. (F) shows the waveform of the signal STP (signal STPR) in the timing detection section 131R, and (G) shows the waveform of the signal EN (signal ENR) in the timing detection section 131R. (H) indicates the count code CDC (count code CDCR) in the timing detection section 131R, and (I) indicates the count code CDF (count code CDFR) in the timing detection section 131R.

29(J) shows the count code CDC1 (count code CDC1A) in the timing detection section 131A, (K) shows the waveform of the pulse signal PLSA supplied to the timing detection section 131A, and (L) shows the timing detection section 131A. (M) shows the waveform of the signal STP (signal STPA) in the timing detection section 131A, (N) shows the waveform of the signal EN (signal ENA) in the timing detection section 131A, and (N) the count code CDF1 (count code CDF1A) in the timing detection section 131A. (O) indicates the count code CDC (count code CDCA) in the timing detection section 131A, and (P) indicates the count code CDF (count code CDFA) in the timing detection section 131A.

At timing t51, the control signal generator 12 changes the signal STR from low level to high level in response to the rising edge of the clock signal CLK ((A) and (B) in FIG. 29). As a result, the counter 42 of the timing detector 131R starts a counting operation based on the rising edge of the clock signal CLK, and the count code CDC1R begins to increment (FIG. 29(C)). Similarly, the counter 42 of the timing detection section 131A starts a counting operation based on the rising edge of the clock signal CLK, and the count code CDC1A starts increasing ((J) in FIG. 29).

Further, based on this change in the control signal STR, the driving section 13 drives the light emitting section 8, and the light emitting section 8 emits the light pulse L0. The optical member 9 guides the light pulse L0 emitted from the light emitting unit 8 to the object to be measured OBJ, and guides part of the light (light pulse L0R) to the light receiving unit PR of the light detection unit 10 . The light receiving part PR generates a pulse signal PLSR by detecting this light pulse L0R. As a result, at timing t52, the pulse signal PLSR changes from low level to high level ((D) in FIG. 29). After that, the timing detection section 131R corresponding to this light receiving section PR operates based on this pulse signal PLSR. In this example, the pulse signal PLSR changes from high level to low level at a timing after a short period of time has passed from timing t52.

At this timing t52, the SR latch 132 of the timing detector 131R is set based on the pulse signal PLSR, and the signal ENR changes from low level to high level (FIG. 29(E)). Then, the signal STPR changes from the high level to the low level according to the change of the signal ENR (FIG. 29(F)).

Based on this change in signal ENR, the oscillation circuit 34 of the timing detector 131R starts oscillating and starts generating multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK27). The frequency divider 45 generates the count code CDF1R based on this multiphase clock signal CLKM (FIG. 29(G)).

Next, at timing t53, the SR latch 132 of the timing detection section 131R is reset based on the clock signal CLK, and the signal ENR changes from high level to low level (FIG. 29(E)). As a result, the oscillation circuit 34 of the timing detector 131R stops oscillating, and updating of the count code CDF1R stops ((G) in FIG. 29). In addition, the signal STPR changes from low level to high level according to the change of the signal ENR (FIG. 29(F)).

Based on this change in the signal STPR, the flip-flop section 43 of the timing detection section 131R latches the count code CDC1R to generate the count code CDCR (FIGS. 29(C) and (H)). In this example, the code value "0" of the count code CDC1R is latched. Based on this latch result, the count code CDCR becomes "0" at timing t55 in this example.

Similarly, based on this change in signal STPR, the flip-flop section 46 of the timing detection section 131R latches the count code CDF1R to generate the count code CDFR (FIGS. 29(G) and (I)). In this example, the code value "1111" of the count code CDF1R is latched. Based on this latch result, the count code CDFR becomes "4" at timing t55 in this example.

After that, after a while, the light receiving part PA detects the reflected light pulse L1 reflected by the object to be measured OBJ to generate the pulse signal PLSA. As a result, at timing t62, the pulse signal PLSA changes from low level to high level ((K) in FIG. 29). After that, the timing detection section 131A corresponding to this light receiving section PA operates based on this pulse signal PLSA. In this example, the pulse signal PLSA changes from high level to low level at a timing after a short period of time has passed from timing t62.

At this timing t62, the SR latch 132 of the timing detection section 131A is set based on the pulse signal PLSA, and the signal ENA changes from low level to high level ((L) in FIG. 29). Then, the signal STPA changes from the high level to the low level according to the change of the signal ENA ((M) in FIG. 29).

Based on this change in signal ENA, the oscillation circuit 34 of the timing detector 131A starts oscillating and starts generating multiphase clock signals CLKM (clock signals CLK0, CLK90, CLK180, CLK27). Frequency divider 45 generates count code CDF1A based on multiphase clock signal CLKM ((N) in FIG. 29).

Next, at timing t63, the SR latch 132 of the timing detector 131A is reset based on the clock signal CLK, and the signal ENA changes from high level to low level ((L) in FIG. 29). As a result, the oscillation circuit 34 of the timing detector 131R stops oscillating, and updating of the count code CDF1A stops ((N) in FIG. 29). Further, the signal STPA changes from the low level to the high level according to the change of the signal ENA ((M) in FIG. 29).

Based on this change in signal STPA, the flip-flop section 43 of the timing detection section 131A latches the count code CDC1A to generate the count code CDCA (FIGS. 29(J) and (O)). In this example, the code value "21" of the count code CDC1A is latched. Based on this latch result, the count code CDCA becomes "21" at timing t65 in this example.

Similarly, based on this change in signal STPA, the flip-flop section 46 of the timing detection section 131A latches the count code CDF1A to generate the count code CDFA ((N), (P) in FIG. 29). In this example, the code value "1110" of the count code CDF1A is latched. Based on this latch result, the count code CDFA becomes "3" at timing t65 in this example.

The TDC unit 130 supplies the count codes CDCR, CDFR and the count codes CDCA, CDFA to the histogram generation unit 17. The histogram generator 17 calculates the flight time Ttof.

FIG. 30 shows an example of the operating state of the TDC section 130 in the operating mode MB. In the operation mode MB, the selectors 133 of the plurality of timing detectors 131 select the signal STR based on the control signal from the control signal generator 12, and send the signal STR to the oscillation circuit 34 as the signal EN. supply. The selector 135 selects the signal STR based on the control signal from the control signal generator 12 and supplies the signal STR to the inverter 136 . The selector 41 selects the clock signal CLK0 generated by the oscillation circuit 34 based on the control signal from the control signal generator 12 and supplies the clock signal CLK0 to the counter 42 .

The operation of the photodetection system 4 in the operation mode MB is the same as that of the photodetection system 1 according to the first embodiment (FIGS. 15 and 17).

As described above, in the photodetection system 4, compared to the photodetection system 1, the configuration of the timing detection section 131 can be simplified. As a result, the circuit area of the photodetection system 4 can be reduced.

[Modification 4-1]
The modification of the first embodiment may be applied to the photodetection system 4 according to the embodiment.

[Modification 4-2]
In the present embodiment, the present technology is applied to the photodetection system 1 according to the first embodiment, but the present technology is not limited to this, and the present technology is applied to the photodetection system 2 according to the second embodiment. may apply.

<5. Example of application to moving objects>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure is implemented as a device mounted on any type of moving object such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may

FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

A vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.

The in-vehicle information detection unit 12040 detects in-vehicle information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.

The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on information on the inside and outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.

Also, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.

The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 31, an audio speaker 12061, a display unit 12062 and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 32 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.

In FIG. 32, the vehicle 12100 has

imaging units

12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

The

imaging units

12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .

Imaging units

12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The forward images acquired by the

imaging units

12101 and 12105 are mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

Note that FIG. 32 shows an example of the imaging range of the imaging units 12101 to 12104. FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the

imaging units

12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic braking control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle autonomously travels without depending on the operation of the driver.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. As a result, the vehicle control system 12000 can improve the detection accuracy of time (TOF value) and distance. As a result, in the vehicle control system 12000, a vehicle collision avoidance or collision mitigation function, a follow-up driving function based on the inter-vehicle distance, a vehicle speed maintenance driving function, a vehicle collision warning function, a vehicle lane deviation warning function, etc. are realized with high accuracy. can.

Although the present technology has been described above with reference to several embodiments, modifications, and specific application examples thereof, the present technology is not limited to these embodiments and the like, and various modifications are possible. is.

For example, in each of the above-described embodiments, the light receiving unit P as shown in FIGS. 4A and 4B is provided, but the circuit configuration of the light receiving unit P is not limited to this, and various circuit configurations can be applied. can do.

It should be noted that the effects described in this specification are only examples and are not limited, and other effects may also occur.

This technology can be configured as follows. According to the present technology having the following configuration, detection accuracy can be improved.

a clock signal generation unit having a reference oscillation circuit that performs an oscillation operation and that generates a clock signal of a predetermined frequency by performing a phase synchronization operation;
a first light receiving unit having a first light receiving element and generating a first pulse signal according to a light receiving result of the first light receiving element;
A first counter that generates a first code by performing a counting operation based on the clock signal, and a first multiphase clock signal that generates a first multiphase clock signal by performing an oscillation operation based on the first pulse signal. a first oscillation circuit; and a first latch section for latching the first code and the second code according to the first multiphase clock signal based on the first pulse signal. a first timing detection unit for detecting a first light receiving timing in the first light receiving unit;
and a correction processing unit that performs a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.
(2)
the reference oscillation circuit performs an oscillation operation based on a control voltage;
The photodetector according to (1), wherein the first oscillation circuit performs an oscillation operation based on the control voltage.
(3)
the reference oscillation circuit and the first oscillation circuit are ring oscillators having circuits in a plurality of stages;
The photodetector according to (1) or (2), wherein the number of stages of the plurality of stages of circuits in the reference oscillation circuit is equal to the number of stages of the plurality of stages of circuits in the first oscillation circuit.
(4)
The first timing detection unit has a correction unit that corrects the second code latched by the first latch unit,
The photodetector according to (2) or (3), wherein the correction processing section controls the operation of the correction section based on the frequency of the clock signal and the frequency of the first multiphase clock signal.
(5)
the photodetector has a first mode of operation and a second mode of operation;
In the second operation mode, the correction processing unit calculates a frequency ratio between the frequency of the clock signal and the frequency of the first multiphase clock signal,
In the first operation mode, the first timing detection section detects the first light receiving timing, and the correction section converts the second code latched by the first latch section to the frequency The photodetector according to (4) above, wherein the correction is performed using a ratio.
(6)
In the second operation mode, the first counter performs a count operation based on the first multiphase clock signal, and the correction processor calculates the frequency ratio based on the result of the count operation. The photodetector according to (5) above.
(7)
The first oscillation circuit has an adjustment section that adjusts an oscillation frequency,
The photodetector according to (2) or (3), wherein the correction processing section controls the operation of the adjustment section based on the frequency of the clock signal and the frequency of the first multiphase clock signal.
(8)
the photodetector has a first mode of operation and a second mode of operation;
In the second operation mode, the correction processing unit adjusts the frequency of the first multiphase clock signal to the frequency of the clock signal based on the frequency of the clock signal and the frequency of the first multiphase clock signal. controlling the operation of the adjustment unit so as to approach
The photodetector according to (7), wherein in the first operation mode, the timing detector detects the first light receiving timing.
(9)
In the second operation mode, the correction processing section controls the operation of the adjusting section based on the magnitude relationship between the frequency of the clock signal and the frequency of the first multiphase clock signal. A photodetector as described.
(10)
a second light receiving unit having a second light receiving element and generating a second pulse signal according to the light receiving result of the second light receiving element;
a second counter for generating a third code by performing a counting operation based on the clock signal; and a second counter for generating a second multiphase clock signal by performing an oscillation operation based on the second pulse signal. and a second latch section for latching the third code and the fourth code according to the second multiphase clock signal based on the second pulse signal. a second timing detection unit for detecting a second light receiving timing in the second light receiving unit;
further comprising
The light according to any one of (1) to (9), wherein the correction processing section performs a second correction process according to a frequency difference between the frequency of the clock signal and the frequency of the second multiphase clock signal. detection device.
(11)
calculating a first timing value corresponding to the first light receiving timing based on the first code and the second code, and calculating the second timing value based on the third code and the fourth code; any one of (1) to (10) above, further comprising a processing unit that calculates a second timing value according to the light receiving timing of and calculates a difference between the first timing value and the second timing value 10. The photodetector according to 1.
(12)
a multiphase clock signal generator having a third oscillation circuit that generates a third multiphase clock signal by performing an oscillation operation;
a selector that selects one of a plurality of clock signals included in the third multiphase clock signal;
a control signal generator that generates a control signal;
a sampling circuit that samples the control signal with a clock signal selected by the selector;
The light according to any one of (1) to (11), wherein the correction processing section performs a third correction process according to a frequency difference between the frequency of the clock signal and the frequency of the third multiphase clock signal. detection device.
(13)
The photodetector according to any one of (1) to (11), wherein the reference oscillation circuit generates a third multiphase clock signal including the clock signal.
(14)
a selector that selects one of a plurality of clock signals included in the third multiphase clock signal;
a control signal generator that generates a control signal;
The photodetector according to (13), further comprising: a sampling circuit that samples the control signal using a clock signal selected by the selector.
(15)
The first light receiving section has a plurality of the first light receiving elements,
The photodetector according to any one of (1) to (14), wherein the first pulse signal is a signal corresponding to light reception results of the plurality of first light receiving elements.
(16)
The photodetector according to any one of (1) to (15), wherein the first light receiving element and the first timing detection section are provided on a first semiconductor substrate.
(17)
The first light receiving element is provided on a first semiconductor substrate,
The photodetector according to any one of (1) to (15), wherein the first timing detection section is provided on a second semiconductor substrate attached to the first semiconductor substrate.
(18)
a light-emitting part that emits light; and a light-detecting part that detects light reflected by a detection target, out of the light emitted from the light-emitting part,
The photodetector is
a clock signal generation unit having a reference oscillation circuit that performs an oscillation operation and that generates a clock signal of a predetermined frequency by performing a phase synchronization operation;
a first light receiving unit having a first light receiving element and generating a first pulse signal according to a light receiving result of the first light receiving element;
A first counter that generates a first code by performing a counting operation based on the clock signal, and a first multiphase clock signal that generates a first multiphase clock signal by performing an oscillation operation based on the first pulse signal. a first oscillation circuit; and a first latch section for latching the first code and the second code according to the first multiphase clock signal based on the first pulse signal. a first timing detection unit for detecting a first light receiving timing in the first light receiving unit;
and a correction processing unit that performs a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.

This application claims priority based on Japanese Patent Application No. 2021-022139 filed on February 15, 2021 at the Japan Patent Office, and the entire contents of this application are incorporated herein by reference. to refer to.

Depending on design requirements and other factors, those skilled in the art may conceive various modifications, combinations, subcombinations, and modifications that fall within the scope of the appended claims and their equivalents. It is understood that

Claims

a clock signal generation unit having a reference oscillation circuit that performs an oscillation operation and that generates a clock signal of a predetermined frequency by performing a phase synchronization operation;
a first light receiving unit having a first light receiving element and generating a first pulse signal according to a light receiving result of the first light receiving element;
A first counter that generates a first code by performing a counting operation based on the clock signal, and a first multiphase clock signal that generates a first multiphase clock signal by performing an oscillation operation based on the first pulse signal. a first oscillation circuit; and a first latch section for latching the first code and the second code according to the first multiphase clock signal based on the first pulse signal. a first timing detection unit for detecting a first light receiving timing in the first light receiving unit;
and a correction processing unit that performs a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.
the reference oscillation circuit performs an oscillation operation based on a control voltage;
The photodetector according to claim 1, wherein the first oscillation circuit performs an oscillation operation based on the control voltage.
the reference oscillation circuit and the first oscillation circuit are ring oscillators having circuits in a plurality of stages;
2. The photodetector according to claim 1, wherein the number of stages of the plurality of stages of circuits in the reference oscillation circuit is equal to the number of stages of the plurality of stages of circuits in the first oscillation circuit.
The first timing detection unit has a correction unit that corrects the second code latched by the first latch unit,
The photodetector according to claim 2, wherein the correction processing section controls the operation of the correction section based on the frequency of the clock signal and the frequency of the first multiphase clock signal.
the photodetector has a first mode of operation and a second mode of operation;
In the second operation mode, the correction processing unit calculates a frequency ratio between the frequency of the clock signal and the frequency of the first multiphase clock signal,
In the first operation mode, the first timing detection section detects the first light receiving timing, and the correction section converts the second code latched by the first latch section to the frequency 5. The photodetector according to claim 4, wherein the correction is performed using a ratio.
In the second operation mode, the first counter performs a count operation based on the first multiphase clock signal, and the correction processor calculates the frequency ratio based on the result of the count operation. 6. The photodetector according to claim 5.
The first oscillation circuit has an adjustment section that adjusts an oscillation frequency,
The photodetector according to claim 2, wherein the correction processing section controls the operation of the adjustment section based on the frequency of the clock signal and the frequency of the first multiphase clock signal.
the photodetector has a first mode of operation and a second mode of operation;
In the second operation mode, the correction processing unit adjusts the frequency of the first multiphase clock signal to the frequency of the clock signal based on the frequency of the clock signal and the frequency of the first multiphase clock signal. controlling the operation of the adjustment unit so as to approach
The photodetector according to claim 7, wherein in the first operation mode, the timing detector detects the first light receiving timing.
9. The correction processing unit according to claim 8, wherein in the second operation mode, the correction processing unit controls the operation of the adjusting unit based on the magnitude relationship between the frequency of the clock signal and the frequency of the first multiphase clock signal. photodetector.
a second light receiving unit having a second light receiving element and generating a second pulse signal according to the light receiving result of the second light receiving element;
a second counter for generating a third code by performing a counting operation based on the clock signal; and a second counter for generating a second multiphase clock signal by performing an oscillation operation based on the second pulse signal. and a second latch section for latching the third code and the fourth code according to the second multiphase clock signal based on the second pulse signal. a second timing detection unit for detecting a second light receiving timing in the second light receiving unit;
further comprising
2. The photodetector according to claim 1, wherein the correction processing section performs second correction processing according to a frequency difference between the frequency of the clock signal and the frequency of the second multiphase clock signal.
calculating a first timing value corresponding to the first light receiving timing based on the first code and the second code, and calculating the second timing value based on the third code and the fourth code; 2. The photodetector according to claim 1, further comprising a processing unit that calculates a second timing value according to the light receiving timing of and calculates a difference between the first timing value and the second timing value.
a multiphase clock signal generator having a third oscillation circuit that generates a third multiphase clock signal by performing an oscillation operation;
a selector that selects one of a plurality of clock signals included in the third multiphase clock signal;
a control signal generator that generates a control signal;
a sampling circuit that samples the control signal with a clock signal selected by the selector;
2. The photodetector according to claim 1, wherein the correction processing section performs a third correction process according to a frequency difference between the frequency of the clock signal and the frequency of the third multiphase clock signal.
2. The photodetector according to claim 1, wherein the reference oscillation circuit generates a third multiphase clock signal including the clock signal.
a selector that selects one of a plurality of clock signals included in the third multiphase clock signal;
a control signal generator that generates a control signal;
14. The photodetector according to claim 13, further comprising a sampling circuit that samples the control signal with a clock signal selected by the selector.
The first light receiving section has a plurality of the first light receiving elements,
2. The photodetector according to claim 1, wherein the first pulse signal is a signal corresponding to the results of light received by the plurality of first light receiving elements.
The photodetector according to claim 1, wherein the first light receiving element and the first timing detection section are provided on a first semiconductor substrate.
The first light receiving element is provided on a first semiconductor substrate,
The photodetector according to claim 1, wherein the first timing detection section is provided on a second semiconductor substrate attached to the first semiconductor substrate.
a light-emitting part that emits light; and a light-detecting part that detects light reflected by a detection target, out of the light emitted from the light-emitting part,
The photodetector is
a clock signal generation unit having a reference oscillation circuit that performs an oscillation operation and that generates a clock signal of a predetermined frequency by performing a phase synchronization operation;
a first light receiving unit having a first light receiving element and generating a first pulse signal according to a light receiving result of the first light receiving element;
A first counter that generates a first code by performing a counting operation based on the clock signal, and a first multiphase clock signal that generates a first multiphase clock signal by performing an oscillation operation based on the first pulse signal. a first oscillation circuit; and a first latch section for latching the first code and the second code according to the first multiphase clock signal based on the first pulse signal. a first timing detection unit for detecting a first light receiving timing in the first light receiving unit;
and a correction processing unit that performs a first correction process according to a frequency difference between the frequency of the clock signal and the frequency of the first multiphase clock signal.