WO2022127470A1 - 供电电路、芯片和显示屏 - Google Patents

供电电路、芯片和显示屏 Download PDF

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Publication number
WO2022127470A1
WO2022127470A1 PCT/CN2021/130747 CN2021130747W WO2022127470A1 WO 2022127470 A1 WO2022127470 A1 WO 2022127470A1 CN 2021130747 W CN2021130747 W CN 2021130747W WO 2022127470 A1 WO2022127470 A1 WO 2022127470A1
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WIPO (PCT)
Prior art keywords
switch
current
current mirror
amplifier
mirror group
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PCT/CN2021/130747
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English (en)
French (fr)
Inventor
马英杰
Original Assignee
北京集创北方科技股份有限公司
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Application filed by 北京集创北方科技股份有限公司 filed Critical 北京集创北方科技股份有限公司
Priority to US18/256,436 priority Critical patent/US20240029635A1/en
Priority to JP2023528200A priority patent/JP2024526479A/ja
Priority to EP21905399.8A priority patent/EP4243007A4/en
Priority to KR1020237004935A priority patent/KR20230037634A/ko
Publication of WO2022127470A1 publication Critical patent/WO2022127470A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present application relates to the field of circuit technology, and in particular, to a power supply circuit, a chip and a display screen.
  • LED (Light Emitting Diode, light-emitting diode) display is a kind of flat panel display, which is composed of small LED module panels. It is a device used to display various information such as text, images, and videos.
  • the LED display integrates microelectronic technology, computer technology and information processing technology. It has the advantages of bright colors, wide dynamic range, high brightness, long life, stable and reliable operation. Based on this, LED displays are widely used in commercial media, cultural performance markets, stadiums, information dissemination, news releases, securities trading and other occasions, which can meet the needs of different environments.
  • the LED display needs a driver chip for display.
  • the current accuracy is usually not high enough to meet the requirements.
  • the purpose of the embodiments of the present application is to provide a power supply circuit, a chip and a display screen.
  • An embodiment of the present application provides a power supply circuit, including: a reference circuit, configured to generate a first-level mirror current; a first current mirror group, connected to the reference circuit; a first switch, connected to the first current mirror group, configured to control the closing or opening of the first current mirror group; a second current mirror group, connected to the first current mirror group; a second switch, connected to the second current mirror group, configured to control the second current mirror group Closing or disconnecting of the current mirror group; when the first switch and the second switch are closed, the first current mirror group and the second current mirror group cooperate to form a current mirror, which is configured to pair the one The mirror current of the stage is mirrored to obtain the output current; the output stage, connected to the second current mirror group, is configured to output the output current.
  • the first current mirror group includes: a first amplifier, an inverting input terminal of the first amplifier is connected to a preset voltage signal; a plurality of first transistors, each of the first transistors The drain of the first amplifier is respectively connected to the non-inverting input terminal of the first amplifier, the gate of the first transistor is connected to the output terminal of the first amplifier through the first switch, and the The source is grounded.
  • the first switch includes: a plurality of first sub-switches, the gate of each of the first transistors is connected to one end of the first sub-switch, and the other end of the first sub-switch is respectively connected connected to the output of the first amplifier.
  • the second current mirror group includes: a second amplifier, the non-inverting input terminal of the second amplifier is connected to the drain of the first triode, and the output terminal of the second amplifier is connected to the an output stage; a plurality of second triodes, the drain of each second triode is respectively connected to the inverting input end of the second amplifier, and the gate of the second triode passes through the The two switches are connected to the output end of the first amplifier, and the source of the second transistor is grounded.
  • the second transistor is an NMOS device.
  • the second switch includes: a plurality of second sub-switches, the gate of each second triode is connected to one end of the second sub-switch, and the other end of the second sub-switch is respectively connected connected to the output of the first amplifier.
  • it further includes: a buffer connected between the first current mirror group and the second current mirror group.
  • the reference circuit includes: a reference amplifier, the inverting input terminal of the reference amplifier is connected to the reference signal; an external resistor, the first end of the external resistor is connected to the non-inverting input terminal of the reference amplifier , the second end of the external resistor is grounded.
  • the reference circuit further includes: a third triode, the gate of the third triode is connected to the output end of the reference amplifier, and the drain of the third triode is connected to the external the first end of the resistor, the source of the third triode is grounded; the fourth triode, the gate of the fourth triode is connected to the output end of the reference amplifier, and the fourth triode is connected to the output end of the reference amplifier.
  • the drains of the triodes are respectively connected to the drains of each of the first triodes, and the sources of the fourth triodes are grounded.
  • the output stage includes: a fifth triode, the gate of the fifth triode is connected to the output end of the second amplifier, and the source of the fifth triode is connected to each The drain of the second triode and the drain of the fifth triode are connected to the driven circuit.
  • it further includes: a controller connected to the first switch and the second switch respectively, and configured to send a control signal to the first switch and the second switch.
  • Embodiments of the present application further provide a driver chip, including: the power supply circuit provided by the embodiments of the present application.
  • the driver chip is a driver chip of an LED display screen.
  • An embodiment of the present application further provides a display screen, comprising: the power supply circuit provided by the embodiment of the present application; the power supply circuit drives the display screen with a common anode; or the power supply circuit drives the display screen with a common cathode .
  • the display screen is an LED display screen.
  • the opening and closing of the two current mirror groups are respectively controlled by arranging a first switch for the first current mirror group and a second switch for the second current mirror group, and When the first switch and the second switch are closed, the first current mirror group and the second current mirror group cooperate to form a current mirror, which is used to perform mirror processing on the first-level mirror current generated by the basic circuit to obtain the output current;
  • the stage outputs the output current as a constant current source. In this way, the influence of the output constant current source switch on the output current accuracy is reduced, the stability of the internal loop is improved, and the current accuracy in the entire current range of the output constant current source is effectively improved.
  • FIG. 1A is a schematic structural diagram of a power supply circuit according to an embodiment of the application.
  • 1B is a schematic structural diagram of a power supply circuit according to an embodiment of the application.
  • 1C is a schematic diagram of the principle of a current mirror according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a power supply circuit according to an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a power supply circuit according to an embodiment of the application.
  • 4A to 4C are schematic diagrams of circuit equivalent structures of the output channel of the constant current source according to the embodiment of the present application.
  • 1-power supply circuit 10-reference circuit, 20-current mirror, 30-output circuit, 21-first current mirror group, 22-first switch, 23-second current mirror group, 24-second switch, 25-output stage , 26-buffer, 27-controller, OP1-first amplifier, NM0-first transistor, K0-first sub-switch, NM1-second transistor, K1-second sub-switch, OP0-reference Amplifier, Rext-external resistor, PM0-third transistor, PM1-fourth transistor, DRIVER_OP-second amplifier, NM2-fifth transistor, I0-reference current, I1-first-level mirror current, Iout-output current, Vref-reference voltage, LED-light-emitting diode.
  • this embodiment provides a power supply circuit 1, which mainly includes three parts: a reference circuit 10, a current mirror 20 and an output circuit 30.
  • the above-mentioned power supply circuit 1 can be applied to a driving chip of an LED display screen In the circuit, it can be used as a constant current source generating circuit.
  • the reference circuit 10 uses the built-in reference voltage VREF and the external resistor Rext to generate the reference current I0, and then the reference current I0 is processed by the current mirror 20 to obtain the current I1; finally, the output circuit 30 generates and drives the output constant current source Iout.
  • the current mirror 20 and the output circuit 30 need to adapt to the LED common anode structure and meet the multi-channel driving capability requirements.
  • this embodiment provides a specific circuit diagram of a power supply circuit 1, including: a reference voltage Vref generated by a bandgap reference voltage source inside the chip, using an error amplifier OP0, a transistor PM0 and an external resistor Rext to form a negative feedback
  • the reference current I0 is obtained as follows:
  • the above-mentioned triode can adopt a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor) device.
  • MOS Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor
  • the current of a MOS device is proportional to the device size under the same voltage bias.
  • the current ratio is determined by the number of MOS devices.
  • the effect of the current mirror can be formed between the transistors NM0, the transistors NM1 and the transistors NM2.
  • the principle of forming the current mirror 20 is described in detail below:
  • the schematic diagram of the current mirror 20 is shown in FIG. 1C , assuming that the transistor NM0 and the transistor NM1 have the same gate voltage Vg1, the gate voltage of the transistor NM2 is Vg2, and the drain voltages of the transistor NM0, the transistor NM1, and the transistor NM2 are Vd0 respectively. , Vd1, Vd2, then if Vg1 is equal to Vg2 and Vd1 is equal to Vd2, then the transistors NM1 and NM2 are under the same bias condition, then the current I1 is equal to the current I2, that is, the current I2 mirrors the current I1.
  • K is the mirror ratio of the transistor PM1 and the transistor NM0, which is determined by the performance of the selected device. Then, using the negative feedback structure formed by the error amplifier OP1 and the triode NM0, set the drain voltage VCRES of the triode NM0, and obtain the gate voltage of the triode NM0 as VGATE.
  • the gate of the triode NM1 needs to be
  • the pole voltage is equal to VGATE
  • the drain voltage is equal to VCRES
  • the negative feedback loop formed by the amplifier DRIVER_OP and the transistor NM2 is used to set the drain voltage of the transistor NM1 equal to the drain voltage of NM0
  • the LED common anode structure driver chip through two current mirroring has the following relationship:
  • the mirror ratio of the transistor NM0 and the transistor NM1 is M:N. In this way, the required precise output current Iout can be obtained by adjusting the ratio of the external resistor Rext and the current mirror.
  • the mirror ratio of the transistor NM0 and the transistor NM1 is M:N. It is necessary to select an appropriate ratio.
  • the branch current of the transistor NM0 can be reduced while maintaining the current accuracy that meets the requirements, and the static power consumption of the chip can be reasonably reduced.
  • this embodiment provides a power supply circuit 1, including: a reference circuit 10, a first current mirror group 21, a first switch 22, a second current mirror group 23, a second switch 24, and an output stage 25, in,
  • a reference circuit 10, configured to generate a first-level mirror current I1; a first current mirror group 21, connected to the reference circuit 10; a first switch 22, connected to the first current mirror group 21, configured to control the first current The closing or opening of the mirror group 21; the second current mirror group 23, connected to the first current mirror group 21; the second switch 24, connected to the second current mirror group 23, configured to control the second current mirror The group 23 is closed or disconnected; when the first switch 22 and the second switch 24 are closed, the first current mirror group 21 and the second current mirror group 23 cooperate to form current mirrors, which are arranged in pairs
  • the first-stage mirror current I1 is mirrored to obtain the output current Iout; the output stage 25, connected to the second current mirror group 23, is configured to output the output current Iout.
  • the buffer 26 further includes: a buffer 26 connected between the first current mirror group 21 and the second current mirror group 23 .
  • the buffer 26 can reduce the feedback noise, ensure the current accuracy, and improve the stability of the negative feedback loop.
  • a controller 27 connected to the first switch 22 and the second switch 24 respectively, and configured to send a control signal to the first switch 22 and the second switch 24 .
  • this embodiment provides a power supply circuit 1, the first current mirror group 21 includes: a first amplifier OP1 and a plurality of first transistors NM0, the inverting input of the first amplifier OP1 The terminal is connected to the preset voltage signal; the drain of each first transistor NM0 is connected to the non-inverting input terminal of the first amplifier OP1 respectively, and the gate of the first transistor NM0 passes through the first transistor NM0.
  • the switch 22 is connected to the output terminal of the first amplifier OP1, and the source of the first transistor NM0 is grounded.
  • four first transistors NM0 are used as an example.
  • the first switch 22 includes: a plurality of first sub-switches K0, the gate of each of the first transistors NM0 is respectively connected to one end of the first sub-switch K0, the first sub-switch K0 The other end of the switch K0 is connected to the output end of the first amplifier OP1.
  • the second current mirror group 23 includes: a second amplifier DRIVER_OP and a plurality of second transistors NM1, and the non-inverting input end of the second amplifier DRIVER_OP is connected to the drain of the first transistor NM0
  • the output terminal of the second amplifier DRIVER_OP is connected to the output stage 25; the drain of each of the second transistors NM1 is connected to the inverting input terminal of the second amplifier DRIVER_OP, respectively.
  • the gate of the transistor NM1 is connected to the output terminal of the first amplifier OP1 through the second switch 24 , and the source of the second transistor NM1 is grounded.
  • four second transistors NM1 are used as an example.
  • the second switch 24 includes: a plurality of second sub-switches K1, the gate of each of the second transistors NM1 is respectively connected to one end of the second sub-switch K1, the second sub-switch K1 The other end of the switch K1 is connected to the output end of the first amplifier OP1.
  • the buffer 26 may be connected between the first current mirror group 21 and the second current mirror group 23 .
  • the reference circuit 10 includes: a reference amplifier OP0, an inverting input terminal of the reference amplifier OP0 is connected to a reference signal, and the reference signal may be a reference voltage Vref; an external resistor Rext, the The first terminal is connected to the non-inverting input terminal of the reference amplifier OP0, and the second terminal of the external resistor Rext is grounded.
  • the reference circuit 10 further includes: a third transistor PM0, the gate of the third transistor PM0 is connected to the output end of the reference amplifier OP0, and the drain of the third transistor PM0 The pole is connected to the first end of the external resistor Rext, the source of the third transistor PM0 is grounded; the fourth transistor PM1, the gate of the fourth transistor PM1 is connected to the reference At the output end of the amplifier OP0, the drain of the fourth transistor PM1 is respectively connected to the drain of each of the first transistors NM0, and the source of the fourth transistor PM1 is grounded.
  • the output stage 25 includes: a fifth transistor NM2, the gate of the fifth transistor NM2 is connected to the output end of the second amplifier DRIVER_OP, and the source of the fifth transistor NM2
  • the electrodes are respectively connected to the drain of each of the second transistors NM1, and the drain of the fifth transistor NM2 is connected to the driven circuit.
  • first transistors NM0 which are transistors NM0:1 to NM0:4 respectively;
  • the second transistor NM1 is 4, respectively, transistors NM1:1 to NM1:4,
  • the first switch 22 is 4, respectively, the first sub-switch K0:1 to the first sub-switch K0:4;
  • the second switch 2 is 4, respectively are the second sub-switch K1:1 to the second sub-switch K1:4; based on this, the detailed principle is explained below:
  • the mirror ratio N/M of the first current mirror group 21 and the second current mirror group 23 is in the range of 4-8, the purpose is to reduce the power consumption of the chip under the condition of satisfying the device performance.
  • the voltage VGATE is sent to the gate of the second transistor NM1 in the channel through a buffer 26.
  • the buffer 26 The constant current source generation circuit is isolated from the constant current source output channel to avoid the influence of the noise generated by the constant current source output channel of the constant current source on the constant current source; in the multiple channel structure, the first amplifier OP1 needs to Driving a plurality of second transistors NM1, the second transistors NM1 may be NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor), which will contribute a lot to the output node of the first amplifier OP1. Large parasitic capacitance, so the buffer 26 not only improves the driving capability of the voltage VGATE, but also reduces the design difficulty of the first amplifier OP1.
  • the first transistor NM0 in the first current mirror group 21 and the mirrored current in its channel are divided into four groups, wherein the control signals of the first sub-switch K0:1 and the second sub-switch K1:1 are the same.
  • the control signals of the sub-switches K0:2 and the second sub-switches K1:2 are the same, the control signals of the first sub-switches K0:3 and the second sub-switches K1:3 are the same, and the first sub-switches K0:4 and the second sub-switches are the same.
  • the control signals of K1:4 are the same, and the control signals of the above switches are given by the controller 27 .
  • the current setting requirements are different, and different groups of the first transistor NM0 and the second transistor NM1 can be turned on through each sub-switch to form different current mirrors, so that the output current Iout range is relatively high. Improve the accuracy of the constant current source under the large premise.
  • the principle is explained as follows:
  • FIG. 4A to 4C are schematic diagrams of equivalent circuits of the output constant current source channel circuit of the power supply circuit 1 of the present embodiment, wherein, FIG. 4A shows the connection circuit diagram of the constant current source output channel and the light emitting diode LED.
  • Voff1 the equivalent offset voltage of the threshold voltage of the NMOS transistor that constitutes the current mirror
  • Voff2 the equivalent input offset voltage of DRIVER_OP1
  • the circuit shown in FIG. 4A can be equivalent to the equivalent circuit shown in FIG. 4B, and further, can be equivalent to the equivalent circuit shown in FIG. 4C, then at this time
  • the current of the output constant current source in FIG. 4A is equivalent to the current of the biased NMOS transistor shown in FIG. 4C .
  • ⁇ is the channel carrier mobility
  • C OX is the gate oxide capacitance per unit area
  • W/L is the width-to-length ratio of the MOS transistor
  • V GS is the voltage between the gate and source of the MOS device
  • V DS is the MOS The voltage between the drain and the source of the device
  • V TH is the threshold voltage of the MOS device.
  • Formula (2) and formula (3) illustrate that the larger the gate-source voltage of the second transistor NM1 is, the smaller the influence of the error source introduced by the offset on the output current Iout is.
  • the first sub-switch K0:2 and the second sub-switch K1:2 are turned on, and so on, with As the set output current Iout increases, the first sub-switches K0:1 to K0:4 and the second sub-switches K1:1 to K1:4 are turned on one by one, that is, when the output current Iout is smaller, a smaller number of groups are used.
  • the NMOS device is turned on, which can improve the current accuracy of the chip.
  • the current range of the constant current source is very large, from several to tens of milliamps. In such a large range, if MOS devices of the same size are used, the current accuracy will change greatly.
  • This embodiment proposes the concept of grouping. For different output current settings, turn on different numbers of MOS tubes, so that different groups adapt to different currents, which improves the current accuracy of the chip in the case of large current changes.
  • the above-mentioned power supply circuit 1 reduces the static power consumption of the chip under the premise of ensuring the current accuracy by selecting the appropriate mirror ratio M:N of the first transistor NM0 and the second transistor NM1; in the current mirror NMOS transistor A buffer 26 is added to the gate voltage VGATE path, which reduces the driving capability requirement of the first amplifier OP1, reduces the feedback noise, ensures the current accuracy, and improves the connection between the first amplifier OP1 and the first transistor NM0.
  • the stability of the negative feedback loop; the constant current source adopts the grouping mode, which effectively guarantees the current accuracy in the entire current range of the output constant current source.
  • the embodiment of the present application further provides a driving chip, including: the power supply circuit 1 of the above-mentioned embodiment.
  • the driver chip may be a driver chip of an LED display screen.
  • An embodiment of the present application further provides a display screen, comprising: the power supply circuit 1 of the above embodiment; wherein the power supply circuit drives the display screen in common anode; or the power supply circuit drives the display screen in common cathode. Therefore, it has all the beneficial effects of the power supply circuit 1 in the above-mentioned embodiment.
  • the display screen can be an LED display screen.
  • the technical solution provided by the present application reduces the influence of the output constant current source switch on the output current accuracy, improves the stability of the inner loop, and effectively improves the current accuracy in the entire current range of the output constant current source.

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Abstract

本申请提供一种供电电路、芯片和显示屏，该电路包括：基准电路，配置成生成一级镜像电流；第一电流镜组，连接所述基准电路；第一开关，连接所述第一电流镜组，配置成控制所述第一电流镜组的闭合或断开；第二电流镜组，连接所述第一电流镜组；第二开关，连接所述第二电流镜组，配置成控制所述第二电流镜组的闭合或断开；在所述第一开关与所述第二开关闭合时，所述第一电流镜组与所述第二电流镜组配合形成电流镜，配置成对所述一级镜像电流进行镜像处理，得到输出电流；输出级，连接所述第二电流镜组，配置成输出所述输出电流。本申请有效的提高了在输出恒流源的整个电流范围内的电流精度。

Description

供电电路、芯片和显示屏
相关申请的交叉引用
本申请要求于2020年12月17日提交中国专利局的申请号为2020115016417、名称为“供电电路、芯片和显示屏”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，具体而言，涉及一种供电电路、芯片和显示屏。
背景技术
LED(Light Emitting Diode，发光二极管)显示屏是一种平板显示器，由一个个小的LED模块面板组成，是一种用于显示文字、图像、视频等各种信息的设备。LED显示屏集微电子技术、计算机技术、信息处理技术于一体，具有色彩鲜艳、动态范围广、亮度高、寿命长、工作稳定可靠等优点。基于此，LED显示屏广泛应用于商业传媒、文化演出市场、体育场馆、信息传播、新闻发布、证券交易等各种场合，可以满足不同环境的需要。
LED显示屏需要驱动芯片以进行显示。然而，在现有的驱动芯片电路中，电流精度通常不高，无法满足需求。
发明内容
本申请实施例的目的在于提供一种供电电路、芯片和显示屏。
本申请实施例提供了一种供电电路，包括：基准电路，配置成生成一级镜像电流；第一电流镜组，连接所述基准电路；第一开关，连接所述第一电流镜组，配置成控制所述第一电流镜组的闭合或断开；第二电流镜组，连接所述第一电流镜组；第二开关，连接所述第二电流镜组，配置成控制所述第二电流镜组的闭合或断开；在所述第一开关与所述第二开关闭合时，所述第一电流镜组与所述第二电流镜组配合形成电流镜，配置成对所述一级镜像电流进行镜像处理，得到输出电流；输出级，连接所述第二电流镜组，配置成输出所述输出电流。
可选地，所述第一电流镜组包括：第一放大器，所述第一放大器的反相输入端连接预设电压信号；多个第一三极管，每个所述第一三极管的漏极分别连接所述第一放大器的正相输入端，所述第一三极管的栅极通过所述第一开关连接所述第一放大器的输出端，所述第一三极管的源极接地。
可选地，所述第一开关包括：多个第一子开关，每个所述第一三极管的栅极分别连接所述第一子开关的一端，所述第一子开关的另一端连接所述第一放大器的输出端。
可选地，所述第二电流镜组包括：第二放大器，所述第二放大器的正相输入端连接所述第一三极管的漏极，所述第二放大器的输出端连接所述输出级；多个第二三极管，每个所述第二三极管的漏极分别连接所述第二放大器的反相输入端，所述第二三极管的栅极通过所述第二开关连接所述第一放大器的输出端，所述第二三极管的源极接地。
可选地，所述第二三极管为NMOS器件。
可选地，所述第二开关包括：多个第二子开关，每个所述第二三极管的栅极分别连接所述第二子开关的一端，所述第二子开关的另一端连接所述第一放大器的输出端。
可选地，还包括：缓冲器，连接在所述第一电流镜组与所述第二电流镜组之间。
可选地，所述基准电路包括：基准放大器，所述基准放大器的反相输入端接入基准信号；外置电阻，所述外置电阻的第一端连接所述基准放大器的正相输入端，所述外置电阻的第二端接地。
可选地，所述基准电路还包括：第三三极管，所述第三三极管的栅极连接所述基准放大器的输出端，所述第三三极管的漏极连接所述外置电阻的所述第一端，所述第三三极管的源极接地；第四三极管，所述第四三极管的栅极连接所述基准放大器的输出端，所述第四三极管的漏极分别连接每个所述第一三极管的漏极，所述第四三极管的源极接地。
可选地，所述输出级包括：第五三极管，所述第五三极管的栅极连接所述第二放大器的输出端，所述第五三极管的源极分别连接每个所述第二三极管的漏极，所述第五三极管的漏极连接被驱动的电路。
可选地，还包括：控制器，分别连接所述第一开关和所述第二开关，配置成向所述第一开关和所述第二开关发送控制信号。
本申请实施例还提供了一种驱动芯片，包括：如本申请实施例提供的所述供电电路。
可选地，所述驱动芯片为LED显示屏的驱动芯片。
本申请实施例还提供了一种显示屏，包括：如本申请实施例提供的所述供电电路；所述供电电路共阳驱动所述显示屏；或所述供电电路共阴驱动所述显示屏。
可选地，所述显示屏为LED显示屏。
本申请提供的供电电路、芯片和显示屏，通过为第一电流镜组设置第一开关，为第二电流镜组设置第二开关，来分别控制两个电流镜组的断开和闭合，并在第一开关与第二开关闭合时，使第一电流镜组与第二电流镜组配合形成电流镜，用于对基本电路生成的一级镜像电流进行镜像处理，得到输出电流；并通过输出级将输出电流作为恒流源输出。如此降低了输出恒流源开关对输出电流精度的影响，以及提升了内部环路稳定性，有效的提高 了在输出恒流源的整个电流范围内的电流精度。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1A为本申请实施例的供电电路的结构示意图；
图1B为本申请实施例的供电电路的结构示意图；
图1C为本申请实施例的电流镜像的原理示意图；
图2为本申请实施例的供电电路的结构示意图；
图3为本申请实施例的供电电路的结构示意图；
图4A至图4C为本申请实施例的恒流源输出通道的电路等效结构示意图。
附图标记：
1-供电电路，10-基准电路，20-电流镜像，30-输出电路，21-第一电流镜组，22第一开关，23-第二电流镜组，24第二开关，25-输出级，26-缓冲器，27-控制器，OP1-第一放大器，NM0-第一三极管，K0-第一子开关，NM1-第二三极管，K1-第二子开关，OP0-基准放大器，Rext-外置电阻，PM0-第三三极管，PM1-第四三极管，DRIVER_OP-第二放大器，NM2-第五三极管，I0-基准电流，I1-一级镜像电流，Iout-输出电流，Vref-基准电压，LED-发光二极管。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
如图1所示，本实施例提供一种供电电路1，主要包括三个部分，分别是：基准电路10、电流镜像20和输出电路30，上述供电电路1可以应用于LED显示屏的驱动芯片中，可作为恒流源产生电路。其中，基准电路10，利用内置基准电压VREF与外置电阻Rext产生基准电流I0，然后基准电流I0经过电流镜像20处理，得到电流I1；最后，输出电路30产生并驱动输出恒流源Iout。其中，电流镜像20和输出电路30需要适应LED共阳结构，并满足多通道驱动能力需求。
如图1B所示，本实施例提供一种供电电路1的具体电路图，包括：芯片内部的带隙基准电压源产生的基准电压Vref，利用误差放大器OP0、三极管PM0以及外置电阻Rext构成负反馈结构，得到基准电流I0如下：
Figure PCTCN2021130747-appb-000001
通过三极管PM0、三极管PM1组成的电流镜，得到精准匹配的电流I1。
上述三极管可以采用MOS(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)器件。在实际应用中，在相同电压偏置下MOS器件的电流与器件尺寸成正比，采用相同尺寸的MOS器件，电流比例则由MOS器件的个数决定，通过调整MOS器件的个数，得到所需要的电流比例。本实施例中三极管NM0、三极管NM1和三极管NM2之间可形成电流镜的效果，下面详细说明形成电流镜像20的原理：
电流镜像20的原理图如图1C所示，假设三极管NM0与三极管NM1具有相同的栅极电压Vg1，三极管NM2的栅极电压为Vg2，三极管NM0、三极管NM1、三极管NM2的漏极电压分别为Vd0、Vd1、Vd2，那么如果Vg1等于Vg2、Vd1等于Vd2，则三极管NM1、三极管NM2两器件处于相同的偏置条件下，则电流I1等于电流I2，即电流I2镜像了电流I1。
基于上述原理，在图1B所示的三极管PM1与三极管NM0的电流支路中有：
I1＝K·I0
其中，K为三极管PM1与三极管NM0的镜像比例，由所选器件的性能决定。然后，利用误差放大器OP1、三极管NM0构成的负反馈结构，设置三极管NM0的漏极电压VCRES，得到三极管NM0的栅极电压为VGATE，同时为了精准的镜像输出通道电流Iout，需要将三极管NM1的栅极电压等于VGATE，漏极电压等于VCRES，利用放大器DRIVER_OP与三极管NM2构成的负反馈环路，设置三极管NM1的漏极电压等于NM0的漏极电压，LED共阳结构的驱动芯片通过两次电流镜像，有如下关系：
I1＝K·I0
Figure PCTCN2021130747-appb-000002
Figure PCTCN2021130747-appb-000003
其中，三极管NM0与三极管NM1的镜像比例为M：N，如此，可以通过调整外置电阻Rext以及电流镜的比例得到所需要的精确输出电流Iout。
上述供电电路，三极管NM0与三极管NM1的镜像比例为M：N，需要选择合适的比 值，在保持满足需求的电流精度情况下可以降低三极管NM0支路电流，合理的降低芯片的静态功耗。
如图2所示，本实施例提供一种供电电路1，包括：基准电路10、第一电流镜组21、第一开关22、第二电流镜组23、第二开关24和输出级25，其中，
基准电路10，配置成生成一级镜像电流I1；第一电流镜组21，连接所述基准电路10；第一开关22，连接所述第一电流镜组21，配置成控制所述第一电流镜组21的闭合或断开；第二电流镜组23，连接所述第一电流镜组21；第二开关24，连接所述第二电流镜组23，配置成控制所述第二电流镜组23的闭合或断开；在所述第一开关22与所述第二开关24闭合时，所述第一电流镜组21与所述第二电流镜组23配合形成电流镜，配置成对所述一级镜像电流I1进行镜像处理，得到输出电流Iout；输出级25，连接所述第二电流镜组23，配置成输出所述输出电流Iout。
可选地，还包括：缓冲器26，连接在所述第一电流镜组21与所述第二电流镜组23之间。缓冲器26可以降低回馈的噪声，保证了电流精度，同时提高负反馈环路的稳定性。
可选地，还包括：控制器27，分别连接所述第一开关22和所述第二开关24，配置成向所述第一开关22和所述第二开关24发送控制信号。
如图3所示，本实施例提供一种供电电路1，所述第一电流镜组21包括：第一放大器OP1和多个第一三极管NM0，所述第一放大器OP1的反相输入端连接预设电压信号；每个所述第一三极管NM0的漏极分别连接所述第一放大器OP1的正相输入端，所述第一三极管NM0的栅极通过所述第一开关22连接所述第一放大器OP1的输出端，所述第一三极管NM0的源极接地。图3中以4个第一三极管NM0为例。
可选地，所述第一开关22包括：多个第一子开关K0，每个所述第一三极管NM0的栅极分别连接所述第一子开关K0的一端，所述第一子开关K0的另一端连接所述第一放大器OP1的输出端。
可选地，所述第二电流镜组23包括：第二放大器DRIVER_OP和多个第二三极管NM1，所述第二放大器DRIVER_OP的正相输入端连接所述第一三极管NM0的漏极，所述第二放大器DRIVER_OP的输出端连接所述输出级25；每个所述第二三极管NM1的漏极分别连接所述第二放大器DRIVER_OP的反相输入端，所述第二三极管NM1的栅极通过所述第二开关24连接所述第一放大器OP1的输出端，所述第二三极管NM1的源极接地。图3中以4个第二三极管NM1为例。
可选地，所述第二开关24包括：多个第二子开关K1，每个所述第二三极管NM1的栅极分别连接所述第二子开关K1的一端，所述第二子开关K1的另一端连接所述第一放大器OP1的输出端。
可选地，缓冲器26可以是，连接在所述第一电流镜组21与所述第二电流镜组23之间。
可选地，所述基准电路10包括：基准放大器OP0，所述基准放大器OP0的反相输入端接入基准信号，基准信号可以是基准电压Vref；外置电阻Rext，所述外置电阻Rext的第一端连接所述基准放大器OP0的正相输入端，所述外置电阻Rext的第二端接地。
可选地，所述基准电路10还包括：第三三极管PM0，所述第三三极管PM0的栅极连接所述基准放大器OP0的输出端，所述第三三极管PM0的漏极连接所述外置电阻Rext的所述第一端，所述第三三极管PM0的源极接地；第四三极管PM1，所述第四三极管PM1的栅极连接所述基准放大器OP0的输出端，所述第四三极管PM1的漏极分别连接每个所述第一三极管NM0的漏极，所述第四三极管PM1的源极接地。
可选地，所述输出级25包括：第五三极管NM2，所述第五三极管NM2的栅极连接所述第二放大器DRIVER_OP的输出端，所述第五三极管NM2的源极分别连接每个所述第二三极管NM1的漏极，所述第五三极管NM2的漏极连接被驱动的电路。
如图3所示，为了进一步清楚的描述本实施例供电电路1的原理，假设第一三极管NM0为4个，分别为三极管NM0:1～三极管NM0:4；第二三极管NM1为4个，分别为三极管NM1:1～三极管NM1:4，第一开关22为4个，分别为第一子开关K0:1～第一子开关K0:4；第二开关2为4个，分别为第二子开关K1:1～第二子开关K1:4；以此为基础，以下进行详细原理说明：
首先，假设第一电流镜组21与第二电流镜组23的镜像比例N/M的范围为4～8，其目的是在满足器件性能的情况下，降低芯片的功耗。
其次，将电压VGATE经过一个缓冲器26送至通道中第二三极管NM1的栅极，相比于将电压VGATE直接送至通道中第二三极管NM1的栅极的方式，缓冲器26将恒流源产生电路与恒流源输出通道进行了隔离，避免了不停开关的恒流源输出通道所产生的噪声对恒流源的影响；在多个通道结构中，第一放大器OP1需要驱动多个第二三极管NM1，第二三极管NM1可以是NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)，其会在第一放大器OP1的输出节点贡献很大的寄生电容，所以缓冲器26不但提高了电压VGATE的驱动能力，同时也降低了第一放大器OP1的设计难度。
最后，将第一电流镜组21中的第一三极管NM0以及其通道中镜像电流分成四组，其中第一子开关K0:1与第二子开关K1:1的控制信号相同，第一子开关K0:2与第二子开关K1:2的控制信号相同，第一子开关K0:3与第二子开关K1:3的控制信号相同，第一子开关K0:4与第二子开关K1:4的控制信号相同，上述开关的控制信号由控制器27给出。在不同的场景对电流设置需求不同，通过各个子开关打开不同组数的第一三极管NM0与第二三极管NM1组合，即可组成不同的电流镜，从而使得在输出电流Iout范围较大的前提下提升 恒流源的精度。为便于理解，原理说明如下：
如图4A至图4C所示，为本实施例的供电电路1输出恒流源通道电路的等效电路示意图，其中，图4A所示为恒流源输出通道与发光二极管LED连接电路图，假设只将器件的失配引入的误差作为恒流源主要的误差源，那么输出恒流源通道中主要有两个误差源：Voff1(构成电流镜的NMOS管的阈值电压的等效失调电压)与Voff2(DRIVER_OP1的等效输入失调电压)，图4A所示的电路可以等效为如图4B所示的等效电路，进一步地，可以等效为如图4C所示的等效电路，则此时图4A中输出恒流源的电流等效于图4C所示偏置的NMOS管的电流。
在实际应用中，NMOS管的电流与其栅极、漏极电压的关系(忽略一些二阶效应)如下公式所示：
Figure PCTCN2021130747-appb-000004
μ为沟道载流子迁移率；C OX为单位面积栅氧化层电容；W/L为MOS管的宽长比；V GS为MOS器件栅极-源极之间的电压；V DS为MOS器件漏极-源极之间的电压；V TH为MOS器件的门限电压。
分别计算电压Voff1与电压Voff2引入的电流误差与漏源电流I DS的比值
Figure PCTCN2021130747-appb-000005
与
Figure PCTCN2021130747-appb-000006
可以得到公式(2)及公式(3)，计算过程如下：
Figure PCTCN2021130747-appb-000007
Figure PCTCN2021130747-appb-000008
可以得到：
Figure PCTCN2021130747-appb-000009
Figure PCTCN2021130747-appb-000010
公式(2)和公式(3)说明，第二三极管NM1的栅极-源极电压越大，失调所引入的误差源对输出电流Iout影响越小。
在实际应用场景中，对于通道电流从几毫安变化到几十毫安，如图3所示的供电电路1正常工作时候的电路连接状态，可以得到V DS保持不变，且等于内部设置的电压VCRES。根据公式(1)可得，减小W/L(即等同于减小第二三极管NM1的个数)相当于增大V GS电压，所以在输出电流Iout较小的时候，只开启第一子开关K0:1以及第二子开关K1:1，此时供电电路1的精度最好。当输出电流Iout增加，超出了第一三极管NM0:1、第二三极管NM1:1的能力，再开启第一子开关K0:2和第二子开关K1:2，如此这样，随着设置的输出电流Iout的增大，逐一打开第一子开关K0:1～K0:4以及第二子开关K1:1～K1:4，即在较小输出电流Iout时使用较少组数的NMOS器件开启，可以提高芯片的电流精度。
一般情况下，恒流源的电流范围很大，几至几十毫安，在这么大的范围内，如果使用同样尺寸的MOS器件会造成电流精度变化很大，本实施例提出分组的概念，针对不同的输出电流设置，开启不同数目的MOS管，如此不同的分组适配不同的电流，提高了芯片在较大电流变化情况下的电流精度。
上述供电电路1，通过选择合适的第一三极管NM0与第二三极管NM1的镜像比例M：N，在保证电流精度的前提下，降低了芯片的静态功耗；在电流镜NMOS管的栅极电压VGATE通路上增加一个缓冲器26，降低了第一放大器OP1的驱动能力需求，降低了回馈的噪声，保证了电流精度，同时提高了第一放大器OP1与第一三极管NM0的负反馈环路 的稳定性；恒流源采用分组模式，有效的保证了在输出恒流源的整个电流范围内的电流精度。本申请实施例还提供了一种驱动芯片，包括：如上述实施例的供电电路1。因此其具备如上述实施例中供电电路1所有的有益效果，详细参见上述实施例的描述，此处不再赘述。可选地，该驱动芯片可以为LED显示屏的驱动芯片。
本申请实施例还提供了一种显示屏，包括：上述实施例的供电电路1；其中所述供电电路共阳驱动所述显示屏；或所述供电电路共阴驱动所述显示屏。因此其具备如上述实施例中供电电路1所有的有益效果，详细参见上述实施例的描述，此处不再赘述。可选地，该显示屏可以为LED显示屏。
虽然结合附图描述了本发明的实施例，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。
工业实用性
本申请提供的技术方案降低了输出恒流源开关对输出电流精度的影响，以及提升了内部环路稳定性，有效的提高了在输出恒流源的整个电流范围内的电流精度。

Claims (15)

  1. 一种供电电路，其特征在于，包括：
    基准电路，配置成生成一级镜像电流；
    第一电流镜组，连接所述基准电路；
    第一开关，连接所述第一电流镜组，配置成控制所述第一电流镜组的闭合或断开；
    第二电流镜组，连接所述第一电流镜组；
    第二开关，连接所述第二电流镜组，配置成控制所述第二电流镜组的闭合或断开；
    在所述第一开关与所述第二开关闭合时，所述第一电流镜组与所述第二电流镜组配合形成电流镜，配置成对所述一级镜像电流进行镜像处理，得到输出电流；
    输出级，连接所述第二电流镜组，配置成输出所述输出电流。
  2. 根据权利要求1所述的供电电路，其特征在于，所述第一电流镜组包括：
    第一放大器，所述第一放大器的反相输入端连接预设电压信号；
    多个第一三极管，每个所述第一三极管的漏极分别连接所述第一放大器的正相输入端，所述第一三极管的栅极通过所述第一开关连接所述第一放大器的输出端，所述第一三极管的源极接地。
  3. 根据权利要求2所述的供电电路，其特征在于，所述第一开关包括：
    多个第一子开关，每个所述第一三极管的栅极分别连接所述第一子开关的一端，所述第一子开关的另一端连接所述第一放大器的输出端。
  4. 根据权利要求2或3所述的供电电路，其特征在于，所述第二电流镜组包括：
    第二放大器，所述第二放大器的正相输入端连接所述第一三极管的漏极，所述第二放大器的输出端连接所述输出级；
    多个第二三极管，每个所述第二三极管的漏极分别连接所述第二放大器的反相输入端，所述第二三极管的栅极通过所述第二开关连接所述第一放大器的输出端，所述第二三极管的源极接地。
  5. 根据权利要求4所述的供电电路，其特征在于，所述第二三极管为NMOS器件。
  6. 根据权利要求4或5所述的供电电路，其特征在于，所述第二开关包括：
    多个第二子开关，每个所述第二三极管的栅极分别连接所述第二子开关的一端，所述第二子开关的另一端连接所述第一放大器的输出端。
  7. 根据权利要求1至6任一项所述的供电电路，其特征在于，还包括：
    缓冲器，连接在所述第一电流镜组与所述第二电流镜组之间。
  8. 根据权利要求2至6任一项所述的供电电路，其特征在于，所述基准电路包括：
    基准放大器，所述基准放大器的反相输入端接入基准信号；
    外置电阻，所述外置电阻的第一端连接所述基准放大器的正相输入端，所述外置电阻的第二端接地。
  9. 根据权利要求8所述的供电电路，其特征在于，所述基准电路还包括：
    第三三极管，所述第三三极管的栅极连接所述基准放大器的输出端，所述第三三极管的漏极连接所述外置电阻的所述第一端，所述第三三极管的源极接地；
    第四三极管，所述第四三极管的栅极连接所述基准放大器的输出端，所述第四三极管的漏极分别连接每个所述第一三极管的漏极，所述第四三极管的源极接地。
  10. 根据权利要求4至6任一项所述的供电电路，其特征在于，所述输出级包括：
    第五三极管，所述第五三极管的栅极连接所述第二放大器的输出端，所述第五三极管的源极分别连接每个所述第二三极管的漏极，所述第五三极管的漏极连接被驱动的电路。
  11. 根据权利要求1至10任一项所述的供电电路，其特征在于，还包括：
    控制器，分别连接所述第一开关和所述第二开关，配置成向所述第一开关和所述第二开关发送控制信号。
  12. 一种驱动芯片，其特征在于，包括：如权利要求1至11中任一项所述的供电电路。
  13. 根据权利要求12所述的驱动芯片，其特征在于，所述驱动芯片为LED显示屏的驱动芯片。
  14. 一种显示屏，其特征在于，包括：如权利要求1所述的供电电路；
    所述供电电路共阳驱动所述显示屏；
    或所述供电电路共阴驱动所述显示屏。
  15. 根据权利要求14所述的显示屏，其特征在于，所述显示屏为LED显示屏。
PCT/CN2021/130747 2020-12-17 2021-11-15 供电电路、芯片和显示屏 WO2022127470A1 (zh)

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