WO2022126895A1 - 64B/66B转换的serdes架构 - Google Patents

64B/66B转换的serdes架构 Download PDF

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WO2022126895A1
WO2022126895A1 PCT/CN2021/082551 CN2021082551W WO2022126895A1 WO 2022126895 A1 WO2022126895 A1 WO 2022126895A1 CN 2021082551 W CN2021082551 W CN 2021082551W WO 2022126895 A1 WO2022126895 A1 WO 2022126895A1
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pcs
pma
layer
data
module
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PCT/CN2021/082551
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English (en)
French (fr)
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李宁
宣学雷
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深圳市紫光同创电子有限公司
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Priority to KR1020237017733A priority Critical patent/KR20230093046A/ko
Publication of WO2022126895A1 publication Critical patent/WO2022126895A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Definitions

  • the present application relates to the technical field of IP design of FPGA chips, in particular to a 64B/66B converted serdes architecture.
  • High Speed Serial Transceiver is an important functional part of high-speed chips including Field Programmable Gate Array (FPGA). It is composed of IP such as PMA) and Physical Coding Sub-layer (PCS). PCS supports the flexible Word Alignment function; Channel Bonding: realizes channel alignment, CTC (Clock Tolerance Compensation): realizes common functions such as compensating for the slight frequency difference between the sending clock and the receiving clock.
  • FPGA Field Programmable Gate Array
  • PCS Physical Coding Sub-layer
  • 64B_66B codec is a common function that needs to be supported.
  • the sending side needs to switch the clock frequency through the tx buffer in the transmission gear box tx_gear_box. Because the clock frequency becomes faster, the read operation is suspended every 33 clock cycles, and idle bytes are inserted to ensure that the Bandwidth matching. After that, the 66bit data is integrated into 64bit data, and the idle byte is deleted to adapt to the requirements of the PCS/PMA interface.
  • the receiving side is opposite to the sending side.
  • the 64bit data is first spliced into 66bit data, and written into the rx buffer to switch the clock domain. Since it switches to a clock domain with a lower clock frequency, every 33 clock cycles Suspend one-beat write operations to ensure that the receive channel bandwidth matches.
  • the PCS and PMA interfaces are 64bit (16bit, 20bit, 32bit, 40bit) bit wide, and the interface rate is the ratio of the high-speed differential line rate to the bit width.
  • the internal processing of PCS includes two clock domains, and the gear module is required for the clock domain. Switching, data reintegration, bit width conversion, and chip design complexity are relatively high.
  • the purpose of this application is to provide a 64B/66B converted serdes architecture.
  • the present application provides a 64B/66B converted serdes architecture, including XLGMII, PCS layer and PMA layer, and the interface bit width of the PCS layer and the PMA layer is configured to be 66 bits.
  • the PCS layer includes a PCS sending device, and the PCS sending device includes an encoding module and a scrambling module,
  • the encoding module is used to encode the interface data of the XLGMII into 64B-66B block data;
  • the scrambling module is used to scramble the 64B_66B block data.
  • the PMA layer includes a PMA sending device.
  • the PCS sending device and the PMA sending device are in the same clock domain.
  • the PCS layer includes a PCS receiving device, and the PCS receiving device includes a block synchronization module, a descrambling code module and a decoding module,
  • the block synchronization module is used for synchronously defining the received 64B-66B block data according to the block synchronization header information
  • the descrambling module is used to descramble the 64B-66B block data
  • the decoding module is configured to decode the descrambled 64B_66B block data and send it to the XLGMII.
  • the PMA layer includes a PMA receiving device.
  • the PCS receiving device and the PMA receiving device are in the same clock domain.
  • a 64B/66B converted serdes architecture is provided, and the 64B/66B converted serdes architecture reduces the number of internal clocks of the PCS by configuring the PCS and the data width of the interface with the PMA to be 66 bits, and effectively reduces the internal clocks of the PCS.
  • the operating frequency and logic complexity of the PCS reduce the timing requirements of the digital design inside the PCS, which can effectively reduce the chip design cost and improve the chip performance and reliability.
  • FIG. 1 is a schematic structural diagram of a serdes architecture of 64B/66B conversion provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of frequency generation of a sending direction clock provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of frequency generation of a clock in a receive direction according to an embodiment of the present application.
  • the embodiment of the present application provides a 64B/66B converted serdes architecture, including XLGMII (Media Independent Interface, media independent interface), a PCS layer and a PMA layer, and the interface bit width of the PCS layer and the PMA layer is configured to be 66 bits.
  • XLGMII Media Independent Interface, media independent interface
  • PCS layer and PMA layer the interface bit width of the PCS layer and the PMA layer is configured to be 66 bits.
  • the serdes architecture of the 64B/66B conversion of the present application reduces the number of internal clocks in the PCS by configuring the PCS and the data width of the interface with the PMA to be 66 bits, effectively reducing the operating frequency and logic complexity inside the PCS, and reducing the timing of the digital design inside the PCS. requirements, can effectively reduce the cost of chip design, improve chip performance and reliability.
  • a line rate with a frequency of 1/66 between the PCS layer and the PMA layer is configured.
  • the PCS layer includes a PCS sending device, and the PCS sending device includes an encoding module and a scrambling module,
  • the encoding module is used to encode the XLGMII data into 64B-66B block data
  • the scrambling module is used to scramble the 64B_66B block data.
  • the PCS layer includes a PCS receiving device, and the PCS receiving device includes a block synchronization module, a descrambling module, and a decoding module,
  • the block synchronization module is used to synchronize and define the received 64B-66B block data according to the block synchronization information
  • the descrambling module is used to descramble the 64B-66B block data
  • the decoding module is configured to decode the descrambled 64B_66B block data and send it to the XLGMII.
  • the PMA layer includes a PMA sending device.
  • the PCS sending device and the PMA sending device are in the same clock domain.
  • the PMA layer includes a PMA receiving device.
  • the PCS receiving device and the PMA receiving device are in the same clock domain.
  • the serdes architecture for 64B/66B conversion includes XLGMII (Media Independent Interface), PCS layer and PMA layer, and interfaces of the PCS layer and the PMA layer are configured
  • the bit width is 66 bits
  • the frequency between the PCS layer and the PMA layer is a line rate of 1/66.
  • the PCS layer includes a PCS sending device PCS Transmit and a PCS receiving device PCS Receive.
  • the PCS transmitting device PCS Transmit includes an encoding module encode and a scrambling module scramble.
  • the encoding module encode is used to encode the interface data of the XLGMII into 64B_66B block data; 8 data bytes or control words and a 2-bit synchronization header (sync_header) form a block of data.
  • the scramble module scramble is used to scramble the 64B_66B block data to reduce the number of "1" and "0" in the 64B_66B block data, and the sync header (sync_header) is not scrambled.
  • the PCS receiving device PCS Receive comprises a block synchronization module block_sync, a descramble module descramble and a decoding module decode.
  • the block synchronization module block_sync is used to synchronously define the received 64B_66B block data according to the block synchronization header (sync_header) information;
  • the descrambling module is used to descramble the 64B-66B block data
  • the decoding module is configured to decode the descrambled 64B_66B block data and send it to the XLGMII.
  • the PMA layer includes a PMA sending device PMA Transmitter and a PMA receiving device PMA Receiver.
  • the PCS transmitting device PCS Transmit and the PMA transmitting device PMA Transmitter are in the same clock domain, that is, each module in the transmitting direction works in the same clock domain, and the clock frequency is the transmission serial data tx_serial_data rate/66, Frequency switching is not required, resources are saved, and design complexity is reduced.
  • the PCS receiving device PCS Receive, the PMA receiving device PMA Receiver are in the same clock domain, that is, each module in the receiving direction all works in the same clock domain, and the clock frequency is to receive serial data rx_serial_data rate/66, does not need Frequency switching is performed to save resources and reduce design complexity.
  • the PCS layer uses the clock generated by the PMA layer.
  • the frequency of the parallel clock pma_tclk in the transmitting direction is the rate of sending serial data tx_serial_data/66
  • the frequency of the parallel clock pma_rclk in the receiving direction The frequency of receiving serial data rx_serial_data rate/66.
  • the number of internal clocks in the PCS layer is reduced, the operating frequency and logic complexity in the PCS layer are effectively reduced, and the timing requirements for digital design in the PCS layer are reduced. Reduce chip design costs and improve chip performance and reliability.
  • FIG. 2 it is a schematic diagram of the frequency generation of the parallel clock pma_tclk in the transmitting direction.
  • the first initial frequency divider D10 is used to set the proportional relationship between the transmitted serial data tx_serial_data (txp/n) and the phase-locked loop clock pllclock to generate high-speed Serial clock s_clk to parallel serial output PISO; and after frequency division by the first frequency divider D11 and the first frequency divider D12, obtain the transmission direction parallel clock pma_tclk that provides the PCS layer; and transmit data tx_data[65: 0] Serial data tx_serial_data(txp/n) is transmitted via the parallel serial output PISO output.
  • the bit width of the interface is 66 bits, set D11 to 11 and set D12 to 3, that is, to generate a parallel clock pma_tclk in the sending direction with the frequency of sending serial data tx_serial_data rate/66.
  • FIG. 3 it is a schematic diagram of the frequency generation of the clock pma_rclk in the receiving direction.
  • the second initial frequency divider D20 is used to set the proportional relationship between the received serial data rx_serial_data (rxd) and the CDR recovery clock rec_clk to generate the high-speed serial clock rec_sclk to the serial and parallel output SIPO; and after frequency division by the second frequency divider D21 and the second frequency divider D22, the parallel clock pma_rclk in the receiving direction that provides the PCS layer is obtained; and the serial data rx_serial_data (rxd) is received by serial Row parallel output SIPO output receive data rx_data[65:0].
  • the bit width of the interface is 66 bits, set D21 to 11 and set D22 to 3, that is, to generate a parallel clock pma_rclk in the receive direction with the frequency of receiving serial data rx_serial_data rate/66.
  • the serdes architecture of 64B/66B conversion configures the interface data bit width between the PCS layer and the PMA layer to 66 bits, and the corresponding interface clock frequency is the rate of sending serial data tx_serial_data/66, which reduces the internal clock of the PCS layer.
  • the bit width is the same as that of the PCS/XLGMII interface
  • the speed of the PCS/XLGMII interface is the same as that of the PCS/PMA interface.

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Abstract

本申请提供了一种64B/66B转换的serdes架构，包括XLGMII、PCS层和PMA层，配置所述PCS层和所述PMA层的接口位宽为66bit。本申请的64B/66B转换的serdes架构，64B/66B转换的serdes架构通过配置PCS及与PMA的接口数据宽度为66bit，减少了PCS内部时钟数量，有效降低PCS内部的工作频率和逻辑复杂度，降低了PCS内部数字设计的时序要求，可有效降低芯片设计成本，提高芯片性能及可靠性。

Description

64B/66B转换的serdes架构 【技术领域】
本申请涉及及FPGA芯片的IP设计技术领域，尤其涉及一种64B/66B转换的serdes架构。
【背景技术】
高速串行收发器(High Speed Serial Transceiver)是当前包括现场可编程门阵列(Field Programmable Gate Array,FPGA)在内的高速芯片中的重要功能组成部分，由物理媒介适配层(Physical Medium Attachment，PMA)和物理编码子层(Physical Coding Sub-layer，PCS)等IP组成。PCS支持灵活的Word Alignment功能；Channel Bonding：实现通道对齐，CTC(Clock Tolerance Compensation)：实现补偿发送时钟和接收时钟的微小频差等常见功能。
在serdes IP中，64B_66B编解码是需要支持的常见功能。现有技术中的架构，发送侧需要在发送变速盒tx_gear_box中通过tx buffer进行时钟频率切换，因时钟频率变快了，所以每33个时钟周期暂停一拍读操作，插入idle字节，以保证带宽匹配。之后将66bit数据整合为64bit数据，再删去idle字节，以适配PCS/PMA接口的要求。
接收侧与发送侧相反，在接收变速盒rx_gear_box中，先将64bit数据拼接为66bit数据，并写入rx buffer进行时钟域切换，由于切换到时钟频率较低的时钟域，所以每33个时钟周期暂停一拍写操作，从而保证接收通道带宽匹配。
此种结构中PCS与PMA接口是64bit(16bit、20bit，32bit，40bit)位宽，接口速率为高速差分线速率与位宽的比值，PCS内部处理包括两个时钟域，须要gear模块进行时钟域切换，数据重新整合，位宽转换，芯片设计复杂度相对较高。
【申请内容】
本申请的目的在于提供了一种64B/66B转换的serdes架构。
为达到上述目的，本申请提供一种64B/66B转换的serdes架构，包括XLGMII、PCS层和PMA层，配置所述PCS层和所述PMA层的接口位宽为66bit。
优选的，所述PCS层包括PCS发送装置，所述PCS发送装置包括编码模块和扰码模块，
所述编码模块，用于将所述XLGMII的接口数据编码为64B_66B块数据；
所述扰码模块，用于将所述64B_66B块数据进行扰码。
优选的，所述PMA层包括PMA发送装置。
优选的，所述PCS发送装置、PMA发送装置处于同一个时钟域。
优选的，所述PCS层包括PCS接收装置，所述PCS接收装置包括块同步模块、解扰码模块和解码模块，
所述块同步模块，用于根据块同步头信息对接收的64B_66B块数据进行同步界定；
所述解扰码模块，用于对所述64B_66B块数据进行解扰码；
所述解码模块，用于将所述解扰码后的64B_66B块数据进行解码并发送至所述XLGMII。
优选的，所述PMA层包括PMA接收装置。
优选的，所述PCS接收装置、PMA接收装置处于同一个时钟域。
本申请的有益效果在于：提供了一种64B/66B转换的serdes架构，64B/66B转换的serdes架构通过配置PCS及与PMA的接口数据宽度为66bit，减少了PCS内部时钟数量，有效降低PCS内部的工作频率和逻辑复杂度，降低了PCS内部数字设计的时序要求，可有效降低芯片设计成本，提高芯片性能及可靠性。
【附图说明】
图1为本申请实施例提供的64B/66B转换的serdes架构的结构示意图；
图2为本申请实施例提供的发送方向时钟的频率生成示意图；
图3为本申请实施例提供的接收方向时钟的频率生成示意图。
【具体实施方式】
下面结合附图和实施方式对本申请作进一步说明。
需要说明的是，本申请实施例中所有方向性指示(诸如上、下、左、右、前、后、内、外、顶部、底部……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
本申请实施例提供一种64B/66B转换的serdes架构，包括XLGMII(Media Independent Interface，介质独立接口)、PCS层和PMA层，配置所述PCS层和所述PMA层的接口位宽为66bit。
本申请的64B/66B转换的serdes架构通过配置PCS及与PMA的接口数据宽度为66bit，减少了PCS内部时钟数量，有效降低PCS内部的工作频率和逻辑复杂度，降低了PCS内部数字设计的时序要求，可有效降低芯片设计成本，提高芯片性能及可靠性。
进一步地，配置所述PCS层和所述PMA层之间频率为1/66的线速率。
本实施例中，所述PCS层包括PCS发送装置，所述PCS发送装置包括编码模块和扰码模块，
所述编码模块，用于将所述XLGMII数据编码为64B_66B块数据；
所述扰码模块，用于将所述64B_66B块数据进行扰码。
本实施例中，所述PCS层包括PCS接收装置，所述PCS接收装置包括块同步模块、解扰码模块和解码模块，
所述块同步模块，用于根据块同步信息对接收的64B_66B块数据进行同步界定；
所述解扰码模块，用于对所述64B_66B块数据进行解扰码；
所述解码模块，用于将所述解扰码后的64B_66B块数据进行解码并发送至所述XLGMII。
优选的，所述PMA层包括PMA发送装置。其中，所述PCS发送装置、PMA发送装置处于同一个时钟域。
优选的，所述PMA层包括PMA接收装置。其中，所述PCS接收装置、PMA接收装置处于同一个时钟域。
如图1所示，本申请实施例提供的64B/66B转换的serdes架构，包括 XLGMII(Media Independent Interface，介质独立接口)、PCS层和PMA层，配置所述PCS层和所述PMA层的接口位宽为66bit，所述PCS层和所述PMA层之间频率为1/66的线速率。
所述PCS层包括PCS发送装置PCS Transmit和PCS接收装置PCS Receive。
其中，所述PCS发送装置PCS Transmit包括编码模块encode和扰码模块scramble。
所述编码模块encode，用于将所述XLGMII的接口数据编码为64B_66B块数据；8个数据字节或控制字、以及2bit的同步头(sync_header)组成一个块数据。
其中，发送方向XLGMII的接口数据包括，TXD[127:0]：数据发送通道，128位并行数据；TXC[15:0]：发送通道控制信号，TXC＝0时，表示TXD上传输的是数据，TXC＝1时，表示TXD上传输的是控制字符；TX_CLK：TXD和TXC的参考时钟，在时钟信号的上升沿和下降沿都采样数据。
所述扰码模块scramble，用于将所述64B_66B块数据进行扰码，以降低64B_66B块数据中数据连“1”连“0”的数目，同步头(sync_header)不扰码。
所述PCS接收装置PCS Receive包括块同步模块block_sync、解扰码模块descramble和解码模块decode。
所述块同步模块block_sync，用于根据块同步头(sync_header)信息对接收的64B_66B块数据进行同步界定；
所述解扰码模块，用于对所述64B_66B块数据进行解扰码；
所述解码模块，用于将所述解扰码后的64B_66B块数据进行解码并发送至所述XLGMII。
其中，接收方向XLGMII的接口数据包括，RXD[127:0]：数据接收通道，128位并行数据；RXC[15:0]：接收通道控制信号，RXC＝0时，表示RXD上传输的是数据，RXC＝1时，表示RXD上传输的是控制字符；RX_CLK：RXD和RXC的参考时钟，在时钟信号的上升沿和下降沿都采样数据。
优选的，所述PMA层包括PMA发送装置PMA Transmitter和PMA接收装置PMA Receiver。
其中，所述PCS发送装置PCS Transmit、PMA发送装置PMA Transmitter处于同一个时钟域，也即，发送方向各个模块均工作在同一个时钟域，且时钟频率均为发送串行数据tx_serial_data速率/66，不需要进行频率切换，节省资源，降低了设计复杂度。所述PCS接收装置PCS Receive、PMA接收装置PMA Receiver处于同一个时钟域，也即，接收方向各个模块均工作在同一个时钟域，且时钟频率均为接收串行数据rx_serial_data速率/66，不需要进行频率切换，节省资源，降低了设计复杂度。
进一步的，PCS层使用时钟由PMA层生成，位宽66bit时，发送方向并行时钟pma_tclk的频率为发送串行数据tx_serial_data速率/66，接收方向并行时钟pma_rclk的频率接收串行数据rx_serial_data速率/66。
通过配置PCS层内部及与PMA层的接口数据宽度为66bit，减少了PCS层内部时钟数量，有效降低PCS层内部的工作频率和逻辑复杂度，降低了PCS层内部数字设计的时序要求，可有效降低芯片设计成本，提高芯片性能及可靠性。
如图2所示，为发送方向并行时钟pma_tclk的频率生成示意图，第一初始分频器D10，用于设置发送串行数据tx_serial_data(txp/n)与锁相环时钟pllclock的比例关系，生成高速串行时钟s_clk至并行串行输出PISO；并经第一一分频器D11、第一二分频器D12分频后，获得提供PCS层的发送方向并行时钟pma_tclk；以及发送数据tx_data[65:0]经并行串行输出PISO输出发送串行数据tx_serial_data(txp/n)。当接口位宽66bit时，设置D11为11，设置D12为3，即生成频率为发送串行数据tx_serial_data速率/66的发送方向并行时钟pma_tclk。
如图3所示，为接收方向时钟pma_rclk的频率生成示意图，第二初始分频器D20，用于设置接收串行数据rx_serial_data(rxd)与CDR恢复时钟rec_clk的比例关系，生成高速串行时钟rec_sclk至串行并行输出SIPO；并经第二一分频器D21、第二二分频器D22分频后，获得提供PCS层的接收方向并行时钟pma_rclk；以及接收串行数据rx_serial_data(rxd)经串行并行输出SIPO输出接收数据rx_data[65:0]。当接口位宽66bit时，设置D21为11，设置D22为3，即生成频率为接收串行数据rx_serial_data速率/66的接收方向并行时 钟pma_rclk。
本申请实施例提供的64B/66B转换的serdes架构将PCS层与PMA层之间接口数据位宽配置为66bit，对应接口时钟频率为发送串行数据tx_serial_data速率/66，即降低了PCS层内部时钟频率，同时又因与PCS/XLGMII接口位宽一致，因此PCS/XLGMII接口速率与PCS/PMA接口速率相同。该架构整个PCS层内部只有一个时钟域，省去了变速箱模块gear box，节省资源，降低了设计复杂度。
以上所述的仅是本申请的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本申请创造构思的前提下，还可以做出改进，但这些均属于本申请的保护范围。

Claims (7)

  1. 一种64B/66B转换的serdes架构，其特征在于，包括XLGMII、PCS层和PMA层，配置所述PCS层和所述PMA层的接口位宽为66bit。
  2. 根据权利要求1所述的64B/66B转换的serdes架构，其特征在于，所述PCS层包括PCS发送装置，所述PCS发送装置包括编码模块和扰码模块，
    所述编码模块，用于将所述XLGMII的接口数据编码为64B_66B块数据；
    所述扰码模块，用于将所述64B_66B块数据进行扰码。
  3. 根据权利要求2所述的64B/66B转换的serdes架构，其特征在于，所述PMA层包括PMA发送装置。
  4. 根据权利要求3所述的64B/66B转换的serdes架构，其特征在于，所述PCS发送装置、PMA发送装置处于同一个时钟域。
  5. 根据权利要求1所述的64B/66B转换的serdes架构，其特征在于，所述PCS层包括PCS接收装置，所述PCS接收装置包括块同步模块、解扰码模块和解码模块，
    所述块同步模块，用于根据块同步头信息对接收的64B_66B块数据进行同步界定；
    所述解扰码模块，用于对所述64B_66B块数据进行解扰码；
    所述解码模块，用于将所述解扰码后的64B_66B块数据进行解码并发送至所述XLGMII。
  6. 根据权利要求5所述的64B/66B转换的serdes架构，其特征在于，所述PMA层包括PMA接收装置。
  7. 根据权利要求6所述的64B/66B转换的serdes架构，其特征在于，所述PCS接收装置、PMA接收装置处于同一个时钟域。
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