WO2022059528A1 - 画像表示装置の製造方法および画像表示装置 - Google Patents

画像表示装置の製造方法および画像表示装置 Download PDF

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Publication number
WO2022059528A1
WO2022059528A1 PCT/JP2021/032529 JP2021032529W WO2022059528A1 WO 2022059528 A1 WO2022059528 A1 WO 2022059528A1 JP 2021032529 W JP2021032529 W JP 2021032529W WO 2022059528 A1 WO2022059528 A1 WO 2022059528A1
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Prior art keywords
light emitting
insulating film
layer
wiring
image display
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PCT/JP2021/032529
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English (en)
French (fr)
Japanese (ja)
Inventor
肇 秋元
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Nichia Corp
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Nichia Corp
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Priority to CN202180059966.0A priority Critical patent/CN116195075A/zh
Priority to EP21869215.0A priority patent/EP4216290A4/en
Priority to JP2022550477A priority patent/JP7669643B2/ja
Publication of WO2022059528A1 publication Critical patent/WO2022059528A1/ja
Priority to US18/176,697 priority patent/US20230215907A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/854—Encapsulations characterised by their material, e.g. epoxy or silicone resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0361—Manufacture or treatment of packages of wavelength conversion means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H10H20/841—Reflective coatings, e.g. dielectric Bragg reflectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8511—Wavelength conversion means characterised by their material, e.g. binder
    • H10H20/8512—Wavelength conversion materials
    • H10H20/8513—Wavelength conversion materials having two or more wavelength conversion materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8515—Wavelength conversion means not being in contact with the bodies

Definitions

  • the embodiment of the present invention relates to a method for manufacturing an image display device and an image display device.
  • a display device using a micro LED which is a fine light emitting element
  • a method of manufacturing a display device using micro LEDs a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced.
  • the number of micro LED elements increases as the image quality becomes higher, such as full high-definition, 4K, 8K, etc.
  • the transfer process requires a huge amount of time. Further, a poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.
  • a technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the electrodes are attached to a circuit board on which a drive circuit is formed (see, for example, Patent Document 1).
  • One embodiment of the present invention provides a method for manufacturing an image display device and an image display device in which the transfer process of the light emitting element is shortened and the yield is improved.
  • the method for manufacturing an image display device includes a step of preparing a semiconductor layer including a light emitting layer, a step of bonding the semiconductor layer to the first surface of a translucent substrate, and a step of bonding the semiconductor layer.
  • the first via is provided between the first wiring layer and the upper surface, and electrically connects the first wiring layer and the upper surface.
  • An image display device includes a light-transmitting member having a first surface, a light-emitting element having a light-emitting surface on the first surface and an upper surface on the opposite side of the light-emitting surface, and the first surface.
  • a first insulating film covering one surface and the light emitting element, a circuit element provided on the first insulating film, a second insulating film covering the first insulating film and the circuit element, and the first insulating film.
  • the first via is provided so as to penetrate the second insulating film, and the first wiring layer is provided on the second insulating film.
  • the first via is provided between the first wiring layer and the upper surface, and electrically connects the first wiring layer and the upper surface.
  • the image display device includes a light transmissive member having a first surface, a first semiconductor layer including a light emitting surface capable of forming a plurality of light emitting regions on the first surface, and the above-mentioned.
  • a plurality of light emitting layers provided on the first semiconductor layer and provided apart from each other, and a plurality of second semiconductor layers provided on the plurality of light emitting layers and having a conductive shape different from that of the first semiconductor layer.
  • a second insulating film covering the first insulating film and the plurality of transistors, a plurality of first vias provided through the first insulating film and the second insulating film, and the second insulating film. It includes a first wiring layer provided above. The plurality of second semiconductor layers and the plurality of light emitting layers are separated by the first insulating film. The plurality of first vias are provided between the first wiring layer and the plurality of second semiconductor layers, respectively, and electrically connect the first wiring layer and the plurality of second semiconductor layers, respectively.
  • An image display device includes a light-transmitting member having a first surface, a plurality of light-emitting elements including a light-emitting surface on the first surface and an upper surface on the opposite side of the light-emitting surface.
  • a first insulating film covering the first surface and the plurality of light emitting elements, a circuit element provided on the first insulating film, a first insulating film and a second insulating film covering the circuit element, and the like. It includes a first insulating film, a plurality of first vias provided so as to penetrate the second insulating film, and a first wiring layer provided on the second insulating film. The plurality of first vias are provided between the first wiring layer and the upper surface, and electrically connect the first wiring layer and the upper surface, respectively.
  • a method for manufacturing an image display device that shortens the transfer process of the light emitting element and improves the yield is realized.
  • an image display device that shortens the transfer process of the light emitting element and improves the yield is realized.
  • FIG. 6 It is a schematic cross-sectional view which illustrates a part of the manufacturing method of the image display apparatus of 5th Embodiment.
  • 6 is a schematic cross-sectional view illustrating a part of the image display device according to the sixth embodiment. 6 is a schematic cross-sectional view illustrating a part of the image display device of the sixth embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus which concerns on 7th Embodiment. It is a schematic cross-sectional view which illustrates a part of the image display apparatus of 7th Embodiment.
  • It is a block diagram which illustrates the image display device which concerns on the modification of 8th Embodiment.
  • FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • FIG. 1 schematically shows the configuration of the sub-pixel 20 of the image display device of the present embodiment.
  • the second embodiment, the fourth embodiment, the sixth embodiment, and the seventh embodiment show an example in which the color filter is not attached.
  • the sub-pixel is one pixel.
  • a light emitting element including one light emitting element is referred to as a subpixel regardless of whether one subpixel forms one pixel or a plurality of subpixels form one pixel. ..
  • the light emitting elements 150 are arranged in a two-dimensional plane as shown in FIG. 9 described later.
  • the light emitting element 150 is provided for each subpixel 20.
  • the two-dimensional plane in which the subpixels 20 are arranged is defined as the XY plane.
  • the subpixels 20 are arranged along the X-axis direction and the Y-axis direction.
  • FIG. 1 shows a cross section seen from an arrow on the AA'line of FIG. 3, which will be described later, and is a cross-sectional view in which cross sections in a plurality of planes perpendicular to the XY plane are connected on one plane. Also in other figures, as in FIG.
  • the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z axis is the XY plane.
  • the positive direction of the Z axis may be referred to as “up” or “upward”
  • the negative direction of the Z axis may be referred to as “down” or “downward”
  • gravity is not necessarily applied in the direction along the Z axis. It is not limited to the direction.
  • the length in the direction along the Z axis may be referred to as height.
  • the subpixel 20 has a light emitting surface 151S substantially parallel to the XY plane.
  • the light emitting surface 151S is a surface that mainly emits light in the negative direction of the Z axis orthogonal to the XY plane. In this embodiment and all embodiments described below, the light emitting surface emits light in the negative direction of the Z axis.
  • the subpixel 20 of the image display device includes a substrate 102, a light emitting element 150, a first interlayer insulating film 156, a transistor (circuit element) 103, a second interlayer insulating film 108, and vias. 161a and a first wiring layer 110 are included.
  • the substrate 102 has two surfaces, and a bonding layer 303 is provided on one surface 102a.
  • the bonded layer 303 has a first surface 103a.
  • the first surface 103a is a flat surface substantially parallel to the XY plane.
  • the color filter is formed on the other surface 102b of the substrate 102.
  • the other surface 102b is the opposite surface of the one surface 102a.
  • the color filter is provided on the surface of the two surfaces of the substrate opposite to the surface on which the light emitting element is formed, as described above. You may.
  • the substrate 102 is a translucent substrate, for example, a glass substrate.
  • the bonded layer 303 is made of a light-transmitting material, and is a layer made of an oxide or a nitride of an inorganic material such as SiO 2 .
  • the bonded layer 303 provides a flat surface for arranging a large number of light emitting elements 150 on the first surface 103a.
  • the bonding layer 303 is provided for facilitating bonding in the wafer bonding step of the manufacturing method of the image display device of the present embodiment.
  • the light emitting element 150 is provided on the first surface 103a.
  • the light emitting element 150 is driven by a transistor 103 provided via the first interlayer insulating film 156.
  • the transistor 103 is a thin film transistor (TFT) and is formed on the first interlayer insulating film 156.
  • TFT thin film transistor
  • the light emitting element 150 includes a light emitting surface 151S provided on the first surface 103a.
  • the light emitting element 150 includes an upper surface 153U provided on the opposite side of the light emitting surface 151S.
  • the outer peripheral shapes of the light emitting surface 151S and the upper surface 153U in XY plan view are square or rectangular, and the light emitting element 150 is a prismatic element having the light emitting surface 151S on the first surface 103a.
  • the cross section of the prism may be a polygon of pentagon or more.
  • the light emitting element 150 is not limited to a prismatic element, and may be a columnar element.
  • the light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153.
  • the n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the light emitting surface 151S toward the upper surface 153U.
  • the light emitting surface 151S, which is the n-type semiconductor layer 151, is provided in contact with the first surface 103a. Therefore, the light emitting element 150 emits light in the negative direction of the Z axis via the bonded layer 303 and the substrate 102.
  • the n-type semiconductor layer 151 includes a connection portion 151a.
  • the connecting portion 151a is provided so as to project on the first surface 103a in one direction from the n-type semiconductor layer 151.
  • the height of the connecting portion 151a from the first surface 103a is the same as the height of the n-type semiconductor layer 151 from the first surface 103a, or lower than the height of the n-type semiconductor layer 151 from the first surface 103a.
  • the connection portion 151a is a part of the n-type semiconductor layer 151.
  • the connecting portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connecting portion 151a.
  • the shape of the light emitting element 150 in XY plane view is, for example, substantially a square or a rectangle.
  • the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corner portion of the light emitting element 150 may be rounded.
  • the shape of the light emitting element 150 in the XY plane view is a columnar shape, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse.
  • a gallium nitride based compound semiconductor including a light emitting layer such as In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) is preferably used.
  • the above-mentioned gallium nitride based compound semiconductor may be simply referred to as gallium nitride (GaN).
  • the light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode.
  • the wavelength of the light emitted by the light emitting element 150 may be any wavelength in the range from the near-ultraviolet region to the visible light region, and is, for example, about 467 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 150 may be bluish purple emission of about 410 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be appropriate.
  • the first interlayer insulating film (first insulating film) 156 covers the first surface 103a and the light emitting element 150.
  • the first interlayer insulating film 156 electrically separates the light emitting elements 150 arranged adjacent to each other.
  • the first interlayer insulating film 156 electrically separates the light emitting element 150 from a circuit element such as a transistor 103.
  • the first interlayer insulating film 156 provides a flat surface for forming a circuit 101 including a circuit element such as a transistor 103.
  • the first interlayer insulating film 156 protects the light emitting element 150 from thermal stress and the like when forming the transistor 103 and the like by covering the light emitting element 150.
  • the first interlayer insulating film 156 is preferably formed of an organic insulating material.
  • the organic insulating material used for the first interlayer insulating film 156 is preferably a white resin.
  • the white resin As the first interlayer insulating film 156, it is possible to reflect the laterally emitted light of the light emitting element 150 and the return light caused by the interface between the bonded layers 303 and the substrates 102. Therefore, the luminous efficiency of the light emitting element 150 is substantially improved. Further, since the first interlayer insulating film 156 has light reflectivity, it is possible to reflect scattered light or the like upward of the light emitting element 150 and suppress the arrival of light at the transistor 103.
  • the white resin is formed by dispersing scatterable fine particles having a Mie scattering effect in a silicon-based resin such as SOG (Spin On Glass) or a transparent resin such as a novolak-type phenol-based resin.
  • the scattering fine particles are colorless or white, and have a diameter of about 1/10 to several times the wavelength of the light emitted by the light emitting element 150.
  • the scatterable fine particles preferably used have a diameter of about 1 ⁇ 2 of the wavelength of light.
  • examples of such scattering fine particles include TiO 2 , Al 2 O 3 , ZnO, and the like.
  • the white resin can also be formed by utilizing a large number of fine pores and the like dispersed in the transparent resin.
  • an ALD Atomic-Layer-Deposition
  • a SiO 2 film formed by CVD may be used on top of the SOG or the like.
  • the first interlayer insulating film 156 may be a black resin.
  • the black resin as the first interlayer insulating film 156, the scattering of light in the subpixel 20 is suppressed, and the stray light is suppressed more effectively.
  • An image display device in which stray light is suppressed can display a sharper image.
  • the TFT lower layer film 106 is formed over the first interlayer insulating film 156.
  • the TFT underlayer film 106 is provided for the purpose of ensuring flatness when the transistor 103 is formed and protecting the TFT channel 104 of the transistor 103 from contamination or the like during heat treatment.
  • the TFT lower layer film 106 is, for example, an insulating film such as SiO 2 .
  • the transistor 103 is formed on the TFT lower layer film 106.
  • circuit elements such as other transistors and capacitors are formed on the TFT lower layer film 106, and the circuit 101 is formed by wiring or the like.
  • the transistor 103 corresponds to the drive transistor 26.
  • the selection transistor 24, the capacitor 28, and the like are circuit elements.
  • the circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a first wiring layer 110.
  • the transistor 103 is a p-channel TFT in this example.
  • the transistor 103 includes a TFT channel 104 and a gate 107.
  • the TFT channel 104 is preferably formed by a Low Temperature Poly Silicon (LTPS) process.
  • LTPS Low Temperature Poly Silicon
  • the TFT channel 104 is formed by polycrystallizing and activating a region of amorphous Si formed on the TFT underlayer film 106. For example, laser annealing with a laser is used for polycrystallization and activation of the amorphous Si region.
  • the TFT formed by the LTPS process has sufficiently high mobility.
  • the TFT channel 104 includes regions 104s, 104i, 104d.
  • the regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106.
  • the area 104i is provided between the area 104s and the area 104d.
  • the regions 104s and 104d are doped with p-type impurities such as boron ion (B + ) or boron trifluoride ion (BF 2+ ), and are ohmic-connected to the vias 111s and 111d.
  • the gate 107 is provided on the TFT channel 104 via the insulating layer 105.
  • the insulating layer 105 is provided to insulate the TFT channel 104 and the gate 107 and to insulate them from other adjacent circuit elements.
  • a potential lower than the region 104s is applied to the gate 107, a channel is formed in the region 104i, so that the current flowing between the regions 104s and 104d can be controlled.
  • the insulating layer 105 is, for example, SiO 2 .
  • the insulating layer 105 may be a multi-layered insulating layer containing SiO 2 or Si 3 N 4 depending on the covering region.
  • the gate 107 may be formed of, for example, polycrystalline Si or a refractory metal such as W or Mo.
  • a refractory metal such as W or Mo.
  • the gate 107 is formed by a polycrystalline Si film, it is formed by, for example, CVD or the like.
  • the second interlayer insulating film 108 is provided on the gate 107 and the insulating layer 105.
  • the second interlayer insulating film 108 is made of the same material as, for example, the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of a white resin, an inorganic film such as SiO 2 , or the like.
  • the second interlayer insulating film 108 also functions as a flattening film for forming the first wiring layer 110.
  • the vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108 and the insulating layer 105.
  • the first wiring layer 110 is formed on the second interlayer insulating film 108.
  • the first wiring layer 110 includes a plurality of wirings having different potentials.
  • the first wiring layer 110 includes wirings 110s, 110d, 110k. These wirings 110s, 110d, 110k are formed separately.
  • a part of the wiring 110s is provided above the area 104s.
  • the other portion of the wiring 110s is connected to, for example, the power supply line 3 shown in FIG. 2, which will be described later.
  • a part of the wiring (first wiring) 110d is provided above the area 104d.
  • the other portion of the wiring 110d is provided above the upper surface 153U.
  • a part of the wiring (second wiring) 110k is provided above the connection portion 151a.
  • the other portion of the wiring 110k is connected to, for example, the ground wire 4 shown in the circuit of FIG. 2 described later.
  • the reference numeral representing the wiring layer shall be displayed next to the wiring constituting the wiring layer.
  • the via 111s is provided between the wiring 110s and the area 104s, and electrically connects the wiring 110s and the area 104s.
  • the via 111d is provided between the wiring 110d and the area 104d, and electrically connects the wiring 110d and the area 104d.
  • the wiring 110s is connected to the area 104s via the via 111s.
  • the region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to, for example, the power supply line 3 shown in the circuit of FIG. 2 described later, via the via 111s and the wiring 110s.
  • the wiring 110d is connected to the area 104d via the via 111d.
  • the region 104d is a drain region of the transistor 103.
  • the via (first via) 161a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 161a is provided between the wiring (first wiring) 110d and the upper surface 153U, and electrically connects the wiring 110d and the p-type semiconductor layer 153. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the via 161a, the wiring 110d, and the via 111d.
  • the via (second via) 161k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 161k is provided between the wiring (second wiring) 110k and the connection portion 151a, and electrically connects the wiring 110k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to the ground wire 4 shown in the circuit of FIG. 2, for example, via the connection portion 151a, the via 161k, and the wiring 110k.
  • the first wiring layer 110 and vias 111s, 111d, 161k are formed of, for example, an alloy of Al or Al, a laminated film of Al and Ti, or the like.
  • Al is laminated on a thin film of Ti, and Ti is further laminated on Al.
  • a protective layer covering them may be provided over the second interlayer insulating film 108 and the first wiring layer 110.
  • FIG. 2 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 1 of the present embodiment includes a display area 2.
  • Subpixels 20 are arranged in the display area 2.
  • the sub-pixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.
  • the image display device 1 further includes a power line 3 and a ground line 4.
  • the power line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the subpixels 20.
  • the power supply line 3 and the ground line 4 are electrically connected to each subpixel 20, and power is supplied to each subpixel 20 from a DC power source connected between the power supply terminal 3a and the GND terminal 4a.
  • the power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with reference to the GND terminal 4a.
  • the image display device 1 further includes a scanning line 6 and a signal line 8.
  • the scanning line 6 is laid out in a direction parallel to the X-axis. That is, the scanning lines 6 are laid out along the row direction arrangement of the subpixels 20.
  • the signal line 8 is laid out in a direction parallel to the Y axis. That is, the signal line 8 is laid out along the arrangement of the subpixels 20 in the column direction.
  • the image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7.
  • the row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2.
  • the row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2.
  • the row selection circuit 5 is electrically connected to the subpixels 20 in each column via the scanning line 6 to supply a selection signal to each subpixel 20.
  • the signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2.
  • the signal voltage output circuit 7 is electrically connected to the subpixel 20 of each line via the signal line 8 to supply a signal voltage to each subpixel 20.
  • the subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28.
  • the selection transistor 24 may be displayed as T1
  • the drive transistor 26 may be displayed as T2
  • the capacitor 28 may be displayed as Cm.
  • the light emitting element 22 is connected in series with the drive transistor 26.
  • the drive transistor 26 is a p-channel TFT, and the anode electrode of the light emitting element 22 is connected to the drain electrode of the drive transistor 26.
  • the main electrodes of the drive transistor 26 and the selection transistor 24 are a drain electrode and a source electrode.
  • the anode electrode of the light emitting element 22 is connected to the p-type semiconductor layer.
  • the cathode electrode of the light emitting element 22 is connected to the n-type semiconductor layer.
  • the series circuit of the light emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4.
  • the drive transistor 26 corresponds to the transistor 103 in FIG.
  • the light emitting element 22 corresponds to the light emitting element 150 in FIG.
  • the current flowing through the light emitting element 22 is determined by the voltage applied between the gate and the source of the drive transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the current flowing through the light emitting element 22.
  • the selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode.
  • the gate electrode of the selection transistor 24 is connected to the scanning line 6.
  • a capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.
  • the row selection circuit 5 selects one row from the array of subpixels 20 in the m row and supplies the selection signal to the scanning line 6.
  • the signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value for each subpixel 20 in the selected row.
  • a signal voltage is applied between the gate and the source of the drive transistor 26 of the subpixel 20 in the selected row.
  • the signal voltage is held by the capacitor 28.
  • the drive transistor 26 causes a current corresponding to the signal voltage to flow through the light emitting element 22.
  • the light emitting element 22 emits light with a brightness corresponding to the flowing current.
  • the row selection circuit 5 sequentially switches the rows to be selected and supplies a selection signal. That is, the row selection circuit 5 scans the row in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light emitting element 22 of the subpixels 20 that are sequentially scanned to emit light. The brightness of the subpixel 20 is determined by the current flowing through the light emitting element 22. The sub-pixel 20 emits light with a gradation based on the determined brightness, and the image is displayed in the display area 2.
  • FIG. 3 is a schematic plan view illustrating a part of the image display device of the present embodiment.
  • the AA'line represents a cutting line in a cross-sectional view such as FIG.
  • the light emitting element 150 and the driving transistor 103 are laminated in the Z-axis direction via the first interlayer insulating film 156.
  • the light emitting element 150 corresponds to the light emitting element 22 in FIG.
  • the drive transistor 103 corresponds to the drive transistor 26 in FIG. 2, and is also referred to as T2.
  • connection portion 151a As shown in FIG. 3, the cathode electrode of the light emitting element 150 is provided by the connection portion 151a.
  • the connection portion 151a is provided below the transistor 103 and the first wiring layer 110.
  • the connection portion 151a is electrically connected to the wiring 110k via the via 161k. More specifically, one end of the via 161k is connected to the connecting portion 151a. The other end of the via 161k is connected to the wiring 110k via the contact hole 161k1.
  • the anode electrode of the light emitting device 150 is provided by the p-type semiconductor layer 153 shown in FIG.
  • the upper surface 153U of the p-type semiconductor layer 153 is connected to the wiring 110d via the via 161a. More specifically, one end of the via 161a is connected to the upper surface 153U. The other end of the via 161a is connected to the wiring 110d via the contact hole 161a1.
  • the other end of the wiring 110d is connected to the drain electrode of the transistor 103 via the via 111d shown in FIG.
  • the drain electrode of the transistor 103 is the region 104d shown in FIG.
  • the source electrode of the transistor 103 is connected to the wiring 110s via the via 111s shown in FIG.
  • the source electrode of the transistor 103 is the region 104s shown in FIG.
  • the first wiring layer 110 includes the power supply line 3, and the wiring 110s is connected to the power supply line 3.
  • the ground wire 4 is provided further above the first wiring layer 110.
  • an interlayer insulating film is further provided on the first wiring layer 110.
  • the ground wire 4 is provided on the interlayer insulating film of the uppermost layer, and is insulated from the power supply line 3.
  • the light emitting element 150 can be electrically connected to the first wiring layer 110 provided above the light emitting element 150 by using the vias 161k and 161a.
  • the manufacturing method of the image display device 1 of this embodiment will be described.
  • 4A to 5B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the semiconductor growth substrate 1194 is prepared.
  • the semiconductor growth substrate 1194 includes a crystal growth substrate 1001 and a semiconductor layer 1150.
  • the crystal growth substrate 1001 is, for example, a Si substrate, a sapphire substrate, or the like.
  • the Si substrate is used as the crystal growth substrate 1001.
  • a low temperature crystal growth process such as a low temperature sputtering method is used as described later, it is also possible to use a cheaper glass substrate or the like.
  • the semiconductor layer 1150 is formed on the crystal growth substrate 1001.
  • the semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153.
  • the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order from the side of the crystal growth substrate 1001.
  • the semiconductor layer 1150 for example, a vapor deposition method (Chemical Vapor Deposition, CVD method) is used, and an organic metal vapor deposition method (Metal Organic Chemical Vapor Deposition, MOCVD method) is preferably used.
  • a vapor deposition method Chemical Vapor Deposition, CVD method
  • an organic metal vapor deposition method Metal Organic Chemical Vapor Deposition, MOCVD method
  • the low temperature sputtering method the epitaxial crystal growth of the semiconductor layer 1150 is possible even at a process temperature of 700 ° C. or lower.
  • a low temperature sputtering method it becomes possible to use a glass substrate or an apparatus having low heat resistance, so that the manufacturing cost can be reduced.
  • the semiconductor layer 1150 includes, for example, GaN, and more particularly includes In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) and the like.
  • crystal defects may occur due to the mismatch of crystal lattice constants, and the crystals with crystal defects exhibit n-shape. Therefore, when the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001 as in this example, a large margin in the production process can be obtained, and the yield can be easily improved. There is an advantage.
  • the semiconductor layer 1150 When the semiconductor layer 1150 is formed on the crystal growth substrate 1001, the semiconductor layer 1150 may be formed via a buffer layer (not shown in FIG. 4A).
  • a buffer layer for example, a nitride such as AlN is used.
  • the mismatch at the interface between the GaN crystal and the crystal growth substrate 1001 can be alleviated. Therefore, it is expected that the quality of the crystal of the semiconductor layer 1150 will be improved.
  • the n-type semiconductor layer 1151 since the n-type semiconductor layer 1151 is bonded to the first surface 103a, a step of removing the buffer layer is added before the bonding.
  • the semiconductor layer 1150 may be formed via the buffer layer.
  • the support substrate 1190 is prepared.
  • the support substrate 1190 is made of, for example, quartz glass, Si, or the like.
  • the semiconductor growth substrate 1194 is arranged so that the exposed surface 1153E of the p-type semiconductor layer 1153 faces one surface 1190E of the support substrate 1190.
  • the semiconductor layer 1150 is bonded to the support substrate 1190.
  • the crystal growth substrate 1001 is removed. For example, wet etching or laser lift-off is used to remove the crystal growth substrate 1001.
  • the semiconductor layer 1150 of the substrate 1195 is bonded to the first surface 103a of the substrate 102.
  • the surface bonded to the first surface 103a is the exposed surface 1151E of the n-type semiconductor layer 1151.
  • the support substrate 1190 is removed. Wet etching and laser lift-off are also used to remove the support substrate 1190.
  • the substrates are bonded to each other by heating and thermocompression bonding each substrate.
  • the bonded surfaces of each substrate are flattened by chemical mechanical polishing (CMP), etc., and then the bonded surfaces are cleaned and adhered by plasma treatment in vacuum. May be good.
  • one semiconductor layer 1150 may be bonded to one substrate 102, or a plurality of semiconductor layers 1150 may be bonded to one substrate 102.
  • the size of the substrate 102 can be, for example, a rectangular shape or a square shape of about several tens of mm square to 150 mm square.
  • the semiconductor layer 1150 formed on the substrate 1195 can be sized according to the size of the substrate 102.
  • a substantially rectangular glass substrate having a size of about 1500 mm ⁇ 1800 mm can be used as the substrate 102.
  • the semiconductor layer 1150 formed on the substrate 1195 has a rectangular shape or a square shape of about several tens of mm square to 150 mm square, and can have a size of, for example, about 4 inches to 6 inches in terms of wafer dimensions.
  • the size of the substrate 102 is appropriately selected according to the size of the image display device and the like.
  • FIG. 6 is a perspective view illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • FIG. 6 schematically shows an example in which a plurality of semiconductor layers 1150 are bonded to one substrate 102.
  • the figure above the arrow in FIG. 6 shows that the plurality of substrates 1195 are arranged in a grid pattern.
  • the figure below the arrow in FIG. 6 shows that the substrate 102 on which the bonding layer 303 is formed is arranged.
  • FIG. 6 shows by arrows that a plurality of substrates 1195 arranged in a grid pattern are bonded to each other at the positions of the two-dot chain line.
  • the end portion of the semiconductor layer 1150 is formed so as to substantially coincide with the end portion of the support substrate 1190. Therefore, the plurality of substrates 1195 are arranged in a grid pattern facing the substrates 102 so as not to form a gap between the adjacent substrates 1195 as much as possible, for example, as shown by the solid line in FIG.
  • the semiconductor layer 1150 is bonded onto the first surface 103a of the substrate 102, as shown by the alternate long and short dash line in FIG.
  • the substrate 102 to which the plurality of semiconductor layers 1150 are bonded is divided in a subsequent step, and an image display of a quantity and a size according to the number of divisions is performed. It can be a device. Since the end portion of the semiconductor layer 1150 having deteriorated crystal quality is preferably the end portion of the display region, the unit to be divided is preferably set to match the shape of the substrate 1195.
  • the process up to the formation of the semiconductor growth substrate 1194 and the process of performing the processing after the substrate 1195 are formed may be executed in the same plant or may be executed in different plants.
  • the substrate 1195 may be manufactured in the first plant, the substrate 1195 may be carried into a second plant different from the first plant, and the bonding step may be executed.
  • the method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and the following method can also be used. That is, the semiconductor layer 1150 is formed on the crystal growth substrate 1001 and then stored in a container. For example, in the container, the support substrate 1190 is mounted and stored. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102. Further, the semiconductor layer 1150 is stored in a container without being mounted on the support substrate 1190. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102 as it is.
  • FIG. 7A to 8B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the semiconductor layer 1150 shown in FIG. 5B is processed into a desired shape by etching to form a light emitting device 150.
  • the connection portion 151a is formed, and then the other portion is formed by further etching.
  • This makes it possible to form a light emitting element 150 having a connecting portion 151a projecting from the n-type semiconductor layer 151 on the first surface 103a in the positive direction of the X-axis.
  • a dry etching process is used for forming the light emitting element 150, and anisotropic plasma etching (Reactive Ion Etching, RIE) is preferably used.
  • the first interlayer insulating film (first insulating film) 156 is formed so as to cover the first surface 103a and the light emitting element 150.
  • the TFT underlayer film 106 is formed on the first interlayer insulating film 156 by, for example, CVD.
  • the Si layer 1104 is formed on the formed TFT lower layer film 106.
  • the Si layer 1104 is an amorphous Si layer at the time of film formation, and after film formation, for example, a polycrystallized Si layer 1104 is formed by scanning an excimer laser pulse a plurality of times.
  • the transistor 103 is formed at a desired position on the TFT underlayer film 106.
  • the transistor 103 is formed as follows.
  • the polycrystalline Si layer 1104 shown in FIG. 7B is processed into an island shape to form a TFT channel 104.
  • the insulating layer 105 is formed so as to cover the TFT underlayer film 106 and the TFT channel 104.
  • the insulating layer 105 functions as a gate insulating film.
  • a gate 107 is formed on the TFT channel 104 via the insulating layer 105.
  • the transistor 103 is formed by selectively doping the gate 107 with an impurity such as B + and thermally activating it.
  • the regions 104s and 104d are p-shaped active regions, and function as source regions and drain regions of the transistor 103, respectively.
  • the region 104i is an n-type active region and functions as a channel.
  • the second interlayer insulating film (second insulating film) 108 is provided so as to cover the insulating layer 105 and the gate 107.
  • An appropriate manufacturing method is applied to the formation of the second interlayer insulating film 108 depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is formed of SiO 2 , techniques such as ALD and CVD are used.
  • the flatness of the second interlayer insulating film 108 may be such that the first wiring layer 110 can be formed, and the flattening step does not necessarily have to be performed.
  • the number of steps can be reduced. For example, when there is a portion around the light emitting element 150 where the thickness of the second interlayer insulating film 108 becomes thin, the depth of the via hole for the vias 161a and 161k can be made shallow, so that the thickness is sufficiently open.
  • the caliber can be secured. Therefore, it becomes easy to secure the electrical connection by the via, and it is possible to suppress the decrease in the yield due to the poor electrical characteristics.
  • Vias 161a and 161k are formed through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 161a is formed so as to reach the upper surface 153U.
  • the via 161k is formed so as to reach the connecting portion 151a.
  • Vias 111s and 111d are formed through the second interlayer insulating film 108 and the insulating layer 105.
  • the vias 111s are formed to reach the region 104s.
  • the via 111d is formed so as to reach the region 104d.
  • RIE or the like is used for forming a via hole for forming the vias 161a, 161k, 111s, 111d.
  • the first wiring layer 110 is formed on the second interlayer insulating film 108.
  • Wiring 110k, 110d, 110s is formed.
  • the wiring 110k is connected to one end of the via 161k.
  • the wiring 110d is connected to one end of the via 161a and one end of the via 111d.
  • the wiring 110s is connected to one end of the via 111s.
  • the first wiring layer 110 may be formed at the same time as the vias 161k, 161a, 111d, 111s are formed.
  • the sub-pixel 20 is formed and the image display device is formed.
  • FIG. 9 is a schematic perspective view illustrating the image display device of the present embodiment.
  • a light emitting circuit unit 172 having a large number of light emitting elements 150 is provided on the substrate 102.
  • the light emitting circuit unit 172 is a structure including a light emitting element 150 and a first interlayer insulating film 156 covering the light emitting element 150.
  • a drive circuit unit 100 is provided on the light emitting circuit unit 172.
  • the drive circuit unit 100 is a structure including the circuit 101 shown in FIG. 1, the second interlayer insulating film, and the TFT lower layer film 106. As described above, the light emitting circuit unit 172 and the drive circuit unit 100 are electrically connected by vias 161a and 161k.
  • the configuration shown in FIG. 9 is an example of the image display device of the present embodiment when the color filter is not provided, and is applied when the color filter is not provided in other embodiments described later.
  • the semiconductor layer 1150 is bonded to the substrate 102, and then the semiconductor layer 1150 is etched to form the light emitting element 150. After that, the light emitting element 150 is covered with the first interlayer insulating film 156, and a circuit 101 including a circuit element such as a transistor 103 for driving the light emitting element 150 is built on the first interlayer insulating film 156. Therefore, the manufacturing process is remarkably shortened as compared with transferring the individualized light emitting elements to the substrate 102 individually.
  • the manufacturing method of the image display device of the present embodiment is as follows. The effect is obtained.
  • the light emitting element is formed by etching after the entire semiconductor layer 1150 is bonded to the substrate 102, so that the transfer step is completed in one time. Therefore, in the manufacturing method of the image display device 1 of the present embodiment, the time of the transfer step can be shortened and the number of steps can be reduced as compared with the conventional manufacturing method.
  • the semiconductor layer 1150 is bonded to the substrate 102 at the wafer level without being fragmented in advance or forming an electrode at a position corresponding to the circuit element. Therefore, alignment at the bonding stage is not required. Therefore, the bonding process can be easily performed in a short time. Since it is not necessary to align the light emitting element 150 at the time of bonding, it is easy to reduce the size of the light emitting element 150, which is suitable for a high-definition display.
  • the glass substrate formed as described above is covered with the first interlayer insulating film 156, and a drive circuit, a scanning circuit, or the like including a TFT or the like is mounted on the flattened surface by using an LTPS process or the like. Can be formed. Therefore, there is an advantage that the existing flat panel display manufacturing process and plant can be used.
  • the light emitting element 150 formed in the lower layer than the transistor 103 or the like has vias 161a, 161k penetrating the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108.
  • it can be electrically connected to a power supply line, a ground line, a driving transistor, or the like formed on the upper layer.
  • a uniform connection structure can be easily realized and the yield can be improved. Therefore, the decrease in yield due to poor connection of the light emitting element or the like is suppressed.
  • the light emitting element 150 is covered with the first interlayer insulating film 156.
  • the first interlayer insulating film 156 is made of a material having high light reflectivity such as white resin, scattering or the like of the light emitting element 150 in a direction other than the direction toward the light emitting surface 151S is scattered on the light emitting surface 151S side. Can be reflected. Therefore, the arrival of scattered light or the like to the transistor 103 is suppressed, and the malfunction of the transistor 103 is prevented.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • the image display device of the present embodiment includes a sub-pixel 220, and the sub-pixel 220 is another embodiment described above in that the p-type semiconductor layer 253 provides a light emitting surface 253S. It is different from the case of.
  • the configuration of the light emitting element 250 is different from that of the other embodiments described above, so that the configuration of the transistor 203 for driving the light emitting element 250 is also different.
  • the same components as in the case of other embodiments are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 220 of the image display device of the present embodiment includes a substrate 102, a light emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261k, and a first wiring layer. 110 and.
  • the light emitting element 250 is provided on the first surface 103a.
  • the light emitting element 250 includes a light emitting surface 253S provided on the first surface 103a.
  • the light emitting surface 253S is in contact with the first surface 103a.
  • the light emitting element 250 includes an upper surface 251U provided on the opposite side of the light emitting surface 253S.
  • the light emitting element 250 is a prismatic or cylindrical element as in the case of the other embodiments described above.
  • the light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251.
  • the p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the light emitting surface 253S toward the upper surface 251U.
  • the light emitting surface 253S is provided by the p-type semiconductor layer 253.
  • the light emitting element 250 includes a connection portion 253a.
  • the connecting portion 253a is provided so as to project on the first surface 103a in one direction from the p-type semiconductor layer 253.
  • the height of the connecting portion 253a from the first surface 103a is the same as or lower than the height of the p-type semiconductor layer 253 from the first surface 103a.
  • the connection portion 253a is a part of the p-type semiconductor layer 253.
  • the connection portion 253a is connected to one end of the via 261a and electrically connects the p-type semiconductor layer 253 to the via 261a.
  • the light emitting element 250 has the same XY plan view shape as the light emitting element 150 of the other embodiment described above. An appropriate shape is selected according to the layout of the circuit element and the like.
  • the light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiment described above. That is, the wavelength of the light emitted by the light emitting element 250 is, for example, blue light emission of about 467 nm ⁇ 30 nm or blue purple light emission of about 410 nm ⁇ 30 nm.
  • the wavelength of the light emitted by the light emitting element 250 is not limited to the above-mentioned value, and may be appropriate.
  • the transistor 203 is provided on the TFT lower layer film 106.
  • the transistor 203 is an n-channel TFT.
  • the transistor 203 includes a TFT channel 204 and a gate 107.
  • the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above.
  • the circuit 101 includes a TFT channel 204, an insulating layer 105, a second interlayer insulating film 108, vias 111s, 111d, and a first wiring layer 110.
  • the TFT channel 204 includes regions 204s, 204i, 204d.
  • the regions 204s, 204i, 204d are provided on the TFT underlayer film 106.
  • the regions 204s and 204d are doped with n-type impurities such as phosphorus ions (P ⁇ ).
  • the region 204s is ohmic contacted with the via 111s.
  • the region 204d is ohmic contacted with the via 111d.
  • the gate 107 is provided on the TFT channel 204 via the insulating layer 105.
  • the insulating layer 105 insulates the TFT channel 204 from the gate 107.
  • the transistor 203 when a voltage higher than the region 204s is applied to the gate 107, a channel is formed in the region 204i.
  • the current flowing between the regions 204s and 204d is controlled by the voltage of the gate 107 with respect to the region 204s.
  • the TFT channel 204 and the gate 107 are formed of the same material and manufacturing method as the TFT channel 104 and the gate 107 in the case of the above-mentioned other embodiments.
  • the first wiring layer 110 includes wirings 210s, 210d, 210a.
  • a part of the wiring (second wiring) 210a is provided above the connection portion 253a.
  • the other portion of the wiring 210a is connected to, for example, the power supply line 3 shown in FIG. 11 described later.
  • the vias 111s and 111d are provided so as to penetrate the second interlayer insulating film 108 and the insulating layer 105.
  • the via 111s is provided between the wiring 210s and the area 204s.
  • the via 111s electrically connects the wiring 210s and the area 204s.
  • the via 111d is provided between the wiring 210d and the area 204d.
  • the via 111d electrically connects the wiring 210d and the area 204d.
  • the vias 111s and 111d are formed of the same materials and manufacturing methods as in the other embodiments described above.
  • the via 261k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 261k is provided between the wiring 210d and the upper surface 251U, and electrically connects the wiring 210d and the upper surface 251U. Therefore, the n-type semiconductor layer 251 is electrically connected to the drain region of the transistor 203 via the via 261k, the wiring 210d, and the via 111d.
  • the via 261a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 261a is provided between the wiring 210a and the connecting portion 253a, and electrically connects the wiring 210a and the connecting portion 253a. Therefore, the p-type semiconductor layer 253 is electrically connected to, for example, the power line 3 of the circuit of FIG. 11 via the connection portion 253a, the via 261a, and the wiring 210a.
  • FIG. 11 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 201 of the present embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207.
  • the sub-pixels 220 are arranged in a grid pattern on the XY plane, as in the case of the other embodiments described above.
  • the subpixel 220 includes a light emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228.
  • the selection transistor 224 may be displayed as T1
  • the drive transistor 226 may be displayed as T2
  • the capacitor 228 may be displayed as Cm.
  • the light emitting element 222 is provided on the power supply line 3 side, and the drive transistor 226 connected in series with the light emitting element 222 is provided on the ground line 4 side. That is, the drive transistor 226 is connected to the lower potential side than the light emitting element 222.
  • the drive transistor 226 is an n-channel transistor.
  • a selection transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208.
  • the capacitor 228 is connected between the gate electrode of the drive transistor 226 and the ground wire 4.
  • the row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage having a polarity different from that of the above-mentioned other embodiments to the signal line 208 in order to drive the drive transistor 226 which is an n-channel transistor.
  • the row selection circuit 205 supplies a selection signal to the scanning line 206 so as to sequentially select one row from the array of subpixels 220 in the m row.
  • the signal voltage output circuit 207 supplies a signal voltage having the required analog voltage value for each subpixel 220 in the selected row.
  • the drive transistor 226 of the subpixel 220 in the selected row causes a current corresponding to the signal voltage to flow through the light emitting element 222.
  • the light emitting element 222 emits light with a brightness corresponding to the current flowing through the light emitting element 222.
  • FIG. 12A to 13 are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the semiconductor growth substrate 1194 is prepared.
  • the semiconductor growth substrate 1194 has the same configuration as that previously described in connection with FIG. 4A.
  • the semiconductor layer 1150 of the semiconductor growth substrate 1194 is bonded to the substrate 102.
  • the exposed surface 1153E of the p-type semiconductor layer 1153 is bonded to the first surface 103a.
  • the crystal growth substrate 1001 is removed by wet etching or laser lift-off.
  • FIGS. 14A to 15B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the semiconductor layer 1150 is transferred to the support substrate 1190 and then bonded to the substrate 102.
  • the semiconductor growth substrate 1294 is prepared.
  • the semiconductor growth substrate 1294 has a different configuration from the semiconductor growth substrate 1194 shown in FIGS. 4A and 12A.
  • the semiconductor layer 1150 is laminated in the order of the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 from the side of the crystal growth substrate 1001.
  • the support substrate 1190 is prepared.
  • the exposed surface 1151E of the n-type semiconductor layer 1151 is joined to one surface 1190E of the support substrate 1190.
  • a substrate 1295 in which the semiconductor layer 1150 is bonded to the support substrate 1190 is prepared.
  • the substrate 1295 is attached to the substrate 102.
  • the bonded surface of the substrate 102 with the first surface 103a is the exposed surface 1153E of the p-type semiconductor layer 1153.
  • the support substrate 1190 is removed. Wet etching and laser lift-off are used to remove the support substrate 1190 as in the other embodiments described above. In this way, the semiconductor layer 1150 can be attached to the substrate 102.
  • 16A to 17B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the semiconductor layer 1150 shown in FIGS. 13 and 15B is processed into a desired shape to form a light emitting device 250.
  • the connection portion 253a is formed and other portions are formed as in the case of the other embodiments described above.
  • the same etching process as in the other embodiments described above is used to form the light emitting element 250.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 103a and the light emitting element 250.
  • the TFT lower layer film 106 is formed on the first interlayer insulating film 156.
  • An amorphous Si layer is formed on the TFT lower layer film 106, and a Si layer 1104 that has been laser-annealed and polycrystallized by an excimer laser or the like is formed.
  • the polycrystalline Si layer 1104 shown in FIG. 16B is processed into an island shape like the transistor 103 shown in FIG. 3 to form a TFT channel 204.
  • the insulating layer 105 is formed so as to cover the TFT underlayer film 106 and the TFT channel 204.
  • a gate 107 is formed on the TFT channel 204 via the insulating layer 105.
  • the transistor 203 is formed by selectively doping the gate 107 with impurities such as P ⁇ and thermally activating the gate 107.
  • the regions 204s and 204d are n-type active regions and function as source regions and drain regions of the transistor 203, respectively.
  • the region 204i is a p-shaped active region and functions as a channel.
  • the second interlayer insulating film 108 is provided so as to cover the insulating layer 105 and the gate 107.
  • Vias 261k and 261a are formed through the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 261k is formed so as to reach the upper surface 251U.
  • the via 261a is formed so as to reach the connecting portion 253a.
  • Vias 111s and 111d are formed through the second interlayer insulating film 108 and the insulating layer 105.
  • the vias 111s are formed to reach the region 204s.
  • the via 111d is formed so as to reach the region 204d.
  • the first wiring layer 110 is formed on the second interlayer insulating film 108.
  • Wiring 210a, 210d, 210s are formed.
  • the wiring 210a is connected to one end of the via 261a.
  • the wiring 210d is connected to one end of the via 261k and one end of the via 111d.
  • the wiring 210s is connected to one end of the via 111s.
  • the first wiring layer 110 may be formed at the same time as the vias 261a, 261k, 111d, 111s are formed.
  • the sub-pixel 220 is formed, and the image display device 201 shown in FIG. 11 is formed.
  • the time of the transfer step for forming the light emitting element 250 can be shortened and the number of steps can be reduced, as in the case of the other embodiments described above.
  • the transfer to the support substrate 1190 can be eliminated, so that the number of steps can be reduced.
  • the p-type semiconductor layer 253 can be the light emitting surface 253S, the degree of freedom in the circuit configuration is increased, and the design efficiency of the product can be improved.
  • FIG. 18 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • This embodiment differs from the other embodiments described above in that the light emitting element 150 having the n-type semiconductor layer 151 as the light emitting surface 151S1 is driven by the n-type transistor 203.
  • the subpixel 320 includes a light shielding layer 330.
  • the sub-pixel 320 is provided with a color filter 180 on the light emitting surface 151S1 side.
  • the same components as in the case of the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 320 of the image display device of the present embodiment includes a color filter 180, a light emitting element 150, a first interlayer insulating film 156, a transistor 203, and a second interlayer insulating film 108. It includes a light-shielding layer 330, a via 361a, and a first wiring layer 110.
  • the transistor 203 is an n-channel TFT.
  • the light emitting element 150 provides a light emitting surface 151S1 having an n-type semiconductor layer 151. In this embodiment, the light emitting surface 151S1 is roughened.
  • the color filter 180 includes a light-shielding unit 181 and a color conversion unit 182.
  • the color filter (wavelength conversion member) 180 includes a color conversion unit 182 having light transmission, and is therefore a light transmission member.
  • the color conversion unit 182 is provided directly below the light emitting surface 151S1 of the light emitting element 150 according to the shape of the light emitting surface 151S1.
  • the portion other than the color conversion unit 182 is a light-shielding unit 181.
  • the light-shielding unit 181 is a so-called black matrix, which reduces bleeding due to color mixing of light emitted from an adjacent color conversion unit 182 and makes it possible to display a sharp image.
  • the color conversion unit 182 has one layer or two or more layers.
  • FIG. 18 shows a case where the color conversion unit 182 has two layers. Whether the color conversion unit 182 has one layer or two layers is determined by the color of the light emitted by the subpixel 320, that is, the wavelength.
  • the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing red light.
  • the color conversion unit 182 is preferably two layers, a color conversion layer 183 and a filter layer 184 for passing green light.
  • the emission color of the subpixel 320 is blue, it is preferably one layer.
  • the first layer is the color conversion layer 183 and the second layer is the filter layer 184.
  • the first color conversion layer 183 is provided at a position closer to the light emitting element 150.
  • the filter layer 184 is laminated on the color conversion layer 183.
  • the color conversion layer 183 converts the wavelength of the light emitted by the light emitting element 150 into a desired wavelength.
  • the light having a wavelength of 467 nm ⁇ 30 nm, which is the wavelength of the light emitting element 150 is converted into light having a wavelength of, for example, about 630 nm ⁇ 20 nm.
  • the light having a wavelength of 467 nm ⁇ 30 nm, which is the wavelength of the light emitting element 150 is converted into light having a wavelength of, for example, about 532 nm ⁇ 20 nm.
  • the filter layer 184 blocks the wavelength component of blue light emission remaining without color conversion in the color conversion layer 183.
  • the color of the light emitted by the subpixel 320 When the color of the light emitted by the subpixel 320 is blue, it may be output as it is without passing through the color conversion layer 183 or the color conversion layer 183.
  • the wavelength of the light emitted by the light emitting element 150 When the wavelength of the light emitted by the light emitting element 150 is about 467 nm ⁇ 30 nm, the light may be output without passing through the color conversion layer 183.
  • the wavelength of the light emitted by the light emitting element 150 is 410 nm ⁇ 30 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ⁇ 30 nm.
  • the sub-pixel 320 may have a filter layer 184.
  • the filter layer 184 By providing the filter layer 184 through which the blue light is transmitted to the blue subpixel 320, minute external light reflection other than the blue light generated on the surface of the light emitting element 150 is suppressed.
  • the color filter 180 has a first surface 180a.
  • a transparent thin film adhesive layer 188 is provided on the first surface 180a.
  • the light emitting element 150 and the first interlayer insulating film 156 are provided on the first surface 180a via the transparent thin film adhesive layer 188.
  • the light emitting surface 151S1 is roughened.
  • a transparent flattening film 155 is provided between the light emitting surface 151S1 and the transparent thin film adhesive layer 188.
  • the transparent flattening film 155 flattens the surface of the roughened light emitting surface 151S1.
  • the light emitting element 150 is a prismatic or columnar element including a light emitting surface 151S1 and an upper surface 153U.
  • the light emitting surface 151S1 is in contact with the transparent thin film adhesive layer 188 via the transparent flattening film 155.
  • the upper surface 153U is a surface provided on the opposite side of the light emitting surface 151S1.
  • the light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153.
  • the n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the light emitting surface 151S1 toward the upper surface 153U.
  • the light emitting element 150 includes a connection portion 151a.
  • the connecting portion 151a is formed so as to project in one direction from the n-type semiconductor layer 151 on the first surface 180a via the transparent thin film adhesive layer 188.
  • the transparent flattening film 155 is also provided between the connecting portion 151a and the transparent thin film adhesive layer 188.
  • the connection portion 151a is a part of the n-type semiconductor layer 151.
  • the connection portion 151a is connected to one end of the via 361k and has a function of connecting the n-type semiconductor layer 151 to the first wiring layer 110 above the light emitting element 150 via the via 361k. It is the same as the case of the embodiment of. Since the configuration of the light emitting element 150 is the same as that of the first embodiment described above except that the light emitting surface 151S1 is roughened, further detailed description will be omitted.
  • the n-channel transistor 203 is formed on the TFT lower layer film 106.
  • the transistor 203 is a TFT, and its configuration and the like are the same as those of the second embodiment described above, and detailed description thereof will be omitted.
  • the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108.
  • the light-shielding layer 330 is provided on the entire surface except for a part on the first interlayer insulating film 156.
  • the light-shielding layer 330 may or may not be conductive as long as it is a light-shielding material, but is made of, for example, a light-reflecting metal material.
  • the light-shielding layer 330 may be formed of a black resin. When the light-shielding layer 330 is formed of black resin, vias can be collectively formed together with the first interlayer insulating film 156 and the like without forming through holes larger than the diameter of the vias in advance.
  • the light-shielding layer 330 has through holes 331a and 331k having a diameter larger than the diameters of the vias 361a and 361k. Is provided.
  • the via 361a penetrates the through hole 331a, and the via 361k penetrates the through hole 331k.
  • the light-shielding layer 330 includes the first portion 330a, and the TFT channel 204 is provided on the first portion 330a.
  • the first portion 330a has a region including the outer circumference of the TFT channel 204 when the TFT channel 204 is projected onto the first portion 330a in an XY plan view. Even when scattered light or the like is emitted upward from the light emitting element 150 provided below the TFT channel 204 by the first portion 330a, the scattered light or the like is shielded by the first portion 330a and the scattered light or the like is emitted. Etc. can hardly reach the TFT channel, so that the malfunction of the transistor 203 can be suppressed.
  • the light-shielding layer 330 is provided over the entire surface of the first interlayer insulating film 156 as in this example, but the light-shielding layer 330 is not limited to the case where it is physically one member.
  • the light-shielding layer 330 may be provided separately in a portion directly below the TFT channel 204 and a portion directly above the light emitting element 150.
  • the light-shielding layer 330 is not connected to any potential, but may be connected to a specific potential such as a ground potential or a power supply potential.
  • the light-shielding layer 330 has a plurality of separated portions, all of them may have a common potential or may be connected to different potentials for each portion.
  • the via 111s is provided between the wiring 310s and the area 204s, and electrically connects the wiring 310s and the area 204s.
  • the via 111d is provided between the wiring 310d and the area 204d, and electrically connects the wiring 310d and the area 204d.
  • the wiring 310s is connected to the area 204s via the via 111s.
  • the region 204s is the source region of the transistor 203. Therefore, the source region of the transistor 203 is electrically connected to the ground wire 4 via the via 111s and the wiring 310s.
  • the wiring 310d is connected to the area 204d via the via 111d.
  • the region 204d is a drain region of the transistor 203.
  • the via 361k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 361k is provided between the wiring 310d and the connecting portion 151a, and electrically connects the wiring 310d and the connecting portion 151a. Therefore, the drain region of the transistor 203 is electrically connected to the n-type semiconductor layer 151 via the via 111d, the wiring 310d, the via 361k, and the connecting portion 151a.
  • the via 361a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156.
  • the via 361a is provided between the wiring 310a and the upper surface 153U, and electrically connects the wiring 310a and the upper surface 153U. Therefore, the p-type semiconductor layer 153 is electrically connected to, for example, the power line 3 of the circuit of FIG. 19 described later, via the via 361a and the wiring 310a.
  • FIG. 19 is a schematic block diagram illustrating the image display device of the present embodiment.
  • the sub-pixels 320 are arranged in the display area 2.
  • the sub-pixels 320 are arranged in a grid pattern, for example.
  • n subpixels 320 are arranged along the X axis
  • m subpixels 320 are arranged along the Y axis.
  • Pixel 10 includes a plurality of sub-pixels 320 that emit light of different colors.
  • the subpixel 320R emits red light.
  • the subpixel 320G emits green light.
  • the subpixel 320B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 320R, 320G, and 320B emitting light at a desired brightness.
  • One pixel 10 includes three sub-pixels 320R, 320G, 320B, and the sub-pixels 320R, 320G, 320B are arranged linearly on the X-axis, for example.
  • sub-pixels of the same color may be arranged in the same column, or sub-pixels of different colors may be arranged in each column as in this example.
  • the configurations of the power supply line 3, the ground line 4, the scanning line 206, and the signal line 208 are the same as those of the second embodiment described above.
  • the image display device 301 is different from the case of the second embodiment in that the emission color and the brightness of one pixel 10 are determined by causing each of the three types of subpixels to emit light at a set brightness. Since it is the same as the example of FIG. 11 in the case of the second embodiment except that the signal configuration for that purpose may be different, detailed description of the circuit configuration will be omitted.
  • FIG. 20A to 23B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the steps from transferring the semiconductor layer to the support substrate to preparing the substrate 1195 shown in FIG. 5A are the same as those of the first embodiment described above. ..
  • the following steps of FIG. 4B in which the substrate 1195 is formed will be described.
  • the n-type semiconductor layer 1151 shown in FIG. 4B is roughened to form a roughened exposed surface 1151E1.
  • a transparent flattening film 1155 is formed over the exposed surface 1151E1, and the exposed surface 1155E of the transparent flattening film 1155 is flattened.
  • CMP is used for flattening the exposed surface 1155E.
  • the semiconductor layer 1150 is bonded to the substrate 102.
  • the semiconductor layer 1150 is the exposed surface 1155E of the transparent flattening film 1155
  • the substrate 102 is the first surface 103a of the bonded layer 303.
  • the semiconductor layer 1150 shown in FIG. 20B is etched into a desired shape to form a light emitting element 150.
  • the step of forming the light emitting element 150 is the same as that of the other embodiments described above.
  • the transparent flattening film 155 is formed by processing the transparent flattening film 1555 before processing shown in FIG. 20B at the same time as the formation of the light emitting element 150.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 103a and the light emitting element 150.
  • the first interlayer insulating film 156 is also provided so as to cover the transparent flattening film 155.
  • the light-shielding layer 330 is formed on the first interlayer insulating film 156.
  • through holes 331a and 331k are formed by etching or the like.
  • the portion of the light-shielding layer 330 other than the through holes 331a and 331k is left on the first interlayer insulating film 156, and the first portion 330a is provided at a position where a transistor is formed in the subsequent steps.
  • the light-shielding layer 330 is made of an insulating material such as black resin, it is not necessary to insulate the light-shielding layer 330 from the vias, so that the through holes 331a and 331k do not need to be formed.
  • the TFT underlayer film 106 is formed on the light-shielding layer 330 by CVD or the like.
  • the locations where the through holes 331a and 331k are formed are embedded in the TFT underlayer film 106, and the surface of the TFT underlayer film 106 is flattened.
  • a polycrystalline Si layer 1104 is formed on the flattened TFT underlayer film 106.
  • the Si layer 1104 shown in FIG. 21B is processed to form the TFT channel 204, the insulating layer 105 is formed, the gate 107 is formed, and the regions 204s, 204d, 204i of the TFT channel 204 are formed.
  • the LTPS process is used.
  • vias 111s, 111d, 361k, 361a are formed, and a first wiring layer 110 is formed. These manufacturing steps are the same as in the case of the second embodiment described above.
  • an adhesive layer 1170 is formed on the second interlayer insulating film 108 and the first wiring layer 110, and the reinforcing substrate 1180 is adhered to the adhesive layer 1170.
  • the substrate 102 shown in FIG. 22B is removed together with the bonded layer 303, and the forming surface 1192A of the color filter 180 is exposed. Wet etching or laser lift-off is used to remove the substrate 102 and the bonded layer 303.
  • the color filter 180 is adhered to the forming surface 1192A via the transparent thin film adhesive layer 188.
  • the color filter 180 may be formed by removing, for example, a part of the substrate 102, not limited to removing all of them. Removing a part of the substrate 102 means thinning the substrate 102 by etching or the like.
  • the substrate 102 may be configured in a multi-layer structure in advance with a transparent resin or the like, and a part of the layers may be peeled off to substantially thin the substrate 102.
  • 24A to 24D are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • 24A to 24D show a method of forming a color filter by an inkjet method. This manufacturing process is applied in place of the process shown in FIG. 23B described above.
  • the substrate 102 and the bonding layer 303 are removed, and the structure 1192 with the forming surface 1192A exposed is prepared.
  • the structure 1192 includes a light emitting element 150, a first interlayer insulating film 156, a light shielding layer 330, a TFT lower layer film 106, a TFT channel 204, an insulating layer 105, a gate 107, vias 111s, 111d, 361k. , 361a and the first wiring layer 110.
  • the light-shielding portion 181 is formed on the region of the color filter forming surface 1192A that does not include the light emitting surface 151S1.
  • the light-shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.
  • the phosphor corresponding to the emission color is ejected from the inkjet nozzle to form the color conversion layer 183.
  • the phosphor colors the region where the light-shielding portion 181 is not formed.
  • the fluorescent material for example, a general fluorescent material, a perovskite fluorescent material, or a fluorescent paint using a quantum dot fluorescent material is used.
  • a perovskite phosphor material or a quantum dot phosphor material it is preferable because each emission color can be realized, the monochromaticity is high, and the color reproducibility can be high.
  • a drying process is performed at an appropriate temperature and time. The thickness of the coating film at the time of coloring is set to be thinner than the thickness of the light-shielding portion 181.
  • the color conversion layer 183 is not formed for the subpixels that emit blue light if the color conversion unit is not formed. Further, when the blue color conversion layer is formed for the subpixels of blue light emission, if the color conversion unit may be one layer, the thickness of the coating film of the blue phosphor is preferably the light-shielding portion 181. It is said to be about the same as the thickness of.
  • the paint for the filter layer 184 is ejected from the inkjet nozzle.
  • the paint is applied over the coating film of the phosphor.
  • the total thickness of the coating film of the phosphor and the paint is the thickness at which the filter layer 184 is laminated on the color conversion layer 183, and is about the same as the thickness of the light-shielding portion 181.
  • the color conversion layer 183 be as thick as possible in order to improve the color conversion efficiency.
  • the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambersian, whereas the emission angle of the non-color-converted blue light is limited by the light-shielding portion 181. .. Therefore, there arises a problem that the display color of the display image is dependent on the viewing angle.
  • the thickness of the color conversion layer 183 should be about half the opening size of the light-shielding portion 181. Is desirable.
  • the pitch of the subpixels 20 is about 30 ⁇ m, so that the thickness of the color conversion layer 183 is preferably about 15 ⁇ m.
  • the color conversion material is made of spherical phosphor particles, it is preferable to stack them in a close-packed structure in order to suppress light leakage from the light emitting element 150. For that purpose, at least three layers of particles need to be formed. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably, for example, about 5 ⁇ m or less, and more preferably about 3 ⁇ m or less. Since the perovskite phosphor material, the quantum dot phosphor material, and the like are easily deteriorated by oxygen and moisture, it is preferable that the color conversion layer 183 is sealed with an inorganic film such as SiO 2 .
  • FIG. 25 is a schematic perspective view illustrating the image display device of the present embodiment.
  • a light emitting circuit unit 172 having a large number of light emitting elements 150 is provided on the color filter 180.
  • a drive circuit unit 100 is provided on the light emitting circuit unit 172.
  • the drive circuit unit 100 is a structure including the circuit 101 shown in FIG. As described above, the light emitting circuit unit 172 and the drive circuit unit 100 are electrically connected by vias 361a and 361k.
  • the color filter 180 is provided to enable the configuration of the full-color image display device 301.
  • the image display device is provided without the color filter. May be configured. In that case, for example, the substrate 102 and the bonded layer 303 may be left as they are without being removed.
  • the time of the transfer step for forming the light emitting element 150 can be shortened and the number of steps can be reduced, as in the case of the other embodiments described above.
  • the light emitting surface 151S1 is an n-type semiconductor layer 151 having a lower resistance than the p-type, the n-type semiconductor layer 151 can be formed thicker and the light emitting surface 151S1 can be sufficiently roughened.
  • the synchrotron radiation is diffused by roughening the light emitting surface 151S1, even a small light emitting element 150 can be used as a light source having a sufficient light emitting area. can.
  • the light emitting element 150 having the light emitting surface 151S1 as the n-type semiconductor layer 151 can be driven by the n-channel transistor 203. Therefore, the degree of freedom in the circuit configuration is increased, and the design efficiency can be improved.
  • the light-shielding layer 330 is provided between the first interlayer insulating film 156 and the second interlayer insulating film 108. That is, the light-shielding layer 330 is provided between the light emitting element 150 and the transistor 203. Therefore, even if scattered light or the like is emitted upward from the light emitting element 150, it is difficult for the emitted light to reach the TFT channel 204, and it is possible to prevent the transistor 203 from malfunctioning.
  • the light-shielding layer 330 can be formed of a conductive material such as metal, and the light-shielding layer 330 can be connected to any potential. For example, by arranging a part of the light-shielding layer 330 directly under a switching element such as a transistor 203 and connecting it to a ground potential, a power supply potential, or the like, it is possible to use it for noise suppression.
  • the light-shielding layer 330 is not limited to the case of the present embodiment, but can be applied in common to the sub-pixels of the other embodiments described above and other embodiments described later. Even when applied to other embodiments, the same effects as described above can be obtained.
  • a roughened light emitting surface can be applied as in the case of the present embodiment.
  • Specific applications include the light emitting device 150 in the case of the first embodiment, the light emitting element 250 in the case of the second embodiment, and the semiconductor layer 750 in the case of the seventh embodiment described later.
  • the roughened light emitting surface can be applied by changing the light emitting element in the case of the fourth embodiment, the fifth embodiment and the sixth embodiment from the vertical type to the horizontal type having a connecting portion. can.
  • FIG. 26 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
  • This embodiment differs from the other embodiments described above in that a second wiring layer 440 is included between the light emitting element 150 and the first surface 103a.
  • the present embodiment is different from the above-mentioned other embodiments in that the third wiring layer 470 is included on the light emitting element 150.
  • it is the same as in the case of the other embodiments described above, and the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • the subpixel 420 of the image display device of the present embodiment includes the substrate 102, the second wiring layer 440, the light emitting element 150, the third wiring layer 470, and the first interlayer insulating film 156. , The transistor 103, the second interlayer insulating film 108, the via 161k, and the first wiring layer 110.
  • the second wiring layer 440 is provided on the first surface 103a.
  • the second wiring layer 440 includes the wiring 440a.
  • the wiring 440a is provided between the light emitting element 150 and the first surface 103a.
  • the second wiring layer 440 includes a plurality of wirings 440a depending on the plurality of light emitting elements 150, and in this example, each wiring 440a is separated.
  • the second wiring layer 440 is formed of a conductive film having light transmission.
  • the conductive film is, for example, a transparent conductive film such as ITO or ZnO.
  • the wiring 440a is also made of the same material.
  • the second wiring layer 440 and the wiring 440a are in contact with the first surface 103a.
  • the light emitting element 150 is in contact with the wiring 440a on the light emitting surface 151S and is electrically connected to the wiring 440a.
  • the outer circumference of the wiring 440a is set to include the outer circumference of the light emitting element 150 when the light emitting element 150 is projected onto the wiring 440a in XY plan view.
  • the wiring 440a is provided so as to project on the first surface 103a in one direction from directly below the light emitting surface 151S.
  • One end of the via 161k is connected to the protruding region of the wiring 440a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 2 described above via the wiring 440a, the via 161k, and the wiring 110k.
  • a resin layer 457 is provided on the first surface 103a, the light emitting element 150, and the second wiring layer 440.
  • the resin layer 457 is, for example, a transparent resin.
  • the third wiring layer 470 is provided on the resin layer 457.
  • the third wiring layer 470 can include a plurality of wirings. For example, some of the wires may be physically separated and have different electrical potentials. Other parts of the plurality of wires are physically connected.
  • the third wiring layer 470 includes the separated wirings 470a and 470b.
  • the wiring (first light-shielding electrode) 470a is provided above and to the side of the light emitting element 150 and covers the upper surface 153U and the side surface of the light emitting element 150. By covering most of the light emitting element except the light emitting surface 151S, the wiring 470a shields the scattered light and the reflected light to the side and the upper side of the light emitting element 150.
  • the connection electrode 461a is provided between the upper surface 153U and the wiring 470a, and electrically connects the upper surface 153U and the wiring 470a.
  • the wiring 470a functions as a light-shielding electrode.
  • the resin layer 457 is made of a transparent resin, scattered light or the like emitted from above or from the side of the light emitting element 150 is reflected to the light emitting surface 151S side by the wiring 470a. Therefore, the substantial luminous efficiency of the light emitting element 150 is improved.
  • the resin layer 457 is made of a material having high light reflectivity such as white resin, the wiring 470a is further provided on the resin layer 457, so that higher light reflectivity can be realized.
  • the via 161a is provided between the wiring 110d and the wiring 470a, and electrically connects the wiring 110d and the wiring 470a. Therefore, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the connection electrode 461a, the wiring 470a, the via 161a, the wiring 110d, and the via 111d.
  • the via 161k is provided between the wiring 110k and the wiring 440a, and electrically connects the wiring 110k and the wiring 440a. Therefore, the n-type semiconductor layer 151 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 2 via the wiring 440a, the via 161k, and the wiring 110k.
  • the first interlayer insulating film 156 is provided so as to cover the resin layer 457 and the third wiring layer 470.
  • the configurations of the TFT lower layer film 106 and the circuit 101 provided on the first interlayer insulating film 156 are the same as those of the other embodiments described above, and detailed description thereof will be omitted.
  • FIGS. 4A and 4B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • the steps described with reference to FIGS. 4A and 4B in the first embodiment are applied, and the following description is applied to the steps after FIG. 4B.
  • a substrate 1195 is prepared, and a light-transmitting conductive film 1440 is formed on the semiconductor layer 1150.
  • the conductive film 1440 is formed on the exposed surface 1151E of the n-type semiconductor layer 1151.
  • the semiconductor layer 1150 is bonded to the first surface 103a via the conductive film 1440.
  • the conductive film 1440 shown in FIG. 27B is processed by etching to form a second wiring layer 440 including the wiring 440a.
  • the semiconductor layer 1150 shown in FIG. 27B is processed by etching to form a light emitting element 150.
  • the resin layer 457 is formed so as to cover the first surface 103a, the light emitting element 150, and the wiring layer 440.
  • An opening 462a is formed in the resin layer 457 so as to expose a part of the upper surface 153U of the light emitting element 150.
  • the metal layer 1470 is formed so as to cover the resin layer 457.
  • the opening 462a shown in FIG. 28A may be simultaneously filled to form the connection electrode 461a, or the opening 462a may be filled to form the connection electrode 461a and then the metal layer 1470 is formed. You may.
  • the metal layer 1470 shown in FIG. 28B is processed by etching to form a third wiring layer 470.
  • the wirings 470a and 470b are formed.
  • the first interlayer insulating film 156 is formed so as to cover the resin layer 457 and the third wiring layer 470.
  • the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the polycrystalline Si layer 1104 is formed on the TFT lower layer film 106.
  • the TFT channel 104, the insulating layer 105, the gate 107, and each region 104s, 104d, 104i are formed by using the LTPS process or the like.
  • vias 111s, 111d, 161a, 161k are formed, and the first wiring layer 110 is formed on the second interlayer insulating film 108.
  • the via 161k is formed by filling a via hole formed so as to reach the wiring 440a with a conductive material.
  • the sub-pixel 420 is formed.
  • the effect of the image display device of this embodiment will be described.
  • the image display device of the present embodiment has the effect of shortening the time of the transfer step for forming the light emitting element 150 and reducing the number of steps, as in the case of the other embodiments described above. .. In addition, it has the following effects.
  • the second wiring layer 440 and the wiring 440a are formed of a light-transmitting conductive film such as ITO, processing is easy, and a series of manufacturing steps of the light emitting element 150 and the second wiring layer 440 can be shortened. In some cases.
  • the vertical light emitting element 150 can be obtained.
  • the current flowing through the semiconductor layer can be made to be in the direction substantially along the Z axis by reducing the component in the direction along the XY plane, so that the loss in the semiconductor layer can be reduced. There is a merit that it can be done.
  • the subpixel 420 includes a third wiring layer 470.
  • the third wiring layer 470 is electrically separated from the light emitting element 150 by the resin layer 457.
  • the third wiring layer 470 includes the wiring 470a, and the wiring 470a covers the upper surface 153U and the side surface of the light emitting element 150 via the resin layer 457. Therefore, it is possible to block light scattered above or to the side of the light emitting element 150. Even if the transistor 103 is provided above the light emitting element 150, scattered light or the like above or to the side of the light emitting element 150 is shielded by the wiring 470a, so that the scattered light or the like reaches the transistor 103. Is suppressed. Therefore, malfunction of the transistor 103 due to scattered light of the light emitting element 150 or the like is prevented.
  • FIG. 31 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
  • a light-shielding electrode 560a that covers the upper surface 153U of the light emitting element 150 is provided, and the light-shielding electrode 560a is connected to a wiring 510d formed on the wall surface of the through hole 511a.
  • a transparent substrate such as a glass substrate is thinned, and a color filter 180 is provided on the thinned substrate 502.
  • the same components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.
  • the subpixel 520 of the image display device of the present embodiment includes a substrate 502, a second wiring layer 440, a light emitting element 150, a light shielding electrode 560a, a first interlayer insulating film 156, and a transistor. It includes 103, a second interlayer insulating film 108, vias 161k, a first wiring layer 110, and a color filter 180.
  • the light emitting element 150 is provided on the wiring 540a of the second wiring layer 440, and is electrically connected to the wiring 540a by the light emitting surface 151S.
  • the substrate 502 is a translucent substrate, for example, a glass substrate.
  • the substrate 502 may be a translucent resin substrate as well as a glass substrate.
  • a bonding layer 303 is provided on one surface 502a of the substrate 502.
  • the bonded layer 303 is the same as in the case of the other embodiment described above.
  • the substrate 502 is a resin substrate, it is provided to facilitate bonding with the semiconductor layer, and is formed of an inorganic compound such as a Si compound such as SiO 2 .
  • a color filter 180 is provided on the other surface 502b of the substrate 502.
  • the color filter 180 is the same as in the case of the other embodiments described above.
  • a through hole 511a is provided above the light emitting element 150.
  • the through hole 511a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reach the upper surface 153U.
  • the inner circumference of the through hole 511a is provided so as to be the same as the outer circumference of the upper surface 153U or slightly inside the outer circumference of the upper surface 153U.
  • a light-shielding electrode (second light-shielding electrode) 560a is provided over the upper surface 153U. Since the light-shielding electrode 560a is provided at the bottom of the through hole 511a, the outer circumference of the light-shielding electrode 560a substantially coincides with the inner circumference of the through hole 511a. Therefore, the light-shielding electrode 560a is provided so as to cover all of the upper surface 153U or most of the upper surface 153U. The light-shielding electrode 560a shields light scattered upward from the light-emitting element 150 and the like. Therefore, it is suppressed that the scattered light or the like from above reaches the transistor 103, so that the transistor 103 is prevented from malfunctioning.
  • the light reflectivity can be improved by forming the light-shielding electrode 560a with a highly reflective material such as Ag, or by providing an ITO film between the light-shielding electrode 560a and the upper surface 153U.
  • a highly reflective material such as Ag
  • ITO film between the light-shielding electrode 560a and the upper surface 153U.
  • the scattered light or the like on the upper surface 153U side can be reflected on the light emitting surface 151S side, and the substantial luminous efficiency of the light emitting element 150 can be improved.
  • the light-shielding electrode 560a can be integrally formed with the wiring 510d formed on the wall surface of the through hole 511a, the light-shielding electrode 560a and the wiring 510d are the vias (first vias) 161a in the above-mentioned other embodiments. And so on.
  • the first wiring layer 110 includes wiring 510d.
  • the wiring 510d is provided on the second interlayer insulating film 108, is provided on the wall surface of the through hole 511a, and is connected to the light-shielding electrode 560a. Since the wiring 510d is connected to the drain region of the transistor 103 via the via 111d, the p-type semiconductor layer 153 is electrically connected to the drain region of the transistor 103 via the light shielding electrode 560a, the wiring 510d and the via 111d. Be connected.
  • FIG. 32 is a schematic block diagram illustrating the image display device of the present embodiment.
  • the sub-pixels 520 are arranged in the display area 2.
  • the sub-pixels 520 are arranged in a grid pattern, for example.
  • n subpixels 520 are arranged along the X axis
  • m are arranged along the Y axis.
  • Pixel 10 includes a plurality of sub-pixels 520 that emit light of different colors.
  • the subpixel 520R emits red light.
  • the subpixel 520G emits green light.
  • the subpixel 520B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 520R, 520G, and 520B emitting light at a desired brightness.
  • the arrangement of each color and the like are the same as in the third embodiment.
  • the configurations of the power supply line 3, the ground line 4, the scanning line 6, and the signal line 8 are the same as those of the first embodiment described above.
  • the image display device 501 is different from the case of the first embodiment in that the emission color and the brightness of one pixel 10 are determined by causing each of the three types of subpixels to emit light at a set brightness. Since it is the same as the example of FIG. 2 in the case of the first embodiment except that the signal configuration for that purpose may be different, detailed description of the circuit configuration will be omitted.
  • 33A to 34B are schematic cross-sectional views illustrating a part of the manufacturing method of the image display device of the present embodiment.
  • the steps described with reference to FIGS. 27A and 27B are applied in the fourth embodiment, and the following description is applied to the steps after FIG. 27B.
  • the light-transmitting conductive film 1440 shown in FIG. 27B is processed by etching to form a second wiring layer 440 and wiring 540a.
  • the first interlayer insulating film 156 is formed so as to cover the first surface 103a, the light emitting element 150, and the second wiring layer 440.
  • FIG. 33B it penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106 and the first interlayer insulating film 156 provided above the upper surface 153U of the light emitting element 150, and reaches the upper surface 153U.
  • a through hole 511a is formed in the hole 511a. By forming the through hole 511a, a part of the upper surface 153U is exposed from the opening 511.
  • the upper surface 153U exposed by the opening 511 of the through hole 511a preferably exposes the entire upper surface 153U, but is set according to the formation accuracy of the through hole 511a.
  • the inner circumference of the through hole 511a is set to be slightly smaller than the outer circumference of the upper surface 153U.
  • a via hole 162k that penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer film 106, and the first interlayer insulating film 156 and reaches the wiring 540a is formed.
  • a via hole 112d that penetrates the second interlayer insulating film 108 and the insulating layer 105 and reaches the region 104d is formed.
  • Via holes 112s that penetrate the second interlayer insulating film 108 and the insulating layer 105 and reach the region 104s are formed.
  • the via holes 162k, 112d, 112s are formed, for example, at the same time.
  • the through hole 511a may be formed at the same time as the via holes 162k, 112d, 112s, or may be formed separately.
  • the via holes 162k, 112d, 112s shown in FIG. 33B are filled with the conductive material to form the vias 161k, 111d, 111s.
  • the bottom portion of the through hole 511a, that is, the upper surface 153U may be covered with a conductive material.
  • the first wiring layer 110 is formed on the second interlayer insulating film 108.
  • a conductive layer forming the first wiring layer 110 is formed on the second interlayer insulating film 108 and processed by etching to include the wiring 110k, 510d, 110s.
  • the wiring layer 110 is formed.
  • the conductive layer is formed on the second interlayer insulating film 108, as well as on the exposed upper surface 153U and the wall surface of the through hole 511a.
  • the wiring 110k connected to the via 161k is formed, the wiring 510d connected to the via 111d is formed, and the wiring 110s connected to the via 111s is formed. Since the wiring 510d is provided over the wall surface of the through hole 511a, it is also connected to the upper surface 153U.
  • An adhesive layer 1170 is provided on the second interlayer insulating film 108 and the first wiring layer 110, and the reinforcing substrate 1180 is adhered by the adhesive layer 1170. After that, the substrate 102 shown in FIG. 33B is thinned by wet etching or the like, and is processed into a thin substrate 502.
  • the color filter 180 is provided on the other surface (second surface) 502b of the substrate 502.
  • the color filter 180 is formed by the inkjet shown in FIGS. 24A to 24D in the case of the other embodiment described above.
  • the color filter 180 can be provided on the surface 502b via the transparent thin film adhesive layer.
  • the substrate 502 may have a resin layer formed on a glass substrate as the substrate 502.
  • the glass substrate may be removed by wet etching or the like, and then the color filter 180 may be formed on the surface 502b from which the glass substrate has been removed.
  • the effect of the image display device of this embodiment will be described.
  • the image display device of the present embodiment has the effect of shortening the time of the transfer step for forming the light emitting element 150 and reducing the number of steps, similarly to the image display device of the other embodiments described above. Play.
  • the light-shielding electrode 560a is provided over the upper surface 153U, it is possible to block the upward scattered light emitted by the light emitting element 150.
  • the transistor 103 provided above the light emitting element 150 is prevented from malfunctioning because the arrival of light is suppressed by the light-shielding electrode 560a.
  • the light-shielding electrode 560a can be formed together with the formation of the via and the formation of the first wiring layer 110, it is not necessary to add a step for forming the light-shielding electrode 560a. Therefore, the manufacturing process can be shortened, and the period from the input of the material to the completion of the product can be shortened.
  • FIG. 35 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
  • the configuration of the light emitting element 650 is different from that of the other embodiments.
  • Other components are the same as in the other embodiments described above. The same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the second wiring layer 440 includes the wiring 640a.
  • the second wiring layer 440 and the wiring 640a are in contact with the first surface 103a.
  • the light emitting element 650 is in contact with the wiring 640a on the light emitting surface 651S and is electrically connected to the wiring 640a.
  • the outer circumference of the wiring 640a is set to include the outer circumference of the light emitting element 650 when the light emitting element 650 is projected onto the wiring 640a in XY plan view.
  • the wiring 640a is provided so as to project on the first surface 103a from directly below the light emitting surface 651S.
  • One end of the via 161k is connected to the protruding region of the wiring 640a. Therefore, the n-type semiconductor layer 651 is electrically connected to, for example, the ground wire 4 of the circuit of FIG. 2 described above via the wiring 640a, the via 161k, and the wiring 110k.
  • the light-shielding layer 330 is provided.
  • the light-shielding layer 330 is the same as that described with reference to FIG. 18 in the third embodiment.
  • the light-shielding layer 330 includes a second portion 630a.
  • the second portion 630a has a region including the outer circumference of the TFT channel 104 when the TFT channel 104 is projected onto the second portion 630a in XY plan view.
  • the light emitting element 650 is provided on the wiring 640a.
  • the light emitting element 650 is a pyramidal trapezoidal or truncated cone-shaped element formed so that the area in the XY plane view becomes smaller toward the positive direction of the Z axis.
  • the light emitting element 650 includes a light emitting surface 651S on the first surface 103a and an upper surface 653U provided on the opposite side of the light emitting surface 651S.
  • the light emitting surface 651S is provided on the first surface 103a.
  • the light emitting element 650 includes an n-type semiconductor layer 651, a light emitting layer 652, and a p-type semiconductor layer 653.
  • the n-type semiconductor layer 651, the light emitting layer 652, and the p-type semiconductor layer 653 are laminated in this order from the side of the first surface 103a.
  • FIG. 36 shows a detailed positional relationship between the first surface 103a and the light emitting element 650.
  • the first surface 103a is a plane substantially parallel to the XY plane.
  • the light emitting element 650 is provided on the first surface 103a
  • the light emitting surface 651S is a surface substantially parallel to the first surface 103a.
  • Wiring 640a is provided on the first surface 103a, and the light emitting surface 651S is provided on the first surface 103a via the wiring 640a.
  • the thickness of the wiring 640a shall be sufficiently thin, and the reflection and absorption of light shall be sufficiently small.
  • the light emitting element 650 has a side surface 655a.
  • the side surface 655a is a surface between the upper surface 653U and the first surface 103a, and is a surface adjacent to the light emitting surface 651S.
  • the internal angle ⁇ of the angle formed between the side surface 655a and the first surface 103a is smaller than 90 °.
  • the internal angle ⁇ is about 70 °. More preferably, the internal angle ⁇ is smaller than the critical angle on the side surface 655a determined based on the refractive index of the light emitting element 650 and the refractive index of the first interlayer insulating film 156.
  • the light emitting element 650 is covered with the first interlayer insulating film 156, and the side surface 655a is in contact with the first interlayer insulating film 156.
  • the critical angle ⁇ c of the internal angle ⁇ formed by the side surface 655a and the first surface 103a of the light emitting element 650 is determined as follows, for example. Assuming that the refractive index n0 of the light emitting element 650 and the refractive index n1 of the first interlayer insulating film 156, the critical angle ⁇ c of the light emitted from the light emitting element 650 to the first interlayer insulating film 156 is determined by using the following equation (1). Desired.
  • the first interlayer insulating film 156 is made of a transparent resin, but even when the transparent resin is made of white resin, the influence on the refractive index of the scattering fine particles due to the white resin is small. Ignored in the calculation.
  • the light having a component in the negative direction of the Z axis is emitted from the side surface 655a at an emission angle corresponding to the refractive index on the side surface 655a.
  • the light incident on the first interlayer insulating film 156 is emitted from the first interlayer insulating film 156 at an angle determined by the refractive index of the first interlayer insulating film 156.
  • the light totally reflected by the side surface 655a is re-reflected by the upper surface 653U, and the light having a negative component in the Z-axis direction among the re-reflected light is emitted from the light emitting surface 651S and the side surface 655a.
  • Light parallel to the first surface 103a and light having a component in the positive direction of the Z axis are totally reflected by the side surface 655a.
  • the light having a component parallel to the first surface 103a and a component in the positive direction of the Z axis has a component directed in the negative direction of the Z axis by the side surface 655a. It is converted into the light it has. Therefore, in the light emitted from the light emitting element 650, the ratio toward the light emitting surface 651S increases, and the substantial luminous efficiency of the light emitting element 650 is improved.
  • the critical angle ⁇ c is about 56 °, so that the internal angle ⁇ to be set is more preferably 45 °, 30 °, or the like. Further, the critical angle ⁇ c becomes smaller in the material having a larger refractive index n. However, even if the internal angle ⁇ is set to about 70 °, most of the light having a component in the negative direction of the Z axis can be converted into light having a component in the positive direction of the Z axis. Then, for example, the internal angle ⁇ may be set to 80 ° or less.
  • the manufacturing process for the light emitting element 650 is different from the case of the other embodiment, and the other manufacturing process can be applied to the case of the other embodiment described above.
  • the different parts of the manufacturing process will be described.
  • the following steps are executed in order to obtain the shape of the light emitting element 650 shown in FIG. 36.
  • the semiconductor layer 1150 shown in FIG. 27B is bonded to the first surface 103a and then processed into the shape of the light emitting element 650 shown in FIG. 35 by etching.
  • the etching rate is selected so that the side surface 655a shown in FIG.
  • etching forms an internal angle ⁇ with respect to the surface of the first surface 103a.
  • a higher etching rate is selected as the upper surface is closer to 653U.
  • the etching rate is set to increase linearly from the side of the light emitting surface 651S toward the side of the upper surface 653U.
  • the resist mask pattern at the time of dry etching at the time of exposure so that it gradually becomes thinner toward the end.
  • the etching amount can be gradually increased from the light emitting surface 651S toward the upper surface 653U by gradually retreating from the thin portion of the resist during dry etching.
  • the side surface 655a of the light emitting element 650 is formed so as to form a constant angle with respect to the first surface 103a. Therefore, in the light emitting element 650, the area of each layer from the upper surface 653U in XY plan is formed so that the area increases in the order of the p-type semiconductor layer 653, the light emitting layer 652, and the n-type semiconductor layer 651.
  • the sub-pixel 620 is formed as in the case of the other embodiments.
  • the image display device of this embodiment has the effect that the time of the transfer step for forming the light emitting element 650 can be shortened and the number of steps can be reduced, similarly to the image display device of the other embodiment described above. In addition, it has the following effects.
  • the light emitting element 650 is formed so as to have a side surface 655a forming an internal angle ⁇ with respect to the first surface 103a provided with the light emitting element 650.
  • the internal angle ⁇ is smaller than 90 ° and is set based on the critical angle ⁇ c determined by the refractive index of each material of the light emitting element 650 and the first interlayer insulating film 156.
  • the internal angle ⁇ can convert the light emitted from the light emitting layer 652 toward the side or the upper side of the light emitting element 650 into the light toward the light emitting surface 651S and emit the light. By sufficiently reducing the internal angle ⁇ , the luminous efficiency of the light emitting element 650 is substantially improved.
  • the light emitting element 650 is a vertical element and is connected to the via 161k by using the second wiring layer 440.
  • the light emitting element may be provided with a connecting portion formed on the first surface 103a so as to be connected to the via 161k via the connecting portion.
  • the connecting portion is provided and connected to the via 161k, the light emitting surface can be roughened.
  • FIG. 37 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
  • the present embodiment differs from the other embodiments in that the image display device includes a subpixel group 720 including a plurality of light emitting regions on one light emitting surface.
  • the same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the image display device of the present embodiment includes a subpixel group 720.
  • the subpixel group 720 includes a substrate 102, a semiconductor layer 750, a first interlayer insulating film 156, a plurality of transistors 103-1 and 103-2, a second interlayer insulating film 108, and a plurality of vias 761a1,761a2. , The first wiring layer 110 and the like.
  • the semiconductor layer 750 is provided on the first surface 103a.
  • the transistors 103-1 and 103-2 by turning on the p-channel transistors 103-1 and 103-2, holes are injected from one of the semiconductor layers 750 via the first wiring layer 110 and vias 761a1 and 761a2.
  • the transistors 103-1 and 103-2 of the p-channel electrons are injected from the other side of the semiconductor layer 750 via the first wiring layer 110. Holes and electrons are injected into the semiconductor layer 750, and the separated light emitting layers 752a1 and 752a2 emit light due to the bonding of holes and electrons.
  • the drive circuit for driving the light emitting layers 752a1 and 752a2 for example, the circuit configuration shown in FIG. 2 is applied.
  • the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer can be interchanged to drive the semiconductor layer with n-channel transistors. In that case, the circuit configuration of FIG. 11 is applied to the drive circuit.
  • the semiconductor layer 750 has a light emitting surface 751S in contact with the first surface 103a.
  • the light emitting surface 751S is a surface of the n-type semiconductor layer 751.
  • the light emitting surface 751S includes a plurality of light emitting regions 751R1 and 751R2.
  • the semiconductor layer 750 includes an n-type semiconductor layer 751, a light emitting layer 752a1, 752a2, and a p-type semiconductor layer 753a1, 753a2.
  • the light emitting layer 752a1 is provided on the n-type semiconductor layer 751.
  • the light emitting layer 752a2 is separated from and separated from the light emitting layer 752a1 and is provided on the n-type semiconductor layer 751.
  • the p-type semiconductor layer 753a1 is provided on the light emitting layer 752a1.
  • the p-type semiconductor layer 753a2 is provided on the light emitting layer 752a2 separately from and separated from the p-type semiconductor layer 753a1.
  • the p-type semiconductor layer 753a1 has an upper surface 753U1 provided on the opposite side of the surface on which the light emitting layer 752a1 is provided.
  • the p-type semiconductor layer 753a2 has an upper surface 753U2 provided on the opposite side of the surface on which the light emitting layer 752a2 is provided.
  • the light emitting region 751R1 substantially coincides with the region of the light emitting surface 751S on the opposite side of the upper surface 753U1.
  • the light emitting region 751R2 substantially coincides with the region of the light emitting surface 751S on the opposite side of the upper surface 753U2.
  • FIG. 38 is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.
  • FIG. 38 is a schematic diagram for explaining the light emitting regions 751R1 and 751R2.
  • the light emitting regions 751R1 and 751R2 are surfaces on the light emitting surface 751S.
  • the portions of the semiconductor layer 750 including the light emitting regions 751R1 and 751R2 are referred to as light emitting units R1 and R2, respectively.
  • the light emitting unit R1 includes a part of the n-type semiconductor layer 751, the light emitting layer 752a1 and the p-type semiconductor layer 753a1.
  • the light emitting unit R2 includes a part of the n-type semiconductor layer 751, the light emitting layer 752a2, and the p-type semiconductor layer 753a2.
  • the semiconductor layer 750 includes the connection portion R0.
  • the connecting portion R0 is provided between the light emitting portions R1 and R2, and is a part of the n-type semiconductor layer 751.
  • One end of the via 761k shown in FIG. 37 is connected to the connecting portion R0, and the connecting portion R0 provides a current path from the via 761k to the light emitting units R1 and R2.
  • the electrons supplied via the connection unit R0 are supplied to the light emitting layer 752a1.
  • the holes supplied through the upper surface 753U1 are supplied to the light emitting layer 752a1.
  • the electrons and holes supplied to the light emitting layer 752a1 are combined and emit light.
  • the light emitted by the light emitting layer 752a1 reaches the light emitting surface 751S through the portion of the n-type semiconductor layer 751 of the light emitting unit R1. Since the light travels substantially straight in the light emitting portion R1 along the Z-axis direction, the light emitted from the light emitting surface 751S is the light emitting region 751R1. Therefore, in this example, the light emitting region 751R1 substantially coincides with the region surrounded by the outer periphery of the light emitting layer 752a1 projected on the light emitting surface 751S in the XY plan view.
  • the light emitting unit R2 is the same as the light emitting unit R1. That is, in the light emitting unit R2, the electrons supplied via the connecting unit R0 are supplied to the light emitting layer 752a2. In the light emitting unit R2, the holes supplied via the upper surface 753U2 are supplied to the light emitting layer 752a2. The electrons and holes supplied to the light emitting layer 752a2 are combined and emit light. The light emitted by the light emitting layer 752a2 reaches the light emitting surface 751S through the portion of the n-type semiconductor layer 751 of the light emitting unit R2.
  • the light emitting region 751R2 substantially coincides with the region surrounded by the outer periphery of the light emitting layer 752a2 projected on the light emitting surface 751S in XY plan view.
  • the semiconductor layer 750 can share the n-type semiconductor layer 751 to form a plurality of light emitting regions 751R1 and 751R2 on the light emitting surface 751S.
  • the semiconductor layer 750 is formed by forming a part of the n-type semiconductor layer 751 as a connecting portion R0 in the plurality of light emitting layers 752a1, 752a2 and the plurality of p-type semiconductor layers 753a1, 753a2 of the semiconductor layer 750. can do. Therefore, the semiconductor layer 750 can be formed in the same manner as the method for forming the light emitting devices 150 and 250 in the case of the first embodiment and the second embodiment described above.
  • the first interlayer insulating film 156 (first insulating film) is provided so as to cover the first surface 103a and the semiconductor layer 750.
  • the TFT lower layer film 106 is formed over the first interlayer insulating film 156.
  • the TFT underlayer film 106 is flattened, and TFT channels 104-1, 104-2, etc. are formed on the TFT underlayer film 106.
  • the insulating layer 105 covers the TFT underlayer film 106 and the TFT channels 104-1 and 104-2.
  • the gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105.
  • the gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105.
  • Transistor 103-1 includes a TFT channel 104-1 and a gate 107-1.
  • Transistor 103-2 includes TFT channel 104-2 and gate 107-2.
  • the second interlayer insulating film (second insulating film) 108 covers the insulating layer 105 and the gates 107-1 and 107-2.
  • the TFT channel 104-1 contains a p-shaped doped region 104s1,104d1, and the region 104s1,104d1 is a source region and a drain region of the transistor 103-1.
  • the region 104i1 is doped in an n-shape and forms a channel of the transistor 103-1.
  • the TFT channel 104-2 includes a p-shaped doped region 104s2, 104d2, and the region 104s2, 104d2 is a source region and a drain region of the transistor 103-2.
  • the region 104i2 is doped in the n form and forms the channel of the transistor 103-2.
  • the circuit 101 includes TFT channels 104-1 and 104-2, an insulating layer 105, a second interlayer insulating film 108, vias 111s1,111d1,111s2,111d2, and a first wiring layer 110.
  • the first wiring layer 110 is provided on the second interlayer insulating film 108.
  • the first wiring layer 110 includes wirings 710s1,710d1,710k, 710d2, 710s2.
  • the wiring 710k is provided above the n-type semiconductor layer 751.
  • the via 761k is provided between the wiring 710k and the n-type semiconductor layer 751, and electrically connects the wiring 710k and the n-type semiconductor layer 751.
  • the wiring 710k is connected to, for example, the ground wire 4 of the circuit of FIG.
  • the vias 111d1, 111s1, 111d2, 111s2 are provided so as to penetrate the second interlayer insulating film 108 and the insulating layer 105.
  • the via 111d1 is provided between the area 104d1 and the wiring 710d1, and electrically connects the area 104d1 and the wiring 710d1.
  • the via 111s1 is provided between the area 104s1 and the wiring 710s1, and electrically connects the area 104s1 and the wiring 710s1.
  • the via 111d2 is provided between the area 104d2 and the wiring 710d2, and electrically connects the area 104d2 and the wiring 710d2.
  • the via 111s2 is provided between the area 104s2 and the wiring 710s2, and electrically connects the area 104s2 and the wiring 710s2.
  • the wirings 710s1 and 710s2 are connected to, for example, the power line 3 of the circuit of FIG.
  • the wiring 710d1 is provided above the upper surface 753U1.
  • the via 761a1 is provided between the wiring 710d1 and the upper surface 753U1, and electrically connects the wiring 710d1 and the upper surface 753U1. Therefore, the p-type semiconductor layer 753a1 is electrically connected to the drain region of the transistor 103-1 via the upper surface 753U1, the via 761a1, the wiring 710d1 and the via 111d1.
  • the wiring 710d2 is provided above the upper surface 753U2.
  • the via 761a2 is provided between the wiring 710d2 and the upper surface 753U2, and electrically connects the wiring 710d2 and the upper surface 753U2. Therefore, the p-type semiconductor layer 753a2 is electrically connected to the drain region of the transistor 103-2 via the upper surface 753U2, the via 761a2, the wiring 710d2, and the via 111d2.
  • the transistors 103-1 and 103-2 are driving transistors of adjacent subpixels and are driven sequentially.
  • the holes supplied from the transistor 103-1 are injected into the light emitting layer 752a1 and the electrons supplied from the wiring 710k are injected into the light emitting layer 752a1, the light emitting layer 752a1 emits light and light is emitted from the light emitting region 751R1.
  • the holes supplied from the transistor 103-2 are injected into the light emitting layer 752a2 and the electrons supplied from the wiring 710k are injected into the light emitting layer 752a2, the light emitting layer 752a2 emits light and light is emitted from the light emitting region 751R2.
  • the holes supplied from the transistor 103-2 are injected into the light emitting layer 752a2 and the electrons supplied from the wiring 710k are injected into the light emitting layer 752a2 emits light and light is emitted from the light emitting region 751R2.
  • the effect of the image display device of this embodiment will be described.
  • the image display device of the present embodiment has the effect of shortening the time of the transfer step for forming the semiconductor layer 750 and reducing the number of steps, similarly to the image display device of the other embodiments described above. Play.
  • the connection unit R0 can be shared by the plurality of light emitting units R1 and R2, the number of vias 761k provided in the connection unit R0 can be reduced. By reducing the number of vias, it becomes possible to reduce the pitch of the light emitting units R1 and R2 constituting the sub-pixel group 720, and it becomes possible to make a small-sized, high-definition image display device.
  • the case of two light emitting regions has been described, but the number of light emitting regions formed on the light emitting surface is not limited to two, and may be any number of three or more.
  • the image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.
  • FIG. 39 is a block diagram illustrating an image display device according to the present embodiment.
  • FIG. 39 shows the main parts of the configuration of a computer display.
  • the image display device 801 includes an image display module 802.
  • the image display module 802 is, for example, an image display device having the configuration of the first embodiment described above.
  • the image display module 802 includes a display area 2, a row selection circuit 5, and a signal voltage output circuit 7 in which a plurality of subpixels including the subpixel 20 are arranged.
  • the image display device 801 further includes a controller 870.
  • the controller 870 inputs a control signal separated and generated by an interface circuit (not shown) to control the drive and drive order of each subpixel to the row selection circuit 5 and the signal voltage output circuit 7.
  • the image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.
  • FIG. 40 is a block diagram illustrating an image display device according to a modified example of the present embodiment.
  • FIG. 40 shows the configuration of a high-definition flat-screen television.
  • the image display device 901 includes an image display module 902.
  • the image display module 902 is, for example, an image display device 1 having the configuration of the first embodiment described above.
  • the image display device 901 includes a controller 970 and a frame memory 980.
  • the controller 970 controls the drive order of each subpixel in the display area 2 based on the control signal supplied by the bus 940.
  • the frame memory 980 stores display data for one frame and is used for processing such as smooth moving image reproduction.
  • the image display device 901 has an I / O circuit 910.
  • the I / O circuit 910 is simply referred to as "I / O" in FIG. 40.
  • the I / O circuit 910 provides an interface circuit or the like for connecting to an external terminal, a device, or the like.
  • the I / O circuit 910 includes, for example, a USB interface for connecting an external hard disk device or the like, an audio interface, or the like.
  • the image display device 901 has a receiving unit 920 and a signal processing unit 930.
  • An antenna 922 is connected to the receiving unit 920, and a necessary signal is separated and generated from the radio wave received by the antenna 922.
  • the signal processing unit 930 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 920 is converted into image data, audio data, etc. by the signal processing unit 930. Separated and generated.
  • an image display device provided with an image display module having an appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.
  • the image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, but may be a modification thereof or the case of another embodiment. As shown in FIGS. 9 and 25, the image display module in the case of the present embodiment and the modified example is configured to include a large number of subpixels.
  • 1,201,301,501,801,901 Image display device 2 Display area, 3 Power supply line, 4 Ground line, 5,205 line selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8, 208 signal line, 10 pixels, 20,220,320,420,520,620 subpixels, 22,222 light emitting element, 24,224 selection transistor, 26,226 drive transistor, 28,228 capacitor, 100 drive circuit unit, 101 Circuit, 102, 402, 502 substrate, 103a, 180a first surface, 103, 103-1, 103-2, 203 transistor, 104, 104-1, 104-2, 204 TFT channel, 105 insulating layer, 107, 107 -1,107-2 gate, 108 second interlayer insulating film, 110 first wiring layer, 150,250,650 light emitting element, 151a, 253a, R0 connection part, 151S, 151S1,253S, 651S, 751S light emitting surface, 156 1st interlayer insulating film, 161a, 161k, 261a,

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JP2022550477A JP7669643B2 (ja) 2020-09-17 2021-09-03 画像表示装置の製造方法および画像表示装置
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