WO2022052001A1 - 增强型半导体结构及其制作方法 - Google Patents

增强型半导体结构及其制作方法 Download PDF

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WO2022052001A1
WO2022052001A1 PCT/CN2020/114581 CN2020114581W WO2022052001A1 WO 2022052001 A1 WO2022052001 A1 WO 2022052001A1 CN 2020114581 W CN2020114581 W CN 2020114581W WO 2022052001 A1 WO2022052001 A1 WO 2022052001A1
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layer
type semiconductor
passivation layer
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algan
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PCT/CN2020/114581
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/628,534 priority Critical patent/US20220359334A1/en
Priority to PCT/CN2020/114581 priority patent/WO2022052001A1/zh
Priority to CN202080103838.7A priority patent/CN116134590A/zh
Publication of WO2022052001A1 publication Critical patent/WO2022052001A1/zh

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Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to an enhancement type semiconductor structure and a fabrication method thereof.
  • III nitride semiconductors are the third generation of new semiconductor materials after the first and second generation semiconductor materials such as Si and GaAs.
  • III nitride semiconductors have high saturation electron mobility, high breakdown voltage and wide band gap. Because of these characteristics, GaN-based High Electron Mobility Transistor (HEMT) devices have broad application prospects.
  • HEMT High Electron Mobility Transistor
  • the principle is that when the HEMT device works in the off state, the electric field strength of the gate biased to the drain side reaches the maximum, and the electrons on the gate transition to the surface of the barrier layer under the action of the electric field force, and donate energy on its surface.
  • the interstage migrates laterally in the direction of the drain, neutralizing the ionized donor on the surface and depleting the electrons in the channel, forming a "virtual gate"; when the working state of the HEMT device changes from off to on, the surface of the barrier layer Electrons migrating from the gate migrate back to the gate at a slow rate.
  • the electrons on the surface of the barrier layer cannot migrate back to the gate in time, resulting in an increase in the resistance in the on-state, which may be several times the static on-resistance, that is, current collapse.
  • the purpose of the present invention is to provide an enhancement type semiconductor structure and a fabrication method thereof to solve the problem of current collapse.
  • a first aspect of the present invention provides a method for fabricating an enhanced semiconductor structure, comprising:
  • the second passivation layer is removed by dry etching, and the first passivation layer is used for the dry etching an etching stop layer during etching;
  • the first passivation layer is removed by wet etching, and the cap layer is used to protect the heterojunction structure during the wet etching;
  • a P-type semiconductor layer is formed at least on the inner wall of the groove.
  • the p-type semiconductor layer is a p-GaN layer, a p-AlGaN layer, a stacked structure of a p-AlGaN layer and a p-GaN layer, or a stacked structure of an AlGaN layer and a p-GaN layer.
  • the manufacturing method of the P-type semiconductor layer is a selective growth method, and the P-type semiconductor layer is only located in the groove;
  • the P-type semiconductor layer is a p-AlGaN layer
  • the P-type semiconductor layer is fabricated by a full-surface epitaxial growth method and selectively etched, and the p-AlGaN layer is also located in the second passivation of the gate region. on the chemical layer;
  • the manufacturing method of the p-type semiconductor layer is a whole-surface epitaxial growth method and selective etching is performed, and the The stacked structure of the p-AlGaN layer and the p-GaN layer is also located on the second passivation layer in the gate region;
  • the manufacturing method of the P-type semiconductor layer is a whole-surface epitaxial growth method and selective etching is performed, and the AlGaN layer is The stacked structure with the p-GaN layer is also on the second passivation layer of the gate region.
  • the material combination of the second passivation layer and the first passivation layer includes: SiNx/amorphous AlN, SiNx / SiO2 , or SiO2 / SiNx .
  • the material of the cap layer is GaN.
  • a gate electrode is formed on the P-type semiconductor layer, and a source electrode and a drain electrode are formed on both sides of the gate electrode.
  • the heterojunction structure includes a channel layer and a barrier layer from bottom to top, and the source electrode and the drain electrode are in contact with the channel layer or the barrier layer.
  • a second aspect of the present invention provides an enhancement-mode semiconductor structure, comprising:
  • the p-type semiconductor layer is a p-GaN layer
  • the p-type semiconductor layer is a p-AlGaN layer, and the p-AlGaN layer is also located on the second passivation layer in the gate region;
  • the p-type semiconductor layer is a stacked structure of p-AlGaN layer and p-GaN layer distributed from bottom to top, and the stacked structure of p-AlGaN layer and p-GaN layer is also located in all parts of the gate region. on the second passivation layer;
  • the p-type semiconductor layer is a p-GaN layer
  • an AlGaN layer is further provided between the p-GaN layer and the cap layer
  • the stacked structure of the AlGaN layer and the p-GaN layer is also located in the gate region. on the second passivation layer.
  • the material combination of the second passivation layer and the first passivation layer includes: SiNx/amorphous AlN, SiNx / SiO2 , or SiO2 / SiNx .
  • the material of the cap layer is GaN.
  • the heterojunction structure includes a Group III nitride material.
  • the semiconductor structure further includes: a gate on the P-type semiconductor layer; and a source electrode and a drain on both sides of the gate.
  • the heterojunction structure includes a channel layer and a barrier layer from bottom to top, and the source electrode and the drain electrode are in contact with the channel layer or the barrier layer.
  • the heterojunction structure includes a Group III nitride material.
  • the enhancement type semiconductor structure further includes: on the P-type semiconductor layer in the gate region, and/or on the heterojunction structure in the source region, and/or on the heterojunction structure in the drain region N-type ion heavily doped layer on a heterojunction structure.
  • the enhancement type semiconductor structure further comprises: a gate electrode located on the N-type ion heavily doped layer in the gate region, a source electrode located on the N-type ion heavily doped layer in the source region , the drain located on the N-type ion heavily doped layer in the drain region.
  • the first passivation layer can be used to detect the etching end point when the second passivation layer is dry-etched to form the groove to avoid over-etching.
  • the first passivation layer exposed at the groove of the second passivation layer may be removed by wet etching.
  • the cap layer has extremely high stability, so the wet etching can not only completely remove the first passivation layer, but also does not damage the cap layer.
  • the non-damaged cap layer can effectively reduce the surface defects of the heterojunction structure to reduce the probability of electrons being trapped by the defects, thereby increasing the rate of electron release back to the gate, reducing the current collapse effect and reducing the dynamic on-resistance.
  • the material of the cap layer is GaN.
  • the negatively polarized charge between the GaN cap layer and the heterojunction structure enhances the electric field in the heterojunction structure, which can increase the rate at which electrons are released back to the gate to further reduce the current collapse effect and reduce the dynamic on-resistance.
  • the material of the second passivation layer is SiN x
  • the material of the first passivation layer is amorphous AlN.
  • SiN x can be removed by dry etching using F-containing gas.
  • F-containing gas has a high etching selectivity ratio for SiN x and amorphous AlN, that is, it has a faster etching rate for SiN x and a slower etching rate for amorphous AlN. Therefore, the dry etching end point can be effectively detected, and the dry etching can be stopped in time.
  • the amorphous AlN exposed by the second passivation layer can be removed by alkaline solutions such as KOH and NaOH, and the alkaline solutions such as KOH and NaOH are non-corrosive on the Ga surface of the GaN cap layer, so it is difficult to remove the amorphous AlN. At the same time, the GaN cap layer will not be damaged.
  • the material of the second passivation layer is SiN x and the material of the first passivation layer is SiO 2 ; or c) the material of the second passivation layer is SiO 2 and the material of the first passivation layer is SiN x .
  • SiN x or SiO 2 can be removed by dry etching using a mixture of CF-based gas and oxygen.
  • the etching selectivity ratio of SiN x and SiO 2 can be increased or decreased, such as b ) scheme, increasing the content of oxygen can significantly improve the etching rate of SiN x , so SiO 2 can effectively detect the end point of dry etching, and stop dry etching in time; c) scheme, reduce the content of oxygen , which can significantly improve the etching rate of SiO 2 , so SiN x can effectively detect the end point of dry etching and stop dry etching in time.
  • the SiO 2 exposed by the second passivation layer can be removed with HF acid solution, and SiN x can be removed with hot phosphoric acid solution, and HF acid and hot phosphoric acid are not corrosive to the GaN cap layer, so while removing the first passivation layer , will not damage the GaN cap layer.
  • FIG. 1 is a flowchart of a method for fabricating an enhancement-mode semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 to 4 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1;
  • FIG. 5 is a schematic cross-sectional structure diagram of the enhancement mode semiconductor structure according to the first embodiment of the present invention.
  • 5-1 is another cross-sectional structural schematic diagram of the enhancement-mode semiconductor structure according to the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of an enhancement-mode semiconductor structure according to a second embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating the enhancement type semiconductor structure in FIG. 6;
  • FIG. 8 is a schematic cross-sectional structure diagram of an enhancement-mode semiconductor structure according to a third embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional structural diagram of an enhancement-mode semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of the enhancement mode semiconductor structure according to the fifth embodiment of the present invention.
  • the first passivation layer 13 The second passivation layer 14
  • Drain region 1c Source region 1b
  • FIG. 1 is a flowchart of a method for fabricating an enhanced semiconductor structure according to a first embodiment of the present invention
  • FIGS. 2 to 4 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 1
  • FIG. 5 is an enhanced semiconductor structure according to the first embodiment of the present invention. Schematic diagram of the cross-sectional structure of the semiconductor structure.
  • a heterojunction structure 11 a cap layer 12 , a first passivation layer 13 and a second passivation layer 14 are sequentially formed on the semiconductor substrate 10 .
  • the material of the semiconductor substrate 10 may be a group III nitride material.
  • the group III nitride material may be at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • a certain material is represented by a chemical element, but the molar ratio of each chemical element in the material is not limited.
  • GaN material contains Ga element and N element, but the molar ratio of Ga element and N element is not limited;
  • AlGaN material contains three elements, Al, Ga, and N, but the molar ratio of each is not limited.
  • the semiconductor substrate 10 may also include: at least one of sapphire, silicon carbide, and silicon, or at least one of sapphire, silicon carbide, and silicon, and a group III nitride material thereon, which is not limited in this embodiment. .
  • the heterojunction structure 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • a two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b.
  • the channel layer 11a and the barrier layer 11b can each have one layer; or b) the channel layer 11a and the barrier layer 11b can each have multiple layers and alternately distributed; or c) one channel layer 11a and two or more barrier layers 11b to meet different functional requirements.
  • the material combination of the channel layer 11a and the barrier layer 11b may include: GaN/AlN, GaN/InN, GaN/AlGaN, GaAs/AlGaAs, GaN/InAlN, or InN/InAlN.
  • the molar ratio of Al may range from 5% to 25%, and the thickness range may range from 1 nm to 20 nm.
  • the formation process of the channel layer 11a and/or the barrier layer 11b may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE) , Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal Organic Compound Chemical Vapor Deposition (MOCVD) , Metal-Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Compound Chemical Vapor Deposition
  • Metal-Organic Chemical Vapor Deposition Metal-Organic Chemical Vapor Deposition
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc.
  • the material of the buffer layer may include At least one of AlN, GaN, AlGaN, and AlInGaN.
  • the nucleation layer can alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction structure 11 and the semiconductor substrate 10, and the buffer layer can reduce the epitaxially grown semiconductor layer The dislocation density and defect density of the layer are improved, and the crystal quality is improved.
  • the material of the cap layer 12 may be GaN.
  • the upper surface of the GaN cap layer may be a Ga face.
  • the GaN crystal has a brazinite structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms bonds with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking the Ga-N bond parallel to the C-axis ([0001] crystal orientation) as a reference, if the Ga atoms in each Ga-N bond are further away from the lower surface, the upper surface is the Ga surface; The N atom in a Ga-N bond is further away from the lower surface, then the upper surface is an N-face.
  • the formation method of the cap layer 12 may refer to the formation process of the channel layer 11a or the barrier layer 11b.
  • the material of the first passivation layer 13 may be amorphous AlN; the material of the second passivation layer 14 may be SiN x . In other optional solutions, the material combination of the second passivation layer 14 and the first passivation layer 13 may also be: SiN x /SiO 2 , or SiO 2 /SiN x .
  • the formation process of the amorphous AlN may include: metal organic compound chemical vapor deposition method, chemical vapor deposition method, physical vapor deposition method, or atomic layer deposition method.
  • the formation process of SiN x or SiO 2 may include chemical vapor deposition, or physical vapor deposition.
  • the second passivation layer 14 may also be SiN x formed by low pressure chemical vapor deposition (LPCVD), and the first passivation layer 13 may be SiN x formed by plasma enhanced chemical vapor deposition (PECVD).
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the above structure includes a gate region 1a, and a source region 1b and a drain region 1c located on both sides of the gate region 1a.
  • a groove 15 penetrating the first passivation layer 13 and the second passivation layer 14 is formed; the second passivation layer 14 adopts a dry etching method Remove, the first passivation layer 13 is used for the etching stop layer during dry etching; the first passivation layer 13 is removed by wet etching, and the cap layer 12 is used to protect the heterojunction structure during wet etching 11.
  • the dry etching may use the patterned mask layer 16 as a mask.
  • the material of the patterned mask layer 16 may be photoresist.
  • the wet etching is maskless etching.
  • the wet etching may also use a mask layer as a mask, and the mask layer has a window for exposing the first passivation layer 13 .
  • SiN x can be dry etched by using F-containing gas (CF 4 , or C 3 F 8 , etc.) Removal, the F-containing gas has a high etching selectivity ratio for SiN x and amorphous AlN, that is, it has a faster etching rate for SiN and a slower etching rate for amorphous AlN, so it can effectively detect dry etching. At the end point, stop dry etching in time.
  • F-containing gas CF 4 , or C 3 F 8 , etc.
  • the amorphous AlN exposed by the second passivation layer 14 can be removed by using alkaline solutions such as KOH, NaOH, etc., and the alkaline solutions such as KOH and NaOH are non-corrosive on the Ga surface of the GaN cap layer. Therefore, in the removal of amorphous AlN At the same time, the GaN cap layer will not be damaged.
  • SiN x can be removed by dry etching using a mixed gas of CF-based gas and oxygen, and can be removed by adjusting the CF-based
  • the mixing ratio of gas and oxygen such as increasing the content of oxygen, can significantly increase the etching rate of SiN, so SiO 2 can effectively detect the end point of dry etching and stop dry etching in time.
  • the SiO 2 exposed by the second passivation layer 14 can be removed by using HF acid solution, and the HF acid is not corrosive to the GaN cap layer, so the GaN cap layer will not be damaged when the first passivation layer 13 is removed.
  • SiO 2 can be removed by dry etching using a mixed gas of CF-based gas and oxygen, and can be removed by adjusting the CF-based
  • the mixing ratio of gas and oxygen such as reducing the content of oxygen, can significantly increase the etching rate of SiO2 , so SiNx can effectively detect the end point of dry etching and stop dry etching in time.
  • the exposed SiN x of the second passivation layer 14 can be removed by using a hot phosphoric acid solution, and the hot phosphoric acid is not corrosive to the GaN cap layer, so the GaN cap layer will not be damaged when the first passivation layer 13 is removed.
  • the P-type semiconductor layer 17 is formed at least on the inner wall of the groove 15 .
  • the P-type semiconductor layer 17 can deplete the two-dimensional electron gas in the heterojunction structure 11 and turn off the conduction of the channel; that is, the P-type semiconductor layer 17 is used to form a normally off state, that is, an enhancement type structure is formed. .
  • the material of the P-type semiconductor layer 17 may be a group III nitride material, and the corresponding formation method may refer to the formation process of the channel layer 11a or the barrier layer 11b.
  • the P-type doping ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions or Ba ions, and an in-situ doping method can be used, that is, doping while growing.
  • the material of the formed P-type semiconductor layer 17 is p-AlGaN.
  • the p-AlGaN layer can be epitaxially grown on the inner wall of the groove 15 and the second passivation layer 14; after that, the p-AlGaN layer outside the gate region 1a is removed by dry etching or wet etching, and the gate is retained.
  • the dry etching may be inductively coupled plasma etching (ICP).
  • the etching gas may include: Cl 2 and BCl 3 .
  • Wet etching can use alkaline solutions such as KOH and NaOH.
  • the formed P-type semiconductor layer 17 may also be a stacked structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top. At this time, the stacked structure of the p-AlGaN layer and the p-GaN layer is not only located on the inner wall of the trench 15 but also on the second passivation layer 14 of the gate region 1a.
  • the material of the formed p-type semiconductor layer 17 is a layered structure of AlGaN and p-GaN distributed from bottom to top.
  • an AlGaN layer is first formed on the inner wall of the groove 15 and the second passivation layer 14; after that, the gate region 1a is removed by dry etching or wet etching.
  • the stacked structure of the AlGaN layer and the p-GaN layer on the second passivation layer 14 in the gate region 1a remains.
  • the material of the formed p-type semiconductor layer 17 is p-GaN, and the p-GaN layer can only be selectively epitaxially grown in the groove 15 .
  • the enhancement type semiconductor structure 1 of the first embodiment includes:
  • the semiconductor substrate 10, the heterojunction structure 11, the cap layer 12, the first passivation layer 13 and the second passivation layer 14 are distributed from bottom to top;
  • the groove 15 (refer to FIG. 4 ) penetrates through the first passivation layer 13 and the second passivation layer 14;
  • the semiconductor substrate 10 may be a Group III nitride material.
  • the group III nitride material may be at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • the semiconductor substrate 10 may also include: at least one of sapphire, silicon carbide, and silicon, or at least one of sapphire, silicon carbide, and silicon, and a group III nitride material thereon, which is not limited in this embodiment. .
  • the heterojunction structure 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • a two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b.
  • the channel layer 11a and the barrier layer 11b can each have one layer; or b) the channel layer 11a and the barrier layer 11b can each have multiple layers and alternately distributed; or c) one channel layer 11a and two or more barrier layers 11b to meet different functional requirements.
  • the material combination of the channel layer 11a and the barrier layer 11b may include: GaN/AlN, GaN/InN, GaN/AlGaN, GaAs/AlGaAs, GaN/InAlN, or InN/InAlN.
  • the molar ratio of Al may range from 5% to 25%, and the thickness range may range from 1 nm to 20 nm.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc.
  • the material of the buffer layer may include At least one of AlN, GaN, AlGaN, and AlInGaN.
  • the nucleation layer can alleviate the problem of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction structure 11 and the semiconductor substrate 10, and the buffer layer can reduce the epitaxially grown semiconductor layer The dislocation density and defect density of the layer are improved, and the crystal quality is improved.
  • the material of the cap layer 12 may be GaN.
  • the upper surface of the GaN cap layer may be a Ga face.
  • the GaN crystal has a brazinite structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms bonds with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking the Ga-N bond parallel to the C-axis ([0001] crystal orientation) as a reference, if the Ga atoms in each Ga-N bond are further away from the lower surface, the upper surface is the Ga surface; The N atom in a Ga-N bond is further away from the lower surface, then the upper surface is an N-face.
  • the material of the first passivation layer 13 may be amorphous AlN; the material of the second passivation layer 14 may be SiN x .
  • the material combination of the second passivation layer 14 and the first passivation layer 13 may also be: SiN x /SiO 2 , or SiO 2 /SiN x .
  • the second passivation layer 14 may also be SiN x formed by low pressure chemical vapor deposition (LPCVD), and the first passivation layer 13 may be SiN x formed by plasma enhanced chemical vapor deposition (PECVD).
  • the p-type semiconductor layer 17 is a p-AlGaN layer.
  • the p-AlGaN layer is not only located on the inner wall of the groove 15, but also on the second passivation layer 14 of the gate region 1a.
  • the p-type semiconductor layer 17 may also be a stacked structure of a p-AlGaN layer and a p-GaN layer distributed from bottom to top. At this time, the stacked structure of the p-AlGaN layer and the p-GaN layer is not only located on the inner wall of the trench 15 but also on the second passivation layer 14 of the gate region 1a.
  • the p-type semiconductor layer 17 is a p-GaN layer.
  • the stacked structure of the AlGaN layer and the p-GaN layer is not only located on the inner wall of the trench 15 but also on the second passivation layer 14 of the gate region 1a.
  • the p-type semiconductor layer 17 is a p-GaN layer, and the p-GaN layer is only located in the groove 15 .
  • the second passivation layer 14 can reduce the gate leakage current formed by channel leakage to the gate 19a (see FIG. 6 ) in the device.
  • the non-damaged cap layer 12 can be formed in the process of etching the grooves 15 .
  • the non-damaged cap layer 12 can effectively reduce the surface defects of the heterojunction structure 11 to reduce the probability of electrons being trapped by the defects, thereby increasing the rate at which electrons are released back to the gate 19a (see FIG. 6 ) to achieve reduced current collapse effect and reduce dynamic on-resistance.
  • the negatively polarized charge between the GaN cap layer and the heterojunction structure 11 enhances the electric field in the heterojunction structure 11, which can further increase the release of electrons back to the gate 19a ( See Figure 6) to further reduce the current collapse effect and reduce the dynamic on-resistance.
  • the enhancement type semiconductor structure 1 can be produced and sold as a semi-finished product of a semiconductor device.
  • FIG. 6 is a schematic cross-sectional structure diagram of an enhancement type semiconductor structure according to a second embodiment of the present invention
  • FIG. 7 is a flowchart of a method for fabricating the enhancement type semiconductor structure in FIG. 6 .
  • the enhancement type semiconductor structure 2 and the fabrication method thereof in the second embodiment are substantially the same as the enhancement type semiconductor structure 1 and the fabrication method in the first embodiment, the only difference being that the enhancement type semiconductor structure 2 also has It includes: a gate electrode 19a located on the P-type semiconductor layer 17; and a source electrode 19b and a drain electrode 19c located on both sides of the gate electrode 19a.
  • the manufacturing method further includes: step S4 , forming a gate electrode 19 a on the P-type semiconductor layer 17 , and forming a source electrode 19 b and a drain electrode 19 c on both sides of the gate electrode 19 a .
  • the second passivation layer 14 , the first passivation layer 13 and the cap layer 12 of the source region 1 b and the drain region 1 c may be removed.
  • the source electrode 19b and the drain electrode 19c are in contact with the barrier layer 11b, and an ohmic contact is formed therebetween. Ohmic contact is also formed between the gate electrode 19a and the P-type semiconductor layer 17 .
  • the material of the source electrode 19b, the drain electrode 19c, and the gate electrode 19a can be metal, for example, existing conductive materials such as Ti/Al/Ni/Au, Ni/Au and the like.
  • the ohmic contact between the source electrode 19b and the barrier layer 11b, the ohmic contact between the drain electrode 19c and the barrier layer 11b, and the ohmic contact between the gate electrode 19a and the P-type semiconductor layer 17 may be formed by high temperature annealing.
  • FIG. 8 is a schematic cross-sectional structure diagram of an enhancement mode semiconductor structure according to a third embodiment of the present invention.
  • the enhancement type semiconductor structure 3 of the third embodiment and the fabrication method thereof are substantially the same as the enhancement type semiconductor structure 2 of the second embodiment and the fabrication method thereof, the only difference being that the source electrode 19b and the drain electrode 19c contact the trenches The track layer 11a is formed, and an ohmic contact is formed therebetween.
  • step S4 of the manufacturing method not only the second passivation layer 14 , the first passivation layer 13 , and the cap layer 12 of the source region 1 b and the drain region 1 c are removed, but also the barrier layer 11 b is removed.
  • the ohmic contact between the source electrode 19b and the channel layer 11a and the ohmic contact between the drain electrode 19c and the channel layer 11a may be formed by high temperature annealing.
  • FIG. 9 is a schematic cross-sectional structure diagram of an enhancement mode semiconductor structure according to a fourth embodiment of the present invention.
  • the enhancement type semiconductor structure 4 of the fourth embodiment is substantially the same as the enhancement type semiconductor structures 2 and 3 of the second and third embodiments, the only difference being that the enhancement type semiconductor structure 4 further includes: N-type ion heavily doped layer 18 between the heterojunction structure 11 in the region 1b and the source electrode 19b, and between the heterojunction structure 11 in the drain region 1c and the drain electrode 19c.
  • N-type ion heavily doped layer 18 between the P-type semiconductor layer 17 and the gate electrode 19a in the gate region 1a.
  • the material of the N-type ion heavily doped layer 18 may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN, wherein the N-type doped ions may be Si ions, Ge ions, Sn ions, Se At least one of ions or Te ions; the corresponding formation method can refer to the formation process of the channel layer 11a or the barrier layer 11b.
  • the doping concentration can be greater than 1E19/cm 3 .
  • the N-type ion heavily doped layer 18 can directly form ohmic contact between the source electrode 19b and the heterojunction structure 11, the drain electrode 19c and the heterojunction structure 11, the gate electrode 19a and the P-type semiconductor layer 17 without high temperature annealing.
  • the performance of the heterojunction structure 11 is prevented from being degraded due to the high temperature in the annealing process, and the electron migration rate is reduced.
  • At least one of the P-type semiconductor layer 17 , the heterojunction structure 11 of the source region 1b and the heterojunction structure 11 of the drain region 1c may have an N-type ion heavily doped layer 18 .
  • the heterojunction structure 11 of the drain region 1c of the N-type ion heavily doped layer 18 forms an ohmic contact with the drain 19c through high temperature annealing.
  • FIG. 10 is a schematic cross-sectional structure diagram of the enhancement mode semiconductor structure according to the fifth embodiment of the present invention.
  • the enhancement type semiconductor structure 5 and its fabrication method of the fifth embodiment are substantially the same as the enhancement type semiconductor structure 4 and its fabrication method of the fourth embodiment, the only difference being that the enhancement type semiconductor structure 5 is an intermediate semiconductor structure , the gate electrode 19a, the source electrode 19b and the drain electrode 19c are not fabricated.
  • step S4 the manufacturing method omits step S4.

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Abstract

本申请提供了一种半导体结构及其制作方法，半导体结构包括：自下而上分布的半导体衬底、异质结结构、帽层、第一钝化层以及第二钝化层；贯穿第一钝化层与第二钝化层的凹槽；以及至少位于凹槽的内壁的P型半导体层。在干法刻蚀第二钝化层形成凹槽后，第一钝化层可用于刻蚀终点检测，避免过刻蚀。在第二钝化层凹槽处暴露出的第一钝化层，可通过湿法刻蚀去除。湿法刻蚀去除第一钝化层时，帽层具有极高的稳定性，所以湿法腐蚀去除第一钝化层后，不会损伤帽层。无损伤的帽层能有效降低异质结结构的表面缺陷，以降低电子被缺陷捕获的几率，实现减弱电流崩塌效应以及降低动态导通电阻。

Description

增强型半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种增强型半导体结构及其制作方法。
背景技术
III氮化物半导体是继Si、GaAs等第一、第二代半导体材料之后的第三代新型半导体材料。III氮化物半导体具有较高的饱和电子迁移速率，高击穿电压和宽禁带宽度，正因为这些特性，基于GaN的高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)器件具有广阔应用前景。
现有的III族氮化物半导体HEMT器件作为高频器件或者高压大功率开关器件使用时，存在“电流崩塌”现象。即当器件工作在直流脉冲模式或者高频模式下，漏极输出电流跟不上栅极控制信号的变化，会出现漏极电流瞬时减小、动态导通电阻增大的情况，这严重影响器件的应用。这种现象归根结底是由于极化效应在带来异质结界面沟道中二维电子气(2DEG)的同时，使得异质结中势垒层上表面形成电荷密度与2DEG浓度相当的带正电荷的离化施主造成的。其原理在于，当HEMT器件工作在截止状态时，栅极偏向漏极一侧的电场强度达到最大，栅极上的电子在电场力的作用下跃迁至势垒层表面，并在其表面施主能级间向漏极的方向横向迁移，中和了表面的离化施主并耗尽沟道中的电子，形成“虚栅”；当HEMT器件的工作状态从截止转为导通时，势垒层表面从栅极迁移来的电子会以缓慢的速率迁移回栅极。但是当HEMT器件以一定的频率开关时，势垒层表面的电子就不能及时迁移回栅极，造成导通状态下的电阻升高，可能几倍于静态导通电阻，即电流崩塌。
有鉴于此，实有必要提供一种新的增强型半导体结构及其制作方法，以解决上述问题。
发明内容
本发明的发明目的是提供一种增强型半导体结构及其制作方法，解决电流崩塌问题。
为实现上述目的，本发明的第一方面提供一种增强型半导体结构的制作方法，包括：
在半导体衬底上依次形成异质结结构、帽层、第一钝化层以及第二钝化层；
形成贯穿所述第一钝化层与所述第二钝化层的凹槽；所述第二钝化层采用干法刻蚀法去除，所述第一钝化层用于所述干法刻蚀时的刻蚀终止层；所述第一钝化层采用湿法刻蚀法去除，所述帽层用于所述湿法刻蚀时保护所述异质结结构；
至少在所述凹槽的内壁形成P型半导体层。
可选地，所述P型半导体层为p-GaN、p-AlGaN层、p-AlGaN层与p-GaN层的叠层结构或AlGaN层与p-GaN层的叠层结构。
可选地：
所述P型半导体层为p-GaN层时，所述P型半导体层制作方法为选择性生长方法，所述P型半导体层只位于凹槽内；
或所述P型半导体层为p-AlGaN层时，P型半导体层制作方法为整面外延生长方法并进行选择性刻蚀，所述p-AlGaN层还位于栅极区域的所述第二钝化层上；
或所述P型半导体层为自下而上分布的p-AlGaN层与p-GaN层的叠层 结构时，P型半导体层制作方法为整面外延生长方式并进行选择性刻蚀，所述p-AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层上；
或所述P型半导体层为自下而上分布的AlGaN层与p-GaN层的叠层结构时，P型半导体层制作方法为整面外延生长方式并进行选择性刻蚀，所述AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层上。
可选地，所述第二钝化层与所述第一钝化层的材料组合包括：SiNx/无定形AlN、SiN x/SiO 2、或SiO 2/SiN x。
可选地，所述帽层的材料为GaN。
可选地，在所述P型半导体层上形成栅极，在所述栅极两侧形成源极与漏极。
可选地，所述异质结结构自下而上包括沟道层与势垒层，所述源极与漏极接触所述沟道层或所述势垒层。
本发明的第二方面提供一种增强型半导体结构，包括：
自下而上分布的半导体衬底、异质结结构、帽层、第一钝化层以及第二钝化层；
贯穿所述第一钝化层与所述第二钝化层的凹槽；
以及至少位于所述凹槽的内壁的P型半导体层。
可选地：
所述P型半导体层为p-GaN层；
或所述P型半导体层为p-AlGaN层，所述p-AlGaN层还位于栅极区域的所述第二钝化层上；
或所述P型半导体层为自下而上分布的p-AlGaN层与p-GaN层的叠层结构，所述p-AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层上；
或所述P型半导体层为p-GaN层，所述p-GaN层与所述帽层之间还具有AlGaN层，所述AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层上。
可选地，所述第二钝化层与所述第一钝化层的材料组合包括：SiNx/无定形AlN、SiN x/SiO 2、或SiO 2/SiN x。
可选地，所述帽层的材料为GaN。
可选地，所述异质结结构包括Ⅲ族氮化物材料。
可选地，所述半导体结构还包括：位于所述P型半导体层上的栅极；以及位于所述栅极两侧的源极与漏极。
可选地，所述异质结结构自下而上包括沟道层与势垒层，所述源极与漏极接触所述沟道层或所述势垒层。
可选地，所述异质结结构包括Ⅲ族氮化物材料。
可选地，所述增强型半导体结构还包括：位于所述栅极区域的P型半导体层上，和/或源极区域的所述异质结结构上，和/或漏极区域的所述异质结结构上的N型离子重掺杂层。
可选地，所述增强型半导体结构还包括：位于所述栅极区域的N型离子重掺杂层上的栅极，位于所述源极区域的N型离子重掺杂层上的源极，位于所述漏极区域的N型离子重掺杂层上的漏极。
与现有技术相比，本发明的有益效果在于：
1)在干法刻蚀第二钝化层形成凹槽后，第一钝化层在干法刻蚀第二钝化层形成凹槽时，可用于刻蚀终点检测，避免过刻蚀。在第二钝化层凹槽处暴露出的第一钝化层，可通过湿法刻蚀去除。湿法刻蚀去除第一钝化层时，帽层具有极高的稳定性，所以湿法腐蚀不但可以完全去除第一钝化层，且不会损伤帽层。无损伤的帽层能有效降低异质结结构的表面缺陷，以降低电子 被缺陷捕获的几率，从而增加电子释放回栅极的速率，实现减弱电流崩塌效应以及降低动态导通电阻。
2)可选方案中，帽层的材料为GaN。GaN帽层和异质结结构之间的负极化电荷，使得异质结结构中的电场增强，能增加电子释放回栅极的速率，以进一步减弱电流崩塌效应以及降低动态导通电阻。
3)可选方案中，a)第二钝化层的材料为SiN x，第一钝化层的材料为无定形AlN。SiN x可以采用含F气体进行干法刻蚀去除，含F气体对SiN x与无定形AlN有高刻蚀选择比，即对SiN x有较快刻蚀速率，而对无定形AlN有较慢刻蚀速率，因而能有效检测到干法刻蚀终点，及时停止干法刻蚀。第二钝化层暴露出的无定形AlN可采用KOH、NaOH等碱性溶液去除，且KOH、NaOH等碱性溶液在GaN帽层的Ga表面上是非腐蚀性的，因而在去除无定形AlN的同时，不会损伤GaN帽层。
或b)第二钝化层的材料为SiN x，第一钝化层的材料为SiO 2；或c)第二钝化层的材料为SiO 2，第一钝化层的材料为SiN x。SiN x或SiO 2可以采用CF基气体与氧气的混合气体进行干法刻蚀去除，可通过调整CF基气体与氧气的混合比例，提高或降低SiN x与SiO 2的刻蚀选择比，例如b)方案中，增大氧气的含量，可显著提高SiN x的刻蚀速率，因而SiO 2能有效检测到干法刻蚀终点，及时停止干法刻蚀；c)方案中，减小氧气的含量，可显著提高SiO 2的刻蚀速率，因而SiN x能有效检测到干法刻蚀终点，及时停止干法刻蚀。第二钝化层暴露出的SiO 2可采用HF酸溶液去除，SiN x可采用热磷酸溶液去除，且HF酸、热磷酸对GaN帽层无腐蚀性，因而在去除第一钝化层的同时，不会损伤GaN帽层。
附图说明
图1是本发明第一实施例的增强型半导体结构的制作方法的流程图；
图2至图4是图1中的流程对应的中间结构示意图；
图5是本发明第一实施例的增强型半导体结构的截面结构示意图；
图5-1是本发明第一实施例的增强型半导体结构的另一截面结构示意图；
图6是本发明第二实施例的增强型半导体结构的截面结构示意图；
图7是图6中的增强型半导体结构的制作方法的流程图；
图8是本发明第三实施例的增强型半导体结构的截面结构示意图；
图9是本发明第四实施例的增强型半导体结构的截面结构示意图；
图10是本发明第五实施例的增强型半导体结构的截面结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
增强型半导体结构1、2、3、4、5  半导体衬底10
异质结结构11              帽层12
第一钝化层13              第二钝化层14
凹槽15                    图形化的掩膜层16
P型半导体层17             N型离子重掺杂层18
沟道层11a                 势垒层11b
栅极19a                   源极19b
漏极19c                   栅极区域1a
漏极区域1c                源极区域1b
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附 图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的增强型半导体结构的制作方法的流程图；图2至图4是图1中的流程对应的中间结构示意图；图5是本发明第一实施例的增强型半导体结构的截面结构示意图。
首先，参照图1中的步骤S1与图2所示，在半导体衬底10上依次形成异质结结构11、帽层12、第一钝化层13以及第二钝化层14。
半导体衬底10的材料可以为Ⅲ族氮化物材料。Ⅲ族氮化物材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
需要说明的是，本实施例中，以化学元素代表某种材料，但不限定该材料中各化学元素的摩尔占比。例如GaN材料中，包含Ga元素与N元素，但不限定Ga元素与N元素的摩尔占比；AlGaN材料中，包含Al、Ga、N三种元素，但不限定各自的摩尔占比大小。
半导体衬底10也可以包括：蓝宝石、碳化硅和硅中的至少一种，或蓝宝石、碳化硅和硅中的至少一种及其上的Ⅲ族氮化物材料，本实施例对此不加以限制。
异质结结构11自下而上可以包括沟道层11a与势垒层11b。沟道层11a与势垒层11b的界面处可形成二维电子气。具体地，a)沟道层11a与势垒层11b可以分别具有一层；或b)沟道层11a与势垒层11b可以分别具有多层，且交替分布；或c)一层沟道层11a与两层或两层以上的势垒层11b，以满足不同功能需求。
沟道层11a与势垒层11b的材料组合可以包括：GaN/AlN、GaN/InN、GaN/AlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
势垒层11b的材料为AlGaN时，Al的摩尔占比范围可以包括：5％～25％，厚度范围可以包括：1nm～20nm。
沟道层11a和/或势垒层11b的形成工艺可以包括：原子层沉积法(ALD， Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学气相沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
异质结结构11与半导体衬底10之间自下而上还可以具有成核层与缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层，例如异质结结构11中的沟道层11a与半导体衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
帽层12的材料可以为GaN。GaN帽层的上表面可以为Ga面。GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面；若每一个Ga-N键中的N原子更远离下表面，则上表面为N面。
帽层12的形成方法可以参照沟道层11a或势垒层11b的形成工艺。
第一钝化层13的材料可以为无定形AlN；第二钝化层14的材料可以为SiN x。其它可选方案中，第二钝化层14与第一钝化层13的材料组合还可以为：SiN x/SiO 2、或SiO 2/SiN x。无定形AlN的形成工艺可以包括：金属有机化合物化学气相沉积法、化学气相沉积法、物理气相沉积法、或原子层沉积法。SiN x或SiO 2的形成工艺可以包括：化学气相沉积法、或物理气相沉积法。
此外，第二钝化层14还可以为低压化学气相沉积法(LPCVD)形成的 SiN x，第一钝化层13可以为等离子体增强化学气相沉积法(PECVD)形成的SiN x。
上述结构包括栅极区域1a，以及位于栅极区域1a两侧的源极区域1b与漏极区域1c。
接着，参照图1中的步骤S2、图2至图4所示，形成贯穿第一钝化层13与第二钝化层14的凹槽15；第二钝化层14采用干法刻蚀法去除，第一钝化层13用于干法刻蚀时的刻蚀终止层；第一钝化层13采用湿法刻蚀法去除，帽层12用于湿法刻蚀时保护异质结结构11。
参照图2所示，干法刻蚀可以采用图形化的掩膜层16作为掩膜。图形化的掩膜层16的材料可以为光刻胶。
参照图3所示，本实施例中，湿法刻蚀为无掩膜刻蚀。其它实施例中，湿法刻蚀也可以以掩膜层作为掩膜，该掩膜层具有暴露第一钝化层13的窗口。
当第二钝化层14的材料为SiN x，第一钝化层13的材料为无定形AlN时：SiN x可以采用含F气体(CF 4、或C 3F 8等)进行干法刻蚀去除，含F气体对SiN x与无定形AlN有高刻蚀选择比，即对SiN有较快刻蚀速率，而对无定形AlN有较慢刻蚀速率，因而能有效检测到干法刻蚀终点，及时停止干法刻蚀。第二钝化层14暴露出的无定形AlN可采用KOH、NaOH等碱性溶液去除，且KOH、NaOH等碱性溶液在GaN帽层的Ga表面上是非腐蚀性的，因而在去除无定形AlN的同时，不会损伤GaN帽层。
当第二钝化层14的材料为SiN x，第一钝化层13的材料为SiO 2时：SiN x可以采用CF基气体与氧气的混合气体进行干法刻蚀去除，可通过调整CF基气体与氧气的混合比例，例如增大氧气的含量，可显著提高SiN的刻蚀速率，因而SiO 2能有效检测到干法刻蚀终点，及时停止干法刻蚀。第二钝化层14暴露出的SiO 2可采用HF酸溶液去除，且HF酸对GaN帽层无腐蚀性，因而在去除第一钝化层13的同时，不会损伤GaN帽层。
当第二钝化层14的材料为SiO 2，第一钝化层13的材料为SiN x时：SiO 2可以采用CF基气体与氧气的混合气体进行干法刻蚀去除，可通过调整CF基气体与氧气的混合比例，例如减小氧气的含量，可显著提高SiO 2的刻蚀速率，因而SiN x能有效检测到干法刻蚀终点，及时停止干法刻蚀。第二钝化层14暴露出的SiN x可采用热磷酸溶液去除，且热磷酸对GaN帽层无腐蚀性，因而在去除第一钝化层13的同时，不会损伤GaN帽层。
之后，参照图1中的步骤S3与图5所示，至少在凹槽15的内壁形成P型半导体层17。
本实施例中，P型半导体层17可以耗尽异质结结构11中的二维电子气，关断沟道的导电；即利用P型半导体层17形成常关态，也即形成增强型结构。
P型半导体层17的材料可以为Ⅲ族氮化物材料，对应的形成方法可以参照沟道层11a或势垒层11b的形成工艺。其中的P型掺杂离子可以为Mg离子、Zn离子、Ca离子、Sr离子或Ba离子中的至少一种，可以采用原位掺杂法，即边生长边掺杂。
更具体地，图5所示实施例中，形成的P型半导体层17的材料为p-AlGaN。p-AlGaN层可外延生长于凹槽15的内壁以及第二钝化层14上；后通过干法刻蚀法或湿法刻蚀法，去除栅极区域1a以外的p-AlGaN层，保留栅极区域1a的第二钝化层14上的p-AlGaN层。
干法刻蚀可以为感应耦合等离子体刻蚀(ICP)。刻蚀气体可以包括：Cl 2与BCl 3。湿法刻蚀可采用KOH、NaOH等碱性溶液。
一些实施例中，形成的P型半导体层17还可以为自下而上分布的p-AlGaN层与p-GaN层的叠层结构。此时，p-AlGaN层与p-GaN层的叠层结构不但位于沟槽15的内壁，还位于栅极区域1a的第二钝化层14上。
一些实施例中，形成的P型半导体层17的材料为为自下而上分布的AlGaN与p-GaN叠层结构。此时，形成的P型半导体层17前，先在凹槽15 的内壁以及第二钝化层14上形成AlGaN层；后通过干法刻蚀法或湿法刻蚀法，去除栅极区域1a以外的AlGaN层与p-GaN层的叠层结构，保留栅极区域1a的第二钝化层14上的AlGaN层与p-GaN层的叠层结构。
一些实施例中，如图5-1所示，形成的P型半导体层17的材料为p-GaN，p-GaN层仅可选择性外延生长于凹槽15内。
参照图5和图5-1所示，本实施例一的增强型半导体结构1包括：
自下而上分布的半导体衬底10、异质结结构11、帽层12、第一钝化层13以及第二钝化层14；
贯穿第一钝化层13与第二钝化层14的凹槽15(参照图4所示)；
以及至少位于凹槽15的内壁的P型半导体层17。
半导体衬底10可以为Ⅲ族氮化物材料。Ⅲ族氮化物材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
半导体衬底10也可以包括：蓝宝石、碳化硅和硅中的至少一种，或蓝宝石、碳化硅和硅中的至少一种及其上的Ⅲ族氮化物材料，本实施例对此不加以限制。
异质结结构11自下而上可以包括沟道层11a与势垒层11b。沟道层11a与势垒层11b的界面处可形成二维电子气。具体地，a)沟道层11a与势垒层11b可以分别具有一层；或b)沟道层11a与势垒层11b可以分别具有多层，且交替分布；或c)一层沟道层11a与两层或两层以上的势垒层11b，以满足不同功能需求。
沟道层11a与势垒层11b的材料组合可以包括：GaN/AlN、GaN/InN、GaN/AlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。
势垒层11b的材料为AlGaN时，Al的摩尔占比范围可以包括：5％～25％，厚度范围可以包括：1nm～20nm。
异质结结构11与半导体衬底10之间自下而上还可以具有成核层与缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层，例如异质结结构11中的沟道层11a与半导体衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
帽层12的材料可以为GaN。GaN帽层的上表面可以为Ga面。GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面；若每一个Ga-N键中的N原子更远离下表面，则上表面为N面。
第一钝化层13的材料可以为无定形AlN；第二钝化层14的材料可以为SiN x。其它可选方案中，第二钝化层14与第一钝化层13的材料组合还可以为：SiN x/SiO 2、或SiO 2/SiN x。此外，第二钝化层14还可以为低压化学气相沉积法(LPCVD)形成的SiN x，第一钝化层13可以为等离子体增强化学气相沉积法(PECVD)形成的SiN x。
图5所示实施例中，P型半导体层17为p-AlGaN层。p-AlGaN层不但位于凹槽15的内壁，还位于栅极区域1a的第二钝化层14上。
一些实施例中，P型半导体层17还可以为自下而上分布的p-AlGaN层与p-GaN层的叠层结构。此时，p-AlGaN层与p-GaN层的叠层结构不但位于沟槽15的内壁，还位于栅极区域1a的第二钝化层14上。
一些实施例中，P型半导体层17为p-GaN层。此时，p-GaN层与帽层12之间还具有AlGaN层。AlGaN层与p-GaN层的叠层结构不但位于沟槽15的内壁，还位于栅极区域1a的第二钝化层14上。
一些实施例中，P型半导体层17为p-GaN层，p-GaN层仅位于凹槽15内。
第二钝化层14可以减小器件中沟道泄漏到栅极19a(参见图6所示)形成的栅泄漏电流。
通过第一钝化层13的设置，刻蚀凹槽15工艺中可形成无损伤的帽层12。无损伤的帽层12能有效降低异质结结构11的表面缺陷，以降低电子被缺陷捕获的几率，从而增加电子释放回栅极19a(参见图6所示)的速率，以实现减弱电流崩塌效应以及降低动态导通电阻。另一方面，帽层12的材料为GaN时，GaN帽层和异质结结构11之间的负极化电荷，使得异质结结构11中电场的增强，能进一步增加电子释放回栅极19a(参见图6所示)的速率，以进一步减弱电流崩塌效应以及降低动态导通电阻。
增强型半导体结构1可以作为半导体器件的半成品生产与销售。
图6是本发明第二实施例的增强型半导体结构的截面结构示意图，图7是图6中的增强型半导体结构的制作方法的流程图。
参照图6与图7所示，本实施例二的增强型半导体结构2及其制作方法与实施例一的增强型半导体结构1及其制作方法大致相同，区别仅在于：增强型半导体结构2还包括：位于P型半导体层17上的栅极19a；以及位于栅极19a两侧的源极19b与漏极19c。
对应地，参照图7所示，制作方法还包括：步骤S4，在P型半导体层17上形成栅极19a，在栅极19a两侧形成源极19b与漏极19c。
具体地，可以去除源极区域1b与漏极区域1c的第二钝化层14、第一钝化层13以及帽层12。
本实施例二中，源极19b与漏极19c接触势垒层11b，且两者之间形成欧姆接触。栅极19a与P型半导体层17之间也形成欧姆接触。源极19b、漏极19c、栅极19a的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电 材质。
源极19b与势垒层11b之间的欧姆接触、漏极19c与势垒层11b之间的欧姆接触、以及栅极19a与P型半导体层17之间的欧姆接触可通过高温退火形成。
图8是本发明第三实施例的增强型半导体结构的截面结构示意图。
参照图8所示，本实施例三的增强型半导体结构3及其制作方法与实施例二的增强型半导体结构2及其制作方法大致相同，区别仅在于：源极19b与漏极19c接触沟道层11a，且两者之间形成欧姆接触。
对应地，制作方法的步骤S4中，不但去除源极区域1b与漏极区域1c的第二钝化层14、第一钝化层13、帽层12，还去除势垒层11b。
源极19b与沟道层11a之间的欧姆接触、漏极19c与沟道层11a之间的欧姆接触可通过高温退火形成。
图9是本发明第四实施例的增强型半导体结构的截面结构示意图。
参照图9所示，本实施例四的增强型半导体结构4与实施例二、实施例三的增强型半导体结构2、3大致相同，区别仅在于：增强型半导体结构4还包括：位于源极区域1b的异质结结构11与源极19b之间，漏极区域1c的异质结结构11与漏极19c之间的N型离子重掺杂层18。
栅极区域1a的P型半导体层17与栅极19a之间也具有N型离子重掺杂层18。
N型离子重掺杂层18的材料可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种，其中的N型掺杂离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种；对应的形成方法可以参照沟道层11a或势垒层11b的形成工艺。对于不同的N型离子，掺杂浓度可以大于1E19/cm 3。
N型离子重掺杂层18能使源极19b与异质结结构11、漏极19c与异质结结构11、栅极19a与P型半导体层17不通过高温退火即可直接形成欧姆接触，以及避免退火过程中的高温造成异质结结构11的性能下降，电子迁移速率降低。
一些实施例中，也可以P型半导体层17、源极区域1b的异质结结构11与漏极区域1c的异质结结构11中的至少一个上具有N型离子重掺杂层18。未设置N型离子重掺杂层18的P型半导体层17与栅极19a、未设置N型离子重掺杂层18的源极区域1b的异质结结构11与源极19b、或未设置N型离子重掺杂层18的漏极区域1c的异质结结构11与漏极19c通过高温退火形成欧姆接触。
图10是本发明第五实施例的增强型半导体结构的截面结构示意图。
参照图10所示，本实施例五的增强型半导体结构5及其制作方法与实施例四的增强型半导体结构4及其制作方法大致相同，区别仅在于：增强型半导体结构5为中间半导体结构，未制作栅极19a、源极19b与漏极19c。
对应地，制作方法省略步骤S4。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

  1. 一种增强型半导体结构的制作方法，其特征在于，包括：
    在半导体衬底(10)上依次形成异质结结构(11)、帽层(12)、第一钝化层(13)以及第二钝化层(14)；
    形成贯穿所述第一钝化层(13)与所述第二钝化层(14)的凹槽(15)；所述第二钝化层(14)采用干法刻蚀法去除，所述第一钝化层(13)用于所述干法刻蚀时的刻蚀终止层；所述第一钝化层(13)采用湿法刻蚀法去除，所述帽层(12)用于所述湿法刻蚀时保护所述异质结结构(11)；
    至少在所述凹槽(15)的内壁形成P型半导体层(17)。
  2. 根据权利要求1所述的增强型半导体结构的制作方法，其特征在于，所述P型半导体层(17)为p-GaN、p-AlGaN层、p-AlGaN层与p-GaN层的叠层结构或AlGaN层与p-GaN层的叠层结构。
  3. 根据权利要求2所述的增强型半导体结构的制作方法，其特征在于：
    所述P型半导体层(17)为p-GaN层时，所述P型半导体层(17)制作方法为选择性生长方法，所述P型半导体层(17)只位于凹槽(15)内；
    或所述P型半导体层(17)为p-AlGaN层时，P型半导体层(17)制作方法为整面外延生长方法并进行选择性刻蚀，所述p-AlGaN层还位于栅极区域的所述第二钝化层(14)上；
    或所述P型半导体层(17)为自下而上分布的p-AlGaN层与p-GaN层的叠层结构时，P型半导体层(17)制作方法为整面外延生长方式并进行选择性刻蚀，所述p-AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层(14)上；
    或所述P型半导体层(17)为自下而上分布的AlGaN层与p-GaN层的叠层结构时，P型半导体层(17)制作方法为整面外延生长方式并进行选择性刻蚀，所述AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层(14)上。
  4. 根据权利要求1所述的增强型半导体结构的制作方法，其特征在于，所述第二钝化层(14)与所述第一钝化层(13)的材料组合包括：SiNx/无定形AlN、SiN x/SiO 2、或SiO 2/SiN x。
  5. 根据权利要求1所述的增强型半导体结构的制作方法，其特征在于，所述帽层(12)的材料为GaN。
  6. 根据权利要求1所述的增强型半导体结构的制作方法，其特征在于，在所述P型半导体层(17)上形成栅极(19a)，在所述栅极(19a)两侧形成源极(19b)与漏极(19c)。
  7. 根据权利要求6所述的增强型半导体结构的制作方法，其特征在于，所述异质结结构(11)自下而上包括沟道层(11a)与势垒层(11b)，所述源极(19b)与漏极(19c)接触所述沟道层(11a)或所述势垒层(11b)。
  8. 一种增强型半导体结构，其特征在于，包括：
    自下而上分布的半导体衬底(10)、异质结结构(11)、帽层(12)、第一钝化层(13)以及第二钝化层(14)；
    贯穿所述第一钝化层(13)与所述第二钝化层(14)的凹槽(15)；
    以及至少位于所述凹槽(15)的内壁的P型半导体层(17)。
  9. 根据权利要求8所述的增强型半导体结构，其特征在于：
    所述P型半导体层(17)为p-GaN层；
    或所述P型半导体层(17)为p-AlGaN层，所述p-AlGaN层还位于栅极区域的所述第二钝化层(14)上；
    或所述P型半导体层(17)为自下而上分布的p-AlGaN层与p-GaN层的叠层结构，所述p-AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层(14)上；
    或所述P型半导体层(17)为p-GaN层，所述p-GaN层与所述帽层(12)之间还具有AlGaN层，所述AlGaN层与p-GaN层的叠层结构还位于栅极区域的所述第二钝化层(14)上。
  10. 根据权利要求8所述的增强型半导体结构，其特征在于，所述第二 钝化层(14)与所述第一钝化层(13)的材料组合包括：SiN x/无定形AlN、SiN x/SiO 2、或SiO 2/SiN x。
  11. 根据权利要求8所述的增强型半导体结构，其特征在于，所述帽层(12)的材料为GaN。
  12. 根据权利要求8所述的增强型半导体结构，其特征在于，所述异质结结构(11)包括Ⅲ族氮化物材料。
  13. 根据权利要求8所述的增强型半导体结构，其特征在于，所述半导体结构还包括：位于所述P型半导体层(17)上的栅极(19a)；以及位于所述栅极(19a)两侧的源极(19b)与漏极(19c)。
  14. 根据权利要求13所述的增强型半导体结构，其特征在于，所述异质结结构(11)自下而上包括沟道层(11a)与势垒层(11b)，所述源极(19b)与漏极(19c)接触所述沟道层(11a)或所述势垒层(11b)。
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