WO2022042611A1 - 芯片时钟驱动单元套件和设计方法以及芯片 - Google Patents

芯片时钟驱动单元套件和设计方法以及芯片 Download PDF

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Publication number
WO2022042611A1
WO2022042611A1 PCT/CN2021/114567 CN2021114567W WO2022042611A1 WO 2022042611 A1 WO2022042611 A1 WO 2022042611A1 CN 2021114567 W CN2021114567 W CN 2021114567W WO 2022042611 A1 WO2022042611 A1 WO 2022042611A1
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clock
chip
driving unit
unit
capability
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PCT/CN2021/114567
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English (en)
French (fr)
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王瑾瑜
黄强
何宏瑾
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中兴通讯股份有限公司
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Publication of WO2022042611A1 publication Critical patent/WO2022042611A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

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  • the present application relates to integrated circuit technology, for example, to a chip clock drive unit kit and design method, and a chip.
  • the chip clock structure is more and more important to the timing closure of the entire chip.
  • Large-scale chips need to use a reasonable clock tree to control the influence of process, voltage, temperature (PVT) and cross-corner, and structurally ensure the clock skew under each corner. ) can be controlled within a reasonable range.
  • PVT process, voltage, temperature
  • OCV on Chip Variation
  • the driving capability of the clock driving unit in the chip is designed according to the maximum clock connection length in the chip, but this is likely to cause overdrive for other clock connection lengths, thereby increasing the consumption on the clock path.
  • Embodiments of the present application provide a chip clock driving unit kit and design method, and a chip.
  • an embodiment of the present application provides a method for designing a chip clock drive unit kit, including: determining the longest clock connection length in the chip; designing the maximum clock drive unit of the chip according to the longest clock connection length, so that the The drive capability of the maximum clock drive unit is the maximum clock drive capability required by the chip corresponding to the longest clock connection length; the clock drive capability of at least one other clock drive unit of the design chip is smaller than the maximum clock drive capability of the at least one other clock drive unit.
  • the clock drive capability of the clock drive unit, and the external dimensions and ports of at least one other clock drive unit are the same as the largest clock drive unit, and the chip clock drive unit kit includes the largest clock drive unit and at least one other clock drive unit.
  • an embodiment of the present application provides a chip clock driving unit kit, including: at least two clock driving units, the clock driving capabilities of the at least two clock driving units are different;
  • the maximum clock drive unit is designed according to the maximum clock drive capacity required by the chip, and the maximum clock drive capacity required by the chip is determined according to the longest clock connection length in the chip;
  • the external dimensions and ports of at least two clock drive units are the same, and at least two The external dimensions and ports of each clock drive unit are determined according to the largest clock drive unit.
  • an embodiment of the present application provides a chip, including: a chip clock driving unit kit as shown in any possible implementation manner of the second aspect.
  • FIG. 1 is a flowchart of a method for designing a chip clock drive unit kit provided by an embodiment
  • FIG. 2 is a flowchart of another chip clock drive unit kit design method provided by an embodiment
  • FIG. 3 is a schematic structural diagram of a chip clock driving unit kit according to an embodiment.
  • FIG. 1 is a flowchart of a method for designing a chip clock driving unit kit provided by an embodiment. As shown in FIG. 1 , the method provided by this embodiment includes the following steps.
  • Step S1010 determining the longest clock connection length in the chip.
  • the chip clock driving unit kit design method provided in this embodiment is used to design a clock driving unit in an integrated circuit chip.
  • a chip in order to realize a variety of different functions, it is necessary to design a plurality of different functional units, and different functional units are realized by designing different arrangements of transistors in the chip.
  • Various different functional units in a chip generally require a clock signal to achieve synchronization, so a clock driving unit needs to be designed in the chip to drive the clock for different functional units in the chip.
  • the design of the clock tree (Clock Tree) is proposed in the chip design, including H-Tree, X-Tree, balanced-Tree and so on.
  • the design of the clock tree can well control the influence of PVT and cross-corner in the chip.
  • the clock drive unit with the maximum clock drive capability is designed in consideration of the maximum clock drive capability required by the chip.
  • the clock driving unit with the maximum clock driving capability is used to drive all the functional units, which increases the consumption on the clock path, thereby increasing the power consumption of the chip.
  • Step S1020 the maximum clock driving unit of the chip is designed according to the longest clock connection length, and the driving capability of the maximum clock driving unit is the maximum clock driving capability required by the chip corresponding to the longest clock connection length.
  • the clock driving capability required by various functional units in the chip is determined according to the length of the clock connection.
  • the maximum clock driving unit of the chip only needs to be able to meet the maximum clock driving capability required by the chip, and the specific design method thereof is a conventional technical means of those skilled in the art, which will not be repeated here.
  • Step S1030 design at least one other clock drive unit of the chip, the clock drive capability of at least one other clock drive unit is smaller than the clock drive capability of the maximum clock drive unit, and the external size and port of the at least one other clock drive unit are the same as the maximum clock drive unit.
  • the units are the same, the chip clock drive unit kit includes the largest clock drive unit and at least one other clock drive unit.
  • a clock drive unit kit in the chip.
  • Multiple clock drive units may be included in a clock drive unit kit.
  • the clock drive unit kit of the chip needs to include at least the largest clock drive unit, and at least one other clock drive unit other than the largest clock drive unit. That is to say, the clock driving unit kit includes at least two clock driving units.
  • the clock driving capability of at least one other clock driving unit is smaller than the clock driving capability of the largest clock driving unit.
  • one of the largest clock drive units is designed according to the maximum clock drive capability required by the chip, and the clock drive capability of at least one other clock drive unit is smaller than the clock drive capability of the largest clock drive unit, That is, some functional units in the chip can be driven by other clock driving units, thereby reducing the power consumption on the clock path.
  • the lengths of the clock connections are 1000u, 500u, and 200u, respectively.
  • the number of the at least one other clock driving unit may be one or more, and the clock driving capability of the at least one other clock driving unit may be any clock driving capability smaller than the clock driving capability of the largest clock driving unit.
  • the external dimensions and interfaces of at least one other clock drive unit can be designed according to the external dimensions and ports of the largest clock drive unit, so that the All clock driver units in the clock driver unit kit have the same external dimensions and ports.
  • the functional unit in the chip is changed and the clock driving unit needs to be replaced, it is only necessary to re-select the clock driving unit that satisfies the changed functional unit from the clock driving unit kit and replace the original clock driving unit.
  • Other parts are redesigned to further improve the efficiency of chip design.
  • the external dimensions and ports of the at least one other clock driving unit are the same as the largest clock driving unit, including: the external dimensions, port positions, port shapes, port sizes, port metal layers and maximum
  • the clock drive unit is the same.
  • the same external dimensions can prevent the replacement of the clock drive unit from affecting the design of other functional units in the chip.
  • the port location, port shape, port size, and port metal layer are the same, so you can replace the clock drive unit without changing the connection method of other functional units. .
  • the longest clock connection length in the chip is first determined, the maximum clock driving capability required by the chip is determined according to the longest clock connection length, and the maximum clock driving capability of the chip is designed according to the maximum clock driving capability.
  • the clock drive capability of at least one other clock drive unit is smaller than the clock drive capability of the largest clock drive unit, and the external size and port of at least one other clock drive unit
  • the clock drive units are the same, so that the largest clock drive unit and at least one other clock drive unit form a clock drive unit suite of the chip, which reduces the power consumption consumed on the clock path in the chip, thereby reducing the power consumption of the entire chip, and also improves the chip. design efficiency.
  • FIG. 2 is a flowchart of another method for designing a chip clock driving unit kit provided by an embodiment. As shown in FIG. 2 , the method provided by this embodiment includes the following steps.
  • Step S2010 determining the longest clock connection length in the chip.
  • the chip clock driving unit kit design method provided in this embodiment is used to design a clock driving unit in an integrated circuit chip.
  • a chip in order to realize a variety of different functions, it is necessary to design a plurality of different functional units, and different functional units are realized by designing different arrangements of transistors in the chip.
  • Various different functional units in a chip generally require a clock signal to achieve synchronization, so a clock driving unit needs to be designed in the chip to drive the clock for different functional units in the chip.
  • the design of the clock tree (Clock Tree) is proposed in the chip design, including H-Tree, X-Tree, balanced-Tree and so on.
  • the design of the clock tree can well control the influence of PVT and cross-corner in the chip.
  • the clock driving unit with the maximum clock driving capability is designed in consideration of the maximum clock driving capability required by the chip.
  • the clock driving unit with the maximum clock driving capability is used to drive all the functional units, which increases the consumption on the clock path, thereby increasing the power consumption of the chip.
  • Step S2020 the maximum clock driving unit of the chip is designed according to the longest clock connection length, and the driving capability of the maximum clock driving unit is the maximum clock driving capability required by the chip corresponding to the longest clock connection length.
  • the clock driving capability required by various functional units in the chip is determined according to the length of the clock connection.
  • the maximum clock driving unit of the chip only needs to be able to meet the maximum clock driving capability required by the chip, and the specific design method thereof is a conventional technical means of those skilled in the art, which will not be repeated here.
  • Step S2030 design the minimum clock driving unit of the chip according to the shortest clock connection length in the chip, and the driving capability of the minimum clock driving unit is the minimum clock driving capability required by the chip corresponding to the shortest clock connection length.
  • the minimum clock driving unit of the chip may also be designed according to the minimum clock driving capability required by the chip.
  • the minimum clock drive unit of the chip is set to provide clock drive to the functional unit in the chip that requires the least clock drive capability. Similar to the method of determining the maximum clock driving unit, first design the minimum clock driving unit of the chip according to the shortest clock connection length. The minimum clock driving unit of the chip only needs to meet the minimum clock driving capability required by the chip. After the minimum clock driving unit of the chip is determined, the maximum clock driving unit and the minimum clock driving unit can be used to provide clock driving for the chip.
  • the external dimensions and ports of the smallest clock driver unit are the same as those of the largest clock driver unit.
  • the chip clock drive unit kit may include the largest clock drive unit and the smallest clock drive unit.
  • Step S2040 design at least one intermediate clock driving unit of the chip, and the clock driving capability of the at least one intermediate clock driving unit is smaller than that of the largest clock driving unit and greater than that of the smallest clock driving unit.
  • At least one intermediate clock driving unit of the chip may also be designed.
  • the clock driving capability of at least one intermediate clock driving unit is located between the largest clock driving unit and the smallest clock driving unit, ie, less than the clock driving capability of the largest clock driving unit and greater than the clock driving capability of the smallest clock driving unit.
  • the number of the at least one intermediate clock driving unit may be one or more.
  • the clock driving capability of the at least one intermediate clock driving unit may be distributed linearly or non-linearly between the maximum clock driving capability required by the chip and the minimum clock driving capability required by the chip.
  • multiple clock driving capabilities can be determined according to the length of the clock connection of the designed functional units in the chip, and then the maximum clock driving unit, the minimum clock driving unit and a plurality of intermediate clock driving units can be correspondingly designed to form a clock driving unit kit.
  • the clock driving capability required by the functional units in the chip changes, you can select other suitable clock driving units in the clock driving unit kit to replace the original clock driving unit.
  • the external dimensions and ports of the at least one intermediate clock driving unit are the same as the largest clock driving unit.
  • the chip clock driving unit kit may include a maximum clock driving unit, a minimum clock driving unit and at least one intermediate clock driving unit.
  • At least one intermediate clock driving capability can also be selected with a preset step size between the maximum clock driving capability and the minimum clock driving capability of the chip, and then at least one intermediate clock driving unit is designed according to the at least one intermediate clock driving capability. That is, after determining the maximum clock driving capability and the minimum clock driving capability of the chip and designing the maximum clock driving unit and the minimum clock driving unit, select a suitable step size, and determine one or more between the maximum clock driving capability and the minimum clock driving capability. Multiple intermediate clock drive capability. Then one or more corresponding intermediate clock driving units are designed according to the one or more intermediate clock driving capabilities, and finally the largest clock driving unit, the smallest clock driving unit and one or more intermediate clock driving units are composed of a clock driving unit kit.
  • a suitable clock driving unit can be selected in the clock driving unit kit, and when the clock driving capability required by each functional unit changes, the clock driving unit kit can be selected from the clock driving unit kit.
  • Select other suitable clock drive units can be set according to requirements. For example, first determine that the longest clock connection length in the chip is 1000u, and the minimum clock connection length is 200u, and respectively design the maximum clock driving unit m and the minimum clock driving unit n. Then, the preset step length is determined to be 200u, and then the intermediate clock driving units corresponding to the minimum clock connection lengths of 800u, 600u, and 400u are designed accordingly.
  • the number of transistors in the maximum clock driving unit may be reduced to obtain at least one other clock driving unit.
  • the clock drive unit in the chip also realizes the function of the clock drive unit through different arrangements and connections of multiple transistors. The greater the clock drive capability required by the clock drive unit, the greater the number of transistors required. Then the number of transistors in the largest clock drive unit with the largest clock drive capability in the chip is also the largest. Therefore, after designing the largest clock driving unit, on the basis of the largest clock driving unit, the design of at least one other clock driving unit can be completed by reducing the number of transistors in the largest clock driving unit. In this way, there is no need to redesign other clock driving units, and it is beneficial to ensure that the external dimensions and ports of at least one other clock driving unit are the same as the largest clock driving unit.
  • the circuit design can be carried out, and the replaced size of the P/N in each clock driving unit is determined by pre-simulation, and then the size is adjusted by simulation.
  • the layout design can be carried out, including the following steps: 1) First establish the layout structure and size of the largest clock drive unit, the largest clock drive unit needs to be completed first, and the entire clock drive unit kit
  • the layout size of each clock drive unit is the same, so the size of the largest clock drive unit is very important. It is necessary to consider the special rules of the layout under the advanced technology, consider the antenna effect, consider the parasitic effect, consider the influence of the outside world on the drive unit, consider the electromigration (Electrical Migration, EM) effect and consider the data flow. Finally, the size of the largest clock drive unit and the position, size and direction of the input and output ports are obtained.
  • FIG. 3 is a schematic structural diagram of a chip clock drive unit kit provided by an embodiment. As shown in FIG. 3 , the chip clock drive unit kit provided by this embodiment includes:
  • At least two clock driving units 31, the clock driving capabilities of the at least two clock driving units 31 are different; the largest clock driving unit with the largest clock driving capability among the at least two clock driving units 31 is designed according to the maximum clock driving capability required by the chip.
  • the required maximum clock driving capability is determined according to the longest clock connection length in the chip; the external dimensions and ports of at least two clock driving units 31 are the same, and the external dimensions and ports of at least two clock driving units 31 are determined according to the maximum clock driving unit Sure.
  • four clock driving units 31 are taken as an example, and each clock driving unit 31 has the same input interface IN and output interface OUT and the same external dimensions.
  • the chip clock drive unit kit provided in this embodiment is designed according to the design method of the chip clock drive unit kit shown in FIG. 1 , and its specific implementation principle and technical effect have been described in detail in the embodiment shown in FIG. 1 , and will not be repeated here. Repeat.
  • the largest clock driving unit with the smallest clock driving capability among the at least two clock driving units 31 is designed according to the minimum clock driving capability required by the chip, and the minimum clock driving capability required by the chip is based on the shortest clock connection length in the chip.
  • At least two clock driving units 31 further include at least one intermediate clock driving unit; the clock driving capability of at least one intermediate clock driving unit is smaller than the clock driving capability of the largest clock driving unit and is greater than the clock driving capability of the smallest clock driving unit Drive capability.
  • the clock driving capability of the at least one intermediate clock driving unit is sequentially set in a preset step size between the maximum clock driving capability and the minimum clock driving capability.
  • At least one other clock driving unit other than the largest clock driving unit in the at least two clock driving units 31 is obtained by reducing the number of transistors on the basis of the largest clock driving unit.
  • the external dimensions, port positions, port shapes, port sizes, and port metal layers of at least two clock driving units 31 are the same.
  • An embodiment of the present application further provides a chip, where the chip includes a chip clock driving unit kit as shown in FIG. 3 .
  • the various embodiments of the present application may be implemented in hardware or special purpose circuits, software, logic, or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
  • Embodiments of the present application may be implemented by the execution of computer program instructions by a data processor of a mobile device, eg in a processor entity, or by hardware, or by a combination of software and hardware.
  • Computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or in any combination of one or more programming languages Written source or object code.
  • ISA Instruction Set Architecture
  • the block diagrams of any logic flow in the figures of the present application may represent program steps, or may represent interconnected logic circuits, modules and functions, or may represent a combination of program steps and logic circuits, modules and functions.
  • Computer programs can be stored on memory.
  • the memory may be of any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random Access Memory (RAM), optical Memory devices and systems (Digital Video Disc (DVD) or compact disc (Compact Disc, CD)), etc.
  • Computer readable media may include non-transitory storage media.
  • Data processors may be any suitable for local technology Type of environment, such as but not limited to general purpose computer, special purpose computer, microprocessor, digital signal processor (Digital Signal Processing, DSP), application specific integrated circuit (SAIC), programmable logic device (Field-Programmable Gate Array, FGPA) and processors based on multi-core processor architectures.
  • DSP Digital Signal Processing
  • SAIC application specific integrated circuit
  • FGPA programmable logic device

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Abstract

一种芯片时钟驱动单元套件和设计方法以及芯片，一种芯片时钟驱动单元套件设计方法包括：确定芯片中的最长时钟连线长度(S1010)；根据最长时钟连线长度设计所述芯片的最大时钟驱动单元，所述最大时钟驱动单元的驱动能力为所述最长时钟连线长度对应的芯片所需最大时钟驱动能力(S1020)；设计芯片的至少一个其他时钟驱动单元，至少一个其他时钟驱动单元的时钟驱动能力均小于最大时钟驱动单元的时钟驱动能力，且至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同，芯片时钟驱动单元套件包括最大时钟驱动单元和至少一个其他时钟驱动单元(S1030)。

Description

芯片时钟驱动单元套件和设计方法以及芯片
相关申请的交叉引用
本申请基于申请号为202010899703.8、申请日为2020年08月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及集成电路技术，例如涉及一种芯片时钟驱动单元套件和设计方法以及芯片。
背景技术
随着芯片规模的扩大，芯片时钟结构对整个芯片的时序收敛越来越重要。大规模芯片需要采用合理的时钟树控制工艺、电压、温度(Process Voltage Temperature，PVT)和混合角(cross-corner)的影响，从结构上保证每个角(corner)下的时钟漂移(clock skew)能控制在合理的范围内。并采用大驱动能力的单元来降低顶层时钟延迟，有助于减少片上扰动(On Chip Variation，OCV)带来的影响，从而保证整个芯片时序的快速收敛。
目前的芯片设计中，根据芯片中的最大时钟连线长度设计芯片中时钟驱动单元的驱动能力，但这样对于其他时钟连线长度容易造成过驱动，从而增加了时钟路径上的消耗。
发明内容
本申请实施例提供一种芯片时钟驱动单元套件和设计方法以及芯片。
第一方面，本申请实施例提供一种芯片时钟驱动单元套件设计方法，包括：确定芯片中的最长时钟连线长度；根据最长时钟连线长度设计所述芯片的最大时钟驱动单元，所述最大时钟驱动单元的驱动能力为所述最长时钟连线长度对应的芯片所需最大时钟驱动能力；设计芯片的至少一个其他时钟驱动单元，至少一个其他时钟驱动单元的时钟驱动能力均小于最大时钟驱动单元的时钟驱动能力，且至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同，芯片时钟驱动单元套件包括最大时钟驱动单元和至少一个其他时钟驱动单元。
第二方面，本申请实施例提供一种芯片时钟驱动单元套件，包括：至少两个时钟驱动单元，至少两个时钟驱动单元的时钟驱动能力不同；至少两个时钟驱动单元中时钟驱动能力最大的最大时钟驱动单元，根据芯片所需最大时钟驱动能力设计，芯片所需最大时钟驱动能力根据芯片中的最长时钟连线长度确定；至少两个时钟驱动单元的外部尺寸和端口相同，且至少两个时钟驱动单元的外部尺寸和端口根据最大时钟驱动单元确定。
第三方面，本申请实施例提供一种芯片，包括：如第二方面任一种可能的实现方式所示的芯片时钟驱动单元套件。
附图说明
图1为一实施例提供的一种芯片时钟驱动单元套件设计方法的流程图；
图2为一实施例提供的另一种芯片时钟驱动单元套件设计方法的流程图；
图3为一实施例提供的一种芯片时钟驱动单元套件的结构示意图。
具体实施方式
下文中将结合附图对本申请的实施例进行详细说明。
图1为一实施例提供的一种芯片时钟驱动单元套件设计方法的流程图，如图1所示，本实施例提供的方法包括如下步骤。
步骤S1010，确定芯片中的最长时钟连线长度。
本实施例提供的芯片时钟驱动单元套件设计方法用于对集成电路芯片中的时钟驱动单元进行设计。在芯片中，为了实现多种不同的功能，需要设计多个不同的功能单元，不同的功能单元均通过对芯片中晶体管的不同排列方式进行设计实现。芯片中的各种不同功能单元一般均需要时钟信号以实现同步，那么在芯片中就需要设计时钟驱动单元，对芯片中的不同功能单元进行时钟驱动。为了实现芯片中的时序收敛，在芯片设计中提出了时钟树(Clock Tree)的设计，包括H-Tree、X-Tree、balanced-Tree等。时钟树的设计可以很好的控制芯片中PVT和cross-corner的影响。而为了降低芯片顶层时钟延迟，需要采用大驱动能力的时钟驱动单元，从而减小OCV带来的影响。但目前芯片中的时钟驱动单元的设计，考虑芯片所需的最大时钟驱动能力设计最大时钟驱动能力的时钟驱动单元。而由于芯片中不同功能单元的时钟连线长度不同，使用最大时钟驱动能力的时钟驱动单元驱动所有功能单元，增加了时钟路径上的消耗，从而增加了芯片的功耗。
因此，在本实施例中，提供一种芯片时钟驱动单元套件设计方法，首先确定芯片中的最长时钟连线长度。芯片中的时钟连线长度根据芯片中各功能单元到时钟驱动单元的连线的实际长度确定。芯片中的时钟连线长度的单位一般为u，u表示10 -6米，即1u＝1微米。在芯片完成功能单元的设计布局后，各功能单元的时钟连线长度即可确定，在其中选择时钟连线长度最长的作为芯片的最长时钟连线长度。
步骤S1020，根据最长时钟连线长度设计芯片的最大时钟驱动单元，最大时钟驱动单元的驱动能力为最长时钟连线长度对应的芯片所需最大时钟驱动能力。
芯片中各种功能单元所需的时钟驱动能力根据其时钟连线长度确定，功能单元的时钟连线长度越长表示距离时钟驱动单元距离越远，意味着需要更大驱动能力的时钟驱动单元才能够驱动该功能单元。那么为了驱动芯片中的所有功能单元，在芯片中必然需要设计满足最大时钟驱动能力需求的功能单元所需的时钟驱动单元，也就是根据芯片中的最长时钟连线长度设计芯片的最大时钟驱动单元。因此，在确定了芯片中的最长时钟连线长度后，即可根据该最长时钟连线长度设计芯片的最大时钟驱动单元。芯片的最大时钟驱动单元只要能够满足芯片所需最大时钟驱动能力即可，其具体的设计方法是本领域技术人员的惯用技术手段，此处不再赘述。
步骤S1030，设计芯片的至少一个其他时钟驱动单元，至少一个其他时钟驱动单元的时钟驱动能力均小于最大时钟驱动单元的时钟驱动能力，且至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同，芯片时钟驱动单元套件包括最大时钟驱动单元和至少一个其他时钟驱动单元。
由于在芯片中，使用驱动能力大的时钟驱动单元驱动时钟连线较短的功能单元，会增加时钟路径上消耗的功耗，因此在本实施例中，提出在芯片中设计时钟驱动单元套件，时钟驱动单元套件中可以包括多个时钟驱动单元。芯片的时钟驱动单元套件中至少需要包括最大时钟驱动单元，还包括最大时钟驱动单元以外的至少一个其他时钟驱动单元。也就是说，时钟驱动单元套件中至少包括两个时钟驱动单元。至少一个其他时钟驱动单元的时钟驱动能力均小于最大时钟驱动单元的时钟驱动能力。那么在芯片中就可以根据不同功能单元的时钟连线长度，采用不同时钟驱动能力的时钟驱动单元进行时钟驱动，从而避免使用最大使用驱动能力的时钟驱动单元驱动所有功能单元而导致的时钟路径上所消耗的功耗。
只要在芯片中设计至少两个时钟驱动单元，其中一个最大时钟驱动单元是根据芯片所需最大时钟驱动能力设计的，至少一个其他时钟驱动单元的时钟驱动能力小于最大时钟驱动单元的时钟驱动能力，即可使芯片中的部分功能单元由其他时钟驱动单元进行驱动，从而降低时钟路径上所消耗的功耗。
例如在芯片中具有3个需要时钟驱动的功能单元，分别为A、B、C，其时钟连线长度分别为1000u、500u和200u。那么首先根据最长时钟连线长度，即1000u设计时钟驱动单元a，然后再设计一个能够驱动时钟连线长度为500u的时钟驱动单元b。那么就可以使用时钟驱动单元a驱动功能单元A，而使用时钟驱动单元b驱动功能单元B和C。这样与使用最大时钟驱动能力的时钟驱动单元驱动芯片的全部功能单元相比，显然降低了时钟路径上功耗。当然还可以再设计一个能够驱动时钟连线长度为200u的时钟驱动单元c，使用时钟驱动单元a驱动功能单元A，使用时钟驱动单元b驱动功能单元B并使用时钟驱动单元c驱动功能单元C。从而进一步降低了时钟路径上功耗。
至少一个其他时钟驱动单元的数量可以为一个或多个，且至少一个其他时钟驱动单元的时钟驱动能力可以为小于最大时钟驱动单元的时钟驱动能力的任意时钟驱动能力。在设计了包括至少两个时钟驱动单元的时钟驱动单元套件后，即可在芯片中更为合理地为不同的功能单元采用不同的时钟驱动单元进行时钟驱动，只要根据不同功能单元的时钟连线长度选择满足功能单元所需时钟驱动能力需求的时钟驱动单元即可。
另外，在芯片的设计过程中，可能会对不同的功能单元进行不断地调整，那么不同功能单元的时钟连线长度就可能发生改变，也就是说在芯片中可能随时需要调整不同功能单元所需的时钟驱动单元的时钟驱动能力。因此，在为芯片设计了包括至少两个时钟驱动单元的时钟驱动单元套件后，即可在芯片中的各功能单元所需时钟驱动能力发生改变时，从时钟驱动单元套件中选择适合的时钟驱动单元，无需重新设计新的时钟驱动单元，从而提高了芯片设计的效率。再考虑到当芯片中的时钟驱动单元需要变更时，避免重新设计时钟驱动单元的位置和端口，可以根据最大时钟驱动单元的外部尺寸和端口设计至少一个其他时钟驱动单元的外部尺寸和接口，使得时钟驱动单元套件中的所有时钟驱动单元具有相同的外部尺寸和端口。这样在芯片中的功能单元发生变更，需要更换时钟驱动单元时，只需要从时钟驱动单元套件中重新选择满足变更后的功能单元的时钟驱动单元更换原有时钟驱动单元即可，无需对芯片的其他部分进行重新设计，从而进一步地提高了芯片设计的效率。
在一实施例中，至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同，包括：至少一个其他时钟驱动单元的外部尺寸、端口位置、端口形状、端口大小、端 口金属层与最大时钟驱动单元相同。其中外部尺寸相同可以避免时钟驱动单元的替换影响芯片中的其他功能单元的设计，端口位置、端口形状、端口大小、端口金属层相同，可以在替换时钟驱动单元时无需改变其他功能单元的连接方式。
本实施例提供的芯片时钟驱动单元套件设计方法，首先确定芯片中的最长时钟连线长度，根据最长时钟连线长度确定芯片所需最大时钟驱动能力并根据最大时钟驱动能力设计芯片的最大时钟驱动单元，然后设计芯片的至少一个其他时钟驱动单元，至少一个其他时钟驱动单元的时钟驱动能力均小于最大时钟驱动单元的时钟驱动能力，且至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同，使得最大时钟驱动单元和至少一个其他时钟驱动单元组成芯片的时钟驱动单元套件，降低了芯片中时钟路径上消耗的功耗，从而降低了整个芯片的功耗，还提高了芯片的设计效率。
图2为一实施例提供的另一种芯片时钟驱动单元套件设计方法的流程图，如图2所示，本实施例提供的方法包括如下步骤。
步骤S2010，确定芯片中的最长时钟连线长度。
本实施例提供的芯片时钟驱动单元套件设计方法用于对集成电路芯片中的时钟驱动单元进行设计。在芯片中，为了实现多种不同的功能，需要设计多个不同的功能单元，不同的功能单元均通过对芯片中晶体管的不同排列方式进行设计实现。芯片中的各种不同功能单元一般均需要时钟信号以实现同步，那么在芯片中就需要设计时钟驱动单元，对芯片中的不同功能单元进行时钟驱动。为了实现芯片中的时序收敛，在芯片设计中提出了时钟树(Clock Tree)的设计，包括H-Tree、X-Tree、balanced-Tree等。时钟树的设计可以很好的控制芯片中PVT和cross-corner的影响。而为了降低芯片顶层时钟延迟，需要采用大驱动能力的时钟驱动单元，从而减小OCV带来的影响。但目前芯片中的时钟驱动单元的设计，考虑芯片所需的最大时钟驱动能力设计最大时钟驱动能力的时钟驱动单元。而由于芯片中不同功能单元的时钟连线长度不同，使用最大时钟驱动能力的时钟驱动单元驱动所有功能单元，增加了时钟路径上的消耗，从而增加了芯片的功耗。
因此，在本实施例中，提供一种芯片时钟驱动单元套件设计方法，首先确定芯片中的最长时钟连线长度。芯片中的时钟连线长度根据芯片中各功能单元到时钟驱动单元的连线的实际长度确定。芯片中的时钟连线长度的单位一般为u，u表示10 -6米，即1u＝1微米。在芯片完成功能单元的设计布局后，各功能单元的时钟连线长度即可确定，在其中选择时钟连线长度最长的作为芯片的最长时钟连线长度。
步骤S2020，根据最长时钟连线长度设计芯片的最大时钟驱动单元，最大时钟驱动单元的驱动能力为最长时钟连线长度对应的芯片所需最大时钟驱动能力。
芯片中各种功能单元所需的时钟驱动能力根据其时钟连线长度确定，功能单元的时钟连线长度越长表示距离时钟驱动单元距离越远，意味着需要更大驱动能力的时钟驱动单元才能够驱动该功能单元。那么为了驱动芯片中的所有功能单元，在芯片中必然需要设计满足最大时钟驱动能力需求的功能单元所需的时钟驱动单元，也就是根据芯片中的最长时钟连线长度设计芯片的最大时钟驱动单元。因此，在确定了芯片中的最长时钟连线长度后，即可根据该最长时钟连线长度设计芯片的最大时钟驱动单元。芯片的最大时钟驱动单元只要能够满足芯片所需最大时钟驱动能力即可，其具体的设计方法是本领域技术人员的惯用技术手段，此处不再赘述。
步骤S2030，根据芯片中的最短时钟连线长度设计芯片的最小时钟驱动单元，最小时钟驱动单元的驱动能力为最短时钟连线长度对应的芯片所需最小时钟驱动能力。
在本实施例中，根据芯片所需最大时钟驱动能力设计了芯片的最大时钟驱动单元后，还可以根据芯片所需最小时钟驱动能力设计芯片的最小时钟驱动单元。芯片的最小时钟驱动单元被设置成为芯片中对时钟驱动能力需求最小的功能单元提供时钟驱动。与确定最大时钟驱动单元的方法类似，首先根据最短时钟连线长度设计芯片的最小时钟驱动单元。芯片的最小时钟驱动单元只要能够满足芯片所需最小时钟驱动能力即可。在确定了芯片的最小时钟驱动单元后，可以使用最大时钟驱动单元和最小时钟驱动单元为芯片提供时钟驱动。最小时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同。那么芯片时钟驱动单元套件可以包括最大时钟驱动单元和最小时钟驱动单元。
步骤S2040，设计芯片的至少一个中间时钟驱动单元，至少一个中间时钟驱动单元的时钟驱动能力小于最大时钟驱动单元的时钟驱动能力且大于最小时钟驱动单元的时钟驱动能力。
在一些实例中，在设计了芯片的最大时钟驱动单元和最小时钟驱动单元后，还可以设计芯片的至少一个中间时钟驱动单元。至少一个中间时钟驱动单元的时钟驱动能力位于最大时钟驱动单元和最小时钟驱动单元之间，即小于最大时钟驱动单元的时钟驱动能力且大于最小时钟驱动单元的时钟驱动能力。至少一个中间时钟驱动单元的数量可以为一个或多个。至少一个中间时钟驱动单元的时钟驱动能力可以在芯片所需最大时钟驱动能力和芯片所需最小时钟驱动能力之间线性分布或者非线性分布。例如可以根据芯片中已设计功能单元的时钟连线长度确定多个时钟驱动能力，然后分别对应设计出最大时钟驱动单元、最小时钟驱动单元和多个中间时钟驱动单元，形成时钟驱动单元套件，当芯片中的功能单元所需时钟驱动能力发生改变，在时钟驱动单元套件中选择其他适合的时钟驱动单元替换原有时钟驱动单元即可。至少一个中间时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同。芯片时钟驱动单元套件可以包括最大时钟驱动单元、最小时钟驱动单元和至少一个中间时钟驱动单元。
另外，还可以在芯片的最大时钟驱动能力和最小时钟驱动能力之间以预设步长选择至少一个中间时钟驱动能力，然后根据至少一个中间时钟驱动能力设计至少一个中间时钟驱动单元。也就是在确定芯片的最大时钟驱动能力和最小时钟驱动能力并设计了最大时钟驱动单元和最小时钟驱动单元之后，选择适合的步长，在最大时钟驱动能力和最小时钟驱动能力之间确定一个或多个中间时钟驱动能力。然后根据一个或多个中间时钟驱动能力设计对应的一个或多个中间时钟驱动单元，最终将最大时钟驱动单元、最小时钟驱动单元和一个或多个中间时钟驱动单元组成时钟驱动单元套件。那么在芯片中就可以根据不同功能单元所需时钟驱动能力，在时钟驱动单元套件中选择适合的时钟驱动单元，并且在各功能单元所需时钟驱动能力发生改变时，可以从时钟驱动单元套件中选择适合的其他时钟驱动单元。上述预设步长可以根据需求设置。例如首先确定芯片中的最长时钟连线长度为1000u，最小时钟连线长度为200u，分别对应设计了最大时钟驱动单元m和最小时钟驱动单元n。然后确定预设步长为200u，接着对应设计出分别与最小时钟连线长度为800u、600u、400u对应的中间时钟驱动单元。
在一实施例中，在设计芯片的最大时钟驱动单元后，可以在最大时钟驱动单元的基础 上，减少最大时钟驱动单元中晶体管的个数，得到至少一个其他时钟驱动单元。芯片中的时钟驱动单元，也是通过多个晶体管的不同排列组合和连接方式，实现时钟驱动单元的功能，时钟驱动单元所需时钟驱动能力越大，所需晶体管的数量也越多。那么芯片中时钟驱动能力最大的最大时钟驱动单元中的晶体管数量也最多。因此可以在设计了最大时钟驱动单元后，在最大时钟驱动单元的基础上，通过减少最大时钟驱动单元中晶体管的数量，完成至少一个其他时钟驱动单元的设计。这样就无需重新设计其他时钟驱动单元，且有利于保证至少一个其他时钟驱动单元的外部尺寸和端口与最大时钟驱动单元相同。
在根据上述实施例完成芯片时钟驱动单元套件的设计后，就可以进行电路设计环节，通过前仿真确定各时钟驱动单元中P/N经替换尺寸大小，然后通过仿真调整尺寸。
在完成电路设计，得到各时钟驱动单元的电路图后，即可进行版图设计，包括如下步骤：1)首先确立最大时钟驱动单元版图架构和大小，最大时钟驱动单元需要首先完成，整个时钟驱动单元套件中各时钟驱动单元的版图大小是一致的，因此最大时钟驱动单元的大小至关重要。需要考虑先进工艺下版图的特殊规则、考虑天线效应、考虑寄生效应、考虑外界对驱动单元的影响、考虑电迁移(Electrical Migration，EM)效应考虑数据流的走线来布局布线。最后得到最大时钟驱动单元的大小和输入输出端口的位置、大小、方向。(输入输出端口的位置、大小、方向可以根据芯片实际需求定制)。2)基于最大时钟驱动单元得到至少一个其他时钟驱动单元的版图，只需要减少最大时钟驱动单元中晶体管的数量，保持输入输出端口不变，通过后仿真来确定至少一个其他时钟驱动单元版图。
图3为一实施例提供的一种芯片时钟驱动单元套件的结构示意图，如图3所示，本实施例提供的芯片时钟驱动单元套件包括：
至少两个时钟驱动单元31，至少两个时钟驱动单元31的时钟驱动能力不同；至少两个时钟驱动单元31中时钟驱动能力最大的最大时钟驱动单元，根据芯片所需最大时钟驱动能力设计，芯片所需最大时钟驱动能力根据芯片中的最长时钟连线长度确定；至少两个时钟驱动单元31的外部尺寸和端口相同，且至少两个时钟驱动单元31的外部尺寸和端口根据最大时钟驱动单元确定。在本实施例中，以4个时钟驱动单元31为例，各时钟驱动单元31具有相同的输入接口IN和输出接口OUT以及相同的外部尺寸。
本实施例提供的芯片时钟驱动单元套件根据图1所示芯片时钟驱动单元套件设计方法设计，其具体的实现原理和技术效果已经在图1所示实施例中进行了详细阐述，此处不再赘述。
在一实施例中，至少两个时钟驱动单元31中时钟驱动能力最小的最大时钟驱动单元，根据芯片所需最小时钟驱动能力设计，芯片所需最小时钟驱动能力根据芯片中的最短时钟连线长度确定。
在一实施例中，至少两个时钟驱动单元31中还包括至少一个中间时钟驱动单元；至少一个中间时钟驱动单元的时钟驱动能力小于最大时钟驱动单元的时钟驱动能力且大于最小时钟驱动单元的时钟驱动能力。
在一实施例中，至少一个中间时钟驱动单元的时钟驱动能力在最大时钟驱动能力和最小时钟驱动能力之间以预设步长依次设置。
在一实施例中，至少两个时钟驱动单元31中最大时钟驱动单元以外的至少一个其他时钟驱动单元是在最大时钟驱动单元的基础上减少晶体管的个数得到的。
在一实施例中，至少两个时钟驱动单元31的外部尺寸、端口位置、端口形状、端口大小、端口金属层相同。
本申请实施例还提供一种芯片，该芯片包括如图3所示的芯片时钟驱动单元套件。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构((Instruction Set Architecture，ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(Read-Only Memory，ROM)、随机访问存储器(Random Access Memory，RAM)、光存储器装置和系统(数码多功能光碟(Digital Video Disc，DVD)或光盘((Compact Disc，CD))等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，SAIC)、可编程逻辑器件(Field-Programmable Gate Array，FGPA)以及基于多核处理器架构的处理器。

Claims (13)

  1. 一种芯片时钟驱动单元套件设计方法，包括：
    确定芯片中的最长时钟连线长度；
    根据所述最长时钟连线长度设计所述芯片的最大时钟驱动单元，所述最大时钟驱动单元的驱动能力为所述最长时钟连线长度对应的所述芯片所需最大时钟驱动能力；
    设计所述芯片的至少一个其他时钟驱动单元，所述至少一个其他时钟驱动单元的时钟驱动能力均小于所述最大时钟驱动单元的时钟驱动能力，且所述至少一个其他时钟驱动单元的外部尺寸和端口与所述最大时钟驱动单元相同，所述芯片时钟驱动单元套件包括所述最大时钟驱动单元和所述至少一个其他时钟驱动单元。
  2. 根据权利要求1所述的方法，其中，所述设计所述芯片的至少一个其他时钟驱动单元，包括：
    根据芯片中的最短时钟连线长度设计所述芯片的最小时钟驱动单元，所述最小时钟驱动单元的驱动能力为所述最短时钟连线长度对应的所述芯片所需最小时钟驱动能力。
  3. 根据权利要求2所述的方法，其中，所述设计所述芯片的至少一个其他时钟驱动单元，还包括：
    设计所述芯片的至少一个中间时钟驱动单元，所述至少一个中间时钟驱动单元的时钟驱动能力小于所述最大时钟驱动单元的时钟驱动能力且大于所述最小时钟驱动单元的时钟驱动能力。
  4. 根据权利要求3所述的方法，其中，设计所述芯片的至少一个中间时钟驱动单元，包括：
    在所述最大时钟驱动能力和所述最小时钟驱动能力之间以预设步长选择至少一个中间时钟驱动能力；
    根据所述至少一个中间时钟驱动能力设计所述至少一个中间时钟驱动单元。
  5. 根据权利要求1～4任一项所述的方法，其中，所述设计所述芯片的至少一个其他时钟驱动单元，包括：
    在所述最大时钟驱动单元的基础上，减少所述最大时钟驱动单元中晶体管的个数，得到所述至少一个其他时钟驱动单元。
  6. 根据权利要求1～4任一项所述的方法，其中，所述至少一个其他时钟驱动单元的外部尺寸和端口与所述最大时钟驱动单元相同，包括：
    所述至少一个其他时钟驱动单元的外部尺寸、端口位置、端口形状、端口大小、端口金属层与所述最大时钟驱动单元相同。
  7. 一种芯片时钟驱动单元套件，包括：
    至少两个时钟驱动单元，所述至少两个时钟驱动单元的时钟驱动能力不同；
    所述至少两个时钟驱动单元中时钟驱动能力最大的最大时钟驱动单元，根据所述芯片所需最大时钟驱动能力设计，所述芯片所需最大时钟驱动能力根据所述芯片中的最长时钟连线长度确定；
    所述至少两个时钟驱动单元的外部尺寸和端口相同，且所述至少两个时钟驱动单元的外部尺寸和端口根据所述最大时钟驱动单元确定。
  8. 根据权利要求7所述的芯片时钟驱动单元套件，其中，所述至少两个时钟驱动单元中时钟驱动能力最小的最大时钟驱动单元，根据所述芯片所需最小时钟驱动能力设计，所述芯片所需最小时钟驱动能力根据所述芯片中的最短时钟连线长度确定。
  9. 根据权利要求8所述的芯片时钟驱动单元套件，其中，所述至少两个时钟驱动单元中还包括至少一个中间时钟驱动单元；
    所述至少一个中间时钟驱动单元的时钟驱动能力小于所述最大时钟驱动单元的时钟驱动能力且大于所述最小时钟驱动单元的时钟驱动能力。
  10. 根据权利要求9所述的芯片时钟驱动单元套件，其中，所述至少一个中间时钟驱动单元的时钟驱动能力在所述最大时钟驱动能力和所述最小时钟驱动能力之间以预设步长依次设置。
  11. 根据权利要求7～10任一项所述的芯片时钟驱动单元套件，其中，所述至少两个时钟驱动单元中所述最大时钟驱动单元以外的至少一个其他时钟驱动单元是在所述最大时钟驱动单元的基础上减少晶体管的个数得到的。
  12. 根据权利要求7～10任一项所述的芯片时钟驱动单元套件，其中，所述至少两个时钟驱动单元的外部尺寸、端口位置、端口形状、端口大小、端口金属层相同。
  13. 一种芯片，包括：如权利要求7～12任一项所述的芯片时钟驱动单元套件。
PCT/CN2021/114567 2020-08-31 2021-08-25 芯片时钟驱动单元套件和设计方法以及芯片 WO2022042611A1 (zh)

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