WO2022011930A1 - 一种高线性GaN基毫米波器件及其制备方法 - Google Patents

一种高线性GaN基毫米波器件及其制备方法 Download PDF

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WO2022011930A1
WO2022011930A1 PCT/CN2020/132734 CN2020132734W WO2022011930A1 WO 2022011930 A1 WO2022011930 A1 WO 2022011930A1 CN 2020132734 W CN2020132734 W CN 2020132734W WO 2022011930 A1 WO2022011930 A1 WO 2022011930A1
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gan
type gan
active region
algan
electrode
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PCT/CN2020/132734
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French (fr)
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王洪
刘晓艺
陈竟雄
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中山市华南理工大学现代产业技术研究院
华南理工大学
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Publication of WO2022011930A1 publication Critical patent/WO2022011930A1/zh
Priority to US17/695,874 priority Critical patent/US20220209002A1/en

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Definitions

  • the invention relates to the technical field of semiconductors, in particular to a high linearity GaN-based millimeter wave device and a preparation method thereof.
  • GaN-based HEMT devices are widely used in satellite, communications, radar and other fields.
  • GaN belongs to group III nitrides, and has the advantages of excellent breakdown capability, higher electron density and speed, high temperature resistance and radiation resistance, and is suitable for the development of high frequency, high temperature and high power electronic devices.
  • the AlGaN/GaN heterojunction has a high concentration of two-dimensional electron gas at the heterojunction interface due to the spontaneous polarization effect and piezoelectric polarization effect at room temperature, so the device with the AlGaN/GaN heterojunction has a high electron concentration. With high electron mobility, it has broad application prospects in the construction of 5G network infrastructure, anti-missile radar and other fields.
  • the linearity requirements of the power amplifier in the circuit are also getting higher and higher.
  • the transconductance of traditional devices exhibits typical peak characteristics, that is, the transconductance is severely degraded at high currents, resulting in rapid compression of device gain at high input power, poor intermodulation characteristics, and low linearity.
  • the large-signal dynamic input of high-power microwave devices such as power amplifiers
  • the large-signal input to the power device will exceed the linear operating region, enter the saturation region and be distorted, so as to transmit wrong information.
  • the purpose of the present invention is to overcome the defects and limitations of the existing high-linearity GaN-based millimeter-wave devices, and propose a method for preparing a high-linearity GaN-based millimeter-wave device from the perspective of using components with different threshold voltages in parallel.
  • the p-type GaN doping concentration achieves different threshold voltages, which can reduce the requirements for the etching accuracy of dry etching and improve the linearity of the device.
  • the object of the present invention is achieved by at least one of the following technical solutions.
  • a high linearity GaN-based millimeter wave device comprising an AlGaN/GaN heterojunction epitaxial layer, the AlGaN/GaN heterojunction epitaxial layer is a boss structure, a protruding part above the boss is an active region, and the upper surface of the active region is The two ends are respectively connected to the source electrode and the drain electrode, the p-type GaN layers with different doping concentrations are located between the source electrode and the drain electrode on the upper surface of the active region, wherein the p-type GaN layers with different doping concentrations are composed of different
  • the first p-type GaN and the second p-type GaN with the same doping concentration but the same thickness are formed along the gate width in front and rear, and the back surface of the first p-type GaN and the front surface of the second p-type GaN are coincident, and the left and right edges are aligned ;
  • the gate electrode is located above the p-type GaN layers with different doping concentrations.
  • the diameter of the AlGaN/GaN heterojunction epitaxial layer is 2-10 inches, and the total thickness is 200 ⁇ m-1 mm.
  • the lengths of the first p-type GaN and the second p-type GaN are both between 10 nm and 100 nm, the widths are greater than 5 ⁇ m, the thicknesses are between 5 nm and 100 nm, and the doping concentrations are both greater than 1 ⁇ 10 3 /cm ⁇ 3 .
  • the source electrode and the drain electrode are Ti/Al/Ni/Au metal layers, the source electrode and the drain electrode are both rectangular parallelepipeds, the length is greater than 10 nm, the width is the same as the overall p-type GaN layer, and the height is greater than 10 nm.
  • the spacing between the drain electrodes is greater than the length of the first p-type GaN and the second p-type GaN; the left side of the source electrode coincides with the left edge of the active region, the right side of the drain electrode coincides with the right edge of the active region, and the source The front and rear edges of the electrode and the drain electrode coincide with the front and rear edges of the active region.
  • the rear edge of the active region coincides with the rear edge of the second p-type GaN
  • the length of the front edge of the active region from the second p-type GaN is greater than 5 ⁇ m
  • the left edge of the active region is separated from the second p-type GaN.
  • the length of the left edge is greater than 100 nm
  • the length of the right edge of the active region is greater than 100 nm from the right edge of the second p-type GaN.
  • the length of the gate electrode is the same as the length of the second p-type GaN
  • the width is the sum of the widths of the first p-type GaN and the second p-type GaN
  • the height is between 50 nm and 1000 nm.
  • the method for preparing a high linearity GaN-based millimeter wave device includes the following steps:
  • Growth of p-type GaN Growth of AlGaN/GaN heterojunction epitaxial layer on the substrate and direct growth of the first p-type GaN on the AlGaN/GaN heterojunction epitaxial layer; the thickness of the first p-type GaN is between 5nm and 5nm. Between 100nm;
  • Secondary growth of p-type GaN with different doping concentrations use photoresist to cover the area except for the secondary growth of the second p-type GaN, wherein the length of the area not covered by photoresist is between 10nm and 100nm, The width is greater than 5 ⁇ m, and the dry etching process is used to etch to within 3 nm above and below the AlGaN; secondary epitaxial growth is performed, and the thickness of the grown second p-type GaN is the same as that of the first p-type GaN in step S1, and the second p-type
  • the doping concentration of GaN is greater than the doping concentration of the first p-type GaN in step S1; finally, the surface of the device is polished by chemical mechanical polishing technology;
  • S4 peel off the source electrode and the drain electrode, and anneal to form an ohmic contact: use the photoresist to define the position and pattern of the source electrode and the drain electrode, so that the position of the source electrode and the drain electrode are at both ends of the upper surface of the active area; the source electrode The front and rear edges of the drain electrode coincide with the front and rear edges of the active area; the area that is not the source electrode and the non-drain electrode is covered by photoresist, first use the dry etching method to etch to the AlGaN surface or overetch the area within 3nm.
  • Source and drain electrodes AlGaN, and then use electron beam evaporation or magnetron sputtering method and lift-off process to form source and drain electrodes, and finally anneal in nitrogen atmosphere at a temperature above 800 °C, so that the source and drain electrodes and AlGaN/GaN heterojunction
  • the epitaxial layers all form ohmic contacts;
  • gate electrode use photoresist to define the position and pattern of the gate electrode, the length is the same as the length of the second p-type GaN in step S2, and is located directly above the first p-type GaN and the second p-type GaN; use Electron beam evaporation or magnetron sputtering method and stripping process form gate electrode; use photoresist to protect gate electrode, source electrode and drain electrode, and use dry etching process to etch the parts not covered by photoresist to The AlGaN layer or the overetched AlGaN layer is within 3 nm; after the etching is completed, the photoresist is removed to complete the preparation of high linearity GaN-based millimeter-wave devices.
  • the substrate material is one of silicon, silicon carbide, sapphire or diamond; in step S1, the impurities doped when growing the first p-type GaN are Mg, Zn or Fe.
  • the doping concentration of the first p-type GaN is above 1 ⁇ 10 3 /cm -3 , and the growth thickness is between 5nm-100nm.
  • the growth methods of the first p-type GaN and the second p-type GaN are both metal organic chemical vapor deposition or molecular beam epitaxy; dry etching is an inductively coupled plasma etching process, a reactive ion etching process or a Any of the other ion etching processes.
  • the gas for etching GaN in the dry etching is one or a mixture of Cl-containing gases such as Cl 2 , BCl 3 , SiCl 4 , or other etchable GaN material gases.
  • the present invention has the following advantages and beneficial effects:
  • the etching before the growth of the p-type GaN layers with different doping concentrations is not limited to etching to the AlGaN surface, there is a certain tolerance, so the need for Etching accuracy requirements.
  • the doping concentration and thickness of p-type GaN can be adjusted, devices with different threshold voltages can have high linearity.
  • FIG. 1 is a flowchart of a method for preparing a GaN-based millimeter-wave device with high linearity in an embodiment of the present invention
  • FIGS 2-5 are three-dimensional perspective views of the GaN-based millimeter-wave device with high linearity during steps S1 to S4 in the preparation process;
  • FIG. 6 is a three-dimensional perspective view of a GaN-based millimeter-wave device with high linearity when the gate electrode is prepared during the preparation process;
  • FIG. 7 is a three-dimensional perspective view of a GaN-based millimeter-wave device with high linearity prepared in an embodiment of the present invention.
  • FIG. 8 is a three-dimensional perspective view of a comparative device of a high linearity GaN-based millimeter-wave device in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a transfer curve of a highly linear GaN-based millimeter-wave device in an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a transconductance curve of a highly linear GaN-based millimeter-wave device in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the variation curve of the cutoff frequency of the highly linear GaN-based millimeter-wave device with the gate voltage in the embodiment of the present invention.
  • FIG. 12 is a schematic diagram of the variation curve of the maximum oscillation frequency with the gate voltage of the highly linear GaN-based millimeter-wave device in the embodiment of the present invention.
  • a high linearity GaN-based millimeter-wave device as shown in FIG. 7, includes an AlGaN/GaN heterojunction epitaxial layer 1, the AlGaN/GaN heterojunction epitaxial layer 1 is a boss structure, and the protruding part above the boss has a
  • the two ends of the upper surface of the active region 4 are respectively connected to the source electrode 5 and the drain electrode 6, and p-type GaN layers with different doping concentrations are located between the source electrode 5 and the drain electrode 6 on the upper surface of the active region 4,
  • the p-type GaN layers with different doping concentrations are formed by the first p-type GaN2 and the second p-type GaN3 with different doping concentrations but the same thickness arranged in front and back along the gate width, and the rear surface of the first p-type GaN2 Coinciding with the front surface of the second p-type GaN 3, the left and right edges are aligned; the gate electrode 7 is located above the p-type GaN
  • the diameter of the AlGaN/GaN heterojunction epitaxial layer 1 is 2 inches, and the total thickness is 800 ⁇ m.
  • the first p-type GaN2 and the second p-type GaN3 are both rectangular parallelepipeds, with a length of 90 nm, a width of 20 ⁇ m, and a thickness of 80 nm.
  • the distance between the source electrode 5 and the drain electrode 6 is 2 ⁇ m.
  • the doping concentrations of the second p-type GaN2 and the second p-type GaN3 were 1 ⁇ 10 8 /cm ⁇ 3 and 1 ⁇ 10 18 /cm ⁇ 3 , respectively .
  • the source electrode 5 and the drain electrode 6 are Ti/Al/Ni/Au metal layers, and the source electrode 5 and the drain electrode 6 are both rectangular parallelepipeds, with a height of 380 nm, a length of 1000 nm, and a width of 40 ⁇ m.
  • the distance between the electrode 5 and the drain electrode 6 is 4.09 ⁇ m; the left side of the source electrode 5 coincides with the left edge of the active region 4, the right side of the drain electrode 6 coincides with the right edge of the active region 4, and the source electrode 5 and The front and rear edges of the drain electrode 6 coincide with the front and rear edges of the active region 4 .
  • the rear edge of the active region 4 is coincident with the rear edge of the second p-type GaN3
  • the front edge of the active region 4 is coincident with the front edge of the first p-type GaN2
  • the height of the active region 4 is 2.02 ⁇ m , with a length of 6.09 ⁇ m and a width of 40 ⁇ m.
  • the gate electrode 7 is a Ni/Au metal layer, is a rectangular parallelepiped, its height is 300 nm, the width is 40 ⁇ m, and the length is the same as that of the second p-type GaN 3 .
  • the method for fabricating a high linearity GaN-based millimeter-wave device includes the following steps:
  • p-type GaN In this embodiment, a silicon substrate is selected, and the AlGaN/GaN heterojunction epitaxial layer 1 and the AlGaN/GaN heterojunction epitaxial layer 1 are grown on the substrate by vapor deposition of metal organic compounds. Directly growing the first p-type GaN2; the thickness of the first p-type GaN2 is 80 nm, the doping impurity is Mg, and the doping concentration is 1 ⁇ 10 8 /cm ⁇ 3 , as shown in FIG. 2 ;
  • the position of the active region 4 is defined with photoresist on the upper surface of the AlGaN/GaN heterojunction epitaxial layer 1 and the active region 4 is covered.
  • the rear edge of the active region 4 is connected to the The rear edges of the second p-type GaN3 overlap, the front edge is 20 ⁇ m away from the front edge of the second p-type GaN3, the left edge is 3 ⁇ m away from the left edge of the second p-type GaN3, and the right edge is 3 ⁇ m away from the right edge of the second p-type GaN3;
  • the upper surface of the AlGaN/GaN heterojunction epitaxial layer 1 of the active region 4 is etched by plasma bombardment, and the etching depth is 200nm-600nm, as shown in FIG. 4 ;
  • S4 peel off the source electrode and the drain electrode, and anneal to form an ohmic contact: in this embodiment, use a negative photoresist to define the position and pattern of the source electrode 5 and the drain electrode 6, so that the position of the source electrode 5 and the drain electrode 6 is in the Both ends of the upper surface of the active region 4; the left edge of the source electrode 5 coincides with the left edge of the active region 4, with a length of 1 ⁇ m and a thickness of 380 nm; the right edge of the drain electrode 6 coincides with the right edge of the active region 4, The length is 1 ⁇ m, and the thickness is 380 nm; the regions other than the source electrode 5 and the non-drain electrode 6 are covered with photoresist, adopt the method of inductively coupled plasma etching, and use a mixture of BCl 3 and Cl 2 to etch to the surface of the AlGaN layer or Over-etch AlGaN within 3nm, and then use electron beam evaporation or magnetron sputtering method and strip
  • a positive electron beam resist is used to define the position and pattern of the gate electrode 7, and the length is the same as that of the second p-type GaN3 in step S2, which is located between the first p-type GaN2 and the Right above the second p-type GaN3; use electron beam evaporation or magnetron sputtering and lift-off process to form gate electrode 7 with a thickness of 300 nm, as shown in Figure 6; use positive photoresist to separate gate electrode 7, source The electrode 5 and the drain electrode 6 are protected, and the area not covered by photoresist is etched to within 3 nm of the AlGaN layer or the overetched AlGaN layer by dry etching process; after the etching is completed, the photoresist is removed to complete the high linearity GaN base The fabrication of millimeter-wave devices is shown in Figure 7.
  • the preparation method of the high linearity GaN-based millimeter wave device proposed by the present invention adopts the method of modulating the threshold voltage of the device with different doping concentrations of p-type GaN, which reduces the requirements for the etching accuracy of the barrier layer and also reduces the saturation current.
  • the influence of p-type GaN thickness and doping concentration on the threshold voltage and transconductance of the device is fully exerted, so that devices with different threshold voltages can achieve high linearity.
  • the p-type GaN under the gate is changed to a single doping concentration, it is a traditional p-type GaN gate device, and its cross-sectional view is shown in Figure 8, where the doping concentration of p-type GaN is 1 ⁇ 10 8 /cm -3 .
  • the DC characteristics and RF characteristics of this example and conventional p-type GaN gate devices were simulated using Silvaco software. The simulation results are shown in Figure 9- Figure 12. As shown in Figure 9, the saturation current of the highly linear GaN-based mmWave device is 4.59% smaller than that of the conventional p-type GaN gate device.
  • the GVS of the highly linear GaN-based mmWave device is 4.2V
  • the GVS of the conventional p-type GaN gate device is 2.6V
  • GVS is defined as the gate span where the transconductance drops by 20%.
  • the curves of cut-off frequency and maximum oscillation frequency with gate voltage are relatively flat under the larger gate bias voltage range.

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Abstract

一种高线性GaN基毫米波器件及其制备方法。所述器件包括AlGaN/GaN异质结外延层(1),所述AlGaN/GaN异质结外延层(1)为凸台结构,凸台上方突起部分为有源区(4),有源区(4)上表面的两端分别连接源电极(5)和漏电极(6),不同掺杂浓度的p型GaN层位于有源区(4)上表面的源电极(5)和漏电极(6)之间,其中,所述不同掺杂浓度的p型GaN层由不同掺杂浓度,但厚度相同的第一p型GaN(2)和第二p型GaN(3)沿栅宽前后排列形成,并且第一p型GaN(2)的后表面和第二p型GaN(3)的前表面相重合,左右边缘对齐;栅电极(7)位于不同掺杂浓度的p型GaN层的上方。所述的在栅电极(7)下放置不同掺杂浓度的p型GaN层的结构,有效地调制了器件的阈值电压,提高了器件的线性度。

Description

一种高线性GaN基毫米波器件及其制备方法 技术领域
本发明涉及半导体技术领域,具体涉及一种高线性GaN基毫米波器件及其制备方法。
背景技术
[0002] GaN基HEMT器件在卫星、通信、雷达等领域有着广泛的应用。GaN属于III族氮化物,具有出色的击穿能力、更高的电子密度及速度、耐高温和耐辐射等优势,适合发展高频、高温以及高功率的电子器件。并且AlGaN/GaN异质结在室温下由于自发极化效应和压电极化效应,在异质结界面存在高浓度的二维电子气,所以具有AlGaN/GaN异质结的器件具有高电子浓度与高电子迁移率,在5G网络基础设施的建设,反导雷达以及其他领域都有着广阔的应用前景。
随着信号动态范围的增大,对电路中功率放大器的线性度要求也越来越高。而传统器件的跨导呈现典型的峰值特性,即跨导在高电流下严重退化,导致在高输入功率下器件增益迅速压缩,交调特性差,线性度低。在高功率微波器件大信号动态输入的应用中,如功率放大器,就会使得输入到功率器件中的大信号超出线性工作区,进入饱和区而失真,以至于传送出错误的信息。
研究人员已经尝试了许多方法来获得更宽的晶体管线性跨导曲线,比如通过抑制源极电阻随漏电流的增大而增大的Fin-HEMT结构和复合沟道异质结构,但是Fin-HEMT结构会降低器件的饱和电流(Zhang M, et al, IEEE Transactions on Electron Devices, 2018, 65(5)),而复合沟道异质结构等外延结构在提高线性度方面十分有限,而且会导致沟道热阻增加。或是通过多个具有连续阈值电压的并联元件来展宽跨导曲线的TRG结构(Wu S, et al, IEEE Electron Device Letters, 2019, 40(6)),但是需要非常精确的光刻和刻蚀过程控制。基于以上情况,如何降低对饱和电流的影响,降低对干法刻蚀的刻蚀精度的要求,达到更高的线性度是GaN基射频器件亟待解决的问题。
技术解决方案
本发明的目的在于克服已有的制备的高线性GaN基毫米波器件的缺陷以及局限,从采用不同阈值电压的元件并联的角度提出一种高线性GaN基毫米波器件的制备方法,其中用不同掺杂浓度的p型GaN实现不同的阈值电压,可以降低对干法刻蚀的刻蚀精度的要求,提高器件的线性度。
本发明的目的至少通过如下技术方案之一实现。
一种高线性GaN基毫米波器件,包括AlGaN/GaN异质结外延层,所述AlGaN/GaN异质结外延层为凸台结构,凸台上方突起部分为有源区,有源区上表面的两端分别连接源电极和漏电极,不同掺杂浓度的p型GaN层位于有源区上表面的源电极和漏电极之间,其中,所述不同掺杂浓度的p型GaN层由不同掺杂浓度,但厚度相同的第一p型GaN和第二p型GaN沿栅宽前后排列形成,并且第一p型GaN的后表面和第二p型GaN的前表面相重合,左右边缘对齐;栅电极位于不同掺杂浓度的p型GaN层的上方。
进一步地,所述AlGaN/GaN异质结外延层的直径为2-10inch,总厚度为200μm-1mm。
进一步地,第一p型GaN和第二p型GaN的长度均在10nm与100nm之间,宽度大于5μm,厚度在5nm与100nm之间,掺杂浓度均大于1×10 3/cm -3
进一步地,源电极和漏电极为Ti/Al/Ni/Au金属层,源电极和漏电极均为长方体,长度均大于10nm,宽度与整体的p型GaN层相同,高度均大于10nm,源电极和漏电极之间的间距大于第一p型GaN和第二p型GaN的长度;源电极的左侧与有源区的左边缘重合,漏电极的右侧与有源区的右边缘重合,源电极和漏电极的前后边缘与有源区的前后边缘重合。
进一步地,有源区的后边缘与第二p型GaN的后边缘重合,有源区的前边缘距第二p型GaN的长度大于5μm,有源区的左边缘距第二p型GaN的左边缘长度大于100nm,有源区的右边缘距第二p型GaN的右边缘长度大于100nm。
进一步地,栅电极的长度与第二p型GaN的长度相同,宽度为第一p型GaN与第二p型GaN宽度之和,高度在50nm与1000nm之间。
制备高线性GaN基毫米波器件的方法,包括以下步骤:
S1、p型GaN的生长:在衬底上生长AlGaN/GaN异质结外延层以及在AlGaN/GaN异质结外延层上直接生长第一p型GaN;第一p型GaN的厚度在5nm与100nm之间;
S2、不同掺杂浓度的p型GaN的二次生长:使用光刻胶覆盖除二次生长的第二p型GaN的区域,其中非光刻胶覆盖的区域的长度在10nm与100nm之间,宽度大于5μm,采用干法刻蚀工艺,刻蚀至AlGaN上下3nm以内;进行二次外延生长,生长的第二p型GaN的厚度与步骤S1中的第一p型GaN相同,第二p型GaN的掺杂浓度大于步骤S1中的第一p型GaN的掺杂浓度;最后使用化学机械抛光技术将器件表面磨平;
S3、器件的相互隔离:在AlGaN/GaN异质结外延层上表面用光刻胶定义有源区的位置并将有源区覆盖,在AlGaN/GaN异质结外延层上表面用光刻胶定义有源区的位置,并将其覆盖;非有源区的AlGaN/GaN异质结外延层上表面采用等离子体轰击刻蚀,刻蚀深度为200nm-600nm;
S4、剥离出源电极和漏电极,退火形成欧姆接触:使用光刻胶定义源电极和漏电极的位置及图形,使得源电极和漏电极的位置在有源区上表面的两端;源电极和漏电极的前后边缘与有源区的前后边缘重合;非源电极并且非漏电极的区域被光刻胶覆盖,先使用干法刻蚀的方法,刻蚀至AlGaN表面或过刻3nm以内的AlGaN,再使用电子束蒸发或者磁控溅射的方法和剥离工艺形成源电极和漏电极,最后在氮气氛围,800℃以上的温度中退火,使源电极、漏电极与AlGaN/GaN异质结外延层均形成欧姆接触;
S5、制备栅电极:使用光刻胶定义栅电极的位置及图形,长度与步骤S2中的第二p型GaN的长度相同,位于第一p型GaN和第二p型GaN的正上方;使用电子束蒸发或者磁控溅射的方法和剥离工艺形成栅电极;使用光刻胶将栅电极,源电极和漏电极保护起来,使用干法刻蚀工艺将非光刻胶覆盖的地方刻蚀至AlGaN层或过刻AlGaN层3nm以内;刻蚀完成后去除光刻胶,完成高线性GaN基毫米波器件的制备。
进一步地,步骤S1中,所述衬底材料为硅、碳化硅、蓝宝石或金刚石中的一种;步骤S1中,在生长第一p型GaN时掺杂的杂质为Mg、Zn或Fe中的一种;第一p型GaN的掺杂浓度在1×10 3/cm -3以上,生长厚度在5nm-100nm之间。
进一步地,第一p型GaN和第二p型GaN的生长方式均为金属有机化学气相沉积法或分子束外延法;干法刻蚀为感应耦合等离子体刻蚀工艺、反应离子刻蚀工艺或其他离子刻蚀工艺中的任意一种。
进一步地,步骤S2中,所述干法刻蚀中刻蚀GaN的气体为Cl 2、BCl 3、SiCl 4等含Cl气体中的一种或混合气体,或其他可刻蚀GaN材料气体。
有益效果
相对于现有技术,本发明具有以下优势及有益效果:
本发明提出的高线性GaN基毫米波器件的制备方法中,由于不同掺杂浓度的p型GaN层生长前的刻蚀不局限于刻蚀至AlGaN表面,有一定的容差,所以降低了对刻蚀精度的要求。同时由于p型GaN的掺杂浓度和厚度均可调控,能满足具有不同阈值电压的器件均具有较高的线性度。
附图说明
图1是本发明实施例中具有高线性GaN基毫米波器件的制备方法的流程图;
图2-图5分别是具有高线性GaN基毫米波器件在制备过程中步骤S1~步骤S4时的三维立体图;
图6为具有高线性GaN基毫米波器件在制备过程中完成制备栅电极时的三维立体图;
图7为本发明实施例中制备完成的具有高线性GaN基毫米波器件的三维立体图;
图8是本发明实施例中高线性GaN基毫米波器件的对比器件的三维立体图;
图9是本发明实施例中的高线性GaN基毫米波器件的转移曲线示意图;
图10是本发明实施例中的高线性GaN基毫米波器件的跨导曲线示意图;
图11是本发明实施例中高线性GaN基毫米波器件的截止频率随栅压的变化曲线示意图;
图12是本发明实施例中高线性GaN基毫米波器件的最大振荡频率随栅压的变化曲线示意图。
本发明的实施方式
以下结合具体实施例和附图对本发明的具体实施作进一步说明,但本发明的实施不限于此。
实施例 1
一种高线性GaN基毫米波器件,如图7所示,包括AlGaN/GaN异质结外延层1,所述AlGaN/GaN异质结外延层1为凸台结构,凸台上方突起部分为有源区4,有源区4上表面的两端分别连接源电极5和漏电极6,不同掺杂浓度的p型GaN层位于有源区4上表面的源电极5和漏电极6之间,其中,所述不同掺杂浓度的p型GaN层由不同掺杂浓度,但厚度相同的第一p型GaN2和第二p型GaN3沿栅宽前后排列形成,并且第一p型GaN2的后表面和第二p型GaN3的前表面相重合,左右边缘对齐;栅电极7位于不同掺杂浓度的p型GaN层的上方。
本实施例中,所述AlGaN/GaN异质结外延层1的直径为2 inch,总厚度为800μm。
本实施例中,第一p型GaN2和第二p型GaN3均为长方体,长度均为90nm,宽度均为20μm,厚度为80nm,源电极5相距2μm,与漏电极6相距2μm,第一p型GaN2和第二p型GaN3的掺杂浓度分别为1×10 8/cm -3和1×10 18/cm -3
本实施例中,源电极5和漏电极6为Ti/Al/Ni/Au金属层,源电极5和漏电极6均为长方体,高度均为380nm,长度均为1000nm,宽度均为40μm,源电极5和漏电极6之间的间距为4.09μm;源电极5的左侧与有源区4的左边缘重合,漏电极6的右侧与有源区4的右边缘重合,源电极5和漏电极6的前后边缘与有源区4的前后边缘重合。
本实施例中,有源区4的后边缘与第二p型GaN3的后边缘重合,有源区4的前边缘与第一p型GaN2的前边缘重合,有源区4的高度为2.02μm,长度6.09μm,宽度为40μm。
本实施例中,栅电极7为Ni/Au金属层,为长方体,其高度为300nm,宽度为40μm,长度与第二p型GaN3的长度相同。
实施例 2
制备高线性GaN基毫米波器件的方法,如图1所示,包括以下步骤:
S1、p型GaN的生长:本实施例中,选用硅衬底,在衬底上通过金属有机化合物气相沉积生长AlGaN/GaN异质结外延层1以及在AlGaN/GaN异质结外延层1上直接生长第一p型GaN2;第一p型GaN2的厚度为80nm,掺杂杂质为Mg,掺杂浓度为1×10 8/cm -3,如图2所示;
S2、不同掺杂浓度的p型GaN的二次生长:本实施例中,使用正性光刻胶覆盖除二次生长的第二p型GaN3的区域,其中非光刻胶覆盖的区域的长度在10nm与100nm之间,宽度大于5μm,采用感应耦合等离子刻蚀的方法,使用BCl 3和Cl 2的混合气刻蚀至AlGaN层上下3nm以内;通过金属有机化合物气相沉积进行二次外延生长,生长的第二p型GaN3的长度为90nm,宽度为20μm,厚度为80nm,掺杂杂质为Mg,掺杂浓度为1×10 18/cm -3;最后使用化学机械抛光技术将器件表面磨平,如图3所示;
S3、器件的相互隔离:本实施例中,在AlGaN/GaN异质结外延层1上表面用光刻胶定义有源区4的位置并将有源区4覆盖,有源区4后边缘与第二p型GaN3的后边缘重合,前边缘距第二p型GaN3的前边缘20μm,左边缘距第二p型GaN3的左边缘3μm,右边缘距第二p型GaN3的右边缘3μm;非有源区4的AlGaN/GaN异质结外延层1上表面采用等离子体轰击刻蚀,刻蚀深度为200nm-600nm,如图4所示;
S4、剥离出源电极和漏电极,退火形成欧姆接触:本实施例中,使用负性光刻胶定义源电极5和漏电极6的位置及图形,使得源电极5和漏电极6的位置在有源区4上表面的两端;源电极5的左边缘与有源区4的左边缘重合,长度为1μm,厚度为380nm;漏电极6的右边缘与有源区4的右边缘重合,长度为1μm,厚度为380nm;非源电极5并且非漏电极6的区域被光刻胶覆盖,采用感应耦合等离子刻蚀的方法,使用BCl 3和Cl 2的混合气刻蚀至AlGaN层表面或过刻3nm以内的AlGaN,再使用电子束蒸发或者磁控溅射的方法和剥离工艺形成源电极5和漏电极6,最后在氮气氛围,800℃以上的温度中退火,使源电极5、漏电极6与AlGaN/GaN异质结外延层1均形成欧姆接触,如图5所示;
S5、制备栅电极:本实施例中,使用正性电子束抗蚀剂定义栅电极7的位置及图形,长度与步骤S2中的第二p型GaN3的长度相同,位于第一p型GaN2和第二p型GaN3的正上方;使用电子束蒸发或者磁控溅射的方法和剥离工艺形成栅电极7,厚度为300nm,如图6所示;使用正性光刻胶将栅电极7、源电极5和漏电极6保护起来,使用干法刻蚀工艺将非光刻胶覆盖的地方刻蚀至AlGaN层或过刻AlGaN层3nm以内;刻蚀完成后去除光刻胶,完成高线性GaN基毫米波器件的制备,如图7所示。
本发明提出的高线性GaN基毫米波器件的制备方法,采用不同掺杂浓度的p型GaN调制器件阈值电压的方法,降低了对势垒层的刻蚀精度的要求,也降低了对饱和电流的影响,充分发挥了p型GaN的厚度和掺杂浓度均对器件的阈值电压和跨导影响的特点,可使得不同阈值电压的器件均可以实现高线性。
将栅极下方的p型GaN改为单一掺杂浓度,则为传统的p型GaN栅极器件,其截面图如图8所示,其中p型GaN的掺杂浓度为1×10 8/cm -3。使用Silvaco软件对本实施例和传统的p型GaN栅极器件进行了直流特性和射频特性的仿真。仿真结果如图9-图12所示。如图9所示,高线性GaN基毫米波器件的饱和电流比传统的p型GaN栅极器件小4.59%。如图10所示,高线性GaN基毫米波器件的GVS为4.2V,传统的p型GaN栅极器件的GVS为2.6V,其中GVS定义为跨导下降20%的栅极跨度。如图11和图12所示,在较大的栅极偏压范围下,截止频率与最大振荡频率随栅极电压变化的曲线较为平坦。
上述实施例仅为本发明的优选实例,不构成对本发明的任何限制,显然对于本领域的专业人员来说,在了解本发明的内容及原理后,能够在不背离本发明的原理和范围的情况下,根据本发明的方法进行形式和细节上的各种修正和改变,但是这些基于本发明的修正和改变仍在本发明的权利要求保护。

Claims (10)

  1. 一种高线性GaN基毫米波器件,其特征在于,包括AlGaN/GaN异质结外延层,所述AlGaN/GaN异质结外延层为凸台结构,凸台上方突起部分为有源区,有源区上表面的两端分别连接源电极和漏电极,不同掺杂浓度的p型GaN层位于有源区上表面的源电极和漏电极之间,其中,所述不同掺杂浓度的p型GaN层由不同掺杂浓度,但厚度相同的第一p型GaN和第二p型GaN沿栅宽前后排列形成,并且第一p型GaN的后表面和第二p型GaN的前表面相重合,左右边缘对齐;栅电极位于不同掺杂浓度的p型GaN层的上方。
  2. 根据权利要求1所述的一种高线性GaN基毫米波器件,其特征在于,所述AlGaN/GaN异质结外延层的直径为2-10inch,总厚度为200μm-1mm。
  3. 根据权利要求1所述的一种高线性GaN基毫米波器件,其特征在于,第一p型GaN和第二p型GaN的长度均在10nm与100nm之间,宽度大于5μm,厚度在5nm与100nm之间,掺杂浓度均大于1×10 3/cm -3
  4. 根据权利要求1所述的一种高线性GaN基毫米波器件,其特征在于,源电极和漏电极为Ti/Al/Ni/Au金属层,源电极和漏电极均为长方体,长度均大于10nm,宽度与整体的p型GaN层相同,高度均大于10nm,源电极和漏电极之间的间距大于第一p型GaN和第二p型GaN的长度;源电极的左侧与有源区的左边缘重合,漏电极的右侧与有源区的右边缘重合,源电极和漏电极的前后边缘与有源区的前后边缘重合。
  5. 根据权利要求1所述的一种高线性GaN基毫米波器件,其特征在于,有源区的后边缘与第二p型GaN的后边缘重合,有源区的前边缘距第二p型GaN的长度大于5μm,有源区的左边缘距第二p型GaN的左边缘长度大于100nm,有源区的右边缘距第二p型GaN的右边缘长度大于100nm。
  6. 根据权利要求1~5任一项所述的一种高线性GaN基毫米波器件,其特征在于,栅电极的长度与第二p型GaN的长度相同,宽度为第一p型GaN与第二p型GaN宽度之和,高度在50nm与1000nm之间。
  7. 制备权利要求1所述的高线性GaN基毫米波器件的方法,其特征在于,包括以下步骤:
    S1、p型GaN的生长:在衬底上生长AlGaN/GaN异质结外延层以及在AlGaN/GaN异质结外延层上直接生长第一p型GaN;第一p型GaN的厚度在5nm与100nm之间;
    S2、不同掺杂浓度的p型GaN的二次生长:使用光刻胶覆盖除二次生长的第二p型GaN的区域,其中非光刻胶覆盖的区域的长度在10nm与100nm之间,宽度大于5μm,采用干法刻蚀工艺,刻蚀至AlGaN上下3nm以内;进行二次外延生长,生长的第二p型GaN的厚度与步骤S1中的第一p型GaN相同,第二p型GaN的掺杂浓度大于步骤S1中的第一p型GaN的掺杂浓度;最后使用化学机械抛光技术将器件表面磨平;
    S3、器件的相互隔离:在AlGaN/GaN异质结外延层上表面用光刻胶定义有源区的位置并将有源区覆盖,在AlGaN/GaN异质结外延层上表面用光刻胶定义有源区的位置,并将其覆盖;非有源区的AlGaN/GaN异质结外延层上表面采用等离子体轰击刻蚀,刻蚀深度为200nm-600nm;
    S4、剥离出源电极和漏电极,退火形成欧姆接触:使用光刻胶定义源电极和漏电极的位置及图形,使得源电极和漏电极的位置在有源区上表面的两端;源电极和漏电极的前后边缘与有源区的前后边缘重合;非源电极并且非漏电极的区域被光刻胶覆盖,先使用干法刻蚀的方法,刻蚀至AlGaN表面或过刻3nm以内的AlGaN,再使用电子束蒸发或者磁控溅射的方法和剥离工艺形成源电极和漏电极,最后在氮气氛围,800℃以上的温度中退火,使源电极、漏电极与AlGaN/GaN异质结外延层均形成欧姆接触;
    S5、制备栅电极:使用光刻胶定义栅电极的位置及图形,长度与步骤S2中的第二p型GaN的长度相同,位于第一p型GaN和第二p型GaN的正上方;使用电子束蒸发或者磁控溅射的方法和剥离工艺形成栅电极;使用光刻胶将栅电极,源电极和漏电极保护起来,使用干法刻蚀工艺将非光刻胶覆盖的地方刻蚀至AlGaN层或过刻AlGaN层3nm以内;刻蚀完成后去除光刻胶,完成高线性GaN基毫米波器件的制备。
  8. 根据权利要求7所述的制备高线性GaN基毫米波器件的方法,其特征在于,步骤S1中,所述衬底材料为硅、碳化硅、蓝宝石或金刚石中的一种;步骤S1中,在生长第一p型GaN时掺杂的杂质为Mg、Zn或Fe中的一种;第一p型GaN的掺杂浓度在1×10 3/cm -3以上,生长厚度在5nm-100nm之间。
  9. 根据权利要求7所述的制备高线性GaN基毫米波器件的方法,其特征在于,第一p型GaN和第二p型GaN的生长方式均为金属有机化学气相沉积法或分子束外延法;干法刻蚀为感应耦合等离子体刻蚀工艺、反应离子刻蚀工艺或其他离子刻蚀工艺中的任意一种。
  10. 根据权利要求7所述的制备高线性GaN基毫米波器件的方法,其特征在于,步骤S2中,所述干法刻蚀中刻蚀GaN的气体为Cl 2、BCl 3、SiCl 4等含Cl气体中的一种或混合气体,或其他可刻蚀GaN材料气体。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080296618A1 (en) * 2007-06-01 2008-12-04 The Regents Of The University Of California P-GaN/AlGaN/AlN/GaN ENHANCEMENT-MODE FIELD EFFECT TRANSISTOR
US20090072272A1 (en) * 2007-09-17 2009-03-19 Transphorm Inc. Enhancement mode gallium nitride power devices
CN108231880A (zh) * 2017-12-22 2018-06-29 苏州闻颂智能科技有限公司 一种增强型GaN基HEMT器件及其制备方法
CN111293173A (zh) * 2018-12-10 2020-06-16 黄山学院 一种硅基氮化镓增强型hemt器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080296618A1 (en) * 2007-06-01 2008-12-04 The Regents Of The University Of California P-GaN/AlGaN/AlN/GaN ENHANCEMENT-MODE FIELD EFFECT TRANSISTOR
US20090072272A1 (en) * 2007-09-17 2009-03-19 Transphorm Inc. Enhancement mode gallium nitride power devices
CN108231880A (zh) * 2017-12-22 2018-06-29 苏州闻颂智能科技有限公司 一种增强型GaN基HEMT器件及其制备方法
CN111293173A (zh) * 2018-12-10 2020-06-16 黄山学院 一种硅基氮化镓增强型hemt器件及其制备方法

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