WO2022005292A1 - Hybrid decoding of product and staircase codes using bounded distance decoding and error and erasure decoding - Google Patents

Abstract

A method for hybrid decoding received data encoded using an error correction code, wherein the method comprises steps of mapping (101) the received data to a hard decision using a pre- defined mapping table, decoding (102) the received data using bounded distance decoding, BDD, determining (102) a first distance metric between the BDD decoded data and the hard decision, calculating (105) a measure of reliability of bits of the hard decision, determining (107) at least two least reliable bits of the hard decision received data, based on the calculated reliability, decoding (108) the received data, using error and erasure decoding, BED, wherein the determined at least two least reliable bits are considered to be erased, determining (109) a second distance metric between the BED decoded data and the hard decision, comparing (110) the first distance metric and the second distance metric, and based on an outcome of the comparing, outputting (111) one of the BDD decoded data and the EED decoded data. This method of hybrid decoding can be applied to decoding of product codes or staircase codes.

Description

HYBRID DECODING OF PRODUCT AND STAIRCASE CODES USING BOUNDED DISTANCE DECODING AND ERROR AND ERASURE DECODING

FIELD OF THE INVENTION

The present disclosure relates to decoding. Particular embodiments relate to a method for decoding received data encoded using an error correction code, and a related computer program, a related computer program product, and a related device.

BACKGROUND

The transmission rate of a single fibre has increased by a factor of 8000 over the past 30 years. Currently available optical line cards feature data rates of 800 Gb/s/l, and next-generation optical line cards target data rates of 1 Tb/s/ l and beyond, to cope with the growing applications such as cloud computing, internet-of-things, and video- on-demand. Reliable transmission at such high data rates cannot be achieved using standard digital signal processing (DSP) blocks, by exclusively relying on the improvement of integrated circuits, due to the end of Moore's law. Therefore, forward error correction (FEC), as an essential component of the receiver DSP, should be adapted accordingly to cope with the current trends on data rate. Designing high- performance FEC decoders for ultra-high speeds is very challenging due to the strict latency and power constraints.

Product codes (PCs) and staircase codes (SCCs) are popular FEC codes, FECs, for high-throughput applications such as fiberoptic systems and have been included in several recommendations (e.g., ITU-T G.709.2/Y.1331.2 and 400ZR). Soft-decision decoding (SDD) of PCs, also known as turbo product decoding (TPD), was proposed already more than 20 years ago in. TPD provides significant gains at the cost of high internal decoding data flow due to the iterative exchange of soft messages. Such soft message passing entails high decoding complexity, e.g., 10 W power consumption for 128 Gbps line rate. An alternative is to employ iterative hard decision decoding (HDD) for PCs and SCCs. HDD requires much lower decoding complexity (e.g., 0.62 W for 317 Gbps information rate), however, it entails large performance losses (1-2 dB depending on code rate) compared to SDD.

Recently, several hybrid decoding architectures have been proposed for both PCs and SCCs, which provide a suitable performance-complexity tradeoff between SDD and HDD. However, the data rate these recently proposed hybrid decoding architectures can achieve can still be improved upon.

SUMMARY OF THE INVENTION

It is an object of embodiments according to the present disclosure to solve the above- mentioned problems. In particular, it is an object of embodiments according to the present disclosure to provide higher data rates.

Therefore, in a first aspect, there is provided a method for decoding received data encoded using an error correction code; the method comprising:

- mapping the received data to a hard decision using a pre-defined mapping table;

- decoding the received data using bounded distance decoding, BDD, in a first decoding step; and

- determining a first distance metric between the BDD decoded data and the hard decision in the first decoding step;

- calculating a measure of reliability of bits of the hard decision; and

- determining at least two least reliable bits of the hard decision received data, based on the calculated reliability, in a second decoding step;

- decoding the received data, using error and erasure decoding, EED, wherein the determined at least two least reliable bits are considered to be erased, in the second decoding step; and

- determining a second distance metric between the EED decoded data and the hard decision, in the second decoding step; and the method further comprising:

- comparing the first distance metric and the second distance metric; and - based on an outcome of the comparing, outputting one of the BDD decoded data and the EED decoded data.

By combining the first decoding step, which is based on BDD, with the second decoding step, which is based on EED, or, in other words, by basing the final output value of the decoding method on the outcome of two different decoding attempts, embodiments according to this method improve robustness, and thus allows for improved data rates.

In particular, by determining a distance metric for each of the two decoding steps, there is provided a handy way of comparing the quality of their resulting decoding outcomes, which allows to keep performance high, and thus allows for improved data rates.

Moreover, embodiments according to the present method allow implementations wherein only so-called hard messages are exchanged between component codes, which improves overall efficiency, and thus allows for improved data rates.

In an embodiment, the error correction code is any one of: a product code; and a staircase code.

Advantageously, these classes of codes lend themselves readily to BDD and EED decoding. Nevertheless, it may be considered to use other types of error correction codes, as long as they are compatible with BDD decoding as well as with EED decoding.

In an embodiment, the measure of reliability is calculated during the first decoding step.

In this way, there is no separate calculation step that is required, but advantageously the reliability may be obtained during, and preferably as a by-product of, the first decoding step. In an embodiment, the measure of reliability is calculated by determining a density evolution at constraint nodes of a Tanner graph of an ensemble comprising a class of the error correction code.

In this way, look-up tables, LUTs, for calculating the measure of reliability can advantageously be determined.

In a further developed embodiment, the ensemble is a generalized low-density parity check ensemble when the error correction code is a product code; and the ensemble is a spatially coupled generalized low-density parity check ensemble when the error correction code is a staircase code.

In an embodiment, the measure of reliability of the bits of the received data is a log- likelihood ratio for the hard decision.

In this way, the measure of reliability has sufficient granularity, and moreover can be calculated relatively efficiently.

In an embodiment, the first decoding step and the second decoding step are performed in parallel.

In this way, overall time efficiency can be improved by better using available computation, since the step of comparing can take place as soon as both distance metrics are available.

In an embodiment, the hard decision is extended by one extra bit in each of its dimensions, wherein the one extra bit is 1 if either or both of the BDD decoding and the EED decoding were successful and is 0 if both of the BDD decoding and the EED decoding failed.

In this way, decoding may take place on binary vectors rather than ternary vectors while still indicating to future decoding attempts whether any decoding attempts were successful or whether both decoding attempts were unsuccessful, thus improving efficiency and, in turn, allowing higher data rates.

Moreover, as component codes are typically relatively long in order to reduce the error floor, the added overhead of one extra bit is relatively low.

In an embodiment, the first distance metric and the second distance metric are generalized distance metrics, wherein a generalized distance metric is represented as:

Nevertheless, in other embodiments, other types of distance metrics may be considered, for example in order to benefit from a higher speed of calculation. In another embodiment, the first distance metric and the second distance metric may even be different types of distance metrics, as long as a valid comparison can still be made between them.

In an embodiment, the method is iterated for a number of iterations, alternating over row decoding and column decoding of the received data.

In a further developed embodiment, the hard decision is updated using the returned decoded data over each iteration.

In this way, improved decoding results from decoding, say, a row can advantageously influence future decoding attempts of, say, a column sharing an item with the row, because that item in that column can be assumed to be correct with higher probability.

In a second aspect, there is provided a computer program comprising instructions configured for, when executed by a processor, causing the processor to perform the method of any previously described embodiment. In a third aspect, there is provided a computer program product storing the computer program according to the above-described embodiment on a storage device.

In a fourth aspect, there is provided a device, preferably an optical transport network device or a wireless network device, comprising:

- at least one processor; and

- at least one memory, the memory storing the computer program according to the above-described embodiment.

The skilled person will understand that, mutatis mutandis, analogous considerations and advantages may apply to embodiment according to the computer program, the computer program product, and the device, to those that were described above with respect to embodiments of the method. In particular, the computer program may be extended to comprise code function blocks corresponding with specific functionality of specific embodiments of the method.

In an embodiment, the device comprises a comparison circuit configured for comparing the first distance metric and the second distance metric, outputting one of the BDD decoded data and the EED decoded data based on an outcome of the comparing, and for updating the hard decision using the returned decoded data.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-described embodiments should not be construed as limiting to the present disclosure, whose scope is defined only by the appended claims. The above-described embodiments can be more fully understood with the help of the description below and with the appended drawings, in which:

Figure 1 schematically illustrates a product code, PC, in pane (a) and a staircase code, SCC, in pane (b);

Figure 2 schematically illustrates operation of an embodiment of a method according to the present disclosure on a product code, PC; Figures 3 and 4 show respectively a schematic of iBDD-CR for decision on code bit at iteration I by ith row decoding with input

; and a schematic of iBDD-

CR for decision on code bit

at iteration I;

Figure 5 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, of one or more embodiments according to the present disclosure with respect to known techniques, for PC with component code ;

Figure 6 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, or transmission reach improvement of one or more embodiments according to the present disclosure with respect to known techniques;

Figure 7 schematically illustrates a Tanner graph of a SC-GLDPC ensemble comprising SCC;

Figure 8 schematically illustrates operation of an embodiment of a method according to the present disclosure on a staircase code, SCC;

Figures 9, 10, 11 and 12 schematically illustrate graphs showing a comparison of performance expressed as a bit error rate, BER, or spectral efficiency, SE, of one or more embodiments according to the present disclosure with respect to known techniques;

Figure 13 schematically illustrates an embodiment of a method according to the present disclosure; and

Figure 14 schematically illustrates an embodiment of a device according to the present disclosure,.

DETAILED DESCRIPTION

Figure 1 schematically illustrates a product code, PC, in pane (a) and a staircase code, SCC, in pane (b). Fig. 1. (a) Schematic of an PC with n = 6. The code bit corresponding to the second row and second column codes is marked in green (b) Schematic of an SCC with n = 6 containing blocks

and

. The code bit corresponding to the second row and column codes in

is marked. Figure 2 schematically illustrates operation of an embodiment of a method according to the present disclosure on a product code, PC. In other words, Figure 2 shows a schematic of BEE-PC corresponding to decoding of the ith row of PC at iteration I.

Figures 3 and 4 show respectively a schematic of iBDD-CR [16] for decision on code bit at iteration I by ith row decoding with input

; and a schematic of iBDD-

CR for decision on code bit

at iteration I.

Figure 5 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, of one or more embodiments according to the present disclosure with respect to known techniques for PC with component code Ci;

Figure 6 schematically illustrates a graph showing a comparison of performance expressed as a bit error rate, BER, or transmission reach improvement of one or more embodiments according to the present disclosure with respect to known techniques. The performance is of iBDD, ideal iBDD, iBDD-SR, iBDD-CR, and BEE-PC for PC with component code C2 in the BICM with (a) 4-QAM, (b) 16-QAM, (c) 64-QAM, and (d) 256-QAM modulation (e) The optical reach improvement of BEE-PC over iBDD as well as the original optical reach of iBDD, corresponding to (a)-(d).

Figure 7 schematically illustrates a Tanner graph of a SC-GLDPC ensemble comprising SCC. The SC-GLDPC ensemble with

degree-2 VNs and n/2 CNs of degree-n. The ith spatial position is shaded in red.

and

are random interleavers corresponding to VNs and CNs, resp., at ith spatial position.

Figure 8 schematically illustrates operation of an embodiment of a method according to the present disclosure on a staircase code, SCC. The schematic of BEE-SCC corresponding to the decision on jth row of

Figures 9, 10, 11 and 12 schematically illustrate graphs showing a comparison of performance expressed as a bit error rate, BER, or spectral efficiency, SE, of one or more embodiments according to the present disclosure with respect to known techniques.

In particular, Figure 9 shows a comparison between the simulation results of iBDD-CR for SCC and PC as well as the DE analysis of iBDD-CR for SC-GLDPC and GLDPC ensembles for (a) component code C₂ (b) component code C3.

Figure 10 shows a performance comparison of iBDD, AD, iBDD-SR, iBDD-CR, and BEE-SCC for staircase code with component code C₂.

Figure 11 shows a performance comparison of iBDD, AD, iBDD-SR, iBDD-CR, and BEE-SCC for SCC with component code C3.

Figure 12 shows a performance comparison of iBDD, ideal iBDD, iBDD-CR, and BEESCC for a BICM system with 256-QAM and SCC with component code C₂.

Reference will further be made to Figures 1-12 in the description below, describing several exemplary embodiments.

Figure 13 schematically illustrates an embodiment of a method 100 according to the present disclosure. The method 100 is for decoding received data encoded using an error correction code. The method 100 comprises mapping 101 the received data to a hard decision using a pre-defined mapping table. The method 100 further comprises in a first decoding step 102 decoding 103 the received data using bounded distance decoding, BDD and determining 104 a first distance metric between the BDD decoded data and the hard decision. The method 100 further comprises calculating 105 a measure of reliability of bits of the hard decision. The method 100 further comprises in a second decoding step 106 determining 107 at least two least reliable bits of the hard decision received data, based on the calculated measure of reliability; decoding 108 the received data, using error and erasure decoding, EED, wherein the determined at least two least reliable bits are considered to be erased; and determining 109 a second distance metric between the EED decoded data and the hard decision. The method 100 further comprises comparing 110 the first distance metric and the second distance metric; and, based on an outcome of the comparing 110, outputting 111, i.e. returning an output as a result of the method to an entity or process that executed the method, e.g. called for execution of the method it in a device such as device 200 of Figure 14, one of the BDD decoded data and the EED decoded data.

As described above, by combining the first decoding step, which is based on BDD, with the second decoding step, which is based on EED, or, in other words, by basing the final output value of the decoding method on the outcome of two different decoding attempts, embodiments according to this method improve robustness, and thus allows for improved data rates.

In particular, by determining a distance metric for each of the two decoding steps, there is provided a handy way of comparing the quality of their resulting decoding outcomes, which allows to keep performance high, and thus allows for improved data rates.

Moreover, method 100 and further developed embodiments thereof allow implementations wherein only so-called hard messages are exchanged between component codes, which improves overall efficiency, and thus allows for improved data rates.

Figure 14 schematically illustrates an embodiment of a device 200 according to the present disclosure. The device 200 may preferably be an optical transport network device or a wireless network device, or may be a device coupled to a memory bank and adapted to correct storage errors of data stored on the memory bank. The device 200 comprises at least one processor 201 and at least one memory 202. The memory 202 stores a computer program according to any above-described embodiment. The processor 201 is operatively coupled to the memory 202, such that it can execute instructions of the computer program in order to perform the method according to any above-described embodiment.

Product codes (PCs) and staircase codes (SCCs) are conventionally decoded based on low-complex iterative bounded distance decoding (iBDD) of the component codes. The performance of iBDD can be improved using soft-aided (hybrid) algorithms. The latest algorithm in this class of decoders is called iBDD with combined reliability (iBDD- CR), recently proposed for PCs.

In example embodiments described in the present disclosure, we generalize iBDD-CR and improve on its performance, and thus, the contributions of the present disclosure are two. First, we extend iBDD-CR to SCCs, where the reliability of BDD outbound messages is estimated through density evolution analysis of the underlying spatially- coupled low-density parity check ensemble. The second contribution is to propose two novel decoding algorithms for PCs and SCCs which improve upon iBDD-CR. The new algorithms use an extra decoding attempt based on error and erasure decoding of the component codes. The proposed algorithms can be efficiently implemented because only the exchange of hard messages between the component decoders is required, making them an attractive solution for high throughput fiber-optic systems. Simulation results show that our algorithms based on two decoding attempts offer gains of up to 0.88 dB for both PCs and SCCs. These gains correspond to a 33% optical reach enhancement over iBDD with bit-interleaved coded modulation using 256 quadrature amplitude modulation.

It is to be noted that the term algorithm may refer to a method, and should not be construed to be limited to a strict computer-science interpretation. In other words, as used in the present disclosure, an algorithm may refer to a practical method, executed on real data stemming from a physical origin, and e.g. executed in a physical device.

The transmission rate of a single optical fiber has increased by a factor of 8000 over the past 30 years [1] Recently, a chip set with the capacity of 800 Gbit/s/l has become commercially available [2] To cope with the growth of applications such as cloud computing, internet-of-things, video-on-demand, etc., next-generation optical line cards target data rate of 1 Tb/s/l and beyond. Reliable transmission at such high data rates cannot be achieved using off-the-shelf digital signal processing (DSP) nor by exclusively relying on the improvement of integrated circuits (due to the end of Moore’s law [3]). Forward error correction (FEC) is an essential component of the receiver DSP and should be adapted accordingly to cope with the current trends on data rate. Designing high-performance FEC decoders for ultra high-speeds is very challenging due to the strict latency and power constraints.

Product codes (PCs) [4] and staircase codes (SCCs) [5] are popular FECs for high- throughput applications such as fiber optic systems and have been included in several recommendations (e.g., ITU-T G.709.2/Y.1331.2 [6] and 400ZR [7]). Soft-decision decoding (SDD) of PCs — also known as turbo product decoding (TPD) — was proposed already more than 20 years ago in [8] TPD provides significant gains at the cost of high internal decoding data flow due to the iterative exchange of soft messages. Such soft message passing entails high decoding complexity, e.g., 10 W power consumption for 128 Gbps line rate [9]1. An alternative is to employ iterative hard decision decoding (HDD) for PCs and SCCs. HDD requires much lower decoding complexity (e.g., 0.62 W for 317 Gbps information rate [10]), however, it entails large performance losses (1-2 dB depending on code rate) compared to SDD. it Recently, several hybrid decoding architectures have been proposed for both PCs and SCCs, which provide a suitable performance-complexity trade-off between SDD and HDD [11]-[16] The idea of hybrid schemes is to employ HDD as the decoding core, while exploiting the channel log-likelihood ratios (LLRs) to improve the overall decoder performance.2 In [11] and [12] two decoding algorithms for PCs were proposed based on generalized minimum distance decoding [24] In [13], a low-complex decoding algorithm based on the scaled reliability (SR) concept (called iBDD-SR) was presented for both PC and SCCs. SR models the reliability of HDD outputs based on combining the scaled HDD output with channel LLRs. In [14], the soft-aided bit-marking (SABM) decoder was proposed for PCs and SCCs based on flipping the least reliable bits and a heuristic miscorrection detection procedure. The performance of SABM was further improved for PCs based by combining SABM with SR principle [15]

The latest algorithm in the class of hybrid decoding architectures was introduced in [16], where a novel decoding technique for PCs called iterative bounded distance decoding with combined reliability (iBDD-CR) was presented. iBDDCR computes an accurate estimate for the reliability of HDD outputs for decoding of PCs. This estimate is found based on density evolution (DE) analysis on the underlying generalized low- density parity-check (GLDPC) code ensemble. Employing the iBDD-CR decoder for SCCs demands finding an accurate estimate of the reliability of the HDD outputs for SCCs, which is not necessarily the same as PCs.

The present disclosure extends our recent contribution [16] in two different directions. First, in various embodiments, we extend iBDD-CR to SCCs. In particular, preferred embodiments perform density evolution (DE) analysis for iBDD-CR employing the spatially-coupled GLDPC (SCGLDPC) ensemble, as the code ensemble containing the SCCs. The derived DE may provide an accurate estimate of the reliability of HDD outputs for SCCs, which is exploited in iBDD-CR. Second, in various embodiments, decoding algorithms for PCs and SCCs are proposed based on improving the iBDD- CR architecture with error and erasure decoding (EDD) of the component codes. We show that the proposed decoders can be efficiently implemented by only exchanging hard messages between component codes. We also perform an algorithmic level complexity comparison between our proposed schemes and decoders of [11]-[16], [21] Simulations results depict that the proposed schemes for both PCs and SCCs provide up to 0.88 dB gain compared to (standard) HDD based on iBDD of the component codes, for transmission in bit-interleaved coded modulation (BICM) using 256 quadrature amplitude modulation (QAM). Such gains are predicted to yield up to 33% optical reach improvement compared to original optical reach of iBDD for BICM with 256-QAM.

The remainder of the present disclosure is organized as follows. In Sec. II, some preliminaries and the system model are explained, and the iBDD-CR algorithm is reviewed. An example embodiment of the new hybrid decoding algorithm for PCs and SCCs is introduced in Secs. Ill and IV, resp. In Sec. V we explain the heuristics behind the proposed hybrid decoders and analyze the complexity of the proposed hybrid decoding schemes. Conclusions are drawn in Sec. VI.

II. PRELIMINARIES

Product-like codes is a family of codes constructed by serial concatenation of component codes. In the present disclosure, we consider binary PCs and SCCs. In the following, we briefly review the structure of PCs and SCCs and also explain the channel model considered in the present disclosure. The last part of this section describes the recently introduced iBDD-CR algorithm.

A. Product and Staircase Codes

Let C be a Bose-Chaudhuri-Hocquenghem (BCH) code constructed over the Galois field GF(2^V). The codeword length of C is n = 2^V -1-s and the number of its information bits is k = 2^V - vt - 1 - s, where t is the error correction capability and s is the shortening parameter of C. A PC with (n; k) component codes is defined as the set of all

arrays such that each row and column of C is a valid codeword of C. The rate

of such PC is R = k2/n . Fig. 1(a) shows the schematic of a PC code array encompassing

, as a code bit corresponding to the second row and second column component codes of a PC. PCs are conventionally decoded based on BDD of component codes. BDD corrects all error patterns with maximum Hamming weight t. If the weight of the error pattern is larger than t and there exists another codeword with Hamming distance less than t to the received codeword, BDD introduces miscorrections. Otherwise, BDD fails, where conventionally it is considered that BDD outputs its input. We refer to iterative applying the BDD on row and column codes as iBDD.

A SCC comprises the set of all matrices B, of size n/2 ^c n/2 , i = 1 ; 2; ... , such that each row of the matrix

is a valid codeword in C. Each matrix B, contains n/2 (n - k) parity bits out of (n²)/4 code bits, hence, the corresponding code rate is R = 1 - 2(n-k)/n . Fig. 1(b) shows an schematic of the SCC comprising the blocks

, and as a code bit corresponding to the second row and second column of

B,. Note that Bo is an all-zeros matrix which initializes the decoding procedure of the SCCs. SCCs are decoded in a windowed-decoding fashion, i.e. , each row of

for staircase blocks within a decoding window is decoded based on BDD [5] We also refer to iteratively applying the BDD on component codes of SCC within the decoding window, as iBDD.

B. System Model

We consider bit-interleaved coded modulation (BICM) based on M²-QAM. In BICM, the code bits are interleaved and then mapped to the constellation points using the binary reflected Gray code (BRGC) mapping. The real and imaginary part of an M²-QAM symbol with M = 2^m are both selected from the set

normalizes the constellation energy to unity. Due to the symmetry of the M²-QAM constellation, we only consider transmission of the real part of the M²-QAM symbol.

The AWGN channel output at time instant i corresponding to transmitted symbol x, X is given by

where n_Ch is the number of channel uses corresponding to a PC or SCC block,

The log likelihood ratio (LLR) of the k-th bit level of is given as

where

are sets of size 2^m symbols with 0 and 1 as the kth bit of the corresponding BRGC label, respectively. For the special case of the binary input AWGN (bi-AWGN) channel,

.

C. iBDD with Combined Reliability

In Secs. Ill and IV, we propose an embodiment of a novel hybrid decoding algorithm, which we call binary message passing based on error and erasure decoding (BEE). BEE is an improved variant of our recently introduced iBDD-CR algorithm. Here we briefly review the architecture of iBDD-CR, which is shown in Fig. 3.

Let us denote by

the decoding output of the n column codes at iteration 1 - 1, i.e.,

corresponds to the decision on code bit The input of the row decoder at iteration I is

. In the following, we just explain the decoding of the ith row code at iteration I, using the input

We denote by

the output of BDD corresponding to code bit In case of correct

decoding or miscorrection, BDD outputs a codeword, hence, we assume

using the mapping

Furthermore, in case of BDD failure, we assume

The LLR on the code bit ci;j after BDD at iteration ‘ is given as [16, Eq. (9)]

where is the channel LLR and

can be computed using a look-up table

(LUT) based on

(see [16, Theorem. 1]). Then,

is mapped to a hard decision using

where B( ) is the mapping

After applying this procedure to all row codes, the matrix

is formed and used as the input for the n column decoders. The column decoding is similar to the row counterpart. The decoding continues by iterating between row and column decoding for a given number of iterations. The additional component of iBDD-CR compared to iBDD is shown as “iBDD-CR core” in Fig. 3. As can be seen, the operations in iBDD-CR core is based on soft values, however, only (binary) hard messages are exchanged between component decoders. Therefore, the contribution of message exchanging between component codes in the overall internal decoder data flow of iBDD-CR is the same as iBDD [16], III. HYBRID DECODING OF PCS A. Generalized Distance Metric

BEE-PC exploits the so-called generalized distance (GD) metric, originally introduced in [24], in order to improve the performance of iBDD-CR. GD is defined as follows. Let

be a binary vector with reliability

. The GD between a and the binary vector

is

where

is the normalized I, i.e. ,

. One can interpret GD as a soft version of the Hamming distance, e.g., assuming

for and for

dGD(a; b) corresponds to the Hamming distance between a and b.

B. BEE-PC Algorithm Fig. 2 shows the block diagram of the proposed BEE algorithm for PCs. Without loss of generality, we explain the BEEPC decision corresponding to the ith row decoding of PC at iteration ‘. BEE-PC encompasses two decoding attempts, each corresponding to a branch, or also decoding step, in Fig. 2. First, we explain the upper branch of Fig.

contains the BDD outcome of n column decoders at iteration I - 1, corresponding to the ith row of the PC codeword, where the components are

explained in iBDD-CR decoder

channel LLRs

, and the iBDD-CR LUT, the LLR vector can be computed, where the corresponding (binary) hard messages are

Then, BDD is performed with the input

, which yields

with three possible values for the components, i.e., {+1, -1} and 0. Using

and the iBDD-CR LUT, the

is computed and the candidate decision

is formed as

. Finally,

as the score of candidate decision

is computed as

where 2n is a constant discussed in Sec.V-A. The second branch of Fig. 2 serves as another decoding attempt based on EED. The two least reliable bits of

are found based on and then erased. Then, the algebraic EED is performed on

based on [25, Sec. 6.6]. Let

be the outcome of EED with three possible values for the components, i.e., {+1, -1} in case of decoding with the mapping according to

, and 0 if EED fails. Similar to what explained for the first branch, the second candidate decision is formed as ,

where the LLR vector

is computed using

, and the iBDD-

CR LUT. Finally, as the score of candidate decision is computed as

Comparing

the candidate codeword with the minimum score is chosen as the BEE-PC decision and the corresponding BDD outcome is used for updating the input for column decoding in the next iteration, i.e. ,

After decoding of all rows of the PC at iteration I,

is utilized as the input to column decoders. To initialize the algorithm, the channel LLRs are employed as the input LLRs of both BDD and EED blocks, i.e.,

. In the last iteration

(I_max) , the BEE-PC decoding output yields from the branch with lowest score, i.e., the decoding output is

C. Numerical Results

In this section, we evaluate the performance of several exemplary embodiments of BEE-PC. Throughout the present disclosure, we consider an extended BCH (eBCH) code Ci, and BCH codes C₂ and C₃ as the component codes, where the corresponding parameters, PC and SCC rates, hard decision (HD) and soft decision (SD) Shannon limits at PC and SCC rates are given in Table I.

We also consider 10 iterations of BEE-PC appended with 2 iBDD iterations. The decision rule of type (4) is unable to correct errors with high reliabilities (code bits in error with high

). This is because for PCs and

for SCCs, i.e., the decision on a code bit is overridden by the channel error. Therefore, the appended iBDD iterations (which disregard reliabilities in the decision rule) helps the decoder to correct the errors with high reliability (see [13, Sec. VI]). For the sake of fairness, we evaluate all other algorithms with the total of 12 iterations.

In Fig. 5, we show the bit error rate (BER) performance of BEE-PC for a PC with component code Ci and transmission over the bi-AWGN channel. For the sake of comparison, we also depict the performance of iBDD, AD [21], iBDD-SR [13], SABM [14], iBDD-CR [16], iGMDD-SR [11], SABMSR [15], We also plot the performance of ideal iBDD which disregards miscorrections using a genie approach, turbo product decoding (TPD) based on the Chase-Pyndiah algorithm [8], and HD and SD Shannon limits. We highlight that iBDD and AD should be compared to HD capacity. However, all other algorithms should be compared to SD capacity, as they all exploit channel LLRs in the decoding rule. As it can be seen, BEE-PC outperforms all other algorithms where the performance gain of BEE-PC over conventional iBDD is 0.68 dB. Furthermore, the gap between BEE-PC and TPD is 0.43 dB. Therefore, BEE-PC can close 0.62% of the gap between (full hard) iBDD and (full soft) TPD. We highlight that the performance of iGMDD-SR, SABM-SR, and BMP-GMDD is close to BEE-PC. However, BMP-GMDD requires up to 30% more message exchanging between component codes than BEE-PC, and both iGMDD-SR and SABM-SR require exchanging soft messages between component decoders, which yields significantly higher decoder data flow than BEE-PC (see Sec. V-B and Table III for high level complexity discussion of different algorithms).

In Fig. 6(a)-(d) the performance of iBDD, ideal iBDD, iBDD-SR, iBDD-CR, and BEE- PC for a PC with component code C2 are shown for transmission in a BICM (employing random interleaver) with 4-QAM, 16-QAM, 64-QAM, and 256-QAM, respectively. As can be seen, BEE-PC outperforms all other decoders and the gain with respect to iBDD increases using higher order modulation. In particular, the performance gain of BEE-PC over iBDD is 0.46 dB, 0.7 dB, 0.79 dB, and 0.88 dB for 4-QAM, 16-QAM, 64- QAM, and 256-QAM, respectively. Fig. 6(e) shows the spectral efficiency (SE) versus the optical reach improvement of BEE-PC over iBDD as well as the original optical reach of iBDD, for transmission on a BICM employing PC with the same component code considered in Fig. 6(a)-(d). In order to predict the transmission reach, we used the enhanced Gaussian noise model [26] with fiber parameters summarized in Table.

III, evaluated at the optimal launched power. We also show reach efficiency h defined as the reach improvement of BEE-PC over iBDD normalized to the original reach of iBDD. As can be seen, increasing the spectral efficiency results in a smaller reach enhancement and larger h. In particular, the reach increase for 4-QAM, 16-QAM, 64- QAM, and 256-QAM are 1600 km, 640 km, 240 km, and 80 km, respectively.

IV. HYBRID DECODING OF SCCS

In this section, we extend iBDD-CR to SCCs through analyzing the decoding behavior using DE for SC-GLDPC ensemble, as the code ensemble encompassing SCCs. Then, we propose an example embodiment of a novel decoding algorithm for SCCs, which improves upon iBDD-CR and is similar in spirit to the BEEPC.

A. iBDD-CR decoding of SCCs Without loss of generality, we assume that and

are within the decoding window and we explain the decision of iBDD-CR at iteration I corresponding to

, which is located in

and also in the j-th row of .

Let us assume that

is the hard decision inputs of iBDD-CR corresponding to

and

is the corresponding channel LLRs.

We denote by the out

put of BDD on the jth row of corresponding to code bit

has three possible values, i.e. ,

. Furthermore, at the de

coding iteration I, let be the

LLR of code bit

after BDD. The hard decision on the code bit

produced by the jth row decoder is formed as

After updating is used as the input for iBDD-CR decoder, which decodes each row of

, This procedure continues until all blocks within the decoding window are decoded for a given number of iterations. In

Fig. 4, a schematic of the iBDD-CR decision for the code bit

corresponding to the decoding iteration I is shown. As can be seen from Fig. 4, the core of iBDD-CR is to compute

. As explained

can be computed using a LUT (see [16, Table I & II]). In [16] the components of this LUT are optimized for an GLDPC ensemble using DE analysis and used for implementing the iBDD-CR for PCs, as a code contained in the GLDPC ensemble. In the following, we extend this DE analysis to SC-GLDPC ensemble, which allows to find the LUT for SCCs and implement the iBDD-CR.

B. DE Analysis of iBDD-CR for SC-GLDPC

Fig. 7 shows the Tanner graph of a SC-GLDPC ensemble with n²/4 degree-2 variable nodes (VNs) and n/2 constraint nodes (CNs) of degree-n. The coupling memory of this SCGLDPC ensemble is 2. Therefore, the VNs at spatial position i are randomly connected to CNs at spatial position i and i + 1. This randomness is denoted in Fig. 7 by the edge interleavers t . Furthermore, CNs at spatial position i are randomly (denoted in Fig. 7 by the edge interleavers t ') connected to VNs at spatial position i - 1 and i. Comparing Fig. 1 (b) with Fig. 7, one can infer that SCCs can be constructed as a particular instance of SC-GLDPC ensemble, where n/2 BCH component code corresponds to CNs and n²/4 code bits of B, corresponds to VNs in spatial position i. We highlight that SCCs are deterministic codes (see [27]), i.e. , the connections of VNs and CNs are determined by the SCC structure, which is not random. The reason for analyzing the SC-GLDPC ensemble instead of the Tanner graph of SCCs is that the randomization in the SC-GLDPC ensemble significantly simplifies the DE analysis. Under other assumptions such as extrinsic message passing [28, Sec. 11— B], BICM channel mixing [29, Sec. IV-A], and employing channel adapters in BICM [30], in what follows we generalize the DE analysis of iBDD-CR originally derived for GLDPC ensemble in [16, Sec. IV], to SC-GLDPC ensemble.

Let us assume BCH codes as the CNs. In the DE analysis of iBDD-CR for the GLDPC ensemble [16, Sec. IV], it is shown that for a given one dimensional modulation order M and noise variance o², the output message error probability of the iBDD-CR at CNs and iteration I is given by

where g( ) is defined by [16, Eq. (15)] and

denotes the input message error probability of CNs. Note that

initializes the DE, where pch defined as the channel output error probability yielded by employing hard detection on channel LLRs. The difference between the Tanner graph of GLDPC codes and SC-GLDPC ensembles is the existence of coupling memory in the Tanner graph of the SC-GLPDC ensemble. To incorporate the effect of coupling in the DE analysis of SC-GLDPC, we should track message error probability corresponding to each spatial position. As we are interested in iBDD-CR for SCCs in the present disclosure, in what follows we consider SC-GLDPC ensemble with coupling width of 2, similar to Fig. 7.

We denote by

the average bit error probability from CNs at spatial position i to connected VNs at positions i and i-1. Furthermore, We denote by x^{(i) (l)} the average bit error probability from VNs at spatial position i to the connected CNs at spatial

can be calculated as

where (10) is employed to compute (12). Recall that window decoder is usually employed for decoding of SCCs. To account for the effect of window decoding in DE analysis of SC-GLDPC ensemble, we assume that the messages only exchange between VN to CNs within the decoding window, i.e. , the first and last VN (CN) position in the decoding window only connects to one CN (VN) which is located in the decoding window. Concretely, let W be the set of spatial positions within the decoding window and

be the average bit error probability from VNs at spatial position within the decoding window.

Employing

- in (11)— (12) yields the DE recursion for the SC-GLDPC ensemble at position i and iteration 1 + 1, which is given as

As shown in [16], the computation of g( ) for a DE recursion of GLDPC ensemble results in a LUT for the values of

(see Fig. 3). Similarly, the computation of

(13) for SC-GLDPC ensemble yields a LUT for the values of

corresponding to spatial position i (see Fig. 4). Due to this similarity and for the sake of compactness of the present disclosure, we refer to employ (13) in [16, Proposition 1] for computing the component values of LUTs.

C. BEE-SCC Algorithm

In this section, an example embodiment of a heuristic decoding algorithm is developed for SCCs. We refer to this new algorithm as binary message passing based on error and erasure decoding of SCCs, in short BEE-SCC. Similar to BEE-PC, BEE-SCC is inspired by iBDD-CR and utilizes the GD metric (5). Fig. 8 shows the schematic of BEE-SCC in making a decision for the jth row of . Similar to Sec. IV, we

denote by

the hard decision input of BEE-SCC corresponding to .

We start by explaining the upper branch of Fig. 8, which has some similarities to iBDD- CR. Following the iBDD-CR algorithm with input

the candidate decision

is computed as

where B( ) applies on each component of

. Then, by employing (5),

defined as the score of candidate decision

is computed as

The lower branch of Fig. 8 serves as a second decoding attempt. In particular, the 2 least reliable bits of

according to reliability vector

are erased and passed to the algebraic EED [25, Sec. 6.6], although a greater number of least reliable bits may also be erased - in that case, it is preferred to erase an even number of bits, as erasing an odd number of bits does not contribute extra to the EED decoding. We denote by

the output of EED with three possible values for the components. Using the same LUT iBDD-CR utilizes, the LLR

is computed. Then, the candidate decision

is formed as

where B( ) applies on each component of

. Afterwards, as the score of candidate decision

is computed as

Finally, the candidate codeword with the minimum score is selected and updates

D. Numerical Results

In this section, we evaluate the performance of example embodiments of iBDD-CR and BEE-SCC. We consider a window decoder with a size of 7 staircase blocks and maximum of 10 iterations, appended with 2 iBDD iterations (see Sec. Ill-C for discussion of appended iBDD iterations). We consider SCCs with even length component codes, hence, when necessary, one bit shortening is done to have the even component code length for SCCs. In order to evaluate the derived DE of iBDD-CR for SCGLDPC ensemble (see Sec. IV- B), in Fig. 9, we compare DE performance with the performance of SCCs with C2 and C3 component codes for transmission over the bi-AWGN channel. For the sake of comparison, we also show the performance of the PCs with the same component codes and DE performance of the GLDPC ensemble [16, Fig. 4], As it can be seen in Fig. 9, DE can predict the performance of SCC with good accuracy and the gap between simulation results and DE is reduced by increasing the code block length (c.f. the gap between dotted curves with solid curves of Fig. 9(a) and Fig. 9(b)). Furthermore, the spatial-coupling gain of SCC over the corresponding PC is also well- predicted by the DE analysis. Therefore, the derived DE for iBDD-CR in Sec. IV-B can be also used for the parameter optimization of SCCs, similar to the approach taken in [31] for parameter optimization of PCs.

In Figs. 10 and 11 , the performance of iBDD-CR and BEE-SCC are compared with iBDD, ideal iBDD, AD, and iBDD-SR for SCCs with C₂ and C3 component codes, and transmission over the bi-AWGN channel. One can see that BEE-SCC and iBDD-CR outperform all other algorithms. In particular the gain of iBDD-CR and BEE-SCC over iBDD is 0.41 dB and 0.55 dB for SCC with C₂, and the same gains are 0.33 dB and 0.44 dB for SCC with C₃.

In Fig. 12, we consider BICM system (employing random interleaver) with 256-QAM and C₂ as component code, where the performance of iBDD, ideal iBDD, iBDD-CR, and BEESCC are compared. For a BER of 10^-7, the performance gain of BEE-SCC and iBDD-CR over iBDD is 0.61 dB and 0.88 dB, respectively. Comparing Fig. 12 with Fig. 10 reveals that the performance improvement of the proposed schemes over iBDD increases by employing the higher order modulation. Finally, employing the GN model and fiber parameters given in Table II, BEE-SCC yields 80 km reach enhancement compared to iBDD, corresponding to reach efficiency of h = 33%.

Comparing Figs. 5, 6, 10, and 11 , one can see that the performance gain of BEE-PC and BEE-SCC over iBDD depends on the component codes. In particular, for a given component code length n, reducing t increases this gain. Furthermore, for a given component code length t, reducing n also increases performance gain. This is due to fact that the probability of component decoding miscorrections and failures increases in such cases, hence, BEE-PC and BEE-SCC (which deal with recovering the miscorrections and failures) can improve more the performance of (standard) iBDD.

V. BEE-PC AND BEE-SCC: HEURISTICS AND COMPLEXITY

A. Heuristics

Some similarities of respective embodiments of BEE-PC and BEE-SCC may be noted. Both algorithms employ an erasure attempt to improve the performance of iBDD-CR. For a component code containing e errors and s erasures, the EED is successful if

, where d_mm is the minimum Hamming distance of the component code [25, Sec. 6] The first attempt of BEE-SCC (corresponding to the upper branches in Fig. 4 and Fig. 8) considers s = 0, therefore it is capable of correcting up to

, i.e., t errors. However, the second attempt (corresponding to the lower branch in Fig. 4 and Fig. 8) considers s = 2, hence it is capable of correcting errors and 2 erasures. One can easily check that

therefore, the second attempt can correct more errors if the least reliable bits corresponds to error bits.

For a component code of length n, one can show that (5) is upper bounded by 2n, hence the definition of

and

for both BEE-PC and BEE-SCC (see (6), (7), (15), and (17)) ensures that the candidate codeword is selected from the branch without a decoding failure.

We also highlight that both BEE-PC and BEE-SCC heuristically employs the same LUT for both decoding attempts. As shown in [16, Appendix A], components of the LUT are derived based on analyzing the behavior of BDD. Following the DE steps in [16], we found that employing EED should in principle yield a new LUT, but unfortunately, finding the exact components of this LUT requires computing of some probabilities which seems to be intractable. Therefore, we pragmatically resorted to the same LUT as given by the DE analysis for iBDD-CR.

The main difference between BEE-PC and BEE-SCC is that each algorithm exploits different soft information values for the erasure attempt. In order to efficiently perform the erasure attempt one needs a reliability measure. In BEEPC,

is used to find the two least reliable bits of

(see Fig. 2). If we use the architecture of iBDDCR to implement BEE-PC, we have to exchange soft values

between component decoders, yielding a significantly higher internal decoder data flow compared to iBDD-CR. To avoid exchanging of the soft values between component codes, BEE-PC modified the iBDD-CR architecture such that the

BDD/EED decisions, i.e.,

are exchanged (c.f. Fig. 3 and the first branch

of Fig. 2). With this modification, both (hard) decisions and LLRs

used in BEE-PC can be computed internally in the decoder using

, channel LLRs, and iBDD-CR LUT.

In BEE-SCC

is used to find the two least reliable bits of

Note that according to the derived DE in Sec. IV-B,

is the reliability of iBDD-CR output

(see Fig. 8). However, in BEE-SCC we pragmatically employ it as the reliability measure for

. The motivation is that BDD reveals also some information about its input, e.g., in the case of decoding failure it shows that the input is not within the t distance of any codewords. We highlight that using

as the reliability measure for erasure attempt has also a practical implication.

is computed inside the decoder by the first decoding attempt

(see first branch of Fig. 8), hence, there is no need to exchange any soft value between component decoders in order to erase the two least reliable bits for the second decoding attempt. We remark that in principle, one can employ the BEE-PC architecture for SCCs as well. However, we found that such scheme yields minor performance improvement compared to iBDD-CR.

B. Complexity

A detailed complexity comparison between BEE-PC, BEESCC, hybrid decoding algorithms [11]-[16], and the AD decoder [21] requires hardware implementation of each decoder, and comparing the corresponding energy consumption. This implementation is beyond the scope of the present disclosure, and thus, here we only consider an algorithmic-level comparison. In the following, we first evaluate the contribution of message exchanging between component codes of BEE-PC and BEESCC in the overall internal decoder data flow, as an essential metric for high- throughput systems [5] Then, we compare other implementation requirements of BEE- PC and BEE-SCC with [11]— [16], [21] from an algorithmic level perspective.

As explained in Sec. Il-C, for the ith row decoding of PC, BEE-PC outputs

with ternary components

, and send it to the column decoder. Therefore, it may seem that the contribution of message exchanging of BEE-PC in decoder data flow is higher than that of iBDD-CR and iBDD, which both exchange only binary messages. However, in what follows, we will show that we can implement BEEPC more efficiently than a plain ternary message passing between component codes.

Recall that the components of

are ternary because BDD or EDD may fail.

In such case, all components of

are zero. If the row decoder can somehow indicate the failure to column decoder (and vice versa), then the components of

become binary. For the efficient implementation of BEE-PC, we suggest to extend

by one bit, i.e. ,

is extended from a length n vector to a vector of length n + 1. We consider that the extra bit is 1 if

corresponds to

BDD/EDD decoding.

, 1} using the mapping according to

. Furthermore, we assume that the extra bit is 0,

corresponds to BDD/EDD failure. In this case the other n

are 0. With this simple bit extension and mapping,

become binary, at the cost of sending only one extra bit per component code. As the component code of a PC is typically long to reduce the error floor, the contribution of exchanging this extra bit on decoder data flow is negligible. For instance, BEE-PC decoding of a PC with BCH component length of 255 and 511, requires only an extra message exchanging of 0.4% and 0.2%, respectively, compared to iBDD-CR and conventional iBDD. As shown in Sec. IV-C, BEE-SCC only exchanges (binary) hard decisions between component decoders (see (18) and Fig. 8), hence, the contribution of message exchanging of BEE-PC in decoder data flow is the same as iBDD-CR and conventional iBDD. Two other implementation aspects we consider here are decoding complexity of EDD and LLR calculations. BDD is usually implemented based on Berlekamp-Massey decoding of BCH codes [32]. EED can also be implemented by modifying the Berlekamp-Massey algorithm, hence, the complexities of EED decoding and BDD are roughly similar [33] BEE-PC and BEE-SCC require to compute channel LLRs for the code bits, store channel LLRs, and a sorting algorithm to find the two least reliable bits per component code. We highlight that the memory required for BEE-PC and BEE- SCC is static, as the LLRs are not updated during the decoding iterations. It is known that static memory is significantly less costly than dynamic memory in hardware implementation [10].

In Table III, we compare different features of AD [21], iBDD-SR [13], SABM [14], iBDD- CR [16], SABM-SR [15], iGMDD-SR [11], and BMP-GMDD [12] algorithms with BEE- PC and BEE-SCC.7 As can be seen from this table, some of the proposed algorithms are evaluated for PCs or for transmission over the bi-AWGN channel, however, the others are investigated for both PCs and SCCs and CM scheme. Furthermore, one can see that each algorithm requires different memory types and message passing. We highlight that the contribution of message passing on decoder data flow is estimated based on BCH component parameters n = 255, n = 511, and t = f2; 3; 4g, which is also considered in the literature [11]-[16], [21]. VI. CONCLUSIONS

In the present disclosure, we extended the recently introduced iBDDCR algorithm for PCs to SCCs, through DE analysis of the SC-GLDPC ensemble, as the code ensemble encompassing PCs. Then, embodiments relating to two novel decoding methods for PCs and SCCs are proposed, which aim to enhance the iBDD-CR using a second decoding attempt based on EED of the component codes. We have shown that the contribution of messages exchanged between component codes on decoder data flow of the BEE-PC and BEE-SCC is roughly similar to (standard) iBDD, which makes BEE- PC and BEE-SCC suitable for next generation high-throughput systems. Simulation results revealed that both BEE-PC and BEE-SCC offer gains up to 0.88 dB compared to iBDD for transmission on BICM using 256-QAM. Finally, we found that the performance gain of BEE-PC and BEESCC over iBDD may further depend on component code parameters and constellation size.

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SELECTED ABBREVIATIONS

ASIC Application-Specific Integrated Circuit

AWGN Additive White Gaussian Noise

BCH Bose-Chaudhuri-Hocquenghem

BDD Bounded Distance Decoding

BEE Binary Message Passing based on EED

BER Bit Error Rate

BICM Bit-Interleaved Coded Modulation

BRGC Binary Reflected Gray Code

CN Constraint Node

DE Density Evolution

DSP Digital Signal Processing eBCH Extended BCH

EDFA Erbium-Doped Fibre Amplifier

EED Error and Erasure Decoding

FEC Forward Error Correction

FPGA Field-Programmable Gate Array GD Generalized Distance

GLDPC Generalized Low-Density Parity Check

HDD Hard Decision Decoding iBDD Iterative BDD iBDD-CR iBDD with Combined Reliability

ITU-T International Telecommunication Union Telecommunication

Standardization Sector LLR Log-Likelihood Ratio

LUT Look-Up Table OTN Optical Transport Network

OTU Optical Transport Unit

PC Product Code

QAM Quadrature Amplitude Modulation

SABM Soft-Aided Bit-Marking SCC Staircase Code

SC-GLDPC Spatially Coupled GLDPC

SDD Soft Decision Decoding

SE Spectral Efficiency

VN Variable Node

Claims

1. A method for decoding received data encoded using an error correction code; the method comprising:

- mapping the received data to a hard decision using a pre-defined mapping table;

- decoding the received data using bounded distance decoding, BDD, in a first decoding step; and

- determining a first distance metric between the BDD decoded data and the hard decision in the first decoding step;

- calculating a measure of reliability of bits of the hard decision; and

- determining at least two least reliable bits of the hard decision received data, based on the calculated measure of reliability, in a second decoding step;

- decoding the received data using error and erasure decoding, EED, in the second decoding step, wherein the determined at least two least reliable bits are considered to be erased; and

- determining a second distance metric between the EED decoded data and the hard decision in the second decoding step; and the method further comprising:

- comparing the first distance metric and the second distance metric; and

- based on an outcome of the comparing, outputting one of the BDD decoded data and the EED decoded data.

2. The method of claim 1, wherein the error correction code is any one of: a product code; and a staircase code.

3. The method of any previous claim, wherein the measure of reliability is calculated during the first decoding step.

4. The method of any previous claim, wherein the measure of reliability is calculated by determining a density evolution at constraint nodes of a Tanner graph of an ensemble comprising a class of the error correction code.

5. The method of claim 4, wherein the ensemble is a generalized low-density parity check ensemble when the error correction code is a product code; and wherein the ensemble is a spatially coupled generalized low-density parity check ensemble when the error correction code is a staircase code.

6. The method of any previous claim, wherein the measure of reliability of the bits of the received data is a log-likelihood ratio for the hard decision.

7. The method of any previous claim, wherein the first decoding step and the second decoding step are performed in parallel.

8. The method of any previous claim, wherein the hard decision is extended by one extra bit in each of its dimensions, wherein the one extra bit is 1 if either or both of the BDD decoding and the EED decoding were successful and is 0 if both of the BDD decoding and the EED decoding failed.

9. The method of any previous claim, wherein the first distance metric and the second distance metric are generalized distance metrics, wherein a generalized distance metric is represented as:

10. The method of any previous claim, iterated for a number of iterations, alternating over row decoding and column decoding of the received data.

11. The method of claim 10, wherein the hard decision is updated using the returned decoded data over each iteration.

12. A computer program comprising instructions configured for, when executed by a processor, causing the processor to perform the method of any previous claim.

13. A computer program product storing the computer program of claim 12 on a storage device.

14. A device, preferably an optical transport network device or a wireless network device, comprising:

- at least one processor; and

- at least one memory, the memory storing the computer program of claim 12.

15. The device of claim 14, comprising a comparison circuit configured for comparing the first distance metric and the second distance metric, outputting one of the BDD decoded data and the EED decoded data based on an outcome of the comparing, and for updating the hard decision using the returned decoded data.