WO2021217529A1 - Procédé et système de communication interprocessus - Google Patents

Procédé et système de communication interprocessus Download PDF

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Publication number
WO2021217529A1
WO2021217529A1 PCT/CN2020/087917 CN2020087917W WO2021217529A1 WO 2021217529 A1 WO2021217529 A1 WO 2021217529A1 CN 2020087917 W CN2020087917 W CN 2020087917W WO 2021217529 A1 WO2021217529 A1 WO 2021217529A1
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Prior art keywords
ipc
engine
callee
data
address
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PCT/CN2020/087917
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English (en)
Chinese (zh)
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张建永
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华为技术有限公司
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Priority to CN202080001704.4A priority Critical patent/CN113939805A/zh
Priority to PCT/CN2020/087917 priority patent/WO2021217529A1/fr
Publication of WO2021217529A1 publication Critical patent/WO2021217529A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • Linux-based IPC mechanisms include, for example, pipe communication, signal communication, message queues, and sockets.
  • Android (android) Linux-based kernel provides a further optimized IPC mechanism: IPC binder.
  • Binder is a communication mechanism based on the client-server (Client-server, CS) mode. All clients obtain server-side services through a centralized binder driver.
  • IPC The performance of IPC is a key factor that affects the overall performance of computing devices. For example, for Android, user space processes need to interact frequently with a large number of user space services, and the delay performance of IPC also directly affects user experience.
  • the callee can create the page table of the process and add it to the MMU according to the starting address and length (size) of the shared memory.
  • the page table defines the segment globally The mapping relationship between the virtual address (VA) and the physical address (PA) of the shared memory, the implementation of the solution of the embodiment of this application can also realize that after the IPC engine is initialized, the operating system allocates the shared memory, and the callee initiates registration After that, the page table of this process is established and managed by MMU, so that the purpose of sharing memory between caller and callee is achieved, and changes to the existing MMU workflow are avoided, page faults are avoided, and the stability of IPC communication is ensured. Sex and safety.
  • mapping relationship between the virtual address of msg and the physical address in the memory segment is consistent with the mapping relationship recorded in the page table managed by the MMU, so, In the subsequent IPC communication, after the msg VA is passed from the caller to the callee through the IPC engine, the callee can access the page table to obtain the data according to the VA, thereby achieving the purpose of sharing memory between the caller and the callee, and avoiding the need for existing The change of the MMU workflow to avoid the occurrence of page faults, and to ensure the stability and security of IPC communication.
  • the processor core before running the client process, is further configured to send registration information of the server process to the IPC engine hardware, where the registration information includes The identifier; the IPC engine hardware is also used to: receive the registration information; in response to the registration information, save the identifier and the server process entry address in the IPC engine hardware; the IPC engine The hardware is specifically used to: find the entry address according to the identifier; set the entry address to the program counter (PC) in the processor core; the processor core is also used to, according to the setting in the The entry address in the PC runs the server process.
  • the IPC engine hardware is specifically used to: find the entry address according to the identifier; set the entry address to the program counter (PC) in the processor core; the processor core is also used to, according to the setting in the The entry address in the PC runs the server process.
  • PC program counter
  • the callee register set further includes a first address register and a counting register.
  • the first address register is used to store the first address of the callee list. Specifically, it may be the first callee entry address in the callee list.
  • the counting register is used to record the number of callee entry addresses (entry list size). Specifically, each time a list entry (ie, a callee entry address) is added to the callee list, the number of the count register records is increased by 1. In this way, through the callee register set, the entry address (callee entry address) of multiple callees can be recorded to the callee list according to the registration status of multiple callees.
  • the IPC engine hardware is further configured to, after receiving the call instruction, query the status register in the processor core to obtain the call of the client process Stack address, and save the call stack address of the client process in the IPC engine hardware; the IPC engine hardware is specifically used to call out the call stack address according to the second processor instruction and instruct The processor core resumes running the client process according to the call stack address.
  • the IPC engine can check at least one of the following conditions through the IPC logic circuit:
  • the IPC logic circuit can determine whether the process context information needs to be migrated according to whether the process is in the same core.
  • the call instruction and the return instruction are both user mode instructions. This satisfies the service call of the caller and the callback of the callee, realizes the interaction of the process at the user mode level, avoids the disadvantages of frequent switching between the user mode and the kernel mode in the existing IPC mechanism (such as the binder mechanism), and realizes that the software does not switch to the kernel. Mode, the IPC engine and CPU work in parallel on the hardware.
  • an embodiment of the present application provides a method for inter-process communication IPC.
  • the method in this embodiment is a method executed in the system described in the first aspect.
  • the method includes: when the IPC engine hardware is initialized by the processor core, a part of the memory space in the memory is configured as the shared memory space of the process, and the shared memory space is used to store the data to be transferred required for inter-process communication;
  • the start address and length of the shared memory space establish a page table, the page table contains the virtual address to the physical address mapping relationship of the shared memory space;
  • the processor core runs a client process, and the client process needs When the service of the server process is called, a first processor instruction is sent to the IPC engine hardware.
  • the first processor instruction is a call instruction of the client process to the service, and the call instruction includes the server process
  • the IPC engine hardware instructs the processor core to run the server process according to the identifier and transfers the The virtual address of the data to be transferred is sent to the server process;
  • the processor core runs the server process, and the server process queries the page table according to the virtual address of the data to be transferred to obtain the Data to be transferred to execute the service;
  • the processor core sends a second processor instruction to the IPC engine hardware, the second processor instruction is a return instruction of the server process;
  • the IPC engine hardware is based on The second processor instruction instructs the processor core to resume running the client process.
  • the processor core allocates a part of the shared memory space to the client process when the client process needs to call the service of the server process, To save the data to be transferred.
  • the method further includes: the IPC engine hardware queries the status register in the processor core To obtain the call stack address of the client process, and save the call stack address of the client process in the IPC engine hardware; correspondingly, the IPC engine hardware according to the second processor instruction, Instructing the processor core to resume running the client process includes: the IPC engine hardware calls out the call stack address according to the second processor instruction, and instructs the processor core according to the call stack address Resume the client process.
  • the method further includes: the IPC engine hardware checks the client Whether the client process and the server meet the requirements of inter-process communication; correspondingly, the IPC engine hardware instructs the processor core to run the server process according to the identifier specifically includes: the client process and the server process When the server meets the requirements of inter-process communication, the IPC engine hardware instructs the processor core to run the server process according to the identifier.
  • the call instruction and the return instruction are both user mode instructions.
  • the present application provides a method for inter-process communication IPC, which is applied to an IPC engine in the form of a physical entity (ie, IPC engine hardware); when the IPC engine hardware is initialized, the processor core will A part of the memory space in the memory is configured as the shared memory space of the process, the shared memory space is used to store the data to be transferred required for inter-process communication; the page table is established according to the starting address and length of the shared memory space, the The page table contains the mapping relationship between the virtual address and the physical address of the shared memory space;
  • the processor core allocates a part of the memory space in the shared memory space to the client process, To save the data to be transferred.
  • the method before the IPC engine receives the call instruction from the client process, the method further includes: the IPC engine accepts the registration of the server process; the IPC engine according to The registration of the server process records the identifier of the server process and the entry address of the server process.
  • the IPC engine activating the server process according to the identifier of the server process includes: the IPC engine finds the entry address of the server process according to the identifier of the server process; the IPC engine according to the identifier of the server process; The entry address of the server process runs the server process.
  • the IPC engine after the IPC engine receives the call instruction from the client process, it further includes: the IPC engine records the entry address of the client process; correspondingly, the IPC engine Restoring the client process according to the return instruction includes: the IPC engine switches the operation of the server process to the operation of the client process according to the entry address of the client process.
  • the method further includes: the IPC engine checks the client process and the server process Whether it meets the requirements of inter-process communication; correspondingly, the IPC engine activates the server process according to the identifier of the server process, including: meeting the requirements of inter-process communication between the client process and the server In this case, the IPC engine activates the server process according to the identifier of the server process.
  • the embodiments of the present application also provide IPC engine hardware, which is used to execute the method described in the third aspect, or can realize the function of the IPC engine hardware in the method described in the second aspect.
  • the IPC engine hardware includes an IPC logic circuit (or called IPC logic), callee register set, link register (or link reg), message register set, the IPC engine can be deployed on the CPU core or independently.
  • the IPC engine hardware may be a coprocessor or an independent processing chip.
  • the IPC engine hardware may be integrated in the processor, and the IPC engine hardware and the CPU core run in parallel.
  • the IPC engine hardware may be independent of the processor and communicate through a communication line/interface.
  • this application provides a computer storage medium for storing a computer program, and when the computer program is executed by one or more processors, any one of the second aspect or the third aspect is provided. Methods.
  • the present application provides a computer program product, the computer program product is used to store a computer program, and when the computer program is executed by one or more processors, any one of the second aspect or the third aspect is provided. Methods.
  • Figure 1 is a schematic diagram of a scene of the existing Binder mechanism
  • FIG. 3 is a schematic diagram of another possible application scenario of communication between a client process and a server process based on the CS mode provided by an embodiment of the present application;
  • 4A is a block diagram of a possible system structure of a computing device in an embodiment of the present application.
  • 4B is an example diagram of a physical hardware system provided by an embodiment of the present application.
  • FIG. 5B is an example diagram of some application scenarios of the IPC engine provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an IPC communication scenario using the solution of the present application provided by an embodiment of the present application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • "The following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • at least one of a, b, or c can mean: a, b, c, "a and b", “a and c", “b and c”, or “a and b and c” ", where a, b, and c can be single or multiple.
  • the client-server (CS) mode involved in the embodiments of the present application is first described below.
  • the requestor of the service can be called the client
  • the implementer of the service can be called the server
  • the process of the client can be referred to as the client process for short
  • the client process is the process that accesses the service.
  • This article can also be referred to as the sender (caller).
  • the server process can be referred to as the server process for short.
  • the server process is a process that provides services, and can also be referred to as a receiving process (callee) in this article.
  • the two processes may also be located on different computing devices, that is, IPC reflects the communication between two different computing devices (computing device 1 and computing device 2), where, The computing device 1 and the computing device 2 may both be terminals, or both may be servers, or one device may be a terminal and the other device may be a server.
  • the operating system type of the computing may be the Android system (Android system).
  • Android system the Android system
  • the inter-process communication method of the present application is applied to the Android system. Examples are explained.
  • caller and callee realize direct IPC communication in user mode, thereby avoiding the delay caused by switching between kernel mode and user mode in the existing scheme, and data between processes
  • the interaction can only transfer the data address (data access right), thereby reducing or even eliminating the occurrence of data copying, greatly improving the efficiency of data transmission, and further reducing the delay of the IPC process.
  • the IPC engine hardware 312 may be a coprocessor or an independent processing chip. In some embodiments, the IPC engine hardware 312 may be integrated in the processor 311, and the IPC engine hardware 312 and the CPU core run in parallel. In still other embodiments, the IPC engine hardware 312 may be independent of the processor 311 and communicate through a communication line/interface. For the specific function implementation of the IPC engine hardware 312, reference may be made to the description of the IPC engine in any embodiment of the present application.
  • the processor 311 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (PCM) interface, and a universal asynchronous transceiver (universal asynchronous transceiver) interface.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • UART universal asynchronous transceiver
  • asynchronous receiver/transmitter, UART mobile industry processor interface
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB Universal Serial Bus
  • the user interface 314 can be used to connect peripheral devices in the computing device 30, such as various input/output devices (I/O devices, sensors, display screens, etc.), which is not limited in the embodiment of the present application.
  • peripheral devices such as various input/output devices (I/O devices, sensors, display screens, etc.), which is not limited in the embodiment of the present application.
  • the hardware architecture may include IPC logic circuit (or IPC logic), callee register set (also referred to as the second register set), link register (or link reg), message register set (also referred to as It is the first register set), the IPC engine can be deployed on the CPU core or independently.
  • IPC logic circuit or IPC logic
  • callee register set also referred to as the second register set
  • link register or link reg
  • message register set also referred to as It is the first register set
  • the IPC engine can be deployed on the CPU core or independently.
  • the IPC logic circuit can respond to two user mode processor instructions ipccall and ipcret.
  • the ipccall and ipcret are instructions that the process can call in the user mode; control the IPC process and complete the callee Check the various conditions of the caller and so on.
  • the callback entry address includes an address pointer of the service function of the callback.
  • the service function may be a callback function (Callback function), that is, the address pointer of the callback points to the callback function (Callback function) registered by the callback. Address, the callback function is used for callee to execute the corresponding service (service).
  • the callback function belongs to a kind of handler, which is a function called through a function pointer, and the call between functions is realized through the callback function. If the pointer (address) of a function is passed as a parameter to another function, when this pointer is used to call the function pointed to by it, the function is called a callback function.
  • the IPC engine can set the Program Counter (PC) in the CPU to the callee entry address, so that the CPU starts to execute the callee process context and run the callee to execute the corresponding service.
  • PC Program Counter
  • each list entry in the callee list can be configured to correspond to an index identification (ID).
  • ID may be the process ID of the callee (ie callee ID), or the index ID may be one-to-one mapped with the process ID, and the index ID may be determined after the callee is registered with the IPC engine. In this way, it is convenient for the client process (caller) to perform IPC with one or more callees.
  • the IPC engine can find the callee entry address according to the ID passed in by the caller.
  • the call instruction (ipccall) initiated by the caller to the IPC engine carries the callee ID (callee ID).
  • the IPC logic circuit can look up the callee list according to the callee ID and index to the callee.
  • the entry address of the callee (callee entry address).
  • the IPC engine can also set the Program Counter (PC) in the CPU to the callee entry address, so that the callee can run and provide corresponding services.
  • the program counter is a register that holds the address (location) of the instruction currently being executed.
  • the storage address of the program counter is incremented by one. After each instruction is fetched, the program counter points to the next instruction in the sequence. Therefore, the IPC engine can send the callee entry address to the PC for recording, so that the CPU executes the command to run the callee.
  • the user interface of the CPU core can provide system calls such as callee entry address addition (add) and removal (remove), and the registration and deregistration of the callee service can also be done through this Interface implementation.
  • a caller can pass in one or more msg addresses through a call instruction (ipccall).
  • the address of the incoming msg may be a virtual address (VA) of the msg.
  • VA virtual address
  • One or more msg entry addresses can be recorded through the message register set each time. When the message register set records msg entry addresses multiple times, these msg entry addresses can form a list, which can be called a msg list (msg list), and this list can be stored in memory for indexing.
  • the message register set can be regarded as the manager of the msg list, providing functions such as editing (adding, deleting), maintaining, accessing, or querying the msg list.
  • the operating system allocates memory to the caller based on the shared memory, that is, allocates a part of the memory space in the shared memory to the caller to save the data to be transferred (msg), and the virtual address of the data (VA ) Indicates to the caller so that the caller can initiate the call instruction ipccall.
  • the ipccall of the caller can carry msg VA (as shown in the VA1), and the IPC logic circuit of the IPC engine can look up the mapping table corresponding to the shared memory based on the msg VA to determine the PA corresponding to the msg VA (as shown in the figure) PA1), the PA is used as the msg entry address, and the msg entry address to the msg list is recorded through the message register set. It is understandable that when multiple msg VAs are passed into the caller, multiple msg entry addresses can be recorded to the msg list through the message register set.
  • the IPC engine can find the PA by looking up the mapping table according to the incoming msg VA, and record the mapping relationship between the VA and the PA to realize the maintenance of the msg list. In this way, on the one hand, the IPC engine only needs to pass msg and VA to the callee without passing msg itself, avoiding the drawbacks of data replication and improving transmission efficiency.
  • the IPC logic circuit of the IPC engine can control the access authority of msg by setting the query authority of the callee to the msg list maintained by the IPC engine.

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Abstract

Procédé et système de communication interprocessus (IPC). Ledit système comprend : un cœur de processeur, un matériel de moteur d'IPC et une mémoire. Le cœur de processeur est utilisé pour configurer, lorsque le matériel de moteur d'IPC est initialisé, une partie de l'espace mémoire de la mémoire devant être un espace mémoire partagé, de manière à économiser des données à transmettre requises pour l'IPC, et à établir une table de pages. Le cœur de processeur exécute un appelant client et envoie une instruction d'appel au matériel de moteur d'IPC, l'instruction d'appel comprenant l'identifiant d'un appelé de serveur et une adresse virtuelle desdites données, et une adresse physique desdites données étant située dans l'espace de mémoire partagé. Le matériel de moteur d'IPC est utilisé pour ordonner au cœur de processeur d'exécuter l'appelé du serveur. Le cœur de processeur exécute l'appelé serveur, et l'appelé serveur interroge la table de pages en fonction de l'adresse virtuelle desdites données pour obtenir lesdites données pour exécuter un service, et envoie une instruction de retour au matériel de moteur d'IPC. Le matériel de moteur d'IPC est utilisé pour ordonner au cœur de processeur de restaurer et d'exécuter l'appelant client. Ainsi, le retard d'IPC peut être réduit, améliorant l'efficacité de transmission de données et améliorant les performances.
PCT/CN2020/087917 2020-04-29 2020-04-29 Procédé et système de communication interprocessus WO2021217529A1 (fr)

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CN115442173B (zh) * 2022-06-07 2024-02-06 北京车和家信息技术有限公司 车辆报文转发、处理方法、装置、电子设备及存储介质
CN115442173A (zh) * 2022-06-07 2022-12-06 北京车和家信息技术有限公司 车辆报文转发、处理方法、装置、电子设备及存储介质
WO2024007207A1 (fr) * 2022-07-06 2024-01-11 Huawei Technologies Co., Ltd. Mécanisme de synchronisation pour communication inter-processus
CN117573386A (zh) * 2023-10-31 2024-02-20 华为技术有限公司 进程间通信方法及装置
CN117573419A (zh) * 2024-01-16 2024-02-20 上海芯联芯智能科技有限公司 一种页面异常处理方法及装置
CN117573419B (zh) * 2024-01-16 2024-04-26 上海芯联芯智能科技有限公司 一种页面异常处理方法及装置
CN117692416A (zh) * 2024-02-04 2024-03-12 苏州元脑智能科技有限公司 网络报文处理方法、装置、计算机设备和存储介质
CN117692416B (zh) * 2024-02-04 2024-05-03 苏州元脑智能科技有限公司 网络报文处理方法、装置、计算机设备和存储介质
CN118467064A (zh) * 2024-07-01 2024-08-09 北京壁仞科技开发有限公司 参数传递方法和电子设备

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