WO2021196175A1 - Procédés et appareil de réglage de fréquence d'horloge sur la base d'une latence de trame - Google Patents

Procédés et appareil de réglage de fréquence d'horloge sur la base d'une latence de trame Download PDF

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Publication number
WO2021196175A1
WO2021196175A1 PCT/CN2020/083263 CN2020083263W WO2021196175A1 WO 2021196175 A1 WO2021196175 A1 WO 2021196175A1 CN 2020083263 W CN2020083263 W CN 2020083263W WO 2021196175 A1 WO2021196175 A1 WO 2021196175A1
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WIPO (PCT)
Prior art keywords
frames
frame
frame latency
gpu
display
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PCT/CN2020/083263
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English (en)
Inventor
Bo Du
Yongjun XU
Riliang PENG
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Qualcomm Incorporated
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Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to PCT/CN2020/083263 priority Critical patent/WO2021196175A1/fr
Publication of WO2021196175A1 publication Critical patent/WO2021196175A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3265—Power saving in display device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/08—Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display or frame processing.
  • GPUs graphics processing unit
  • Such computing devices may include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles.
  • GPUs execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output a frame.
  • a central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU.
  • Modern day CPUs are typically capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution.
  • a device that provides content for visual presentation on a display generally includes a GPU.
  • a GPU of a device is configured to perform the processes in a graphics processing pipeline.
  • graphics processing pipeline For the advent of wireless communication and smaller, handheld devices, there has developed an increased need for improved graphics processing.
  • the apparatus may be a display processing unit (DPU) , a GPU, a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, or a CPU.
  • the apparatus can determine a frame latency of one or more frames of a plurality of frames in a display.
  • the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time.
  • the apparatus can also calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames.
  • the apparatus can also communicate the determined frame latency of each of the one or more frames in the display. Further, the apparatus can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module. The apparatus can also analyze the frame latency of each of the one or more frames. Additionally, the apparatus can adjust or maintain a clock frequency based on the frame latency of each of the one or more frames. The apparatus can also increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold. Moreover, the apparatus can maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold. The apparatus can also adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames.
  • dcvs dynamic clock voltage scaling
  • FIG. 1 is a block diagram that illustrates an example content generation system in accordance with one or more techniques of this disclosure.
  • FIG. 2 illustrates an example GPU in accordance with one or more techniques of this disclosure.
  • FIG. 3 illustrates an example timing diagram in accordance with one or more techniques of this disclosure.
  • FIG. 4 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.
  • FIG. 5 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.
  • FIG. 6 illustrates an example diagram of display processing in accordance with one or more techniques of this disclosure.
  • FIG. 7 illustrates an example flowchart of an example method in accordance with one or more techniques of this disclosure.
  • a jank or frame drop may indicate the GPU is not performing at a sufficient level.
  • present GPU algorithms may not be sensitive or fast enough to adjust a GPU clock frequency quickly. Based on this, present GPU algorithms may cause continuous janks or frame drops in subsequent frames. For example, when a GPU is running too slowly and experiencing janks, GPU algorithms may not adjust the GPU clock frequency fast enough to quickly avoid janks. Aspects of the present disclosure can increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated.
  • the present disclosure can detect a frame latency or jank in a current display frame, and then adjust the GPU clock frequency such that in the subsequent display frame the frame latency or jank is reduced or eliminated. Aspects of the present disclosure can also efficiently implement a proper GPU clock frequency in order to optimize the amount of power expended.
  • processors include microprocessors, microcontrollers, graphics processing units (GPUs) , general purpose GPUs (GPGPUs) , central processing units (CPUs) , application processors, digital signal processors (DSPs) , reduced instruction set computing (RISC) processors, systems-on-chip (SOC) , baseband processors, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , programmable logic devices (PLDs) , state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure.
  • processors include microprocessors, microcontrollers, graphics processing units (GPUs) , general purpose GPUs (GPGPUs) , central processing units (CPUs) , application processors, digital signal processors (DSPs) , reduced instruction set computing (RISC) processors, systems-on-chip (SOC) , baseband processors, application specific integrated circuits (ASICs) ,
  • One or more processors in the processing system may execute software.
  • Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
  • the term application may refer to software.
  • one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions.
  • the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory.
  • Hardware described herein such as a processor may be configured to execute the application.
  • the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein.
  • the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein.
  • components are identified in this disclosure.
  • the components may be hardware, software, or a combination thereof.
  • the components may be separate components or sub-components of a single component.
  • the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer.
  • such computer-readable media can comprise a random access memory (RAM) , a read-only memory (ROM) , an electrically erasable programmable ROM (EEPROM) , optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.
  • RAM random access memory
  • ROM read-only memory
  • EEPROM electrically erasable programmable ROM
  • optical disk storage magnetic disk storage
  • magnetic disk storage other magnetic storage devices
  • combinations of the aforementioned types of computer-readable media or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.
  • this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and/or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU.
  • a processing unit i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU.
  • this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.
  • instances of the term “content” may refer to “graphical content, ” “image, ” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech.
  • the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline.
  • the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing.
  • the term “graphical content” may refer to a content produced by a graphics processing unit.
  • the term “display content” may refer to content generated by a processing unit configured to perform displaying processing.
  • the term “display content” may refer to content generated by a display processing unit.
  • Graphical content may be processed to become display content.
  • a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer) .
  • a display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content.
  • a display processing unit may be configured to perform composition on one or more rendered layers to generate a frame.
  • a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame.
  • a display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame.
  • a frame may refer to a layer.
  • a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.
  • FIG. 1 is a block diagram that illustrates an example content generation system 100 configured to implement one or more techniques of this disclosure.
  • the content generation system 100 includes a device 104.
  • the device 104 may include one or more components or circuits for performing various functions described herein.
  • one or more components of the device 104 may be components of an SOC.
  • the device 104 may include one or more components configured to perform one or more techniques of this disclosure.
  • the device 104 may include a processing unit 120, and a system memory 124.
  • the device 104 can include a number of optional components, e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131.
  • the display 131 may refer to the one or more displays 131.
  • the display 131 may include a single display or multiple displays.
  • the display 131 may include a first display and a second display.
  • the first display may be a left-eye display and the second display may be a right-eye display.
  • the first and second display may receive different frames for presentment thereon.
  • the first and second display may receive the same frames for presentment thereon.
  • the results of the graphics processing may not be displayed on the device, e.g., the first and second display may not receive any frames for presentment thereon. Instead, the frames or graphics processing results may be transferred to another device. In some aspects, this can be referred to as split-rendering.
  • the processing unit 120 may include an internal memory 121.
  • the processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107.
  • the device 104 may include a display processor, such as the display processor 127, to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before presentment by the one or more displays 131.
  • the display processor 127 may be configured to perform display processing.
  • the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120.
  • the one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127.
  • the one or more displays 131 may include one or more of: a liquid crystal display (LCD) , a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • a projection display device an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.
  • Memory external to the processing unit 120 may be accessible to the processing unit 120.
  • the processing unit 120 may be configured to read from and/or write to external memory, such as the system memory 124.
  • the processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 may be communicatively coupled to each other over the bus or a different connection.
  • the internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices.
  • internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM) , electrically erasable programmable ROM (EEPROM) , flash memory, a magnetic data media or an optical storage media, or any other type of memory.
  • the internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples.
  • the term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.
  • the processing unit 120 may be a central processing unit (CPU) , a graphics processing unit (GPU) , a general purpose GPU (GPGPU) , or any other processing unit that may be configured to perform graphics processing.
  • the processing unit 120 may be integrated into a motherboard of the device 104.
  • the processing unit 120 may be present on a graphics card that is installed in a port in a motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104.
  • the processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , arithmetic logic units (ALUs) , digital signal processors (DSPs) , discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.
  • processors such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs) , field programmable gate arrays (FPGAs) , arithmetic logic units (A
  • the content generation system 100 can include an optional communication interface 126.
  • the communication interface 126 may include a receiver 128 and a transmitter 130.
  • the receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, or location information, from another device.
  • the transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content.
  • the receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and/or transmitting function described herein with respect to the device 104.
  • the graphics processing pipeline 107 may include a determination component 198 configured to determine a frame latency of one or more frames of a plurality of frames in a display.
  • the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time.
  • the determination component 198 can also be configured to calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames.
  • the determination component 198 can also be configured to communicate the determined frame latency of each of the one or more frames in the display.
  • the determination component 198 can also be configured to communicate the calculated frame latency information for the one or more frames from a display module to a graphics module.
  • the determination component 198 can also be configured to analyze the frame latency of each of the one or more frames.
  • the determination component 198 can also be configured to adjust or maintain a clock frequency based on the frame latency of each of the one or more frames.
  • the determination component 198 can also be configured to increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold.
  • the determination component 198 can also be configured to maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold.
  • the determination component 198 can also be configured to adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames.
  • a device such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein.
  • a device may be a server, a base station, user equipment, a client device, a station, an access point, a computer, e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device, e.g., a portable video game device or a personal digital assistant (PDA) , a wearable computing device, e.g., a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-car computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described
  • GPUs can process multiple types of data or data packets in a GPU pipeline.
  • a GPU can process two types of data or data packets, e.g., context register packets and draw call data.
  • a context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how a graphics context will be processed.
  • context register packets can include information regarding a color format.
  • Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD) , a vertex shader (VS) , a shader processor, or a geometry processor, and/or in what mode the processing unit functions.
  • GPUs can use context registers and programming data.
  • a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state.
  • Certain processing units, e.g., a VFD can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.
  • FIG. 2 illustrates an example GPU 200 in accordance with one or more techniques of this disclosure.
  • GPU 200 includes command processor (CP) 210, draw call packets 212, VFD 220, VS 222, vertex cache (VPC) 224, triangle setup engine (TSE) 226, rasterizer (RAS) 228, Z process engine (ZPE) 230, pixel interpolator (PI) 232, fragment shader (FS) 234, render backend (RB) 236, L2 cache (UCHE) 238, and system memory 240.
  • FIG. 2 displays that GPU 200 includes processing units 220-238, GPU 200 can include a number of additional processing units. Additionally, processing units 220-238 are merely an example and any combination or order of processing units can be used by GPUs according to the present disclosure.
  • GPU 200 also includes command buffer 250, context register packets 260, and context states 261.
  • a GPU can utilize a CP, e.g., CP 210, or hardware accelerator to parse a command buffer into context register packets, e.g., context register packets 260, and/or draw call data packets, e.g., draw call packets 212.
  • the CP 210 can then send the context register packets 260 or draw call data packets 212 through separate paths to the processing units or blocks in the GPU.
  • the command buffer 250 can alternate different states of context registers and draw calls.
  • a command buffer can be structured in the following manner: context register of context N, draw call (s) of context N, context register of context N+1, and draw call (s) of context N+1.
  • aspects of mobile devices or smart phones can utilize buffer mechanisms to distribute or coordinate a buffer between an application rendering side of the device, e.g., a GPU or CPU, and a display or composition side of the device, e.g., a display engine.
  • some mobile devices can utilize a buffer queue mechanism to distribute or coordinate a buffer between an application rendering side and a display or composition side, which can include a buffer compositor or a hardware composer (HWC) .
  • the application rendering side can be referred to as a producer, while the display or composition side can be referred to as a consumer.
  • a synchronization divider or fence can be used to synchronize content between the application rendering side and the display or composition side. Accordingly, a fence can be referred to as a synchronization divider, and vice versa.
  • a variety of factors can be performance indicators for display processing between an application rendering side and a display or composition side. For instance, frames per second (FPS) and janks, i.e., delays or pauses in frame rendering or composition, are key performance indicators (KPI) .
  • KPI key performance indicators
  • a jank can be a perceptible pause in the rendering of a software application’s user interface. Both FPS and janks are KPIs in game performance and/or device display capability.
  • janks can be the result of a number of factors, such as slow operations or poor interface design.
  • a jank can also correspond to a change in the refresh rate of the display at the device. Janks are important to gaming applications because if the display fresh latency is not stable, this can impact the user experience. Accordingly, some aspects of the mobile gaming industry are focused on reducing janks and increasing FPS.
  • Applications can run at a variety of different FPS modes. In some aspects, applications can run at 30 FPS mode. In other aspects, applications can run at different FPS modes, e.g., 20 or 60 FPS. Aspects of the present disclosure can include a current frame latency time, which can refer to the time difference between when a previous frame completes being displayed and when a current frame completes being displayed. The frame latency time can also refer to the time between successive refreshing frames. The frame latency time can also be based on a frame rate.
  • the frame latency time for each frame can be 33.33 ms (e.g., corresponding to 30 FPS) , 16.67 ms (e.g., corresponding to 60 FPS) , or 50 ms (e.g., corresponding to 20 FPS) .
  • Jank reduction technology can be utilized in a number of different scenarios. For instance, slow frames, e.g., frames under 30 FPS, may optimize janks reduction differently than fast frames. For example, there may be frame pacing issues for frames under 30 FPS, which may utilize a different janks reduction technology than faster frames.
  • different mechanisms or designs may have the ability to detect janks. Also, once janks are detected, other mechanisms can be triggered. For example, a compositor can be directly triggered to bypass a vertical synchronization (VSYNC) time in order to avoid janks.
  • VSYNC vertical synchronization
  • the threshold of the janks reduction technology may be platform dependent, which may need certain tuning efforts.
  • a frame buffer or buffer queue can queue frames waiting to be sent to the display. If a frame takes too long to be rendered, then the frame may not be consumed or sent to the buffer queue by the scheduled VSYNC time.
  • a compositor may consume a frame or help send the frame buffer to the display. If the renderer takes too long to render a frame, then the compositor may be delayed in consuming the frame, so the frame will be delayed in being transmitted to the display. As such, a delay in rendering can cause a resulting delay in frame consumption or display transmission. In some aspects, if a frame has not finished rendering by a scheduled VSYNC time, then the frame will not be consumed by the compositor until the next VSYNC time. In these aspects, if there are no frames in the buffer queue, then the compositor may not be triggered to consume the frame. As the frame is not consumed, this can result in a jank.
  • a GPU can support a GPU clock frequency (clk freq) or a set of GPU clock frequencies.
  • Each of the GPU clock frequencies may include a specific GPU power level, which can also correspond to a specific GPU performance level.
  • the GPU clock frequency can be dynamically adjusted by a GPU dynamic clock voltage scaling (dcvs) algorithm, e.g., according to a GPU workload. Accordingly, the GPU dcvs algorithm can adjust the clock frequency of the GPU.
  • dcvs GPU dynamic clock voltage scaling
  • the GPU clock frequency can control the speed at which the GPU is running.
  • the GPU clock frequency can also correspond to the amount of power utilized, e.g., as the amount of voltage utilized corresponds to the GPU clock frequency. As such, if the GPU utilizes a higher clock frequency, the GPU may expend an increased amount of power.
  • GPU software or driver can continuously collect GPU workloads for previous frames from a GPU hardware’s internal performance counter over a certain time interval. Then the GPU software or driver can instruct the GPU dcvs algorithm to dynamically adjust the GPU clock frequency to match current GPU workloads.
  • the GPU dcvs algorithm can be power oriented.
  • the GPU dcvs algorithm may not be performance oriented by default. Based on this, the GPU dcvs algorithm can attempt to determine a minimum GPU clock frequency to match current GPU workloads. If the GPU dcvs algorithm is power oriented, it may be focused on conserving power, not optimizing performance. As such, when janks are experienced, the GPU dcvs algorithm may not increase the GPU clock frequency fast enough to eliminate these janks.
  • a GPU may not adjust or increase the GPU clock frequency to a higher level fast enough to quickly eliminate these janks.
  • a jank or frame drop may indicate the GPU is not performing at a sufficiently high level, so the GPU clock frequency may need to be adjusted or increased.
  • present GPU algorithms are not sensitive or fast enough to adjust the GPU clock frequency quickly. Based on this, present GPU algorithms may cause continuous janks or frame drops in subsequent frames. In addition, the average frame rate may reduce, so the average GPU workload may be even further reduced. As such, GPU algorithms may not sufficiently increase the GPU clock frequency, which may run into a negative feedback loop.
  • GPUs may not adjust the GPU clock frequency fast enough to avoid janks in subsequent frames.
  • GPU algorithms may not adjust the GPU clock frequency fast enough to quickly avoid janks. Accordingly, there is a present need to increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated.
  • aspects of the present disclosure can increase the adjustment speed of the GPU clock frequency, such that janks can be quickly reduced or eliminated.
  • the present disclosure can detect a frame latency or jank in a current display frame, and then adjust the GPU clock frequency such that in the subsequent display frame the frame latency or jank is reduced or eliminated.
  • aspects of the present disclosure can also efficiently implement a proper GPU clock frequency, such that the amount of power expended is optimized. Accordingly, aspects of the present disclosure can efficiently increase the GPU clock frequency to reduce janks, while at the same time optimizing the amount of power utilized.
  • aspects of the present disclosure can collect or determine the display frame latency information at the DPU, which can directly reflect the risk of a jank or frame drop. Display frame latency information can also be useful in deciding a workable or optimized GPU running clock frequency at the GPU. Additionally, aspects of the present disclosure can utilize a novel GPU dcvs algorithm based on display frame latency. As indicated above, some aspects of the present disclosure can collect or determine this display frame latency at the DPU.
  • the DPU hardware may start transmitting display frame data at each VSYNC boundary. Also, each VSYNC boundary may occur at a certain period, e.g., every 16.67 ms for a 60 FPS display or panel.
  • a display or panel can include multiple overlapping buffers or sections within the display.
  • Each of the buffers or sections can include a synchronization fence in order to synchronize with other buffers or sections.
  • each of the overlapping sections can be stored in a buffer prior to being transmitted to the display.
  • a display can include multiple buffers or sections, and a synchronization fence can be utilized to synchronize the buffers or sections of the display.
  • each synchronization fence can help to determine when the GPU completes rendering each buffer or section of the display.
  • FIG. 3 illustrates timing diagram 300 in accordance with one or more techniques of this disclosure.
  • timing diagram 300 includes frame 301, frame 302, frame 303, frame 304, GPU rendering process 310, and frame display process 320.
  • timing diagram 300 includes frame rendering completion times 312, 313, and 314, which are the rendering completion time for frames 302, 303, and 304, respectively.
  • Timing diagram 300 also includes a number of vertical synchronization (VSYNC) times, e.g., VSYNC 331, VSYNC 332, VSYNC 333, VSYNC 334, and VSYNC 335.
  • VSYNC vertical synchronization
  • Timing diagram 300 also includes latency threshold 340 and frame latency 350.
  • FIG. 3 shows that the time period between two VSYNC times, e.g., VSYNC 332 and VSYNC 333, is a VSYNC period.
  • the GPU may need to complete rendering a frame prior to a latency threshold, e.g., latency threshold 340, before the next VSYNC time. For instance, if the GPU completes rendering a frame after the next VSYNC time, then a jank or frame drop may be experienced.
  • a latency threshold e.g., latency threshold 340
  • frame 303 completes rendering after VSYNC 333, which can cause a jank or frame drop. Based on this, frame 303 may not be transmitted to the display, so frame 302 is displayed again.
  • the DPU may begin transferring lines or sections of the frame to the display at a VSYNC time. For instance, the DPU can transfer lines or sections of the frame to the display in a certain amount of time. For example, the DPU can transfer the entire frame in around 15 ms. If the frame rendering completion time occurs prior to the next VSYNC time, then the DPU can transfer all the lines or sections of the frame smoothly by the next VSYNC time, or within one VSYNC period. As indicated above, if a GPU does not finish rendering a frame by the next VSYNC time, the frame may not be ready to be transferred at the subsequent VSYNC time, which can produce a jank or frame drop.
  • a display frame latency can be equal to a difference between a rendering completion time of each frame and the next VSYNC boundary.
  • the frame latency 350 of frame 304 is equal to the difference between frame rendering completion time 314 and VSYNC 335.
  • the frame rendering completion time can be referred to as an input fence time stamp. If the GPU finishes rendering a frame before the next VSYNC time, the frame latency may be negative. For instance, as the frame rendering completion time is less than the next VSYNC time, subtracting the VSYNC boundary from the frame rendering completion time can produce a negative result. If the GPU finishes rendering a frame after the next VSYNC time, then the frame latency may be positive. In this instance, as the frame rendering completion time is greater than the next VSYNC boundary, subtracting the VSYNC boundary from the frame rendering completion time can produce a positive result.
  • aspects of the present disclosure can collect a maximum display frame latency by the DPU driver and transmit it to the GPU driver. This can occur when several frames are displayed simultaneously. Also, aspects of the present disclosure may compare the maximum display frame latency to a latency threshold. As indicated above, this latency threshold can be an amount of time or gap between a frame rendering completion time and the next VSYNC time. For example, the latency threshold can be a number of ms, e.g., -1 ms, prior to a subsequent VSYNC time. In some aspects, the latency threshold can be pre-selected or be a previously determined amount, e.g., -1 ms. Additionally, the latency threshold can be adjustable or tunable, e.g., based on the GPU workload.
  • a display frame latency that is less than a latency threshold may extend farther away from the next VSYNC time.
  • frame latency 350 extends farther away from VSYNC 335 than latency threshold 340, but frame latency 350 may be referred to as less than latency threshold 340 if both values are negative.
  • the display frame latency is greater than a latency threshold, there may be a risk of missing the next VSYNC time.
  • the frame rendering completion time may occur after the next VSYNC time. This scenario may cause a jank or the frame to be dropped.
  • Some aspects of the present disclosure can also feedback or transmit display frame latency information from the DPU to the GPU.
  • this frame latency information can include the frame latency of one or more display frames.
  • the GPU software or kernel driver can provide a callback function to the DPU software or kernel driver.
  • the DPU software may call back this information in each frame display cycle.
  • the GPU software can obtain the display frame latency information on a frame-by-frame basis.
  • aspects of the present disclosure can adjust or maintain the display frame latency information as an input parameter of the GPU dcvs algorithm.
  • a previous or original GPU dcvs algorithm may include a GPU hardware internal performance counter as an input parameter.
  • aspects of the present disclosure can extend the GPU dcvs algorithm to include the display frame latency information as a second input parameter. This may achieve an improved control for the GPU running clock frequency.
  • aspects of the present disclosure can determine or identify a display frame latency parameter. As indicated above, if the display frame latency is greater than the latency threshold value, such that the frame rendering completion time occurs after the start of the latency threshold, aspects of the present disclosure may increase the GPU clock frequency to a higher level. Otherwise, the present disclosure may run the previous GPU dcvs algorithm and fallback to the previous GPU clock frequency. This can occur if the display frame latency is less than or equal to the latency threshold value, such that the frame rendering completion time occurs before the start of the latency threshold. Accordingly, if the display frame latency is greater than the latency threshold value, the GPU clock frequency can be increased to reduce any potential janks. If the display frame latency is less than the latency threshold value, then the GPU clock frequency can be maintained.
  • FIG. 4 illustrates diagram 400 of display processing in accordance with one or more techniques of this disclosure.
  • diagram 400 includes a number of steps or processes for DPU 410, e.g., a DPU software pipeline, and GPU 420, e.g., a GPU software pipeline.
  • steps 412, 414, and 416 can be performed by DPU 410.
  • steps 422, 424, 426, 428, and 430 can be performed by GPU 420.
  • the DPU 410 can wait for all synchronization fences or pipes input fences to be signaled.
  • DPU 410 can calculate or determine the display frame latency information.
  • DPU 410 can communicate the display frame latency information to the GPU, i.e., call the GPU callback function to feedback the display frame latency information.
  • DPU 410 can transmit the current frame data to the display panel.
  • GPU 420 can perform idle checking.
  • GPU 420 can read or receive the display frame latency information communicated from the DPU.
  • GPU 420 can read or receive the GPU hardware performance counter for a GPU busy rate. This GPU hardware performance counter can indicate whether the GPU workload is high, or include another GPU performance indicator. Also, the GPU hardware performance counter can help to determine if the GPU clock frequency should be adjusted. Accordingly, the GPU clock frequency can be adjusted based on the GPU hardware performance counter.
  • GPU 420 can run a GPU dcvs algorithm.
  • GPU 420 can adjust a GPU running clock frequency, e.g., based on the display frame latency information, the GPU dcvs algorithm, or the GPU hardware performance counter.
  • FIG. 5 illustrates diagram 500 of display processing in accordance with one or more techniques of this disclosure.
  • diagram 500 includes a number of steps or processes for a GPU dcvs algorithm 510.
  • the GPU dcvs algorithm 510 can include an entry point.
  • aspects of the present disclosure e.g., the GPU dcvs algorithm 510, can determine whether the display frame latency is greater than a latency threshold. In some aspects, if the display frame latency is greater than a latency threshold, at step 516, the present disclosure can increase the GPU clock frequency.
  • the present disclosure can maintain the GPU clock frequency, e.g., by utilizing the original or previous GPU dcvs algorithm.
  • aspects of the present disclosure can adjust the GPU dcvs algorithm in order to adjust the GPU clock frequency.
  • the GPU dcvs algorithm 510 can include an exit point.
  • FIG. 6 illustrates diagram 600 of display processing in accordance with one or more techniques of this disclosure. More specifically, diagram 600 includes components of display processing for clock frequency adjustment based on frame latency. As shown in FIG. 6, diagram 600 includes GPU 610, DPU 620, display 630, and frames 640. GPU 610 can include clock frequency 612. FIG. 6 illustrates the communication of each of these components during display or frame processing. For instance, GPU 610 can communicate with DPU 620, and vice versa, and DPU 620 can communicate with display 630. In some instances, GPU 610, DPU 620, and display 630 can communicate one or more frames, e.g., frames 640.
  • aspects of the present disclosure can include a number of different techniques for clock frequency adjustment.
  • aspects of the present disclosure e.g., GPUs, DPUs, compositors, hardware composers, frame processors, or CPUs herein, can utilize frame latency for clock frequency adjustment.
  • GPUs and DPUs herein e.g., GPU 610 and DPU 620, can determine a frame latency of one or more frames, e.g., frames 640, of a plurality of frames in a display, e.g., display 630.
  • the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time, e.g., frame rendering completion time 314, of the frame, e.g., frame 304, and a vertical synchronization (VSYNC) time, e.g., VSYNC 335.
  • a rendering completion time e.g., frame rendering completion time 314, of the frame, e.g., frame 304
  • VSYNC vertical synchronization
  • GPUs and DPUs herein can also calculate frame latency information for the one or more frames, e.g., frames 640, based on the frame latency of each of the one or more frames.
  • GPUs and DPUs herein can also communicate the determined frame latency of each of the one or more frames, e.g., frames 640, in the display, e.g., display 630.
  • GPUs and DPUs herein can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module, e.g., frames 640.
  • GPUs and DPUs herein can also analyze the frame latency of each of the one or more frames, e.g., frame latency 350. Additionally, GPUs and DPUs herein can adjust or maintain a clock frequency, e.g., clock frequency 612, based on the frame latency of each of the one or more frames, e.g., frame latency 350.
  • the clock frequency e.g., clock frequency 612
  • the clock frequency can be a graphics processing unit (GPU) clock frequency.
  • the clock frequency, e.g., clock frequency 612 can be adjusted or maintained based on the calculated frame latency information for the one or more frames, e.g., frames 640.
  • GPUs and DPUs herein can also increase the clock frequency, e.g., clock frequency 612, when the frame latency of each of the one or more frames, e.g., frame latency 350, is greater than a frame latency threshold, e.g., latency threshold 340.
  • the frame latency threshold e.g., latency threshold 340
  • the frame latency threshold can be adjustable or tunable.
  • the frame latency threshold can be adjustable or tunable based on the clock frequency, e.g., clock frequency 612.
  • GPUs and DPUs herein can maintain the clock frequency, e.g., clock frequency 612, when the frame latency of each of the one or more frames, e.g., frame latency 350, is less than or equal to a frame latency threshold, e.g., latency threshold 340.
  • a frame latency threshold e.g., latency threshold 340.
  • the clock frequency e.g., clock frequency 612
  • dcvs dynamic clock voltage scaling
  • GPUs and DPUs herein can also adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm, e.g., GPU dcvs algorithm 510, based on the frame latency of each of the one or more frames, e.g., frame latency 350.
  • the clock frequency e.g., clock frequency 612
  • the GPU performance counter can include at least one performance parameter.
  • the frame latency of the one or more frames can be determined by a display processing unit (DPU) , e.g., DPU 620.
  • the frame latency of the one or more frames can be communicated to a GPU, e.g., GPU 610.
  • FIG. 7 illustrates an example flowchart 700 of an example method in accordance with one or more techniques of this disclosure.
  • the method may be performed by an apparatus, e.g., a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, a display processing unit (DPU) , a CPU, a GPU, or an apparatus for display or frame processing.
  • an apparatus e.g., a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, a display processing unit (DPU) , a CPU, a GPU, or an apparatus for display or frame processing.
  • DPU display processing unit
  • the apparatus can determine a frame latency of one or more frames of a plurality of frames in a display, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the frame latency of each of the one or more frames can be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can calculate frame latency information for the one or more frames based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can communicate the determined frame latency of each of the one or more frames in the display, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can communicate the calculated frame latency information for the one or more frames from a display module to a graphics module, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can analyze the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can adjust or maintain a clock frequency based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the clock frequency can be a graphics processing unit (GPU) clock frequency, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the clock frequency can be adjusted or maintained based on the calculated frame latency information for the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can increase the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the frame latency threshold can be adjustable or tunable, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can maintain the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the clock frequency can be adjusted or maintained based on a dynamic clock voltage scaling (dcvs) algorithm, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the apparatus can adjust or maintain a dynamic clock voltage scaling (dcvs) algorithm based on the frame latency of each of the one or more frames, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the clock frequency can be adjusted or maintained based on a GPU performance counter, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the GPU performance counter can include at least one performance parameter, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the frame latency of the one or more frames can be determined by a display processing unit (DPU) , as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • the frame latency of the one or more frames can be communicated to a GPU, as described in connection with the examples in FIGs. 3, 4, 5, and 6.
  • a method or apparatus for graphics processing may be a compositor, a frame compositor, a composer, a hardware composer, a frame composer, a frame processor, a display processor, a display processing unit (DPU) , a CPU, a GPU, or an apparatus for frame or graphics processing.
  • the apparatus may be the processing unit 120 within the device 104, or may be some other hardware within device 104 or another device.
  • the apparatus may include means for determining a frame latency of one or more frames of a plurality of frames in a display, where the frame latency of each of the one or more frames may be equal to a difference between a rendering completion time of the frame and a vertical synchronization (VSYNC) time.
  • the apparatus may also include means for communicating the determined frame latency of each of the one or more frames in the display.
  • the apparatus may also include means for adjusting or maintaining a clock frequency based on the frame latency of each of the one or more frames.
  • the apparatus may also include means for increasing the clock frequency when the frame latency of each of the one or more frames is greater than a frame latency threshold.
  • the apparatus may also include means for maintaining the clock frequency when the frame latency of each of the one or more frames is less than or equal to a frame latency threshold.
  • the apparatus may also include means for analyzing the frame latency of each of the one or more frames, wherein the clock frequency is adjusted or maintained based on the analyzed frame latency of each of the one or more frames.
  • the apparatus may also include means for calculating frame latency information for the one or more frames based on the frame latency of each of the one or more frames.
  • the apparatus may also include means for communicating the calculated frame latency information for the one or more frames from a display module to a graphics module.
  • the apparatus may also include means for adjusting or maintaining the dcvs algorithm based on the frame latency of each of the one or more frames.
  • the described display processing techniques can be used by compositors, frame compositors, composers, hardware composers, frame composers, frame processors, display processors, DPUs, CPUs, GPUs, or other display or frame processors to enable the aforementioned clock frequency adjustment. This can also be accomplished at a low cost compared to other display or frame processing techniques.
  • the display or frame processing techniques herein can improve or speed up data processing or execution. Further, the display or frame processing techniques herein can improve the data utilization and/or resource efficiency of DPUs or GPUs.
  • the display or frame processing techniques herein can include clock frequency adjustments based on frame latency that can optimize the amount of power utilized. Clock frequency adjustment techniques herein can also increase the clock frequency in order to reduce the amount of janks experienced.
  • the term “or” may be interrupted as “and/or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.
  • the functions described herein may be implemented in hardware, software, firmware, or any combination thereof.
  • processing unit has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave.
  • Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices.
  • Disk and disc includes compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
  • a computer program product may include a computer-readable medium.
  • the code may be executed by one or more processors, such as one or more digital signal processors (DSPs) , general purpose microprocessors, application specific integrated circuits (ASICs) , arithmetic logic units (ALUs) , field programmable logic arrays (FPGAs) , or other equivalent integrated or discrete logic circuitry.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • ALUs arithmetic logic units
  • FPGAs field programmable logic arrays
  • the techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set.
  • IC integrated circuit
  • Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.
  • GPU can support a set/list of GPU clk freq, and each GPU clk freq is binding to a specific GPU power level, which is also binding to a specific GPU performance level.
  • GPU clk freq is dynamically adjusted by a GPU dcvs (dynamically clock voltage scale) algorithm according to current GPU's work loads.
  • GPU SW/Driver is continuously collecting the GPU's work loads in the past few frames from GPU HW's internal perf counter in a certain time interval, then input to the GPU dcvs algorithm to dynamically adjust the GPU clk freq to match the current GPU's work loads.
  • GPU dcvs algorithm is mainly power oriented, not performance oriented by default, it is trying the best to find a minimum GPU clk freq to match the current GPU's work loads.
  • Part 1 -collect the display frame latency info in DPU side:
  • DPU HW should start display data transmitting at each Vsync boundary which comes in a certain period like 16.7ms for 60fps display.
  • DPU SW kernel driver
  • the display frame latency input fence time stamp of each frame -Vsync boundary
  • the maximum display frame latency is collected in DPU driver and pass to GPU driver, and the maximum display frame latency is compared to one Threshold ( ⁇ 0) , such as -1.0ms,
  • GPU SW kernel driver
  • DPU SW kernel driver
  • the original GPU dcvs algorithm only take GPU HW internal perf counter as input parameter.

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Abstract

La présente invention concerne des procédés et un appareil de traitement d'affichage. L'appareil peut déterminer une latence de trame d'une ou de plusieurs trames d'une pluralité de trames dans une unité d'affichage. Selon certains aspects, la latence de trame de chacune de la ou des trames peut être égale à une différence entre un temps d'exécution de rendu de la trame et un temps de synchronisation verticale (VSYNC). L'appareil peut également communiquer la latence de trame déterminée de chacune de la ou des trames dans l'unité d'affichage. De plus, l'appareil peut régler ou maintenir une fréquence d'horloge sur la base de la latence de trame de chacune de la ou des trames. L'appareil peut également régler ou maintenir un algorithme de mise à l'échelle de tension d'horloge dynamique (dcvs) sur la base de la latence de trame de chacune de la ou des trames. De plus, l'appareil peut analyser la latence de trame de la ou des trames.
PCT/CN2020/083263 2020-04-03 2020-04-03 Procédés et appareil de réglage de fréquence d'horloge sur la base d'une latence de trame WO2021196175A1 (fr)

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