WO2021192562A1 - System and method for accelerating ageing of interconnections used for interconnecting power semiconductors - Google Patents

System and method for accelerating ageing of interconnections used for interconnecting power semiconductors Download PDF

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Publication number
WO2021192562A1
WO2021192562A1 PCT/JP2021/002118 JP2021002118W WO2021192562A1 WO 2021192562 A1 WO2021192562 A1 WO 2021192562A1 JP 2021002118 W JP2021002118 W JP 2021002118W WO 2021192562 A1 WO2021192562 A1 WO 2021192562A1
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WIPO (PCT)
Prior art keywords
piezoelectric material
power semiconductors
interconnecting power
interconnection
piezoelectric
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PCT/JP2021/002118
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French (fr)
Inventor
Nicolas Degrenne
Merouane OUHAB
Stefan MOLLOV
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Mitsubishi Electric Corp
Mitsubishi Electric R&D Centre Europe BV Netherlands
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Mitsubishi Electric Corp
Mitsubishi Electric R&D Centre Europe BV Netherlands
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Publication of WO2021192562A1 publication Critical patent/WO2021192562A1/en
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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/22—Measuring piezoelectric properties

Definitions

  • the present invention relates generally to a system for accelerating the ageing of interconnections used for interconnecting power semiconductors.
  • Wire bond lift-off and die solder cracking are pointed out as the most recurrent degradation processes under field conditions due to thermomechanical fatigue.
  • the dissipated losses during operation flow through the multi-layers of the power semiconductor assembly and are extracted by means of the heatsink.
  • Thermal cycling is a testing method, where the temperature of the whole device under test package is isothermally cycled using a climatic room temperature. The applied thermal cycle lasts usually for many minutes. This test emulates the variation of ambient temperature.
  • the present invention aims to provide a system for accelerating the ageing of interconnections used for interconnecting power semiconductors.
  • the present invention concerns a system for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the system comprises:
  • the interconnection(s) can be subjected to an ageing process by electromechanical dilatation using a cyclic electric field instead of using power cycling tests that are energy consuming and present high cost.
  • the interconnection used for interconnecting power semiconductors is composed of a metallization on which a wire or a foil or a ribbon is bonded.
  • the metallization allows to apply a uniform electric field within the piezoelectric material.
  • it further comprises a third electrode that is connected to the wire or the foil or the ribbon and means for monitoring the resistance between the first and third electrodes.
  • the third electrode allows an on-line measurement of the interconnection resistance that is correlated to the degradation level of the contact between the wire/foil/ribbon and the metallization.
  • the interconnection used for interconnecting power semiconductors is a solder or a sintering joint.
  • solders Sn-Ag-Cu alloys
  • advanced die attaches based on sintering can be tested to measure their reliability, since they are considered as critical regions in standard power devices.
  • it further comprises a third electrode that is connected to the solder or the sintering joint and means for monitoring the resistance between the second and third electrodes.
  • the system comprises two interconnections used for interconnecting power semiconductors.
  • a first interconnection located on the top of the piezoelectric element is composed of a metallization on which a wire or a foil or a ribbon is bonded and a second interconnection located on the bottom of the piezoelectric element is a solder or a sintering joint.
  • the system comprises:
  • no electric field is applied between the first and second electrodes of one piezoelectric material during a given time and the first and second electrodes are used for measuring the voltage across said piezoelectric material in order to estimate the local effective strain during the given time.
  • the system comprises:
  • the system is further mounted on a ceramic base plate.
  • the ceramic offers an electrical isolation and a mechanical stability.
  • the present invention concerns also a method for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the method comprises the steps of:
  • the interconnect! on(s) can be subjected to an ageing process by electromechanical dilatation using a cyclic electric field instead of using power cycling tests that are energy consuming and present high cost.
  • the method further comprises the steps of:
  • this technique allows a close monitoring of crack propagation in the interconnections from one side based on a cross-section that preserves its electrical functionality.
  • Crack conditions might be monitored using for example a Digital Image Correlation (DIC) method, Scanning Acoustic Microscopy (SAM) or crystallography to analyse the microstructure change with the ageing process.
  • DIC Digital Image Correlation
  • SAM Scanning Acoustic Microscopy
  • Figure 1 represents a first example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Figure 2 represents a second example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Figure 3 represents a third example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Figure 4 represents a fourth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Figure 5 represents a fifth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • Figure 6 represents a sixth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • Figure 7 represents a device that is able to execute the method disclosed in reference of Fig. 8.
  • Figure 8 represents an example of an algorithm for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • Figure 9 represent an example of views of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors provided by the algorithm of Fig. 8.
  • Figure 10 represent an example of views of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors provided by the algorithm of Fig. 8.
  • Figure 11 represents a seventh example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Figure 12 represents an eighth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • Fig. 1 represents a first example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises a piezoelectric material 10a, an interconnection 13a used for interconnecting power semiconductors located on the bottom of the piezoelectric material 10a.
  • the interconnection 13a used for interconnecting power semiconductors is a solder or a sintered joint.
  • the interconnection 13a is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
  • SAC Sn-Ag-Cu
  • the system comprises a first electrode 11a disposed on the top of the piezoelectric material 10a and a second electrode 12a disposed on the bottom of the piezoelectric material 10a that are used for applying an electric field between the top and the bottom of the piezoelectric material 10 a.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular sinusoidal or a sawtooth waveform.
  • the electric field may be also a time dependent profile which reproduces complex mechanical loading.
  • Fig. 2 represents a second example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises a piezoelectric material 10b, an interconnection used for interconnecting power semiconductors located on the top of the piezoelectric material 10b.
  • the interconnection used for interconnecting power semiconductors is composed of a metallization 14b on which a wire or a foil or a ribbon 15b is bonded.
  • the interconnection is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm.
  • the wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm.
  • the system comprises a first electrode l ib disposed on the top of the metallization 14b and a second electrode 12b disposed on the bottom of the piezoelectric material 10b that are used for applying an electric field between the top and the bottom of the piezoelectric material 10b.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may be also be spring-loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
  • the electric field may be also a time dependent profile which reproduces complex mechanical loading.
  • Fig. 3 represents a third example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises a piezoelectric material 10c and two interconnections 13c and 15b used for interconnecting power semiconductors.
  • the interconnection 13c is used for interconnecting power semiconductors located on the bottom of the piezoelectric material 10c.
  • the interconnection 13c used for interconnecting power semiconductors is a solder or a sintering joint.
  • the interconnection 13c is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
  • SAC Sn-Ag-Cu
  • the system comprises a first electrode 11c disposed on the top of the piezoelectric material 10c and a second electrode 12c disposed on the bottom of the piezoelectric material 10c that are used for applying an electric field between the top and the bottom of the piezoelectric material 10c.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
  • the electric field may be also a time dependent profile which reproduces complex mechanical loading.
  • the interconnection used for interconnecting power semiconductors is composed of a metallization 14c on which a wire or a foil or a ribbon 15c is bonded and is disposed on the top of the piezoelectric material 10c.
  • the interconnection 15c is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm.
  • the wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm.
  • Fig. 4 represents a fourth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises a piezoelectric material lOd, an interconnection 13d used for interconnecting power semiconductors located on the bottom of the piezoelectric material lOd.
  • the interconnection 13d used for interconnecting power semiconductors is a solder or a sintering joint.
  • the interconnection 13d is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
  • SAC Sn-Ag-Cu
  • the system comprises a first electrode l id disposed on the top of the piezoelectric material lOd and a second electrode 12d disposed on the bottom of the piezoelectric material 1 Od that are used for applying an electric field between the top and the bottom of the piezoelectric material lOd.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
  • the electric field may also be a time dependent profile which reproduces complex mechanical loading.
  • the system further comprises a ceramic base plate (16d) on which the second electrode 12d is mounted.
  • the baseplate is made of Alumina (A1203)- or Aluminium Nitride (AlN)-based ceramic with a thickness higher than 700 um.
  • the ceramic baseplate is used to provide a mechanical stability for the assembly during the fatigue test, it reproduces more accurately the structure of a power module, and thus, the strain/stress is also more realistically reproduced on the wire and/or the solder/sintered layer.
  • the ceramic baseplate may be replaced by a direct bonded copper ( DBC) substrate.
  • DBC direct bonded copper
  • Fig. 5 represents a fifth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • the system comprises a piezoelectric material lOe, an interconnection 13e used for interconnecting power semiconductors located on the bottom of the piezoelectric material lOe.
  • the interconnection 13e used for interconnecting power semiconductors is a solder or a sintering joint.
  • the interconnection 13e is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
  • SAC Sn-Ag-Cu
  • the system comprises a first electrode l ie disposed on the top of the piezoelectric material lOe, a second electrode 12e disposed on the bottom of the piezoelectric material 1 Oe that are used for applying an electric field between the top and the bottom of the piezoelectric material 1 Oe.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
  • the electric field may be also a time dependent profile which reproduces complex mechanical loading.
  • the system further comprises a third electrode 17e that is connected to the solder or the sintering joint and means 18e for monitoring the resistance between the second and third electrodes.
  • Fig. 6 represents a sixth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • the system comprises a piezoelectric material lOf, an interconnection 13f used for interconnecting power semiconductors located on the top of the piezoelectric material lOf.
  • the interconnection used for interconnecting power semiconductors is composed of a metallization 14f on which a wire or a foil or a ribbon 15f is bonded.
  • the interconnection is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm.
  • the wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm.
  • the system comprises a first electrode I lf disposed on the top of the metallization 14b and a second electrode 12f disposed on the bottom of the piezoelectric material 1 Of that are used for applying an electric field between the top and the bottom of the piezoelectric material lOf.
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
  • the electric field may be also a time dependent profile which reproduces complex mechanical loading.
  • the system further comprises a third electrode 19f that is connected to the wire or the foil or the ribbon 15f and means 18f for monitoring the resistance between the first and third electrodes.
  • Fig. 7 represents a device that is able to execute the method disclosed in reference of Fig. 8.
  • the device 100 has, for example, an architecture based on components connected together by a bus 701 and a processor 700 controlled by a program.
  • the bus 701 links the processor 700 to a read only memory ROM 702, a random access memory RAM 703, and an input output I/O interface I/F 705.
  • the memory 703 contains registers intended to receive variables and the instructions of the program related to the algorithm disclosed in Fig. 8.
  • the read-only memory or possibly a flash memory 702, contains instructions of the program related to the algorithm disclosed in Fig. 8.
  • the instructions stored in the memory 702 are transferred to the random access memory 703.
  • the device 100 includes circuitry enabling the estimation module 107 to perform the program as disclosed in Fig. 8.
  • Fig. 8 represents an example of an algorithm for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
  • the device 100 commands through the input output I/O interface I/F 705 the disposing of two interconnections used for interconnecting power semiconductors located on the tops 14g and 15g and on the bottom 13g of the piezoelectric material 1 Og.
  • the device 100 commands through the input output I/O interface I/F the coating in a resin of the interconnections 13g and 15g used for interconnecting power semiconductors located on the top and the bottom of a piezoelectric material and the piezoelectric material lOg as shown in Fig. 9.
  • the device 100 commands through the input output I/O interface I/F to perform a micro-section of the interconnection used for interconnecting power semiconductors as disclosed in Fig. 10. For that, the device 100 commands through the input output I/O interface I/F to cut on a vertical axis the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material and the piezoelectric material. At the same step, the device 100 commands through the input output I/O interface I/F the removing of the resin using, for example, dedicated chemicals.
  • the device 100 commands through the input output I/O interface I/F the applying, during a predetermined period, of an electric field between the top and the bottom of the piezoelectric material using a first electrode 1 lg disposed on the top of the piezoelectric material and a second electrode 12g disposed on the bottom of the piezoelectric material lOg.
  • the device 100 commands through the input output I/O interface I/F a Digital Image Correlation system and/or a Scanning Acoustic Microscopy system or crystallography analysis system in order to measure the behaviour of the least one interconnection used for interconnecting power semiconductors.
  • Fig. 11 represents a seventh example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises plural piezoelectric materials lOh, 10h’, lOh” and lOh’”, one interconnection used for interconnecting power semiconductors located on the top of the piezoelectric materials lOh, 10h’, lOh” and 10h” ⁇
  • the piezoelectric materials have the same piezoelectric property.
  • the interconnection used for interconnecting power semiconductors is composed of metallization 14h, 14h’, 14h” and 14h’” on which a wire or a foil or a ribbon 15h is bonded.
  • the system comprises for each piezoelectric material a first electrode l lh, 1 lh’, 1 lh” and l lh’” disposed on the top of the metallization 14h, 14h’, 14h” and 14h’” and a second electrode 12h disposed on the bottom of the piezoelectric material lOh that are used for applying an electric field between the top and the bottom of the piezoelectric materials lOh, 10h’, lOh” and 10h” ⁇
  • each electrode metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the electrodes may also be spring-loaded in order to provide a reliable contact with the piezoelectric material.
  • the electric field between the top and the bottom of each piezoelectric material is different of the electric field applied between the top and the bottom of at least one other piezoelectric materials.
  • no electric field is applied between the first and second electrodes of one piezoelectric material during a given time and the first and second electrodes are used for measuring the voltage across said piezoelectric material in order to estimate the local effective strain during the given time.
  • Fig. 12 represents an eighth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
  • the system comprises plural piezoelectric materials lOi, 10i’, lOi” and lOi’”, one interconnection used for interconnecting power semiconductors located on the top of the piezoelectric materials lOh, 10h’, 1 Oh” and 10h” ⁇
  • the piezoelectric materials have different piezoelectric properties.
  • the interconnection used for interconnecting power semiconductors is composed of a metallization on which a wire or a foil or a ribbon 15i is bonded.
  • the system comprises for the piezoelectric materials a first electrode l li disposed on the top of the metallization and a second electrode 12i disposed on the bottom of the piezoelectric material lOi that are used for applying an electric field between the top and the bottom of the piezoelectric materials lOi, 10i’, lOi” and 10i” ⁇
  • the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern.
  • the first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
  • each piezoelectric material is the same as the electric field applied between the top and the bottom of the other piezoelectric materials.

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Abstract

The present invention concerns a system for accelerating the ageing of interconnections used for interconnecting power semiconductors. The system comprises: a piezoelectric material, at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material, means for applying an electric field between the top and the bottom of the piezoelectric material using a first electrode disposed on the top of the piezoelectric material and a second electrode disposed on the bottom of the piezoelectric material, means for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.

Description

[DESCRIPTION]
[Tile of Invention]
SYSTEM AND METHOD FOR ACCELERATING AGEING OF INTERCONNECTIONS USED FOR INTERCONNECTING POWER SEMICONDUCTORS [Technical Field]
[0001]
The present invention relates generally to a system for accelerating the ageing of interconnections used for interconnecting power semiconductors.
[Background Art]
[0002]
Understanding the effect of mechanical stress on the strength and the lifetime of interconnections in power semiconductor devices is necessary to face the high requirements in terms of reliability level. Mechanical testing plays an important role in the design stage of power semiconductors and even after the manufacturing of the power semiconductor. Mechanical testing of interconnections enables to measure and improve reliability and robustness of the interconnection, reduce qualification tests, optimize designs for specific performances and develop physics-based lifetime models.
[0003]
Wire bond lift-off and die solder cracking are pointed out as the most recurrent degradation processes under field conditions due to thermomechanical fatigue. [0004]
The dissipated losses during operation flow through the multi-layers of the power semiconductor assembly and are extracted by means of the heatsink.
[0005]
This causes temperature gradients inside the multi-layered structure. The mismatch in the Coefficient of Thermal Expansion (CTE) of the stacked layers generates high shear stresses at interfaces, which induce voids formation and cracks propagation in wire bonds and die solder joints. Consequently, the losses increase and the thermal path degrades causing an overheating in the power semiconductor zone leading to more accumulated damage over the time until the device failure. [0006]
Thermal cycling is a testing method, where the temperature of the whole device under test package is isothermally cycled using a climatic room temperature. The applied thermal cycle lasts usually for many minutes. This test emulates the variation of ambient temperature.
[Summary of Invention] [0007]
The present invention aims to provide a system for accelerating the ageing of interconnections used for interconnecting power semiconductors.
[0008]
To that end, the present invention concerns a system for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the system comprises:
- a piezoelectric material,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material,
- means for applying an electric field between the top and the bottom of the piezoelectric material using a first electrode disposed on the top of the piezoelectric material and a second electrode disposed on the bottom of the piezoelectric material. Since the electrodes will not be tested for ageing, they must be more reliable compared to the interconnections used for interconnecting power semiconductors. To achieve it:
- means for measuring the behaviour of the least one interconnection used for interconnecting power semiconductors.
[0009]
Thus, the interconnection(s) can be subjected to an ageing process by electromechanical dilatation using a cyclic electric field instead of using power cycling tests that are energy consuming and present high cost.
[0010]
According to a particular feature, the interconnection used for interconnecting power semiconductors is composed of a metallization on which a wire or a foil or a ribbon is bonded.
[0011]
Thus, it is possible to replicate the wire/foil/ribbon-metallization structure found in standard power devices, and therefore to generate similar interface stress profile. Moreover, the metallization allows to apply a uniform electric field within the piezoelectric material.
[0012]
According to a particular feature, it further comprises a third electrode that is connected to the wire or the foil or the ribbon and means for monitoring the resistance between the first and third electrodes.
[0013]
Thus, the third electrode allows an on-line measurement of the interconnection resistance that is correlated to the degradation level of the contact between the wire/foil/ribbon and the metallization.
[0014]
According to a particular feature, the interconnection used for interconnecting power semiconductors is a solder or a sintering joint.
[0015]
Thus, standard solders (Sn-Ag-Cu alloys) or advanced die attaches based on sintering can be tested to measure their reliability, since they are considered as critical regions in standard power devices.
[0016]
According to a particular feature, it further comprises a third electrode that is connected to the solder or the sintering joint and means for monitoring the resistance between the second and third electrodes.
[0017]
Thus, it allows to monitor the degradation of the solder or the sintering joint based on the resistance as an electrical indicator.
[0018]
According to a particular feature, the system comprises two interconnections used for interconnecting power semiconductors. A first interconnection located on the top of the piezoelectric element is composed of a metallization on which a wire or a foil or a ribbon is bonded and a second interconnection located on the bottom of the piezoelectric element is a solder or a sintering joint.
[0019]
Thus, it is possible to conduct an ageing test for both critical interconnections in power devices at the same time, i.e. top and bottom interconnections. Here, it is possible to study under which conditions one of the interconnections is more prone to degradation and failure (or lifetime limited) than the other.
[0020]
According to a particular feature, the system comprises:
- at least two piezoelectric materials having the same properties,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric materials,
- means for applying an electric field between the top and the bottom of each piezoelectric material separately, the electric field being different of the electric field applied between the top and the bottom of at least one other piezoelectric material,
- means for measuring the behaviour of the least one interconnection used for interconnecting power semiconductors.
[0021]
According to a particular feature, no electric field is applied between the first and second electrodes of one piezoelectric material during a given time and the first and second electrodes are used for measuring the voltage across said piezoelectric material in order to estimate the local effective strain during the given time.
[0022]
Thus, it is possible to control fully the strain-stress profile generated over the surface of the piezoelectric material. Therefore, a specific ageing profile can be applied to test the targeted interconnection(s).
[0023]
According to a particular feature, the system comprises:
- at least two piezoelectric materials having different properties,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric materials,
- means for applying an electric field between the top and the bottom of each piezoelectric material using one electrode disposed on the top of the piezoelectric materials and the electrode disposed on the bottom of the piezoelectric materials,
- means for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[0024]
According to a particular feature, the system is further mounted on a ceramic base plate.
[0025]
Thus, it would be possible to reproduce the same multi-layered stack that can be found in standard power devices and modules. In addition, the ceramic offers an electrical isolation and a mechanical stability.
[0026]
The present invention concerns also a method for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the method comprises the steps of:
- disposing one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of a piezoelectric material,
- applying an electric field between the top and the bottom of the piezoelectric material using a first electrode disposed on the top of the piezoelectric material and a second electrode disposed on the bottom of the piezoelectric material,
- measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[0027]
Thus, the interconnect! on(s) can be subjected to an ageing process by electromechanical dilatation using a cyclic electric field instead of using power cycling tests that are energy consuming and present high cost.
[0028]
According to a particular feature, the method further comprises the steps of:
- coating, prior applying the electrical field, in a resin the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of a piezoelectric material and the piezoelectric material,
- cutting, prior applying the electrical field, on a vertical axis the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material and the piezoelectric material,
- removing the resin prior applying the electrical field, and the measuring of the behaviour of the at least one interconnection used for interconnecting power semiconductors is performed using a Digital Image Correlation method, Scanning Acoustic Microscopy or crystallography.
[0029]
Thus, this technique allows a close monitoring of crack propagation in the interconnections from one side based on a cross-section that preserves its electrical functionality. Crack conditions might be monitored using for example a Digital Image Correlation (DIC) method, Scanning Acoustic Microscopy (SAM) or crystallography to analyse the microstructure change with the ageing process.
[Brief Description of Drawings]
[0030]
The characteristics of the invention will emerge more clearly from a reading of the following description of example embodiments, the said description being produced with reference to the accompanying drawings.
[0031]
[Fig- 1]
Figure 1 represents a first example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Fig- 2]
Figure 2 represents a second example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Fig-3]
Figure 3 represents a third example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Fig- 4] Figure 4 represents a fourth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Fig. 5]
Figure 5 represents a fifth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Fig. 6]
Figure 6 represents a sixth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Fig. 7]
Figure 7 represents a device that is able to execute the method disclosed in reference of Fig. 8.
[Fig. 8]
Figure 8 represents an example of an algorithm for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Fig. 9]
Figure 9 represent an example of views of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors provided by the algorithm of Fig. 8.
[Fig. 10]
Figure 10 represent an example of views of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors provided by the algorithm of Fig. 8.
[Fig- Ill
Figure 11 represents a seventh example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Fig. 12]
Figure 12 represents an eighth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[Description of Embodiments] [0032]
Fig. 1 represents a first example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0033]
The system comprises a piezoelectric material 10a, an interconnection 13a used for interconnecting power semiconductors located on the bottom of the piezoelectric material 10a. The interconnection 13a used for interconnecting power semiconductors is a solder or a sintered joint.
[0034]
In one example of implementation, the interconnection 13a is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
[0035]
The system comprises a first electrode 11a disposed on the top of the piezoelectric material 10a and a second electrode 12a disposed on the bottom of the piezoelectric material 10a that are used for applying an electric field between the top and the bottom of the piezoelectric material 10 a.
[0036]
In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0037]
The electric field is for example a square, triangular sinusoidal or a sawtooth waveform.
[0038]
The electric field may be also a time dependent profile which reproduces complex mechanical loading.
[0039]
Fig. 2 represents a second example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0040]
The system comprises a piezoelectric material 10b, an interconnection used for interconnecting power semiconductors located on the top of the piezoelectric material 10b. The interconnection used for interconnecting power semiconductors is composed of a metallization 14b on which a wire or a foil or a ribbon 15b is bonded. [0041]
The interconnection is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm. The wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm.
[0042]
The system comprises a first electrode l ib disposed on the top of the metallization 14b and a second electrode 12b disposed on the bottom of the piezoelectric material 10b that are used for applying an electric field between the top and the bottom of the piezoelectric material 10b.
[0043]
In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may be also be spring-loaded in order to provide a reliable contact with the piezoelectric material. [0044]
The electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
[0045]
The electric field may be also a time dependent profile which reproduces complex mechanical loading.
[0046]
Fig. 3 represents a third example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0047]
The system comprises a piezoelectric material 10c and two interconnections 13c and 15b used for interconnecting power semiconductors.
[0048]
The interconnection 13c is used for interconnecting power semiconductors located on the bottom of the piezoelectric material 10c. The interconnection 13c used for interconnecting power semiconductors is a solder or a sintering joint.
[0049]
The interconnection 13c is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
[0050]
The system comprises a first electrode 11c disposed on the top of the piezoelectric material 10c and a second electrode 12c disposed on the bottom of the piezoelectric material 10c that are used for applying an electric field between the top and the bottom of the piezoelectric material 10c.
[0051]
In order to improve the reliability of the first, second and third electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0052]
The electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
[0053]
The electric field may be also a time dependent profile which reproduces complex mechanical loading.
[0054]
The interconnection used for interconnecting power semiconductors is composed of a metallization 14c on which a wire or a foil or a ribbon 15c is bonded and is disposed on the top of the piezoelectric material 10c.
[0055]
The interconnection 15c is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm. The wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm. [0056]
Fig. 4 represents a fourth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0057]
The system comprises a piezoelectric material lOd, an interconnection 13d used for interconnecting power semiconductors located on the bottom of the piezoelectric material lOd. The interconnection 13d used for interconnecting power semiconductors is a solder or a sintering joint.
[0058]
The interconnection 13d is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
[0059]
The system comprises a first electrode l id disposed on the top of the piezoelectric material lOd and a second electrode 12d disposed on the bottom of the piezoelectric material 1 Od that are used for applying an electric field between the top and the bottom of the piezoelectric material lOd.
[0060] In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0061]
The electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
[0062]
The electric field may also be a time dependent profile which reproduces complex mechanical loading.
[0063]
The system further comprises a ceramic base plate (16d) on which the second electrode 12d is mounted. The baseplate is made of Alumina (A1203)- or Aluminium Nitride (AlN)-based ceramic with a thickness higher than 700 um. [0064]
The ceramic baseplate is used to provide a mechanical stability for the assembly during the fatigue test, it reproduces more accurately the structure of a power module, and thus, the strain/stress is also more realistically reproduced on the wire and/or the solder/sintered layer.
[0065]
It has to be noted here that the ceramic baseplate may be replaced by a direct bonded copper ( DBC) substrate.
[0066]
Fig. 5 represents a fifth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[0067]
The system comprises a piezoelectric material lOe, an interconnection 13e used for interconnecting power semiconductors located on the bottom of the piezoelectric material lOe. The interconnection 13e used for interconnecting power semiconductors is a solder or a sintering joint.
[0068]
The interconnection 13e is a conductive joint including at least a Sn-Ag-Cu (SAC) alloy with a thickness comprised between 10 pm and 500 pm.
[0069]
The system comprises a first electrode l ie disposed on the top of the piezoelectric material lOe, a second electrode 12e disposed on the bottom of the piezoelectric material 1 Oe that are used for applying an electric field between the top and the bottom of the piezoelectric material 1 Oe.
[0070]
In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0071]
The electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
[0072]
The electric field may be also a time dependent profile which reproduces complex mechanical loading.
[0073]
The system further comprises a third electrode 17e that is connected to the solder or the sintering joint and means 18e for monitoring the resistance between the second and third electrodes.
[0074]
Fig. 6 represents a sixth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[0075]
The system comprises a piezoelectric material lOf, an interconnection 13f used for interconnecting power semiconductors located on the top of the piezoelectric material lOf. The interconnection used for interconnecting power semiconductors is composed of a metallization 14f on which a wire or a foil or a ribbon 15f is bonded.
[0076]
The interconnection is for example composed of a cylindrical aluminium wire with a diameter comprised between 50 pm and 800 pm. The wire is bonded onto the metallization that is made of aluminium with a thickness less than 10 pm.
[0077]
The system comprises a first electrode I lf disposed on the top of the metallization 14b and a second electrode 12f disposed on the bottom of the piezoelectric material 1 Of that are used for applying an electric field between the top and the bottom of the piezoelectric material lOf.
[0078] In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0079]
The electric field is for example a square, triangular, sinusoidal or a sawtooth waveform.
[0080]
The electric field may be also a time dependent profile which reproduces complex mechanical loading.
[0081]
The system further comprises a third electrode 19f that is connected to the wire or the foil or the ribbon 15f and means 18f for monitoring the resistance between the first and third electrodes.
[0082]
Fig. 7 represents a device that is able to execute the method disclosed in reference of Fig. 8.
[0083]
The device 100 has, for example, an architecture based on components connected together by a bus 701 and a processor 700 controlled by a program. [0084]
The bus 701 links the processor 700 to a read only memory ROM 702, a random access memory RAM 703, and an input output I/O interface I/F 705.
[0085]
The memory 703 contains registers intended to receive variables and the instructions of the program related to the algorithm disclosed in Fig. 8.
[0086]
The read-only memory, or possibly a flash memory 702, contains instructions of the program related to the algorithm disclosed in Fig. 8.
[0087]
When the device 100 is powered on, the instructions stored in the memory 702 are transferred to the random access memory 703.
[0088]
In other words, the device 100 includes circuitry enabling the estimation module 107 to perform the program as disclosed in Fig. 8.
[0089]
Fig. 8 represents an example of an algorithm for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention and for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[0090]
At step S80, the device 100 commands through the input output I/O interface I/F 705 the disposing of two interconnections used for interconnecting power semiconductors located on the tops 14g and 15g and on the bottom 13g of the piezoelectric material 1 Og.
[0091]
At step S 81, the device 100 commands through the input output I/O interface I/F the coating in a resin of the interconnections 13g and 15g used for interconnecting power semiconductors located on the top and the bottom of a piezoelectric material and the piezoelectric material lOg as shown in Fig. 9.
[0092]
At step S82, the device 100 commands through the input output I/O interface I/F to perform a micro-section of the interconnection used for interconnecting power semiconductors as disclosed in Fig. 10. For that, the device 100 commands through the input output I/O interface I/F to cut on a vertical axis the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material and the piezoelectric material. At the same step, the device 100 commands through the input output I/O interface I/F the removing of the resin using, for example, dedicated chemicals.
[0093]
At step S83, the device 100 commands through the input output I/O interface I/F the applying, during a predetermined period, of an electric field between the top and the bottom of the piezoelectric material using a first electrode 1 lg disposed on the top of the piezoelectric material and a second electrode 12g disposed on the bottom of the piezoelectric material lOg.
[0094]
At step S84, the device 100 commands through the input output I/O interface I/F a Digital Image Correlation system and/or a Scanning Acoustic Microscopy system or crystallography analysis system in order to measure the behaviour of the least one interconnection used for interconnecting power semiconductors.
[0095]
Fig. 11 represents a seventh example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0096]
The system comprises plural piezoelectric materials lOh, 10h’, lOh” and lOh’”, one interconnection used for interconnecting power semiconductors located on the top of the piezoelectric materials lOh, 10h’, lOh” and 10h”\ The piezoelectric materials have the same piezoelectric property. The interconnection used for interconnecting power semiconductors is composed of metallization 14h, 14h’, 14h” and 14h’” on which a wire or a foil or a ribbon 15h is bonded.
[0097]
The system comprises for each piezoelectric material a first electrode l lh, 1 lh’, 1 lh” and l lh’” disposed on the top of the metallization 14h, 14h’, 14h” and 14h’” and a second electrode 12h disposed on the bottom of the piezoelectric material lOh that are used for applying an electric field between the top and the bottom of the piezoelectric materials lOh, 10h’, lOh” and 10h”\
[0098]
In order to improve the reliability of the electrodes, each electrode metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The electrodes may also be spring-loaded in order to provide a reliable contact with the piezoelectric material.
[0099]
In the example of Fig. 11, the electric field between the top and the bottom of each piezoelectric material is different of the electric field applied between the top and the bottom of at least one other piezoelectric materials.
[0100]
It has to be noted here that, in a particular mode of realization, no electric field is applied between the first and second electrodes of one piezoelectric material during a given time and the first and second electrodes are used for measuring the voltage across said piezoelectric material in order to estimate the local effective strain during the given time.
[0101]
Fig. 12 represents an eighth example of a system for accelerating the ageing of interconnections used for interconnecting power semiconductors according to the present invention.
[0102]
The system comprises plural piezoelectric materials lOi, 10i’, lOi” and lOi’”, one interconnection used for interconnecting power semiconductors located on the top of the piezoelectric materials lOh, 10h’, 1 Oh” and 10h”\ The piezoelectric materials have different piezoelectric properties. The interconnection used for interconnecting power semiconductors is composed of a metallization on which a wire or a foil or a ribbon 15i is bonded.
[0103] The system comprises for the piezoelectric materials a first electrode l li disposed on the top of the metallization and a second electrode 12i disposed on the bottom of the piezoelectric material lOi that are used for applying an electric field between the top and the bottom of the piezoelectric materials lOi, 10i’, lOi” and 10i”\
[0104]
In order to improve the reliability of the first and second electrodes, the electrodes metallization can be designed using a specific material (Nickel, Silver ...etc.), thickness and/or pattern. The first and second electrodes may also be spring- loaded in order to provide a reliable contact with the piezoelectric material.
[0105]
In the example of Fig. 12, the electric field between the top and the bottom of each piezoelectric material is the same as the electric field applied between the top and the bottom of the other piezoelectric materials.
[0106]
Naturally, many modifications can be made to the embodiments of the invention described above without departing from the scope of the present invention.

Claims

[CLAIMS]
[Claim 1]
A system for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the system comprises:
- a piezoelectric material,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material,
- means for applying an electric field between the top and the bottom of the piezoelectric material using a first electrode disposed on the top of the piezoelectric material and a second electrode disposed on the bottom of the piezoelectric material,
- means for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Claim 2]
The system according to claim 1, characterized in that the interconnection used for interconnecting power semiconductors is composed of a metallization layer on which a wire or a foil or a ribbon is bonded.
[Claim 3]
The system according to claim 2, characterized in that it further comprises a third electrode that is connected to the wire or the foil or the ribbon and means for monitoring the resistance between the first and third electrodes.
[Claim 4]
The system according to claim 1, characterized in that the interconnection used for interconnecting power semiconductors is a solder or a sintered joint.
[Claim 5]
The system according to claim 4, characterized in that it further comprises a third electrode that is connected to the solder or the sintered joint and means for monitoring the resistance between the second and third electrodes.
[Claim 6]
The system according to claim 1 , characterized in that the system comprises two interconnections used for interconnecting power semiconductors, a first interconnection located on the top of the piezoelectric element is composed of a metallization on which a wire or a foil or a ribbon is bonded and a second interconnection located on the bottom of the piezoelectric element is a solder or a sintered joint.
[Claim 7]
The system according to claim 1, characterized in that the system comprises:
- at least two piezoelectric materials having the same properties,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric materials,
- means for applying an electric field between the top and the bottom of each piezoelectric material, the electric field being different of the electric field applied between the top and the bottom of the at least one other piezoelectric material,
- means for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Claim 8]
The system according to claim 7, characterized in that no electric field is applied between the first and second electrodes of one piezoelectric material during a given time and the first and second electrodes are used for measuring the voltage across said piezoelectric material in order to estimate the local effective strain during the given time.
[Claim 9]
The system according to claim 1, characterized in that the system comprises:
- at least two piezoelectric materials having different properties,
- at least one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric materials,
- means for applying an electric field between the top and the bottom of each piezoelectric material using one electrode disposed on the top of the piezoelectric materials and one electrode disposed on the bottom of the piezoelectric materials,
- means for measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Claim 10]
The system according to any of the claim's 1 to 4, characterized in that the system is further mounted on a ceramic base plate.
[Claim 11]
A method for accelerating the ageing of interconnections used for interconnecting power semiconductors, characterized in that the method comprises the steps of:
- disposing one interconnection used for interconnecting power semiconductors located on the top and/or the bottom of a piezoelectric material,
- applying an electric field between the top and the bottom of the piezoelectric material using a first electrode disposed on the top of the piezoelectric material and a second electrode disposed on the bottom of the piezoelectric material,
- measuring the behaviour of the at least one interconnection used for interconnecting power semiconductors.
[Claim 12]
The method according to claim 11 , characterized in that the method further comprises the steps of:
- coating, prior applying the electrical field, in a resin the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of a piezoelectric material and the piezoelectric material,
- cutting, prior applying the electrical field, on a vertical axis the interconnection used for interconnecting power semiconductors located on the top and/or the bottom of the piezoelectric material and the piezoelectric material,
- removing the resin prior applying the electrical field, and the measuring a Digital Image Correlation system and/or a Scanning Acoustic Microscopy system or crystallography analysis system.
PCT/JP2021/002118 2020-03-26 2021-01-15 System and method for accelerating ageing of interconnections used for interconnecting power semiconductors Ceased WO2021192562A1 (en)

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