WO2021143180A1 - 半导体器件及半导体器件的制备方法 - Google Patents

半导体器件及半导体器件的制备方法 Download PDF

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WO2021143180A1
WO2021143180A1 PCT/CN2020/115805 CN2020115805W WO2021143180A1 WO 2021143180 A1 WO2021143180 A1 WO 2021143180A1 CN 2020115805 W CN2020115805 W CN 2020115805W WO 2021143180 A1 WO2021143180 A1 WO 2021143180A1
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window
dielectric layer
barrier layer
layer
semiconductor device
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PCT/CN2020/115805
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English (en)
French (fr)
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吴秉桓
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长鑫存储技术有限公司
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Priority to US17/435,967 priority Critical patent/US12027418B2/en
Priority to EP20913458.4A priority patent/EP3933903B1/en
Publication of WO2021143180A1 publication Critical patent/WO2021143180A1/zh

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    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof.
  • Integrated circuits include many interconnected structures, and the materials of these interconnected structures are often prone to diffusion.
  • the invention provides a semiconductor device and a preparation method thereof.
  • the present invention provides a method for manufacturing a semiconductor device, including: providing a first dielectric layer; forming a first window in the first dielectric layer; forming a first connecting structure in the first window; A second dielectric layer is formed on the dielectric layer, the second dielectric layer has a second window, and the second window at least exposes the first communication structure; and a first barrier is formed on the sidewall and bottom of the second window
  • the first barrier layer includes an opening that exposes a portion of the first communication structure; and a second communication structure is formed in the second window.
  • the present invention also provides a semiconductor device, including: a first dielectric layer with a first window in the first dielectric layer; a first connecting structure located in the first window; and a second dielectric layer located in the first window.
  • the second dielectric layer On a dielectric layer, the second dielectric layer has a second window that at least exposes the first communication structure; and a first barrier layer located on the sidewall and bottom of the second window, the The first barrier layer includes an opening that exposes a portion of the first communication structure; and the second communication structure is located in the second window.
  • FIG. 1 is a flow chart of the method for manufacturing the semiconductor device of the present invention.
  • FIG. 10 is also a schematic diagram of the structure presented by the semiconductor device of the present invention.
  • the interconnecting material diffuses into the dielectric layer, it may cause a short circuit and affect the device yield.
  • An embodiment, as shown in FIG. 1, provides a method for manufacturing a semiconductor device, including: providing a first dielectric layer 10; forming a first window 101 in the first dielectric layer 10; and forming a first window 101 in the first window 101 Connecting structure 20; forming a second dielectric layer 30 on the first dielectric layer 10, the second dielectric layer 30 has a second window 301, the second window 301 at least reveals the first connecting structure 20; on the sidewalls of the second window 301 and A first barrier layer 40 is formed at the bottom.
  • the first barrier layer 40 includes an opening 401 that exposes a part of the first communication structure 20; and a second communication structure 50 is formed in the second window 301.
  • the above-mentioned manufacturing method of the semiconductor device can not only prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30, but also improve the gap between the first connecting structure 20 and the second connecting structure 50.
  • the first barrier layer 40 is formed on the sidewall and bottom of the second window 301 to prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30.
  • the first barrier layer 40 includes the opening 401 ,
  • the opening 401 exposes part of the first communication structure 20, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication can be improved.
  • the electrical conduction efficiency between the structure 20 and the second connecting structure 50 improves the performance of the device.
  • a first dielectric layer 10 is provided.
  • the method for forming the first dielectric layer 10 includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
  • the material of the first dielectric layer 10 includes one of silicon oxide, silicon nitride, and silicon oxynitride. Or several combinations.
  • step S10 includes: providing a substrate, and forming the first dielectric layer 10 on the upper surface of the substrate.
  • step S10 the method further includes:
  • a second barrier layer 60 is formed on the surface of the first dielectric layer 10.
  • the method for forming the second barrier layer 60 includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
  • the material of the second barrier layer 60 includes silicon nitride, silicon oxynitride, silicon carbide, and carbonitride. One or several combinations of silicon and silicon oxycarbide.
  • the second barrier layer 60 is formed on the surface of the first dielectric layer 10, which can prevent the second connecting material from diffusing into the first dielectric layer 10 due to the existence of the opening 401, thereby further reducing the risk of diffusion.
  • the second barrier layer 60 can be used as an etching barrier layer when forming the second window 301 to improve the etching uniformity, and the second barrier layer 60 can be used as a polishing barrier layer when forming the first interconnection structure 20, so that redundant first interconnections are formed.
  • the material layer 201 can be removed more cleanly and can reduce scratches.
  • the method of forming the first window 101 includes dry etching or wet etching, and wet etching is easier to form the inclined sidewall 1011.
  • a first window 101 is formed in the first dielectric layer 10 and the second barrier layer 60, and the first window 101 penetrates the first dielectric layer 10 and the second barrier layer 60. At least the side wall of the upper part of the first window 101 is an inclined side wall.
  • step S20 includes:
  • S203 An etching process removes part of the first connecting material layer 201 and part of the first dielectric layer 10 to form the first window 101.
  • At least the side wall of the upper part of the first window 101 is an inclined side wall.
  • the shape of the first window 101 includes a funnel shape.
  • the shape of the first window 101 includes a funnel shape.
  • the first connecting structure 20 is formed, the first connecting material layer 201 is first filled in the first window 101, and then the excess first connecting material layer 201 is removed by a planarization process.
  • the edges of the upper surface of the first connecting structure 20 formed have edges 202, so that when the first barrier layer 40 is formed, the first barrier layer 40
  • An annular opening 401 is formed at the raised edge 202, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication can be improved.
  • the electrical conduction efficiency between the structure 20 and the second connecting structure 50 improves the performance of the device.
  • a first connecting structure 20 is formed in the first window 101.
  • the first communication structure 20 is formed in the first window 101.
  • the top of the first connecting structure 20 is higher than the upper surface of the second barrier layer 60, and the upper surface of the first connecting structure 20 and the upper surface of the second barrier layer 60 have an overlapping portion, that is, the first connecting structure 20 has an edge 202 .
  • step S30 includes:
  • S301 As shown in FIG. 5, deposit a first connected material layer 201 in the first window 101 and on the first dielectric layer 10;
  • At least the side wall of the upper part of the first window 101 is an inclined side wall, so that the boundary between the first communication structure 20 and the first dielectric layer 10 includes a raised edge 202.
  • the shape of the first window 101 is funnel-shaped, a first connected material layer 201 is formed in the first window 101 and on the first dielectric layer 10, and then a planarization process is used to remove the The first connected material layer 201 forms the first connected structure 20.
  • a planarization process is used to remove the The first connected material layer 201 forms the first connected structure 20.
  • the interface between the first connected material layer 201 and the first medium layer 10 is not vertical but a sloped slope, and the first connected The material layer 201 and the first dielectric layer 10 are made of different materials.
  • the planarization will result in the formation of the upper surface of the first connecting structure 20 with a raised edge 202, which refers to the first connecting structure 20
  • the edge of the upper surface has a protruding part, the protruding part is located above the first dielectric layer 10 and there is a gap between the protruding part and the first dielectric layer 10, and the protruding part has an overlapping area with the first dielectric layer 10.
  • the method for depositing the first connected material layer 201 includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
  • the first connected material layer 201 includes copper, aluminum, nickel, gold, silver, titanium, and tungsten.
  • the planarization process includes chemical mechanical polishing (CMP).
  • the boundary between the first connecting structure 20 and the first dielectric layer 10 includes a raised edge 202.
  • the raised edge 202 means that the upper part of the first communication structure 20 is a convex part protruding above the first dielectric layer 10, the side wall of the convex part is an inclined side wall, and the inclined side wall is relatively The inclination angle of the upper surface of the first dielectric layer 10 is less than 90°.
  • the sidewall of the first window 101 includes an inclined sidewall 1011.
  • the first connecting structure 20 includes a raised edge 202 formed at the junction of the first connecting structure 20 and the first dielectric layer 10 so that the first barrier layer 40 includes an opening 401.
  • the first connecting structure 20 includes a raised edge 202.
  • a second dielectric layer 30 is formed on the first dielectric layer 10.
  • the second dielectric layer 30 has a second window 301, and the second window 301 at least exposes the first connecting structure 20.
  • the method for forming the second dielectric layer 30 includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
  • the material of the second dielectric layer 30 includes one of silicon oxide, silicon nitride, and silicon oxynitride. Or several combinations.
  • the second dielectric layer 30 is formed on the upper surface of the second barrier layer 60.
  • the second dielectric layer 30 has a second window 301, and the second window 301 at least exposes the first connecting structure 20.
  • step S40 includes:
  • a second window 301 is formed in the second dielectric layer 30, and the second window 301 at least exposes the first connecting structure 20.
  • the second barrier layer 60 serves as an etching barrier layer when step S402 is performed to improve etching uniformity.
  • the ratio of the thickness of the removed second barrier layer 60 to the thickness of the second barrier layer 60 is between Between 10% and 60%.
  • a first barrier layer 40 is formed on the sidewall and bottom of the second window 301.
  • the first barrier layer 40 includes an opening 401, and the opening 401 exposes a part of the first connecting structure 20.
  • the method for forming the first barrier layer 40 includes chemical vapor deposition, physical vapor deposition or atomic layer deposition.
  • the material of the first barrier layer 40 includes titanium, tantalum, tungsten, titanium nitride, tantalum nitride, One or several combinations of tungsten nitride.
  • a first barrier layer 40 is formed on the upper surface of the first connecting structure 20, the exposed upper surface of the second barrier layer 60, and the sidewall of the second window 301, and the first barrier layer 40 includes an opening 401, The opening 401 exposes part of the first communication structure 20.
  • the first barrier layer 40 on the upper surface of the first connecting structure 20 and the first barrier layer 40 on the upper surface of the second barrier layer 60 are not located on the same horizontal plane, and there is a gap between them, that is, an opening 401.
  • the shape of the opening 401 includes a ring shape, and the opening 401 is located at the junction of the first communication structure 20 and the first dielectric layer 10.
  • the opening 401 is located at the junction of the first communication structure 20 and the second barrier layer 60.
  • the method for forming the second connecting structure 50 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the material of the second connecting structure 50 includes copper, aluminum, nickel, gold, silver, titanium, and tungsten.
  • the material of the second connecting structure 50 is copper.
  • step S60 includes:
  • S602 Use a planarization process to remove the second connecting material on the surface of the second barrier layer 60 to form a second connecting structure 50.
  • the boundary between the first connecting structure 20 and the first dielectric layer 10 includes a raised edge 202.
  • the raised edge 202 means that the upper part of the first communication structure 20 is a convex part protruding above the first dielectric layer 10, the side wall of the convex part is an inclined side wall, and the inclined side wall is relatively The inclination angle of the upper surface of the first dielectric layer 10 is less than 90°.
  • the sidewall of the first window 101 includes an inclined sidewall 1011.
  • the first connecting structure 20 formed has an edge 202, so that when the first barrier layer 40 is formed, the first barrier layer 40 There is an opening 401 at the rising edge 202, and the inclined side wall 1011 does not have the first barrier layer 40, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the first communication structure 20 and the second communication structure can be directly contacted.
  • the resistance between 50 is reduced, and the electrical conduction efficiency between the first communication structure 20 and the second communication structure 50 can be improved, and the performance of the device can be improved.
  • the shape of the first window 101 is funnel-shaped, a first connected material layer 201 is formed in the first window 101 and on the first dielectric layer 10, and then a planarization process is used to remove the The first connected material layer 201 forms the first connected structure 20.
  • a planarization process is used to remove the The first connected material layer 201 forms the first connected structure 20.
  • the interface between the first connected material layer 201 and the first medium layer 10 is not vertical but a sloped slope, and the first connected The material layer 201 and the first dielectric layer 10 are made of different materials.
  • the planarization will result in the formation of the upper surface of the first connecting structure 20 with a raised edge 202, which refers to the first connecting structure 20
  • the edge of the upper surface has a protruding part, the protruding part is located above the first dielectric layer 10 and there is a gap between the protruding part and the first dielectric layer 10, and the protruding part has an overlapping area with the first dielectric layer 10;
  • a second dielectric layer 30 is formed on the layer 10, and the second dielectric layer 30 has a second window 301; and then the first barrier layer 40 is deposited.
  • the protruding part has a height with the first dielectric layer 10
  • the upper surface of the protruding part and the upper surface of the first dielectric layer 10 have the first barrier layer 40, but there is no first barrier layer 40 on the first dielectric layer 10 directly under the protruding part.
  • the protruding part of the first communication structure 20 is exposed to the outside; then, a second communication structure 50 is formed in the second window 301.
  • the second communication structure 50 can directly contact the first communication structure 20, which can reduce the first communication structure.
  • the resistance between the connecting structure 20 and the second connecting structure 50 improves the electrical conduction efficiency and improves the performance of the device.
  • forming the first barrier layer 40 on the sidewall and bottom of the second window 301 can prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30.
  • the first barrier layer 40 includes openings. 401.
  • the opening 401 exposes the first communication structure 20, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication can be improved.
  • the electrical conduction efficiency between the structure 20 and the second connecting structure 50 improves the performance of the device.
  • the first barrier layer 40 does not form an opening 401 but has a thin layer area. At this time, the resistance between the first communication structure 20 and the second communication structure 50 can also be reduced, and the first communication structure can be improved. The efficiency of electrical conduction between 20 and the second connecting structure 50 improves the performance of the device.
  • This thin layer area also belongs to the opening 401, and this solution also belongs to the protection scope of the present invention.
  • the second connecting material is prone to diffusion. If the second connecting material diffuses into the first dielectric layer 10 and the second dielectric layer 30, it may cause a short circuit and affect the performance of the device.
  • the first barrier layer 40 can avoid the first The second connecting material diffuses into the first dielectric layer 10 and the second dielectric layer 30, but the first barrier layer 40 can increase the contact resistance of the first connecting structure 20 and the second connecting structure 50, and the opening 401 can make the first connecting structure 20 Direct contact with the second communication structure 50 can solve the above-mentioned problems, reduce the resistance between the first communication structure 20 and the second communication structure 50, and improve the electrical conduction efficiency between the first communication structure 20 and the second communication structure 50, Improve device performance.
  • step S60 the method further includes:
  • a third barrier layer 70 is formed on the second connecting structure 50.
  • the method for forming the third barrier layer 70 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the material of the third barrier layer 70 includes silicon nitride, silicon oxynitride, silicon carbide, and carbonitride. One or several combinations of silicon and silicon oxycarbide.
  • An embodiment, as shown in FIG. 10, provides a semiconductor device, including: a first dielectric layer 10 having a first window 101 in the first dielectric layer 10; a first connecting structure 20 located in the first window 101; The second dielectric layer 30 is located on the first dielectric layer 10, the second dielectric layer 30 has a second window 301, and the second window 301 at least exposes the first communication structure 20; the first barrier layer 40 is located on the sidewall of the second window 301 And at the bottom, the first barrier layer 40 includes an opening 401 that exposes the first communication structure 20; the second communication structure 50 is located in the second window 301.
  • the above-mentioned semiconductor device can not only prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30, but also improve the electrical conduction between the first connecting structure 20 and the second connecting structure 50.
  • the first barrier layer 40 located on the sidewall and bottom of the second window 301 can prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30.
  • the first barrier layer 40 includes an opening 401, and the opening 401 is exposed
  • the first connecting structure 20 enables the first connecting structure 20 and the second connecting structure 50 to directly contact, so that the resistance between the first connecting structure 20 and the second connecting structure 50 is reduced, and the first connecting structure 20 and the second connecting structure 20 can be improved.
  • the electrical conduction efficiency between the connecting structures 50 improves the performance of the device.
  • the material of the first dielectric layer 10 includes one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the second barrier layer 60 includes one or a combination of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbide.
  • it further includes: a second barrier layer 60 located on the surface of the first dielectric layer 10, the upper surface of the second barrier layer 60 is lower than the top of the first communication structure 20; the first window 101 It penetrates the second barrier layer 60 and the first dielectric layer 10.
  • the second barrier layer 60 is located on the surface of the first dielectric layer 10, which can prevent the second connecting material from diffusing into the first dielectric layer 10 due to the existence of the opening 401, and further reduce the risk of diffusion.
  • the second barrier layer 60 can be used as The etching barrier layer when forming the second window 301 improves the etching uniformity.
  • the second barrier layer 60 can be used as a polishing barrier layer when forming the first connecting structure 20, so that the excess first connecting material layer 201 can be removed more cleanly. And can reduce scratches.
  • At least the side wall of the upper part of the first window 101 is an inclined side wall, so that the boundary between the first communication structure 20 and the first dielectric layer 10 includes a raised edge 202.
  • the sidewall of the first window 101 includes an inclined sidewall 1011.
  • the first connecting structure 20 formed has an edge 202, so that when the first barrier layer 40 is formed, the first barrier layer 40
  • the opening 401 is formed at the edge 202, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication structure can be improved.
  • the efficiency of electrical conduction between 20 and the second connecting structure 50 improves the performance of the device.
  • the shape of the first window 101 includes a funnel shape.
  • the shape of the first window 101 includes a funnel shape.
  • the first connecting structure 20 is formed, the first connecting material layer 201 is first filled in the first window 101, and then the excess first connecting material layer 201 is removed by a planarization process.
  • the edges of the upper surface of the first connecting structure 20 formed have edges 202, so that when the first barrier layer 40 is formed, the first barrier layer 40
  • An annular opening 401 is formed at the raised edge 202, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication can be improved.
  • the electrical conduction efficiency between the structure 20 and the second connecting structure 50 improves the performance of the device.
  • the first connecting material layer 201 includes one or a combination of copper, aluminum, nickel, gold, silver, titanium, and tungsten.
  • the first connecting structure 20 includes a raised edge 202 located at the junction of the first connecting structure 20 and the first dielectric layer 10, so that the first barrier layer 40 includes an opening 401.
  • the first connecting structure 20 includes a raised edge 202, so that when the first barrier layer 40 is formed, the first barrier layer 40 forms an opening 401 at the raised edge 202, so that the first connecting structure 20 and the second connecting structure 50 can directly contact.
  • the resistance between the first communication structure 20 and the second communication structure 50 is reduced, the electrical conduction efficiency between the first communication structure 20 and the second communication structure 50 can be improved, and the device performance can be improved.
  • the boundary between the first connecting structure 20 and the first dielectric layer 10 includes a raised edge 202.
  • the rising edge 202 means that the upper part of the first communication structure 20 is a convex part protruding above the first dielectric layer 10, the side wall of the convex part is an inclined side wall, and the inclined side wall is relatively The inclination angle of the upper surface of the first dielectric layer 10 is less than 90°.
  • the material of the second dielectric layer 30 includes one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the first barrier layer 40 includes one or a combination of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, and tungsten nitride.
  • forming the first barrier layer 40 on the sidewall and bottom of the second window 301 can prevent the second connecting material from diffusing into the first dielectric layer 10 and the second dielectric layer 30.
  • the first barrier layer 40 includes openings. 401.
  • the opening 401 exposes the first communication structure 20, so that the first communication structure 20 and the second communication structure 50 can directly contact, so that the resistance between the first communication structure 20 and the second communication structure 50 is reduced, and the first communication can be improved.
  • the electrical conduction efficiency between the structure 20 and the second connecting structure 50 improves the performance of the device.
  • the shape of the opening 401 includes a ring shape, and the opening 401 is located at the junction of the first communication structure 20 and the first dielectric layer 10.
  • the first barrier layer 40 does not form an opening 401 but has a thin layer area. At this time, the resistance between the first communication structure 20 and the second communication structure 50 can also be reduced, and the first communication structure can be improved. The efficiency of electrical conduction between 20 and the second connecting structure 50 improves the performance of the device.
  • This thin layer area also belongs to the opening 401, and this solution also belongs to the protection scope of the present invention.
  • the second connecting material is prone to diffusion. If the second connecting material diffuses into the first dielectric layer 10 and the second dielectric layer 30, it may cause a short circuit and affect the performance of the device.
  • the first barrier layer 40 can avoid the first The second connecting material diffuses into the first dielectric layer 10 and the second dielectric layer 30, but the first barrier layer 40 can increase the contact resistance of the first connecting structure 20 and the second connecting structure 50, and the opening 401 can make the first connecting structure 20 Direct contact with the second communication structure 50 can solve the above-mentioned problems, reduce the resistance between the first communication structure 20 and the second communication structure 50, and improve the electrical conduction efficiency between the first communication structure 20 and the second communication structure 50, Improve device performance.
  • the material of the second connecting structure 50 includes one or a combination of copper, aluminum, nickel, gold, silver, titanium, and tungsten.
  • the material of the second connecting structure 50 is copper.
  • it further includes: a third barrier layer 70 located on the second connecting structure 50.
  • the material of the third barrier layer 70 includes one or a combination of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbide.
  • the first communication structure 20 and the second barrier layer 60 have overlapping portions.
  • the first barrier layer 40 is located on the upper surface of the first communication structure 20, part of the upper surface of the second barrier layer 60 at the bottom of the second window 301, and the sidewall of the second window 301, and the first communication structure 20
  • the bottom of the first barrier layer 40 on the upper surface is higher than the top of the first barrier layer 40 on the upper surface of the second barrier layer 60.
  • the upper surface of the second barrier layer 60 in the second window 301 has a recess, and the depth of the recess accounts for a ratio of 10% to 60% of the thickness of the second barrier layer 60.

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Abstract

一种半导体器件及其制备方法，半导体器件的制备方法包括：提供第一介质层（10）；于第一介质层内形成第一窗口（101）；于第一窗口内形成第一连通结构（20）；于第一介质层上形成第二介质层（30），第二介质层具有第二窗口（301），第二窗口至少显露第一连通结构；于第二窗口的侧壁及底部形成第一阻挡层（40），第一阻挡层包括开口，开口显露部分第一连通结构；于第二窗口内形成第二连通结构（50）。这种半导体器件的制备方法不仅能避免第二连通材料扩散到第一介质层和第二介质层中，而且能提高第一连通结构与第二连通结构之间的电传导效率，提高器件性能。

Description

半导体器件及半导体器件的制备方法
相关申请交叉引用
本申请要求2020年01月17日递交的、标题为“半导体器件及其制备方法”、申请号为2020100527725的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及半导体制造领域，特别是涉及一种半导体器件及其制备方法。
背景技术
集成电路中包括很多连通结构，这些连通结构的材料往往容易发生扩散。
发明内容
本发明提供一种半导体器件及其制备方法。
本发明提供一种半导体器件的制备方法，包括：提供第一介质层；于所述第一介质层内形成第一窗口；于所述第一窗口内形成第一连通结构；于所述第一介质层上形成第二介质层，所述第二介质层具有第二窗口，所述第二窗口至少显露所述第一连通结构；以及于所述第二窗口的侧壁及底部形成第一阻挡层，所述第一阻挡层包括开口，所述开口显露部分所述第一连通结构；于所述第二窗口内形成第二连通结构。
本发明还提供一种半导体器件，包括：第一介质层，所述第一介质层内具有第一窗口；第一连通结构，位于所述第一窗口内；第二介质层，位于所述第一介质层上，所述第二介质层具有第二窗口，所述第二窗口至少显露所述第一连通结构；以及第一阻挡层，位于所述第二窗口的侧壁及底部，所述第一阻挡层包括开口，所述开口显露部分所述第一连通结构；第二连通结构，位于所述第二窗口内。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明的半导体器件的制备方法的流程图。
图2～图10为本发明的半导体器件的制备方法各步骤所呈现的结构示意图；其中图10亦为本发明的半导体器件所呈现的结构示意图。
图中：10-第一介质层；101-第一窗口；1011-倾斜侧壁；20-第一连通结构；201-第一连通材料层；202-起边；30-第二介质层；301-第二窗口；40-第一阻挡层；401-开口；50-第二连通结构；60-第二阻挡层；70-第三阻挡层。
具体实施方式
如背景技术部分所述，如果连通材料扩散到介质层中就有可能导致短路，影响器件良率。
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
一个实施例，如图1所示，提供一种半导体器件的制备方法，包括：提 供第一介质层10；于第一介质层10内形成第一窗口101；于第一窗口101内形成第一连通结构20；于第一介质层10上形成第二介质层30，第二介质层30具有第二窗口301，第二窗口301至少显露第一连通结构20；于第二窗口301的侧壁及底部形成第一阻挡层40，第一阻挡层40包括开口401，开口401显露部分第一连通结构20；于第二窗口301内形成第二连通结构50。
在本实施例中，上述半导体器件的制备方法不仅能避免第二连通材料扩散到第一介质层10和第二介质层30中，而且能提高第一连通结构20与第二连通结构50之间的电传导效率，于第二窗口301的侧壁及底部形成第一阻挡层40能避免第二连通材料扩散到第一介质层10和第二介质层30中，第一阻挡层40包括开口401，开口401显露部分第一连通结构20，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
S10：如图2所示，提供第一介质层10。
在本实施例中，形成第一介质层10的方法包括物理气相沉积、化学气相沉积或原子层沉积工艺，第一介质层10的材质包括氧化硅、氮化硅、氮氧化硅中的一种或几种组合。
在一个实施例中，步骤S10包括：提供一基底，于基底的上表面形成第一介质层10。
在一个实施例中，步骤S10之后，还包括：
S11：如图3所示，于第一介质层10的表面形成第二阻挡层60。
在一个实施例中，形成第二阻挡层60的方法包括物理气相沉积、化学气相沉积或原子层沉积工艺，第二阻挡层60的材质包括氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氧化硅中的一种或几种组合。
在本实施例中，于第一介质层10的表面形成第二阻挡层60，能避免由于开口401的存在导致第二连通材料扩散到第一介质层10中，进一步减小扩散的风险性，第二阻挡层60能作为形成第二窗口301时的刻蚀阻挡层，提高刻蚀均匀性，第二阻挡层60能作为形成第一连通结构20时的抛光阻挡层，使得多余的第一连通材料层201去除更干净，而且能减少刮痕。
S20：如图4所示，于第一介质层10内形成第一窗口101。
在本实施例中，形成第一窗口101的方法包括干法刻蚀或湿法刻蚀，其中湿法刻蚀更容易形成倾斜侧壁1011。
在一个实施例中，于第一介质层10和第二阻挡层60内形成第一窗口101，第一窗口101贯穿第一介质层10和第二阻挡层60。至少所述第一窗口101上部的侧壁为倾斜侧壁。
在另一个实施例中，步骤S20包括：
S201：于第一介质层10内形成通孔；
S202：于通孔内填充第一连通材料层201；
S203：刻蚀工艺去除部分所述第一连通材料层201和部分所述第一介质层10，以形成所述第一窗口101。
在一个实施例中，至少所述第一窗口101上部的侧壁为倾斜侧壁。
在一个实施例中，第一窗口101的形状包括漏斗状。第一窗口101的形状包括漏斗状，在形成第一连通结构20时，首先于第一窗口101内填充第一连通材料层201，然后通过平坦化工艺去除多余的第一连通材料层201，在进行平坦化处理时，由于第一窗口101的形状是漏斗状，使得形成的第一连通结构20的上表面边缘都具有起边202，使得在形成第一阻挡层40时，第一阻挡层40在起边202处形成环状开口401，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
S30：于第一窗口101内形成第一连通结构20。
在一个实施例中，于第一窗口101内形成第一连通结构20。第一连通结构20的顶部高于第二阻挡层60的上表面，第一连通结构20的上表面与第二阻挡层60的上表面具有重叠部分，也就是第一连通结构20具有起边202。
在一个实施例中，步骤S30包括：
S301：如图5所示，于第一窗口101内和第一介质层10上沉积第一连通材料层201；
S302：如图6所示，通过平坦化工艺去除第一介质层10上的第一连通材料层201，形成第一连通结构20。
在一个实施例中，至少所述第一窗口101上部的侧壁为倾斜侧壁，以使 所述第一连通结构20与所述第一介质层10的交界处包括起边202。
在一个实施例中，第一窗口101的形状是漏斗状，于第一窗口101内和第一介质层10上形成第一连通材料层201，然后采用平坦化工艺去除第一介质层10上的第一连通材料层201，以形成第一连通结构20，此时，由于第一连通材料层201与第一介质层10的交界面不是竖直的而是一具有坡度的斜面，而且第一连通材料层201与第一介质层10的材质不同，在这种情况下，进行平坦化会导致形成的第一连通结构20的上表面具有起边202，起边202是指第一连通结构20的上表面的边缘具有凸出部分，凸出部分位于第一介质层10的上方而且与第一介质层10之间具有间隙，凸出部分与第一介质层10具有重叠区域。
在本实施例中，沉积第一连通材料层201的方法包括物理气相沉积、化学气相沉积或原子层沉积工艺，第一连通材料层201包括铜、铝、镍、金、银、钛、钨中的一种或几种组合，平坦化工艺包括化学机械抛光(CMP)。
在本实施例中，第一连通结构20与第一介质层10的交界处包括起边202。具体地，起边202是指第一连通结构20的上部为突出于所述第一介质层10上方的凸部，所述凸部的侧壁为倾斜侧壁，且所述倾斜侧壁相较于所述第一介质层10的上表面倾斜的角度小于90°。第一窗口101的侧壁包括倾斜侧壁1011，在形成第一连通结构20时，首先于第一窗口101内填充第一连通材料层201，然后通过平坦化工艺去除多余的第一连通材料层201，在进行平坦化处理时，由于第一窗口101的侧壁具有倾斜侧壁1011，使得形成的第一连通结构20具有起边202。
在一个实施例中，第一连通结构20包括起边202，起边202形成于第一连通结构20与第一介质层10的交界处，以使第一阻挡层40包括开口401。第一连通结构20包括起边202。
S40：如图7所示，于第一介质层10上形成第二介质层30，第二介质层30具有第二窗口301，第二窗口301至少显露第一连通结构20。
在本实施例中，形成第二介质层30的方法包括物理气相沉积、化学气相沉积或原子层沉积工艺，第二介质层30的材质包括氧化硅、氮化硅、氮氧化硅中的一种或几种组合。
在一个实施例中，于第二阻挡层60的上表面形成第二介质层30，第二 介质层30具有第二窗口301，第二窗口301至少显露第一连通结构20。
在一个实施例中，步骤S40包括：
S401：于第一介质层10上形成第二介质层30；
S402：于第二介质层30内形成第二窗口301，第二窗口301至少显露第一连通结构20。
在一个实施例中，第二阻挡层60作为进行步骤S402时的刻蚀阻挡层，提高刻蚀均匀性。
在一个实施例中，于第二介质层30内形成第二窗口301时，还去除部分厚度的第二阻挡层60，去除的第二阻挡层60厚度占第二阻挡层60厚度的比例介于10％～60％之间。
S50：如图8所示，于第二窗口301的侧壁及底部形成第一阻挡层40，第一阻挡层40包括开口401，开口401显露部分第一连通结构20。
在本实施例中，形成第一阻挡层40的方法包括化学气相沉积、物理气相沉积或原子层沉积工艺，第一阻挡层40的材质包括钛、钽、钨、氮化钛、氮化钽、氮化钨中的一种或几种组合。
在一个实施例中，于第一连通结构20的上表面、暴露的第二阻挡层60的上表面和第二窗口301的侧壁形成第一阻挡层40，第一阻挡层40包括开口401，开口401显露部分第一连通结构20。第一连通结构20上表面的第一阻挡层40和第二阻挡层60上表面的第一阻挡层40不位于同一水平面上，而且它们之间具有间隙，也就是开口401。
在一个实施例中，开口401的形状包括环状，开口401位于第一连通结构20与第一介质层10的交界处。
在另一个实施例中，开口401位于第一连通结构20与第二阻挡层60的交界处。
S60：如图9所示，于第二窗口301内形成第二连通结构50。
在本实施例中，形成第二连通结构50的方法包括化学气相沉积、物理气相沉积或原子层沉积工艺，第二连通结构50的材质包括铜、铝、镍、金、银、钛、钨中的一种或几种组合，可选地，第二连通结构50的材质为铜。
在一个实施例中，步骤S60包括：
S601：于第二窗口301内和第一阻挡层40表面形成第二连通材料；
S602：采用平坦化工艺去除第二阻挡层60表面的第二连通材料，形成第二连通结构50。
在一个实施例中，第一连通结构20与第一介质层10的交界处包括起边202。具体地，起边202是指第一连通结构20的上部为突出于所述第一介质层10上方的凸部，所述凸部的侧壁为倾斜侧壁，且所述倾斜侧壁相较于所述第一介质层10的上表面倾斜的角度小于90°。第一窗口101的侧壁包括倾斜侧壁1011，在形成第一连通结构20时，首先于第一窗口101内填充第一连通材料层201，然后通过平坦化工艺去除多余的第一连通材料层201，在进行平坦化处理时，由于第一窗口101的侧壁具有倾斜侧壁1011，使得形成的第一连通结构20具有起边202，使得在形成第一阻挡层40时，第一阻挡层40在起边202处出现开口401，倾斜侧壁1011上不具有第一阻挡层40，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在一个实施例中，第一窗口101的形状是漏斗状，于第一窗口101内和第一介质层10上形成第一连通材料层201，然后采用平坦化工艺去除第一介质层10上的第一连通材料层201，以形成第一连通结构20，此时，由于第一连通材料层201与第一介质层10的交界面不是竖直的而是一具有坡度的斜面，而且第一连通材料层201与第一介质层10的材质不同，在这种情况下，进行平坦化会导致形成的第一连通结构20的上表面具有起边202，起边202是指第一连通结构20的上表面的边缘具有凸出部分，凸出部分位于第一介质层10的上方而且与第一介质层10之间具有间隙，凸出部分与第一介质层10具有重叠区域；然后于第一介质层10上形成第二介质层30，第二介质层30具有第二窗口301；然后沉积第一阻挡层40，此时，由于起边202的存在，凸出部分与第一介质层10存在高度差，此时，凸出部分的上表面和第一介质层10的上表面具有第一阻挡层40，但凸出部分正下方的第一介质层10上没有第一阻挡层40，此时，第一连通结构20凸出部分下方暴露在外；然后，于第二窗口301内形成第二连通结构50，此时，第二连通结构50与第一连通结构20能直接接触，这样能降低第一连通结构20与第二连通结构50之间的电阻，提高电传导效率，提高器件性能。
在本实施例中，于第二窗口301的侧壁及底部形成第一阻挡层40能避免第二连通材料扩散到第一介质层10和第二介质层30中，第一阻挡层40包括开口401，开口401显露第一连通结构20，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在一个实施例中，第一阻挡层40没有形成开口401但具有薄层区域，此时，也能使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。此薄层区域也属于开口401，此方案也属于本发明的保护范围。
在一个实施例中，第二连通材料容易发生扩散，如果第二连通材料扩散到第一介质层10和第二介质层30中可能会导致短路，影响器件性能，第一阻挡层40能够避免第二连通材料扩散到第一介质层10和第二介质层30中，但是第一阻挡层40能提高第一连通结构20和第二连通结构50的接触电阻，开口401能使得第一连通结构20和第二连通结构50直接接触，能够解决上述问题，使得第一连通结构20与第二连通结构50之间的电阻降低，提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在一个实施例中，步骤S60之后，还包括：
S70：如图10所示，于第二连通结构50上形成第三阻挡层70。
在一个实施例中，形成第三阻挡层70的方法包括化学气相沉积、物理气相沉积或原子层沉积工艺，第三阻挡层70的材质包括氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氧化硅中的一种或几种组合。
一个实施例，如图10所示，提供一种半导体器件，包括：第一介质层10，第一介质层10内具有第一窗口101；第一连通结构20，位于第一窗口101内；第二介质层30，位于第一介质层10上，第二介质层30具有第二窗口301，第二窗口301至少显露第一连通结构20；第一阻挡层40，位于第二窗口301的侧壁及底部，第一阻挡层40包括开口401，开口401显露第一连通结构20；第二连通结构50，位于第二窗口301内。
在本实施例中，上述半导体器件不仅能避免第二连通材料扩散到第一介质层10和第二介质层30中，而且能提高第一连通结构20与第二连通结构 50之间的电传导效率，第一阻挡层40位于第二窗口301的侧壁及底部能避免第二连通材料扩散到第一介质层10和第二介质层30中，第一阻挡层40包括开口401，开口401显露第一连通结构20，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在本实施例中，第一介质层10的材质包括氧化硅、氮化硅、氮氧化硅中的一种或几种组合。第二阻挡层60的材质包括氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氧化硅中的一种或几种组合。
在一个实施例中，还包括：第二阻挡层60，位于第一介质层10的表面，所述第二阻挡层60的上表面低于所述第一连通结构20的顶部；第一窗口101贯穿第二阻挡层60和第一介质层10。第二阻挡层60位于第一介质层10的表面，能避免由于开口401的存在导致第二连通材料扩散到第一介质层10中，进一步减小扩散的风险性，第二阻挡层60能作为形成第二窗口301时的刻蚀阻挡层，提高刻蚀均匀性，第二阻挡层60能作为形成第一连通结构20时的抛光阻挡层，使得多余的第一连通材料层201去除更干净，而且能减少刮痕。
在一个实施例中，至少所述第一窗口101上部的侧壁为倾斜侧壁，以使所述第一连通结构20与所述第一介质层10的交界处包括起边202。第一窗口101的侧壁包括倾斜侧壁1011，在形成第一连通结构20时，首先于第一窗口101内填充第一连通材料层201，然后通过平坦化工艺去除多余的第一连通材料层201，在进行平坦化处理时，由于第一窗口101的侧壁具有倾斜侧壁1011，使得形成的第一连通结构20具有起边202，使得在形成第一阻挡层40时，第一阻挡层40在起边202处形成开口401，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在一个实施例中，第一窗口101的形状包括漏斗状。第一窗口101的形状包括漏斗状，在形成第一连通结构20时，首先于第一窗口101内填充第一连通材料层201，然后通过平坦化工艺去除多余的第一连通材料层201，在进行平坦化处理时，由于第一窗口101的形状是漏斗状，使得形成的第一连通 结构20的上表面边缘都具有起边202，使得在形成第一阻挡层40时，第一阻挡层40在起边202处形成环状开口401，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在本实施例中，第一连通材料层201包括铜、铝、镍、金、银、钛、钨中的一种或几种组合。
在一个实施例中，第一连通结构20包括起边202，起边202位于第一连通结构20与第一介质层10的交界处，以使第一阻挡层40包括开口401。第一连通结构20包括起边202，使得在形成第一阻挡层40时，第一阻挡层40在起边202处形成开口401，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在本实施例中，第一连通结构20与第一介质层10的交界处包括起边202。具体的，起边202是指第一连通结构20的上部为突出于所述第一介质层10上方的凸部，所述凸部的侧壁为倾斜侧壁，且所述倾斜侧壁相较于所述第一介质层10的上表面倾斜的角度小于90°。
在本实施例中，第二介质层30的材质包括氧化硅、氮化硅、氮氧化硅中的一种或几种组合。
在本实施例中，第一阻挡层40的材质包括钛、钽、钨、氮化钛、氮化钽、氮化钨中的一种或几种组合。
在本实施例中，于第二窗口301的侧壁及底部形成第一阻挡层40能避免第二连通材料扩散到第一介质层10和第二介质层30中，第一阻挡层40包括开口401，开口401显露第一连通结构20，使得第一连通结构20与第二连通结构50能直接接触，使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在一个实施例中，开口401的形状包括环状，开口401位于第一连通结构20与第一介质层10的交界处。
在一个实施例中，第一阻挡层40没有形成开口401但具有薄层区域，此 时，也能使得第一连通结构20与第二连通结构50之间的电阻降低，能提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。此薄层区域也属于开口401，此方案也属于本发明的保护范围。
在一个实施例中，第二连通材料容易发生扩散，如果第二连通材料扩散到第一介质层10和第二介质层30中可能会导致短路，影响器件性能，第一阻挡层40能够避免第二连通材料扩散到第一介质层10和第二介质层30中，但是第一阻挡层40能提高第一连通结构20和第二连通结构50的接触电阻，开口401能使得第一连通结构20和第二连通结构50直接接触，能够解决上述问题，使得第一连通结构20与第二连通结构50之间的电阻降低，提高第一连通结构20与第二连通结构50之间电传导效率，提高器件性能。
在本实施例中，第二连通结构50的材质包括铜、铝、镍、金、银、钛、钨中的一种或几种组合，可选地，第二连通结构50的材质为铜。
在一个实施例中，还包括：第三阻挡层70，位于第二连通结构50上。第三阻挡层70的材质包括氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氧化硅中的一种或几种组合。
在一个实施例中，第一连通结构20与第二阻挡层60具有重叠部分。
在一个实施例中，第一阻挡层40位于第一连通结构20的上表面、第二窗口301底部的部分第二阻挡层60的上表面和第二窗口301的侧壁，第一连通结构20上表面的第一阻挡层40的底部高于第二阻挡层60上表面的第一阻挡层40的顶部。
在一个实施例中，第二窗口301内的第二阻挡层60的上表面具有凹部，凹部的深度占第二阻挡层60厚度的比例介于10％～60％之间。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件的制备方法，包括：
    提供第一介质层；
    于所述第一介质层内形成第一窗口；
    于所述第一窗口内形成第一连通结构；
    于所述第一介质层上形成第二介质层，所述第二介质层具有第二窗口，所述第二窗口至少显露所述第一连通结构；以及
    于所述第二窗口的侧壁及底部形成第一阻挡层，所述第一阻挡层包括开口，所述开口显露部分所述第一连通结构；
    于所述第二窗口内形成第二连通结构。
  2. 根据权利要求1所述的半导体器件的制备方法，其中所述第一连通结构包括起边，所述起边形成于所述第一连通结构与所述第一介质层的交界处，以使所述第一阻挡层包括所述开口。
  3. 根据权利要求2所述的半导体器件的制备方法，其中至少所述第一窗口上部的侧壁为倾斜侧壁，以使所述第一连通结构与所述第一介质层的交界处包括起边。
  4. 根据权利要求3所述的半导体器件的制备方法，其中所述第一窗口的形状包括漏斗状。
  5. 根据权利要求3所述的半导体器件的制备方法，其中于所述第一介质层内形成所述第一窗口包括：
    于所述第一介质层内形成通孔；
    于所述通孔内填充第一连通材料层；以及
    刻蚀工艺去除部分所述第一连通材料层和部分所述第一介质层，以形成所述第一窗口。
  6. 根据权利要求3所述的半导体器件的制备方法，其中所述倾斜侧壁相较于所述第一介质层的上表面倾斜的角度小于90°。
  7. 根据权利要求1所述的半导体器件的制备方法，其中于所述第一介质层内形成所述第一窗口之前还包括：于所述第一介质层的表面形成第二阻挡层，所述第二阻挡层的上表面低于所述第一连通结构的顶部。
  8. 根据权利要求1所述的半导体器件的制备方法，其中所述开口的形状 包括环状，所述开口位于所述第一连通结构与所述第一介质层的交界处。
  9. 根据权利要求7所述的半导体器件的制备方法，其中所述于所述第一介质层上形成第二介质层，所述第二介质层具有第二窗口，所述第二窗口至少显露部分所述第一连通结构包括：去除部分厚度的所述第二阻挡层，去除的所述第二阻挡层的厚度占所述第二阻挡层的厚度的比例介于10％～60％之间。
  10. 根据权利要求1所述的半导体器件的制备方法，其中所述第一阻挡层具有薄层区域。
  11. 一种半导体器件，其中包括：
    第一介质层，所述第一介质层内具有第一窗口；
    第一连通结构，位于所述第一窗口内；
    第二介质层，位于所述第一介质层上，所述第二介质层具有第二窗口，所述第二窗口至少显露所述第一连通结构；
    第一阻挡层，位于所述第二窗口的侧壁及底部，所述第一阻挡层包括开口，所述开口显露部分所述第一连通结构；以及
    第二连通结构，位于所述第二窗口内。
  12. 根据权利要求11所述的半导体器件，其中所述第一连通结构包括起边，所述起边位于所述第一连通结构与所述第一介质层的交界处，以使所述第一阻挡层包括所述开口。
  13. 根据权利要求12所述的半导体器件，其中至少所述第一窗口上部的侧壁为倾斜侧壁，以使所述第一连通结构与所述第一介质层的交界处包括起边。
  14. 根据权利要求13所述的半导体器件，其中所述第一窗口的形状包括漏斗状，所述开口的形状包括环状，所述开口位于所述第一连通结构与所述第一介质层的交界处。
  15. 根据权利要求13所述的半导体器件，其中所述倾斜侧壁相较于所述第一介质层的上表面倾斜的角度小于90°。
  16. 根据权利要求11所述的半导体器件，其中还包括：第二阻挡层，位于所述第一介质层的表面，所述第二阻挡层的上表面低于所述第一连通结构的顶部；所述第一窗口贯穿所述第二阻挡层和所述第一介质层。
  17. 根据权利要求16所述的半导体器件，其中所述第一连通结构与所述第二阻挡层具有重叠部分。
  18. 根据权利要求16所述的半导体器件，其中所述第一阻挡层位于所述第一连通结构的上表面、所述第二窗口底部的部分所述第二阻挡层的上表面和所述第二窗口的侧壁，所述第一连通结构上表面的所述第一阻挡层的底部高于所述第二阻挡层上表面的所述第一阻挡层的顶部。
  19. 根据权利要求16所述的半导体器件，其中所述第二阻挡层的厚度被部分去除，去除的所述第二阻挡层的厚度占所述第二阻挡层的厚度的比例介于10％～60％之间。
  20. 根据权利要求11所述的半导体器件，其中所述第一阻挡层具有薄层区域。
PCT/CN2020/115805 2020-01-17 2020-09-17 半导体器件及半导体器件的制备方法 WO2021143180A1 (zh)

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