WO2021102836A1 - Photosensitive device and manufacturing method and apparatus therefor, silicon substrate and manufacturing method and apparatus therefor - Google Patents

Photosensitive device and manufacturing method and apparatus therefor, silicon substrate and manufacturing method and apparatus therefor Download PDF

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WO2021102836A1
WO2021102836A1 PCT/CN2019/121715 CN2019121715W WO2021102836A1 WO 2021102836 A1 WO2021102836 A1 WO 2021102836A1 CN 2019121715 W CN2019121715 W CN 2019121715W WO 2021102836 A1 WO2021102836 A1 WO 2021102836A1
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photosensitive
silicon substrate
area
temperature
logic circuit
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徐泽
肖�琳
周雪梅
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深圳市大疆创新科技有限公司
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    • HELECTRICITY
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    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868Passivation
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    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

Provided are a photosensitive device and a manufacturing method and apparatus therefor, and a silicon substrate and a manufacturing method therefor. The manufacturing method for the photosensitive device comprises: processing a silicon substrate; and after the processing, forming a photosensitive area on the silicon substrate, the photosensitive area being covered with a surface passivation layer, wherein the processing enables the forbidden band width of at least the portion of the surface passivation layer close to the surface to be greater than the forbidden band width of the photosensitive area. By enabling the forbidden band width of at least the portion of the surface passivation layer close to the surface to be greater than the forbidden band width of the photosensitive area, the surface passivation layer can absorb less light, so that the quantum efficiency of the photosensitive device can be improved.

Description

感光器件及其制作方法与装置、硅衬底及其制作方法与装置Photosensitive device and its manufacturing method and device, silicon substrate and its manufacturing method and device
版权申明Copyright statement
本专利文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该专利文件或者该专利披露。The content disclosed in this patent document contains copyrighted material. The copyright belongs to the copyright owner. The copyright owner does not object to anyone copying the patent document or the patent disclosure in the official records and archives of the Patent and Trademark Office.
技术领域Technical field
本申请涉及半导体制作领域,并且具体地,涉及一种感光器件及其制作方法与装置、硅衬底及其制作方法与装置。This application relates to the field of semiconductor manufacturing, and in particular, to a photosensitive device, a manufacturing method and device thereof, a silicon substrate, and a manufacturing method and device thereof.
背景技术Background technique
感光区是互补金属氧化物半导体图像传感器(CMOS Image Sensor,CIS)的核心元素,感光区用于感测外界光线,实现光信号到电信号的转换。感光区可以包括一个或多个光电二极管(Photo-Diode,PD)。The photosensitive area is the core element of a complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS). The photosensitive area is used to sense external light and realize the conversion of optical signals to electrical signals. The photosensitive area may include one or more photo-diodes (PD).
硅衬底的表面缺陷可能会导致光电二极管中的暗电流。通常,为了减小硅衬底的表面缺陷对光电二极管的影响,在感光区与硅衬底的表面之间形成表面钝化层。外界光线在进入感光区之前,会先穿过表面钝化层。由于表面钝化层本身也是硅材料构成,其也会吸收一部分光线,导致这部分光线无法进入感光区(即这部分光线无法进入光电二极管),会造成量子效率的损失。Surface defects of the silicon substrate may cause dark current in the photodiode. Generally, in order to reduce the influence of surface defects of the silicon substrate on the photodiode, a surface passivation layer is formed between the photosensitive area and the surface of the silicon substrate. The external light passes through the surface passivation layer before entering the photosensitive area. Since the surface passivation layer itself is also made of silicon material, it will also absorb part of the light, causing this part of the light to not enter the photosensitive area (that is, this part of the light cannot enter the photodiode), which will cause the loss of quantum efficiency.
发明内容Summary of the invention
本申请提供一种感光器件及其制作方法与装置,以及硅衬底及其制作方法与装置,可以提高感光器件的量子效率。The application provides a photosensitive device, a manufacturing method and device thereof, and a silicon substrate and a manufacturing method and device thereof, which can improve the quantum efficiency of the photosensitive device.
第一方面,提供一种感光器件,所述感光器件包括:硅衬底;感光区,位于所述硅衬底中,所述感光区覆盖有表面钝化层,其中,所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。In a first aspect, there is provided a photosensitive device, the photosensitive device comprising: a silicon substrate; a photosensitive area located in the silicon substrate, the photosensitive area covered with a surface passivation layer, wherein the surface passivation layer The forbidden band width of at least the part close to the surface is greater than the forbidden band width of the photosensitive zone.
第二方面,提供一种感光器件的制作方法,所述制作方法包括:对硅衬底进行处理;在所述处理之后,在所述硅衬底上形成感光区,所述感光区覆盖有表面钝化层,其中,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。In a second aspect, a method for manufacturing a photosensitive device is provided. The manufacturing method includes: processing a silicon substrate; after the processing, forming a photosensitive area on the silicon substrate, the photosensitive area being covered with a surface The passivation layer, wherein the treatment makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive zone.
第三方面,提供一种硅衬底,所述硅衬底用于形成感光区,所述感光区覆盖有表面钝化层,所述硅衬底中靠近表面的硅层的禁带宽度大于所述硅衬底中远离表面的硅层的禁带宽度,这能够使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。In a third aspect, a silicon substrate is provided, the silicon substrate is used to form a photosensitive area, the photosensitive area is covered with a surface passivation layer, and the band gap of the silicon layer near the surface of the silicon substrate is greater than that of the silicon layer. The forbidden band width of the silicon layer far from the surface of the silicon substrate can make the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive region.
第四方面,提供一种硅衬底的制作方法,所述硅衬底用于形成感光区,所述感光区覆盖有表面钝化层,所述制作方法包括:对所述硅衬底进行处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。In a fourth aspect, a method for manufacturing a silicon substrate is provided, the silicon substrate is used to form a photosensitive area, the photosensitive area is covered with a surface passivation layer, and the manufacturing method includes: processing the silicon substrate , The treatment makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive zone.
第五方面,提供一种感光器件,所述感光器件包括:硅衬底,包括像素区与逻辑电路区;感光区,位于所述像素区;逻辑电路,位于所述逻辑电路区,所述逻辑电路用于处理所述感光区光电转换得到的电信号,其中,所述逻辑电路区的表面低于所述像素区的表面。In a fifth aspect, a photosensitive device is provided. The photosensitive device includes: a silicon substrate including a pixel area and a logic circuit area; a photosensitive area located in the pixel area; a logic circuit located in the logic circuit area; The circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
第六方面,提供一种感光器件的制作方法,所述制作方法包括:对包括像素区与逻辑电路区的硅衬底的所述逻辑电路区进行表面硅层去除处理,使所述逻辑电路区的表面低于所述像素区的表面;在所述像素区形成感光区;在经过所述表面硅层去除处理之后的所述逻辑电路区上形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号。In a sixth aspect, a method for manufacturing a photosensitive device is provided. The manufacturing method includes: performing surface silicon layer removal processing on the logic circuit area of a silicon substrate including a pixel area and a logic circuit area, so that the logic circuit area The surface of the pixel area is lower than the surface of the pixel area; a photosensitive area is formed in the pixel area; a logic circuit is formed on the logic circuit area after the surface silicon layer is removed, and the logic circuit is used to process the The electrical signal obtained by photoelectric conversion of the photosensitive area.
第七方面,提供一种感光器件,所述感光器件包括:硅衬底,包括像素区与逻辑电路区;感光区,位于所述像素区,所述感光区覆盖有表面钝化层,所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度;逻辑电路,位于所述逻辑电路区,所述逻辑电路用于处理所述感光区光电转换得到的电信号,其中,所述逻辑电路区的表面低于所述像素区的表面。In a seventh aspect, a photosensitive device is provided. The photosensitive device includes: a silicon substrate including a pixel area and a logic circuit area; a photosensitive area located in the pixel area; the photosensitive area is covered with a surface passivation layer; The forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive area; the logic circuit is located in the logic circuit area, and the logic circuit is used to process the photoelectric conversion of the photosensitive area. Signal, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
第八方面,提供一种感光器件的制作方法,所述制作方法包括:对包括像素区与逻辑电路区的硅衬底进行处理;在所述处理之后,对所述逻辑电路区进行表面硅层去除处理,使所述逻辑电路区的表面低于所述像素区的表面;在所述处理之后,在所述像素区形成感光区,所述感光区覆盖有表面钝化层,其中,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度;在所述表面硅层去除处理之后,在所述逻辑电路区上形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号。In an eighth aspect, a method for manufacturing a photosensitive device is provided. The manufacturing method includes: processing a silicon substrate including a pixel area and a logic circuit area; after the processing, performing a surface silicon layer on the logic circuit area Removal processing makes the surface of the logic circuit area lower than the surface of the pixel area; after the processing, a photosensitive area is formed in the pixel area, and the photosensitive area is covered with a surface passivation layer, wherein the The processing makes the forbidden band width of at least the part close to the surface of the surface passivation layer greater than the forbidden band width of the photosensitive area; after the surface silicon layer is removed, a logic circuit is formed on the logic circuit area, so The logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area.
基于上述描述,本申请通过在硅衬底上制作感光区之前对该硅衬底进行 处理,使得硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度,这能够使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,从而使表面钝化层相对于感光区对光的吸收较少,因此,在外界光线穿过表面钝化层进入感光区的过程中,相对于现有技术,可以使得较多的光线进入感光区,从而可以提高感光器件的量子效率。Based on the above description, this application processes the silicon substrate before fabricating the photosensitive area on the silicon substrate, so that the band gap of the silicon layer near the surface of the silicon substrate is greater than that of the silicon layer far from the surface on the silicon substrate. Band width, which can make the forbidden band width of at least the part close to the surface of the surface passivation layer greater than the forbidden band width of the photosensitive area, so that the surface passivation layer absorbs less light relative to the photosensitive area. Therefore, in the external light In the process of entering the photosensitive area through the surface passivation layer, compared with the prior art, more light can enter the photosensitive area, thereby improving the quantum efficiency of the photosensitive device.
附图说明Description of the drawings
图1为CMOS图像传感器的结构示意图。Figure 1 is a schematic diagram of the structure of a CMOS image sensor.
图2为本说明书实施例的感光器件的制作方法的示意性流程图。Fig. 2 is a schematic flow chart of a method for manufacturing a photosensitive device according to an embodiment of the specification.
图3为本说明书实施例的感光器件的制作方法的另一示意性流程图。FIG. 3 is another schematic flowchart of the manufacturing method of the photosensitive device according to the embodiment of the specification.
图4至图6为本说明书实施例的感光器件的制作工艺流程的示意图。4 to 6 are schematic diagrams of the manufacturing process flow of the photosensitive device according to the embodiment of the specification.
图7为本说明书实施例的感光器件的结构示意图。FIG. 7 is a schematic diagram of the structure of the photosensitive device according to the embodiment of the specification.
图8为本说明书实施例的感光器件的另一结构示意图。FIG. 8 is a schematic diagram of another structure of the photosensitive device according to the embodiment of the specification.
图9为本说明书实施例的硅衬底的制作方法的示意性流程图。FIG. 9 is a schematic flow chart of a manufacturing method of a silicon substrate according to an embodiment of the specification.
图10为本说明书实施例的硅衬底的示意图。Fig. 10 is a schematic diagram of a silicon substrate according to an embodiment of the specification.
图11为本说明书实施例的硅衬底的另一示意图。FIG. 11 is another schematic diagram of the silicon substrate according to the embodiment of the specification.
图12为本说明书实施例的感光器件的又一结构示意图。FIG. 12 is a schematic diagram of another structure of the photosensitive device according to the embodiment of the specification.
图13为本说明书实施例的感光器件的制作方法的又一示意性流程图。FIG. 13 is another schematic flowchart of the manufacturing method of the photosensitive device according to the embodiment of the specification.
图14为本说明书实施例的感光器件的制作方法的再一示意性流程图。FIG. 14 is another schematic flowchart of the method for manufacturing the photosensitive device according to the embodiment of the specification.
具体实施方式Detailed ways
下面将结合附图,对本说明书实施例中的技术方案进行描述。The technical solutions in the embodiments of this specification will be described below in conjunction with the accompanying drawings.
为了便于理解本说明书实施例,下面先结合图1描述CMOS图像传感器的基本原理与结构。In order to facilitate the understanding of the embodiments of this specification, the basic principle and structure of the CMOS image sensor will be described below with reference to FIG. 1.
CMOS图像传感器的基本工作原理是,将光信号转换为电信号,将电信号转换为数字图像信号。The basic working principle of the CMOS image sensor is to convert optical signals into electrical signals and convert electrical signals into digital image signals.
如图1所示,CMOS图像传感器100包括硅衬底110、感光区121与逻辑电路131。感光区121可以包括一个或多个光电二极管(Photo-Diode,PD)。感光区121用于通过光电二极管将光信号转换为电信号。逻辑电路131用于将感光区121转换得到的电信号转换为数字图像信号。例如,感光区121所在的区域(如图1中120指示的区域)可以称为像素区。逻辑电路131所在 的区域(如图1中130指示的区域)可以为逻辑电路区。As shown in FIG. 1, the CMOS image sensor 100 includes a silicon substrate 110, a photosensitive area 121 and a logic circuit 131. The photosensitive area 121 may include one or more photo-diodes (PD). The photosensitive area 121 is used to convert a light signal into an electric signal through a photodiode. The logic circuit 131 is used to convert the electrical signal obtained by the conversion of the photosensitive area 121 into a digital image signal. For example, the area where the photosensitive area 121 is located (the area indicated by 120 in FIG. 1) may be referred to as a pixel area. The area where the logic circuit 131 is located (the area indicated by 130 in FIG. 1) may be a logic circuit area.
硅衬底的硅表面缺陷会导致光电二极管产生暗电流。为了降低硅表面缺陷对光电二极管的影响,通常在感光区与硅表面之间形成表面钝化层。如图1所示,在感光区121与硅衬底110的硅表面之间具有表面钝化层122。The silicon surface defects of the silicon substrate can cause dark currents in the photodiodes. In order to reduce the impact of silicon surface defects on the photodiode, a surface passivation layer is usually formed between the photosensitive area and the silicon surface. As shown in FIG. 1, there is a surface passivation layer 122 between the photosensitive area 121 and the silicon surface of the silicon substrate 110.
表面钝化层可以通过对感光区与硅衬底的表面之间的硅材料进行离子注入的方式形成。例如,在光电二极管的PN结的P型掺杂区与硅表面之间通过离子注入的方式形成P型掺杂的表面钝化层(PIN)。The surface passivation layer can be formed by ion implantation of silicon material between the photosensitive area and the surface of the silicon substrate. For example, a P-type doped surface passivation layer (PIN) is formed between the P-type doped region of the PN junction of the photodiode and the silicon surface by means of ion implantation.
外界光线在进入光电二极管之前,会先穿过表面钝化层。由于表面钝化层本身也是由硅材料构成,其也会吸收一部分光线,导致这部分光线无法被感光区吸收(即无法被光电二极管吸收),导致量子效率的损失。The external light passes through the surface passivation layer before entering the photodiode. Since the surface passivation layer itself is also made of silicon material, it will also absorb a part of the light, causing this part of the light to be unable to be absorbed by the photosensitive area (that is, unable to be absorbed by the photodiode), resulting in a loss of quantum efficiency.
针对上述问题,本说明书提出一种感光器件及其制作方法与装置,可以提高感光器件的量子效率。In view of the above problems, this specification proposes a photosensitive device and a manufacturing method and device thereof, which can improve the quantum efficiency of the photosensitive device.
图2为本说明书实施例的感光器件的制作方法的示意性流程图。该感光器件为包括感光区的半导体器件。例如,该感光器件为CMOS图像传感器。Fig. 2 is a schematic flow chart of a method for manufacturing a photosensitive device according to an embodiment of the specification. The photosensitive device is a semiconductor device including a photosensitive region. For example, the photosensitive device is a CMOS image sensor.
本说明书中提及的感光区可以包括一个或多个光电二极管。The photosensitive area mentioned in this specification may include one or more photodiodes.
如图2所示,该制作方法包括步骤S210与步骤S220。As shown in FIG. 2, the manufacturing method includes step S210 and step S220.
S210,对硅衬底进行处理。S210, processing the silicon substrate.
步骤S210中对硅衬底的处理,使得该硅衬底上靠近表面的硅层(记为第一硅层)的禁带宽度大于硅衬底上远离表面的硅层(记为第二硅层)的禁带宽度。The processing of the silicon substrate in step S210 makes the band gap of the silicon layer near the surface (denoted as the first silicon layer) on the silicon substrate larger than that of the silicon layer far from the surface (denoted as the second silicon layer) on the silicon substrate. ) Forbidden band width.
S220,在进行步骤S210中的处理之后,在该硅衬底上形成感光区,该感光区覆盖有表面钝化层。S220, after performing the processing in step S210, a photosensitive area is formed on the silicon substrate, and the photosensitive area is covered with a surface passivation layer.
应理解,在步骤S220中,通过使该感光区距离硅衬底的表面的距离大于该第一硅层的厚度,则可以实现覆盖该感光区的表面钝化层中至少靠近表面的部分的禁带宽度大于该感光区的禁带宽度。也就是说,步骤S210中对硅衬底的处理,可以使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度。It should be understood that, in step S220, by making the distance between the photosensitive area and the surface of the silicon substrate greater than the thickness of the first silicon layer, at least the part of the surface passivation layer covering the photosensitive area that is close to the surface can be restricted. The belt width is greater than the forbidden band width of the photosensitive zone. In other words, the processing of the silicon substrate in step S210 can make the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive area.
还应理解,若第一硅层的形状不规整,则在步骤S220中,在硅衬底上形成感光区的过程中,使得感光区距离硅衬底的表面的距离大于该第一硅层的最大厚度。It should also be understood that if the shape of the first silicon layer is irregular, in step S220, in the process of forming the photosensitive area on the silicon substrate, the distance between the photosensitive area and the surface of the silicon substrate is greater than that of the first silicon layer. Maximum thickness.
基于硅材料的特性,可以理解到,硅的禁带宽度越大,对光的吸收越少。 在本实施例中,因为表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,所以,表面钝化层相对于感光区对光的吸收较少。换言之,在外界光线穿过表面钝化层进入感光区的过程中,相对于现有技术,本实施例的方案可以使得较多的光线进入感光区,从而可以提高感光器件的量子效率。Based on the characteristics of silicon materials, it can be understood that the greater the band gap of silicon, the less light absorption. In this embodiment, because the forbidden band width of at least the part close to the surface of the surface passivation layer is larger than the forbidden band width of the photosensitive area, the surface passivation layer absorbs less light relative to the photosensitive area. In other words, when external light enters the photosensitive area through the surface passivation layer, compared with the prior art, the solution of this embodiment can make more light enter the photosensitive area, thereby improving the quantum efficiency of the photosensitive device.
因此,本说明书实施例通过在硅衬底上制作感光区之前对该硅衬底进行处理,使得硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度,这能够使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,从而使表面钝化层相对于感光区对光的吸收较少,因此,在外界光线穿过表面钝化层进入感光区的过程中,相对于现有技术,可以使得较多的光线进入感光区,从而可以提高感光器件的量子效率。Therefore, in the embodiment of the present specification, the silicon substrate is processed before the photosensitive area is formed on the silicon substrate, so that the band gap of the silicon layer near the surface of the silicon substrate is greater than that of the silicon layer far away from the surface of the silicon substrate. Band width, which can make the forbidden band width of at least the part close to the surface of the surface passivation layer greater than the forbidden band width of the photosensitive area, so that the surface passivation layer absorbs less light relative to the photosensitive area. Therefore, in the external light In the process of entering the photosensitive area through the surface passivation layer, compared with the prior art, more light can enter the photosensitive area, thereby improving the quantum efficiency of the photosensitive device.
在步骤S210中,可以采用多种方式对硅衬底进行处理,以使得该硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度。In step S210, the silicon substrate can be processed in various ways so that the band gap of the silicon layer close to the surface on the silicon substrate is greater than the band gap of the silicon layer far from the surface on the silicon substrate.
例如,在步骤S210中,对硅衬底进行先加热后冷却处理,以使得该硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度。For example, in step S210, the silicon substrate is heated and then cooled, so that the band gap of the silicon layer close to the surface of the silicon substrate is greater than the band gap of the silicon layer far away from the surface of the silicon substrate.
再例如,在步骤S210中,还可以采用其它可行的方式对硅衬底进行处理,只要使得该硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度即可。For another example, in step S210, the silicon substrate can also be processed in other feasible ways, as long as the band gap of the silicon layer close to the surface on the silicon substrate is greater than that of the silicon layer far away from the surface on the silicon substrate. The width is sufficient.
下文将描述在步骤S210中采用先加热后冷却的方式对硅衬底进行处理。Hereinafter, it will be described that the silicon substrate is processed by heating and then cooling in step S210.
可选地,在步骤S210中,对硅衬底进行先加热后冷却处理,包括:将硅衬底加热至第一温度;以大于自然冷却速度的第一速度将硅衬底从第一温度冷却至第二温度。Optionally, in step S210, performing heating and then cooling processing on the silicon substrate includes: heating the silicon substrate to a first temperature; cooling the silicon substrate from the first temperature at a first speed greater than the natural cooling speed To the second temperature.
例如,第一温度为1150摄氏度~1250摄氏度,第二温度为室温~600摄氏度。For example, the first temperature is 1150 degrees Celsius to 1250 degrees Celsius, and the second temperature is room temperature to 600 degrees Celsius.
可选地,第一速度远大于自然冷却速度。Optionally, the first speed is much greater than the natural cooling speed.
例如,第一速度为80摄氏度每秒~200摄氏度每秒。For example, the first speed is 80 degrees Celsius per second to 200 degrees Celsius per second.
在第一速度远大于自然冷却速度的情况下,先加热后冷却处理可以视为先加热后快速冷却处理。In the case where the first speed is much greater than the natural cooling speed, the heating first and then the cooling treatment can be regarded as the heating first and then the rapid cooling treatment.
可选地,在步骤S210中,在以第一速度将硅衬底从第一温度冷却至第二温度之前,还包括:维持硅衬底的温度为第一温度预设时长。Optionally, in step S210, before cooling the silicon substrate from the first temperature to the second temperature at the first speed, the method further includes: maintaining the temperature of the silicon substrate at the first temperature for a preset period of time.
例如,该预设时长为1分钟~120分钟,优选地时长为10分钟~120分钟。For example, the preset duration is 1 minute to 120 minutes, and preferably the duration is 10 minutes to 120 minutes.
再例如,步骤S210中对硅衬底的处理可以通过高温退火的工艺实现。For another example, the processing of the silicon substrate in step S210 may be achieved through a high-temperature annealing process.
应理解,硅衬底的表面散热较快,内部散热较慢。因此,在硅衬底经过先加热后冷却的处理后,硅衬底表面的硅晶格迅速稳定,内部的硅晶格逐渐收缩稳定。在内部的硅晶格逐渐收缩的过程中,会使近表面的硅晶格受到压应力,该压应力会使得近表面的硅材料的原子间距变短。基于硅材料的特性可知,原子间距越短的硅材料的禁带宽度越大。因此,硅衬底的近表面的硅材料的原子间距变短,相应地,这部分硅材料的禁带宽度变大。因此,本实施例中对硅材料的处理,可以使得硅衬底的近表面的硅材料的禁带宽度变大,即硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度。It should be understood that the surface heat dissipation of the silicon substrate is faster, and the internal heat dissipation is slower. Therefore, after the silicon substrate is heated and then cooled, the silicon lattice on the surface of the silicon substrate quickly stabilizes, and the internal silicon lattice gradually shrinks and stabilizes. In the process of the gradual shrinkage of the internal silicon lattice, the silicon lattice near the surface will be subjected to compressive stress, and the compressive stress will shorten the atomic distance of the silicon material near the surface. Based on the characteristics of silicon materials, it can be known that the shorter the atomic distance, the greater the band gap of the silicon material. Therefore, the atomic distance of the silicon material near the surface of the silicon substrate becomes shorter, and accordingly, the band gap of this part of the silicon material becomes larger. Therefore, the processing of the silicon material in this embodiment can make the forbidden band width of the silicon material near the surface of the silicon substrate larger, that is, the forbidden band width of the silicon layer near the surface of the silicon substrate is larger than that of the silicon substrate far away from the silicon substrate. The band gap of the silicon layer on the surface.
需要说明的是,本说明书中提及的原子间距变短、禁带宽度变大,是针对于未经过离子注入的硅材料。由于在离子注入之后,注入离子会导致注入后材料的晶格产生变化,而先加热后冷却的过程中材料内部的晶格收缩会具有不确定性,除硅材料本身变化,注入离子也会受到影响。因此,在对硅材料处理时,会使用未经过离子注入处理的硅晶圆。It should be noted that the shorter atomic distance and larger band gap mentioned in this specification are for silicon materials that have not undergone ion implantation. After the ion implantation, the implanted ions will cause the crystal lattice of the implanted material to change, and the lattice shrinkage inside the material during the process of heating and then cooling will be uncertain. In addition to the change of the silicon material itself, the implanted ions will also be affected. influences. Therefore, when processing silicon materials, silicon wafers that have not undergone ion implantation are used.
通过以上描述可知,步骤S210中对硅衬底进行的先加热后冷却处理,可以使硅衬底中靠近表面的硅材料的原子间距变短,但不会使硅衬底中远离表面的硅材料(例如,位于硅衬底中心的硅材料)的原子间距发生变化。也就是说,步骤S210中的处理可以使硅衬底的近表面的硅材料的禁带宽度变大,但不会使硅衬底中远离表面的硅材料的禁带宽度变大。It can be seen from the above description that the heating and then cooling of the silicon substrate in step S210 can shorten the atomic distance of the silicon material near the surface in the silicon substrate, but will not make the silicon material far away from the surface of the silicon substrate. (For example, the silicon material located in the center of the silicon substrate) the atomic distance changes. In other words, the processing in step S210 can increase the band gap of the silicon material near the surface of the silicon substrate, but will not increase the band gap of the silicon material far from the surface of the silicon substrate.
假设,将在步骤S210的作用下硅衬底中禁带宽度变大的硅材料记为第一硅层。在步骤S220中,在硅衬底上形成感光区的过程中,通过使得感光区距离硅衬底的表面的深度大于该第一硅层的厚度,则可以实现,覆盖该感光区的表面钝化层中至少靠近表面的部分的禁带宽度大于该感光区的禁带宽度。It is assumed that the silicon material whose band gap becomes larger in the silicon substrate under the action of step S210 is recorded as the first silicon layer. In step S220, in the process of forming the photosensitive area on the silicon substrate, by making the depth of the photosensitive area from the surface of the silicon substrate greater than the thickness of the first silicon layer, passivation of the surface covering the photosensitive area can be achieved. The forbidden band width of at least the part close to the surface of the layer is greater than the forbidden band width of the photosensitive zone.
因此,通过在硅衬底上制作感光区之前,对硅衬底进行先加热后冷却处理,可以使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,从而可以提高感光器件的量化效率。Therefore, by heating and cooling the silicon substrate before making the photosensitive area on the silicon substrate, the forbidden band width of at least the part close to the surface of the surface passivation layer can be greater than the forbidden band width of the photosensitive area. Improve the quantitative efficiency of photosensitive devices.
本说明书中提及的感光区可以通过对硅衬底进行离子注入的方式形成。The photosensitive region mentioned in this specification can be formed by ion implantation on a silicon substrate.
本说明书中提及的感光区可以包括一个或多个光电二极管。The photosensitive area mentioned in this specification may include one or more photodiodes.
光电二极管的核心部分是PN结。当有光照时,光子进入该PN结,产生光生载流子,即实现光信号到电信号的转换。The core part of the photodiode is the PN junction. When there is light, photons enter the PN junction to generate photo-generated carriers, that is, the conversion of light signals to electrical signals is realized.
光电二极管的PN结可以通过在硅衬底上采用离子注入的方式形成。作为示例而非限定,在硅衬底上形成光电二极管的基本流程包括,通过在硅衬底上通过离子注入的方式分别形成第一掺杂区与第二掺杂区,该第一掺杂区与第二掺杂区形成光电二极管的PN结。其中,第一掺杂区为P型掺杂区,第二掺杂区为N型掺杂区;或者,第一掺杂区为N型掺杂区,第二掺杂区为P型掺杂区。The PN junction of the photodiode can be formed by ion implantation on the silicon substrate. As an example and not a limitation, the basic process of forming a photodiode on a silicon substrate includes forming a first doped region and a second doped region by ion implantation on the silicon substrate, the first doped region The PN junction of the photodiode is formed with the second doped region. Wherein, the first doped region is a P-type doped region, and the second doped region is an N-type doped region; or, the first doped region is an N-type doped region, and the second doped region is a P-type doped region. Area.
本说明书中提及的表面钝化层可以通过在感光区与硅衬底的表面之间进行离子注入的方式形成。例如,在光电二极管的PN结的P型掺杂区与硅表面之间通过离子注入的方式形成P型掺杂的表面钝化层(PIN)。The surface passivation layer mentioned in this specification can be formed by ion implantation between the photosensitive area and the surface of the silicon substrate. For example, a P-type doped surface passivation layer (PIN) is formed between the P-type doped region of the PN junction of the photodiode and the silicon surface by means of ion implantation.
应理解,关于感光区以及光电二极管的制作流程为已知的公开技术,本说明书不作赘述。关于表面钝化层的制作流程也为已知的公开技术,本说明书也不作赘述。It should be understood that the manufacturing process of the photosensitive area and the photodiode is a known public technology, and will not be repeated in this specification. The production process of the surface passivation layer is also a known public technology, and will not be repeated in this specification.
本说明书中提及的“近表面”包括“靠近表面”,还可以包括“表面”。例如,上文提及的硅衬底的近表面的硅材料的原子间距变短,表示硅衬底中靠近表面的硅材料的原子间距变短,或者表示硅衬底表面的硅材料以及靠近表面的硅材料的原子间距变短。The "near surface" mentioned in this specification includes "near the surface" and may also include the "surface". For example, the above-mentioned silicon material near the surface of the silicon substrate has a shorter atomic distance, which means that the silicon material near the surface of the silicon substrate has a shorter atomic distance, or it means that the silicon material on the surface of the silicon substrate and the silicon material near the surface are shorter. The atomic distance of the silicon material becomes shorter.
本说明书实施例涉及的硅衬底可以为硅晶片。The silicon substrate involved in the embodiment of this specification may be a silicon wafer.
在现有技术中,有些场景下会在对硅衬底进行离子注入的操作之后,对硅衬底进行高温退火。In the prior art, in some scenarios, the silicon substrate is annealed at a high temperature after ion implantation is performed on the silicon substrate.
而在本说明书提供的方案中,步骤S210在步骤S220之前执行,即是在对该硅衬底进行离子注入的操作之前,对硅衬底进行处理,使得硅衬底靠近表面的硅层的禁带宽度大于硅衬底中远离表面的硅层的禁带宽度。In the solution provided in this specification, step S210 is performed before step S220, that is, the silicon substrate is processed before ion implantation is performed on the silicon substrate, so that the silicon substrate is close to the silicon layer on the surface. The band width is greater than the forbidden band width of the silicon layer far from the surface in the silicon substrate.
因此,本说明书实施例的步骤S210对硅衬底的处理,不同于现有技术中对硅衬底的高温退火,因为二者的执行时机不同,相应地,所起的作用也不同。Therefore, the processing of the silicon substrate in step S210 in the embodiment of the present specification is different from the high-temperature annealing of the silicon substrate in the prior art because the execution timing of the two is different, and accordingly, the roles played are also different.
还应理解,通过在对硅衬底进行离子注入的操作之前,对硅衬底进行处理,使得硅衬底靠近表面的硅层的禁带宽度大于硅衬底中远离表面的硅层的禁带宽度,从而可以实现表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度。It should also be understood that by processing the silicon substrate before performing the ion implantation operation on the silicon substrate, the forbidden band width of the silicon layer near the surface of the silicon substrate is greater than the forbidden band of the silicon layer far away from the surface of the silicon substrate. Therefore, the forbidden band width of at least the part close to the surface of the surface passivation layer can be greater than the forbidden band width of the photosensitive area.
在图2所示实施例中,硅衬底除了包括用于形成感光区的像素区,还包括用于形成逻辑电路的逻辑电路区。In the embodiment shown in FIG. 2, the silicon substrate not only includes a pixel area for forming a photosensitive area, but also includes a logic circuit area for forming a logic circuit.
如图3所示,可选地,在图2所示实施例中,硅衬底包括像素区与逻辑电路区,其中,感光区位于像素区,该制作方法还包括步骤S230。As shown in FIG. 3, optionally, in the embodiment shown in FIG. 2, the silicon substrate includes a pixel area and a logic circuit area. The photosensitive area is located in the pixel area. The manufacturing method further includes step S230.
S230,在逻辑电路区形成逻辑电路,该逻辑电路用于处理感光区光电转换得到的电信号。S230: A logic circuit is formed in the logic circuit area, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion in the photosensitive area.
本说明书中提及的逻辑电路可以通过对硅衬底进行离子注入的方式形成。关于逻辑电路的制作流程也为已知的公开技术,本说明书也不作赘述。The logic circuit mentioned in this specification can be formed by ion implantation into a silicon substrate. The manufacturing process of the logic circuit is also a known public technology, and will not be repeated in this specification.
步骤S220与步骤S230的执行顺序没有限定。The execution order of step S220 and step S230 is not limited.
应理解,在硅衬底还包括用于形成逻辑电路的逻辑电路区的情形下,步骤S210中对硅衬底的处理,也会使逻辑电路区中靠近表面的硅层的禁带宽度变大,这可能会影响逻辑电路的性能。It should be understood that when the silicon substrate also includes a logic circuit area for forming a logic circuit, the processing of the silicon substrate in step S210 will also increase the band gap of the silicon layer near the surface in the logic circuit area. , This may affect the performance of the logic circuit.
针对该问题,本申请提出通过对逻辑电路区进行表面硅层去除处理,使得逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层。In response to this problem, this application proposes to remove the surface silicon layer of the logic circuit area so that the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
继续参见图3,可选地,在图2所示实施例中,该制作方法还包括步骤S240,该步骤S240位于步骤S210之后,位于步骤S230之前。Continuing to refer to FIG. 3, optionally, in the embodiment shown in FIG. 2, the manufacturing method further includes step S240, which is located after step S210 and before step S230.
S240,对逻辑电路区进行表面硅层去除处理,使得逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层。S240: Perform surface silicon layer removal processing on the logic circuit area, so that the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
步骤S210中的处理,使得该硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度。假设,将在步骤S210的作用下硅衬底中禁带宽度变大的硅材料记为第一硅层。在步骤S240中,若逻辑电路区被去除的表面硅层的厚度大于或等于该第一硅层的厚度,即可以实现逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层。The processing in step S210 makes the band gap of the silicon layer close to the surface on the silicon substrate larger than the band gap of the silicon layer far from the surface on the silicon substrate. It is assumed that the silicon material whose band gap becomes larger in the silicon substrate under the action of step S210 is recorded as the first silicon layer. In step S240, if the thickness of the removed surface silicon layer of the logic circuit region is greater than or equal to the thickness of the first silicon layer, it can be realized that the logic circuit region does not include a silicon layer with a band gap greater than that of the photosensitive region.
可选地,在步骤S240中,可以基于预设深度对逻辑电路区进行表面硅层去除处理,使得逻辑电路区被去除预设深度的表面硅层。Optionally, in step S240, a surface silicon layer removal process may be performed on the logic circuit area based on a preset depth, so that the logic circuit area is removed from the surface silicon layer of the preset depth.
该预设深度与步骤S210中使得硅衬底中禁带宽度变大的硅层的厚度相关。假设,将在步骤S210的作用下硅衬底中禁带宽度变大的硅材料记为第一硅层,则该预设深度大于或等于该第一硅层的厚度。The preset depth is related to the thickness of the silicon layer that increases the forbidden band width in the silicon substrate in step S210. Assuming that the silicon material whose band gap becomes larger in the silicon substrate under the action of step S210 is denoted as the first silicon layer, the predetermined depth is greater than or equal to the thickness of the first silicon layer.
该预设深度可以是经验值。例如,该预设深度为0.01微米~0.1微米。The preset depth may be an empirical value. For example, the preset depth is 0.01 micrometers to 0.1 micrometers.
应理解,步骤S240,会使逻辑电路区的表面低于像素区的表面。例如,在上面例子中,逻辑电路区的表面低于像素区的表面的深度为0.01微米~0.1 微米。It should be understood that in step S240, the surface of the logic circuit area is lower than the surface of the pixel area. For example, in the above example, the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
例如,在步骤S240中,可以通过蚀刻的方式,对逻辑电路区进行表面硅层去除处理。For example, in step S240, the logic circuit area may be subjected to surface silicon layer removal processing by etching.
作为示例,在步骤S240中,可以通过光刻与蚀刻的方式,去除逻辑电路区的表面硅层。如图5所示,先在像素区410的表面覆盖光刻胶(photo resist)401,然后对逻辑电路区410的硅表面进行蚀刻(etch)402。其中,通过蚀刻402,去除逻辑电路区420硅表面的第一深度403的硅层。As an example, in step S240, the surface silicon layer of the logic circuit area may be removed by means of photolithography and etching. As shown in FIG. 5, the surface of the pixel area 410 is first covered with a photoresist 401, and then the silicon surface of the logic circuit area 410 is etched 402. Wherein, by etching 402, the silicon layer of the first depth 403 on the silicon surface of the logic circuit region 420 is removed.
因此,通过对逻辑电路区进行表面硅层去除处理,使得逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层,从而可以保证在该逻辑电路区上形成的电路模型的准确性。Therefore, by removing the surface silicon layer of the logic circuit area, the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area, thereby ensuring the accuracy of the circuit model formed on the logic circuit area .
本说明书中,表述“逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层”可以替换为“逻辑电路区的禁带宽度与感光区的禁带宽度相同”。In this specification, the expression "the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area" can be replaced with "the forbidden band width of the logic circuit area is the same as that of the photosensitive area".
作为示例而非限定,图4至图6示出本说明书实施例中制作CMOS图像传感器的工艺流程示意图。As an example and not a limitation, FIG. 4 to FIG. 6 show a schematic diagram of a process flow of manufacturing a CMOS image sensor in an embodiment of this specification.
第一步,如图4所示,初始化硅衬底400。该硅衬底400可以划分为像素区410与逻辑电路区420。In the first step, as shown in FIG. 4, the silicon substrate 400 is initialized. The silicon substrate 400 can be divided into a pixel area 410 and a logic circuit area 420.
应理解,像素区410与逻辑电路区420表示在功能上的划分。实际工艺流程中,可以没有划分像素区410与逻辑电路区420的步骤。It should be understood that the pixel area 410 and the logic circuit area 420 represent functional divisions. In the actual process flow, there may not be a step of dividing the pixel area 410 and the logic circuit area 420.
第二步,将硅衬底400置于高温炉中加热,加热至1150摄氏度~1250摄氏度,维持10分钟~120分钟。In the second step, the silicon substrate 400 is heated in a high-temperature furnace, heated to 1150 degrees Celsius to 1250 degrees Celsius, and maintained for 10 minutes to 120 minutes.
第三步,在维持10分钟~120分钟之后,将硅衬底400从高温炉中迅速取出,以80摄氏度每秒~200摄氏度每秒的速度快速冷却至600摄氏度以下。In the third step, after maintaining for 10 minutes to 120 minutes, the silicon substrate 400 is quickly taken out of the high temperature furnace, and rapidly cooled to below 600 degrees Celsius at a rate of 80 degrees Celsius per second to 200 degrees Celsius per second.
应理解,基于前文描述,第二步与第三步可以使得硅衬底400靠近表面的硅晶格受到压应力,从而使得硅衬底400靠近表面的硅材料的禁带宽度变大。It should be understood that, based on the foregoing description, the second step and the third step can cause the silicon lattice near the surface of the silicon substrate 400 to be subjected to compressive stress, so that the band gap of the silicon material near the surface of the silicon substrate 400 becomes larger.
第四步,对逻辑电路区420的硅表面进行蚀刻处理。如图5所示,先在像素区410的表面覆盖光刻胶(photo resist)401,然后对逻辑电路区410的硅表面进行蚀刻(etch)402。其中,通过蚀刻402,去除逻辑电路区420硅表面的第一深度403的硅层。例如,第一深度403为0.01微米~0.1微米。In the fourth step, the silicon surface of the logic circuit area 420 is etched. As shown in FIG. 5, the surface of the pixel area 410 is first covered with a photoresist 401, and then the silicon surface of the logic circuit area 410 is etched 402. Wherein, by etching 402, the silicon layer of the first depth 403 on the silicon surface of the logic circuit region 420 is removed. For example, the first depth 403 is 0.01 micrometers to 0.1 micrometers.
应理解,完成逻辑电路区420的硅表面的蚀刻之后,去除像素区410上的光刻胶401。It should be understood that after the etching of the silicon surface of the logic circuit area 420 is completed, the photoresist 401 on the pixel area 410 is removed.
第五步,如图6所示,在逻辑电路区420上制作逻辑电路421,在像素区410上制作感光区411。感光区411可以包括一个或多个光电二极管。在感光区411与像素区410的硅表面之间,通过离子注入,形成表面钝化层412。In the fifth step, as shown in FIG. 6, a logic circuit 421 is formed on the logic circuit area 420, and a photosensitive area 411 is formed on the pixel area 410. The photosensitive area 411 may include one or more photodiodes. Between the photosensitive area 411 and the silicon surface of the pixel area 410, a surface passivation layer 412 is formed by ion implantation.
应理解,通过第二步与第三步,使得硅衬底400靠近表面的硅材料的禁带宽度变大,从而使得表面钝化层412至少靠近表面的硅材料的禁带宽度变大,进而使得表面钝化层412对光的吸收变少,使得更多的光进入感光区411,即使得更多的光吸收后成为有效的光生信号电子,可以提高感光器件的量子效率。It should be understood that through the second and third steps, the forbidden band width of the silicon material near the surface of the silicon substrate 400 becomes larger, so that the surface passivation layer 412 at least the forbidden band width of the silicon material near the surface becomes larger. As a result, the surface passivation layer 412 absorbs less light, so that more light enters the photosensitive region 411, that is, more light is absorbed to become effective photo-generated signal electrons, which can improve the quantum efficiency of the photosensitive device.
应理解,像素区除了包括感光区,还可以被设计为还包括其它线路与元件,例如,用于存储光信号的元件,本说明书对此不作限定。关于像素区内的感光区以及其它线路或元件的制作流程为已知的公开技术,因此,不再赘述。It should be understood that, in addition to the photosensitive area, the pixel area may also be designed to include other circuits and elements, for example, elements for storing optical signals, which are not limited in this specification. The production process of the photosensitive area and other circuits or components in the pixel area is a known public technology, so it will not be repeated here.
还应理解,逻辑电路区除了逻辑电路,还可以被设计为还包括其它线路或电子元件,本说明书对此不作限定。关于逻辑电路区内的逻辑电路以及其它线路或元件的制作流程为已知的公开技术,因此,不再赘述。It should also be understood that in addition to the logic circuit, the logic circuit area may also be designed to include other circuits or electronic components, which are not limited in this specification. The manufacturing process of the logic circuit and other circuits or components in the logic circuit area is a known public technology, so it will not be repeated here.
基于上述描述可知,通过图4至图6所示的方法制作CMOS图像传感器,相对于现有技术,可以提高CMOS图像传感器的量子效率。Based on the above description, it can be known that the CMOS image sensor manufactured by the method shown in FIG. 4 to FIG. 6 can improve the quantum efficiency of the CMOS image sensor compared with the prior art.
图7为本说明书实施例提供的感光器件700的示意性框图。该感光器件700包括硅衬底710与感光区720。感光区720可以包括一个或多个光电二极管。感光区720位于硅衬底710中,感光区720覆盖有表面钝化层730。其中,表面钝化层730中至少靠近表面的部分的禁带宽度大于感光区720的禁带宽度。FIG. 7 is a schematic block diagram of a photosensitive device 700 provided by an embodiment of this specification. The photosensitive device 700 includes a silicon substrate 710 and a photosensitive area 720. The photosensitive area 720 may include one or more photodiodes. The photosensitive area 720 is located in the silicon substrate 710, and the photosensitive area 720 is covered with a surface passivation layer 730. Wherein, the forbidden band width of at least the part close to the surface of the surface passivation layer 730 is greater than the forbidden band width of the photosensitive region 720.
应理解,因为表面钝化层730中至少靠近表面的部分的禁带宽度大于感光区720的禁带宽度,所以,表面钝化层730相对于感光区720对光的吸收较少。换言之,在外界光线穿过表面钝化层730进入感光区720的过程中,相对于现有技术,本实施例的感光器件700可以使得较多的光线进入感光区720,从而可以提高感光器件的量子效率。It should be understood that because the forbidden band width of at least the part close to the surface of the surface passivation layer 730 is greater than the forbidden band width of the photosensitive region 720, the surface passivation layer 730 absorbs less light relative to the photosensitive region 720. In other words, when external light enters the photosensitive area 720 through the surface passivation layer 730, compared with the prior art, the photosensitive device 700 of this embodiment can make more light enter the photosensitive area 720, thereby improving the performance of the photosensitive device. Quantum efficiency.
因此,本实施例的感光器件700,由于表面钝化层730中至少靠近表面的部分的禁带宽度大于感光区720的禁带宽度,因此可以提高感光器件的量子效率。Therefore, in the photosensitive device 700 of the present embodiment, since the forbidden band width of at least the part close to the surface of the surface passivation layer 730 is greater than the band gap of the photosensitive region 720, the quantum efficiency of the photosensitive device can be improved.
可选地,在如图7所示实施例中,硅衬底710在感光区720形成之前, 被进行如上文实施例中步骤S210所描述的处理,该处理可以使得表面钝化层730中至少靠近表面的部分的禁带宽度大于感光区720的禁带宽度。具体描述详见上文关于步骤S210的描述,为了简洁,这里不再赘述。Optionally, in the embodiment shown in FIG. 7, before the photosensitive region 720 is formed, the silicon substrate 710 is processed as described in step S210 in the above embodiment, which can make at least the surface passivation layer 730 The forbidden band width of the part close to the surface is larger than the forbidden band width of the photosensitive area 720. For the specific description, please refer to the description of step S210 above, for the sake of brevity, it is not repeated here.
可选地,如图8所示,硅衬底710包括像素区711与逻辑电路区712,其中,感光区720位于像素区711。该感光器件700还包括逻辑电路740,位于逻辑电路区712,逻辑电路740用于处理感光区720光电转换得到的电信号。Optionally, as shown in FIG. 8, the silicon substrate 710 includes a pixel area 711 and a logic circuit area 712, wherein the photosensitive area 720 is located in the pixel area 711. The photosensitive device 700 further includes a logic circuit 740 located in the logic circuit area 712, and the logic circuit 740 is used to process the electrical signals obtained by the photoelectric conversion of the photosensitive area 720.
可选地,在如图8所示实施例中,逻辑电路区712不包括禁带宽度大于感光区720的禁带宽度的硅层。Optionally, in the embodiment shown in FIG. 8, the logic circuit region 712 does not include a silicon layer with a band gap greater than that of the photosensitive region 720.
应理解,逻辑电路区712不包括禁带宽度大于感光区720的禁带宽度的硅层,可以保证在该逻辑电路区712形成的逻辑电路740的准确性。It should be understood that the logic circuit region 712 does not include a silicon layer with a band gap greater than that of the photosensitive region 720, which can ensure the accuracy of the logic circuit 740 formed in the logic circuit region 712.
可选地,在如图8所示实施例中,逻辑电路区712在逻辑电路740形成之前,经过如上文实施例中步骤S240描述的表面硅层去除处理,该表面硅层去除处理使得逻辑电路区712不包括禁带宽度大于感光区720的禁带宽度的硅层。具体描述详见上文关于步骤S240的描述,为了简洁,这里不再赘述。Optionally, in the embodiment shown in FIG. 8, before the logic circuit 740 is formed, the logic circuit area 712 undergoes the surface silicon layer removal process as described in step S240 in the above embodiment, and the surface silicon layer removal process makes the logic circuit The region 712 does not include a silicon layer with a band gap greater than that of the photosensitive region 720. For the specific description, please refer to the above description of step S240, for the sake of brevity, it will not be repeated here.
如图8所示,逻辑电路区712的表面低于像素区711的表面。As shown in FIG. 8, the surface of the logic circuit area 712 is lower than the surface of the pixel area 711.
例如,逻辑电路区712的表面低于像素区711的表面的深度为0.01微米~0.1微米。For example, the depth of the surface of the logic circuit region 712 lower than the surface of the pixel region 711 is 0.01 micrometers to 0.1 micrometers.
例如,图7或图8所示的感光器件700可以为任意包括感光区的器件。For example, the photosensitive device 700 shown in FIG. 7 or FIG. 8 may be any device including a photosensitive region.
再例如,图8所示感光器件700为CMOS图像传感器。For another example, the photosensitive device 700 shown in FIG. 8 is a CMOS image sensor.
本说明书还提出一种硅衬底及其制作方法与装置,使得基于该硅衬底制作的感光器件,可以提高感光器件的量子效率。This specification also proposes a silicon substrate and a manufacturing method and device thereof, so that a photosensitive device made based on the silicon substrate can improve the quantum efficiency of the photosensitive device.
图9为本说明书实施例的硅衬底的制作方法的示意性流程图。该硅衬底用于形成感光区,该感光区覆盖有表面钝化层。FIG. 9 is a schematic flow chart of a manufacturing method of a silicon substrate according to an embodiment of the specification. The silicon substrate is used to form a photosensitive area, and the photosensitive area is covered with a surface passivation layer.
如图9所示,该制作方法包括步骤S910。As shown in FIG. 9, the manufacturing method includes step S910.
S910,对硅衬底进行处理,该处理使得该硅衬底中靠近表面的硅层的禁带宽度大于该硅衬底中远离表面的硅层的禁带宽度,这能够使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度。S910. The silicon substrate is processed to make the forbidden band width of the silicon layer close to the surface of the silicon substrate larger than the forbidden band width of the silicon layer far from the surface in the silicon substrate, which can make the surface passivation layer At least the forbidden band width of the part close to the surface is larger than the forbidden band width of the photosensitive area.
应理解,本实施例可以使得硅衬底中靠近表面的硅层的禁带宽度大于该硅衬底中远离表面的硅层的禁带宽度,因此,当在该硅衬底上形成感光区, 可以实现覆盖在感光区的表面钝化层中至少靠近表面的部分的禁带宽度大于该感光区的禁带宽度。因为表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,所以表面钝化层相对于感光区对光的吸收较少。换言之,在外界光线穿过表面钝化层进入感光区的过程中,相对于现有技术,本实施例的方案可以使较多的光线进入感光区,从而可以提高感光器件的量子效率。It should be understood that this embodiment can make the forbidden band width of the silicon layer near the surface in the silicon substrate larger than the forbidden band width of the silicon layer far from the surface in the silicon substrate. Therefore, when the photosensitive area is formed on the silicon substrate, It can be realized that the forbidden band width of at least the part close to the surface of the surface passivation layer covering the photosensitive area is larger than the forbidden band width of the photosensitive area. Because the forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive area, the surface passivation layer absorbs less light relative to the photosensitive area. In other words, when external light enters the photosensitive area through the surface passivation layer, compared with the prior art, the solution of this embodiment can allow more light to enter the photosensitive area, thereby improving the quantum efficiency of the photosensitive device.
步骤S910可以对应上文实施例中的步骤S210,具体详见上文,这里不再赘述。Step S910 may correspond to step S210 in the above embodiment. For details, please refer to the above, and will not be repeated here.
可选地,在图9所示实施例中,硅衬底包括像素区与逻辑电路区,其中,感光区位于像素区,逻辑电路区用于形成逻辑电路,逻辑电路用于处理感光区光电转换得到的电信号;如图9所示,该制作方法还包括步骤S920。Optionally, in the embodiment shown in FIG. 9, the silicon substrate includes a pixel area and a logic circuit area, wherein the photosensitive area is located in the pixel area, the logic circuit area is used to form a logic circuit, and the logic circuit is used to process photoelectric conversion of the photosensitive area. Obtained electrical signals; as shown in FIG. 9, the manufacturing method further includes step S920.
S920,在步骤S910之后,对逻辑电路区进行表面硅层去除处理,使得逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层。S920, after step S910, perform surface silicon layer removal processing on the logic circuit area, so that the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
步骤S910可以对应上文实施例中的步骤S240,具体详见上文,这里不再赘述。Step S910 may correspond to step S240 in the above embodiment. For details, please refer to the above, which will not be repeated here.
例如,图9所示实施例中的硅衬底可用于制作包含感光区的器件。For example, the silicon substrate in the embodiment shown in FIG. 9 can be used to fabricate a device containing a photosensitive region.
例如,图9所示实施例中的硅衬底可用于制作CMOS图像传感器。For example, the silicon substrate in the embodiment shown in FIG. 9 can be used to make a CMOS image sensor.
图10为本说明书实施例提供的硅衬底1000的示意图。该硅衬底1000用于形成感光区,感光区覆盖有表面钝化层。该硅衬底1000中靠近表面的硅层(如图10中1010指示的硅层)的禁带宽度大于硅衬底1000中远离表面的硅层(如图10中1020指示的硅层)的禁带宽度。FIG. 10 is a schematic diagram of a silicon substrate 1000 provided by an embodiment of this specification. The silicon substrate 1000 is used to form a photosensitive area, and the photosensitive area is covered with a surface passivation layer. The forbidden band width of the silicon layer near the surface of the silicon substrate 1000 (the silicon layer indicated by 1010 in FIG. 10) is greater than that of the silicon layer far away from the surface (the silicon layer indicated by 1020 in FIG. 10) in the silicon substrate 1000. Band width.
应理解,因为硅衬底1000中靠近表面的硅层的禁带宽度大于该硅衬底1000中远离表面的硅层的禁带宽度,因此,当在该硅衬底1000上形成感光区,可以实现覆盖在感光区的表面钝化层中至少靠近表面的部分的禁带宽度大于该感光区的禁带宽度。因为表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度,所以表面钝化层相对于感光区对光的吸收较少。换言之,在外界光线穿过表面钝化层进入感光区的过程中,相对于现有技术,本实施例的方案可以使较多的光线进入感光区,从而可以提高感光器件的量子效率。It should be understood that because the band gap of the silicon layer near the surface of the silicon substrate 1000 is greater than the band gap of the silicon layer far from the surface of the silicon substrate 1000, therefore, when the photosensitive area is formed on the silicon substrate 1000, The forbidden band width of at least the part close to the surface of the surface passivation layer covering the photosensitive area is greater than the forbidden band width of the photosensitive area. Because the forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive area, the surface passivation layer absorbs less light relative to the photosensitive area. In other words, when external light enters the photosensitive area through the surface passivation layer, compared with the prior art, the solution of this embodiment can allow more light to enter the photosensitive area, thereby improving the quantum efficiency of the photosensitive device.
需要说明的是,图10中标记1010与1020分别指示的硅层仅为示意而非限定。例如,实际应用中,1010指示的硅层的截面不一定是规整的。It should be noted that the silicon layers indicated by the marks 1010 and 1020 in FIG. 10 are only for illustration and not for limitation. For example, in practical applications, the cross section of the silicon layer indicated by 1010 is not necessarily regular.
可选地,硅衬底1000经过上文实施例中步骤S210的处理,该处理使得硅衬底中靠近表面的硅层的禁带宽度大于硅衬底中远离表面的硅层的禁带宽度。具体描述详见上文关于步骤S210的描述,为了简洁,这里不再赘述。Optionally, the silicon substrate 1000 undergoes the processing of step S210 in the above embodiment, which makes the band gap of the silicon layer near the surface in the silicon substrate larger than the band gap of the silicon layer far from the surface in the silicon substrate. For the specific description, please refer to the description of step S210 above, for the sake of brevity, it is not repeated here.
可选地,如图11所示,硅衬底1000包括像素区1001与逻辑电路区1002,其中,像素区1001用于形成感光区,逻辑电路区1002用于形成逻辑电路,逻辑电路用于处理感光区光电转换得到的电信号,其中,逻辑电路区1002不包括禁带宽度大于感光区的禁带宽度的硅层。Optionally, as shown in FIG. 11, the silicon substrate 1000 includes a pixel area 1001 and a logic circuit area 1002, wherein the pixel area 1001 is used to form a photosensitive area, the logic circuit area 1002 is used to form a logic circuit, and the logic circuit is used for processing. The electrical signal obtained by photoelectric conversion of the photosensitive area, wherein the logic circuit area 1002 does not include a silicon layer with a band gap greater than that of the photosensitive area.
如图11所示,逻辑电路区1002的表面低于像素区1001的表面。As shown in FIG. 11, the surface of the logic circuit area 1002 is lower than the surface of the pixel area 1001.
例如,在图11的示例中,逻辑电路区1002的表面低于像素区1001的表面的深度大于或等于硅层1010的厚度。For example, in the example of FIG. 11, the depth of the surface of the logic circuit region 1002 lower than the surface of the pixel region 1001 is greater than or equal to the thickness of the silicon layer 1010.
例如,逻辑电路区1002的表面低于像素区1001的表面的深度为0.01微米~0.1微米。For example, the depth of the surface of the logic circuit region 1002 lower than the surface of the pixel region 1001 is 0.01 micrometers to 0.1 micrometers.
可选地,硅衬底1000在经过步骤S240的处理之后,还经过上文实施例中的步骤S240的处理,该处理使得逻辑电路区1002不包括禁带宽度大于感光区的禁带宽度的硅层。具体描述详见上文关于步骤S240的描述,为了简洁,这里不再赘述。Optionally, after the silicon substrate 1000 undergoes the processing of step S240, it also undergoes the processing of step S240 in the above embodiment. This processing makes the logic circuit region 1002 not include silicon with a band gap greater than that of the photosensitive region. Floor. For the specific description, please refer to the above description of step S240, for the sake of brevity, it will not be repeated here.
例如,图10或图11所示实施例中的硅衬底1000可用于制作包含感光区的器件。For example, the silicon substrate 1000 in the embodiment shown in FIG. 10 or FIG. 11 can be used to fabricate a device including a photosensitive region.
例如,图10或图11所示实施例中的硅衬底1000可用于制作CMOS图像传感器。For example, the silicon substrate 1000 in the embodiment shown in FIG. 10 or FIG. 11 can be used to fabricate a CMOS image sensor.
本说明书实施例还提供一种感光器件1200。The embodiment of the present specification also provides a photosensitive device 1200.
图12为感光器件1200的示意图。感光器件1200包括硅衬底1210,硅衬底1210包括像素区1211与逻辑电路区1212。感光器件1200还包括位于像素区1211的感光区1220,以及位于逻辑电路区1212的逻辑电路1230。逻辑电路1230用于处理感光区1220光电转换得到的电信号。逻辑电路区1212的表面低于像素区1211的表面。FIG. 12 is a schematic diagram of a photosensitive device 1200. As shown in FIG. The photosensitive device 1200 includes a silicon substrate 1210, and the silicon substrate 1210 includes a pixel area 1211 and a logic circuit area 1212. The photosensitive device 1200 further includes a photosensitive area 1220 located in the pixel area 1211 and a logic circuit 1230 located in the logic circuit area 1212. The logic circuit 1230 is used to process the electrical signal obtained by the photoelectric conversion of the photosensitive area 1220. The surface of the logic circuit area 1212 is lower than the surface of the pixel area 1211.
如图12所示,感光区1220覆盖有表面钝化层1240。As shown in FIG. 12, the photosensitive area 1220 is covered with a surface passivation layer 1240.
可选地,在图12所示实施例中,表面钝化层1240中至少靠近表面的部分的禁带宽度大于感光区1220的禁带宽度。Optionally, in the embodiment shown in FIG. 12, the forbidden band width of at least the part close to the surface of the surface passivation layer 1240 is larger than the forbidden band width of the photosensitive region 1220.
可选地,在图12所示的实施例中,逻辑电路区1211不包括禁带宽度大于感光区1220的禁带宽度的硅层。Optionally, in the embodiment shown in FIG. 12, the logic circuit region 1211 does not include a silicon layer with a band gap greater than that of the photosensitive region 1220.
可选地,在图12所示的实施例中,逻辑电路区1211的表面低于像素区1212的表面的深度为0.01微米~0.1微米。Optionally, in the embodiment shown in FIG. 12, the depth of the surface of the logic circuit region 1211 lower than the surface of the pixel region 1212 is 0.01 micrometers to 0.1 micrometers.
可选地,在图12所示的实施例中,硅衬底1210在感光区1220形成之前经过上文实施例中步骤S210的处理,该处理可以使得硅衬底1210中靠近表面的硅层的禁带宽度大于硅衬底1210中远离表现的硅层的禁带宽度。关于该处理的描述,详见上文关于步骤S210的描述,这里不再赘述。Optionally, in the embodiment shown in FIG. 12, the silicon substrate 1210 undergoes the processing of step S210 in the above embodiment before the photosensitive region 1220 is formed. This processing can make the silicon substrate 1210 close to the surface of the silicon layer The forbidden band width is greater than the forbidden band width of the silicon layer farther from the performance in the silicon substrate 1210. For the description of this processing, please refer to the above description of step S210, which will not be repeated here.
例如,在图12所示的实施例中,硅衬底1210在感光区1220形成之前经过步骤S210的处理,能够使得表面钝化层1240中至少靠近表面的部分的禁带宽度大于感光区1220的禁带宽度。For example, in the embodiment shown in FIG. 12, the silicon substrate 1210 is processed in step S210 before the photosensitive region 1220 is formed, so that at least the portion of the surface passivation layer 1240 close to the surface has a band gap greater than that of the photosensitive region 1220. Band gap width.
可选地,在图12所示的实施例中,硅衬底1210在经过步骤S210的处理之后,还经过上文实施例中步骤S240的表面硅层去除处理,该表面硅层去除处理使得逻辑电路区1212不包括禁带宽度大于感光区1220的禁带宽度的硅层。关于该表面硅层去除处理的描述,详见上文关于步骤S240的描述,这里不再赘述。Optionally, in the embodiment shown in FIG. 12, after the silicon substrate 1210 undergoes the processing of step S210, it also undergoes the surface silicon layer removal processing of step S240 in the above embodiment. The surface silicon layer removal processing makes the logic The circuit region 1212 does not include a silicon layer with a band gap greater than that of the photosensitive region 1220. For the description of the removal of the surface silicon layer, please refer to the description of step S240 above, which will not be repeated here.
图12所示的感光器件1200可以为包含感光区的半导体器件。The photosensitive device 1200 shown in FIG. 12 may be a semiconductor device including a photosensitive region.
例如,图12所示的感光器件1200可以为CMOS图像传感器。For example, the photosensitive device 1200 shown in FIG. 12 may be a CMOS image sensor.
如图13所示,本说明书中还提供一种感光器件的制作方法。例如,该感光器件为如图12所示的感光器件1200。如图13所示,该制作方法包括如下步骤。As shown in Figure 13, this specification also provides a method for manufacturing a photosensitive device. For example, the photosensitive device is a photosensitive device 1200 as shown in FIG. 12. As shown in Figure 13, the manufacturing method includes the following steps.
S1310,对包括像素区与逻辑电路区的硅衬底的逻辑电路区进行表面硅层去除处理,使逻辑电路区的表面低于像素区的表面。S1310: Perform surface silicon layer removal processing on the logic circuit region of the silicon substrate including the pixel region and the logic circuit region, so that the surface of the logic circuit region is lower than the surface of the pixel region.
S1320,在像素区形成感光区。S1320, forming a photosensitive area in the pixel area.
S1330,在经过步骤S1310处理之后的逻辑电路区上形成逻辑电路,逻辑电路用于处理感光区光电转换得到的电信号。S1330, forming a logic circuit on the logic circuit area processed in step S1310, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area.
在图13所示实施例中,感光区覆盖有表面钝化层。In the embodiment shown in FIG. 13, the photosensitive area is covered with a surface passivation layer.
可选地,在图13所示实施例中,在步骤S1310之前,该制作方法还包括步骤S1340。Optionally, in the embodiment shown in FIG. 13, before step S1310, the manufacturing method further includes step S1340.
S1340,对硅衬底进行处理,该处理使得该硅衬底上靠近表面的硅层的禁带宽度大于硅衬底上远离表面的硅层的禁带宽度。In S1340, the silicon substrate is processed to make the band gap of the silicon layer close to the surface on the silicon substrate larger than the band gap of the silicon layer far from the surface on the silicon substrate.
步骤S1340如上文实施例中的步骤S210。相关描述详见上文关于步骤S210的描述,这里不再赘述。Step S1340 is the same as step S210 in the above embodiment. For related descriptions, please refer to the above description of step S210, which will not be repeated here.
可选地,在图13所示实施例的制作方法包括步骤S210的情况下,步骤S1310可以通过上文实施例中的步骤S240实现。相关描述详见上文关于步骤S240的描述,这里不再赘述。Optionally, in the case where the manufacturing method of the embodiment shown in FIG. 13 includes step S210, step S1310 may be implemented by step S240 in the above embodiment. For related descriptions, please refer to the above description of step S240, which will not be repeated here.
如图14所示,本说明书中还提供一种感光器件的制作方法。例如,该感光器件为如图12所示的感光器件1200。如图14所示,该制作方法包括如下步骤。As shown in Figure 14, this specification also provides a method for manufacturing a photosensitive device. For example, the photosensitive device is a photosensitive device 1200 as shown in FIG. 12. As shown in Figure 14, the manufacturing method includes the following steps.
S1410,对硅衬底进行处理,硅衬底包括像素区与逻辑电路区。S1410: The silicon substrate is processed, and the silicon substrate includes a pixel area and a logic circuit area.
步骤S1410与上文实施例中的步骤S210相同,详见上文,这里不再赘述。Step S1410 is the same as step S210 in the above embodiment, see the above for details, and will not be repeated here.
S1420,在步骤S1410的处理之后,对逻辑电路区进行表面硅层去除处理,使逻辑电路区的表面低于像素区的表面。S1420, after the processing of step S1410, perform surface silicon layer removal processing on the logic circuit area so that the surface of the logic circuit area is lower than the surface of the pixel area.
S1430,在步骤S1410的处理之后,在像素区形成感光区。S1430, after the processing of step S1410, a photosensitive area is formed in the pixel area.
例如,步骤S1430也可以在步骤S1420之后执行。For example, step S1430 can also be executed after step S1420.
S1440,在步骤S1420的处理之后,在逻辑电路区上形成逻辑电路,逻辑电路用于处理感光区光电转换得到的电信号。S1440: After the processing of step S1420, a logic circuit is formed on the logic circuit area, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area.
其中,步骤S1410对硅衬底的处理,使得表面钝化层中至少靠近表面的部分的禁带宽度大于感光区的禁带宽度。Wherein, in step S1410, the silicon substrate is processed so that the forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive area.
步骤S1430与步骤S1440的执行顺序没有限定。The execution order of step S1430 and step S1440 is not limited.
可选地,在图14所示实施例中,步骤S1420通过上文实施例中的步骤S240实现,该表面硅层去除处理,使得逻辑电路区不包括禁带宽度大于感光区的禁带宽度的硅层。步骤S1420的实现方式详见上文关于步骤S240的描述,这里不再赘述。Optionally, in the embodiment shown in FIG. 14, step S1420 is implemented by step S240 in the above embodiment. The surface silicon layer is removed so that the logic circuit area does not include a band gap greater than that of the photosensitive region. Silicon layer. For the implementation of step S1420, please refer to the above description of step S240, which will not be repeated here.
本说明书实施例还提供一种感光器件的制作装置,该制作装置用于执行上文实施例中感光器件的制作方法。The embodiment of this specification also provides a manufacturing apparatus of a photosensitive device, and the manufacturing apparatus is used to implement the manufacturing method of the photosensitive device in the above embodiment.
本说明书实施例还提供一种硅衬底的制作装置,该制作装置用于执行上文实施例中硅衬底的制作方法。The embodiment of this specification also provides a manufacturing device of a silicon substrate, and the manufacturing device is used to implement the manufacturing method of the silicon substrate in the above embodiment.
除非另有定义,本说明书所使用的所有的技术和科学术语与属于本说明书的技术领域的技术人员通常理解的含义相同。本说明书中在本说明书的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请的保护范围。Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field of this specification. The terms used in this specification in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the protection scope of this application.
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限 于此,任何熟悉本技术领域的技术人员在本说明书揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of this application, but the scope of protection of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this specification. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (110)

  1. 一种感光器件,其特征在于,包括:A photosensitive device, characterized in that it comprises:
    硅衬底;Silicon substrate
    感光区,位于所述硅衬底中,所述感光区覆盖有表面钝化层,The photosensitive area is located in the silicon substrate, and the photosensitive area is covered with a surface passivation layer,
    其中,所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。Wherein, the forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive zone.
  2. 根据权利要求1所述的感光器件,其特征在于,所述硅衬底包括像素区与逻辑电路区,其中,所述感光区位于所述像素区;The photosensitive device according to claim 1, wherein the silicon substrate comprises a pixel area and a logic circuit area, wherein the photosensitive area is located in the pixel area;
    其中,所述感光器件还包括:Wherein, the photosensitive device further includes:
    逻辑电路,位于所述逻辑电路区,所述逻辑电路用于处理所述感光区光电转换得到的电信号。The logic circuit is located in the logic circuit area, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area.
  3. 根据权利要求2所述的感光器件,其特征在于,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to claim 2, wherein the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
  4. 根据权利要求2或3所述的感光器件,其特征在于,所述逻辑电路区的表面低于所述像素区的表面。The photosensitive device according to claim 2 or 3, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  5. 根据权利要求4所述的感光器件,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The photosensitive device according to claim 4, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  6. 根据权利要求1至5中任一项所述的感光器件,其特征在于,所述硅衬底在所述感光区形成之前经过处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The photosensitive device according to any one of claims 1 to 5, wherein the silicon substrate is processed before the photosensitive region is formed, and the processing makes the surface passivation layer at least close to the surface Part of the forbidden band width is greater than the forbidden band width of the photosensitive area.
  7. 根据权利要求6所述的感光器件,其特征在于,所述处理包括:先加热后冷却处理。7. The photosensitive device according to claim 6, wherein the processing comprises: heating first and then cooling processing.
  8. 根据权利要求7所述的感光器件,其特征在于,所述先加热后冷却处理包括:8. The photosensitive device according to claim 7, wherein the heating first and then cooling treatment comprises:
    加热至第一温度;Heated to the first temperature;
    以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度。Cooling from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  9. 根据权利要求8所述的感光器件,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。8. The photosensitive device according to claim 8, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  10. 根据权利要求8或9所述的感光器件,其特征在于,所述以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度,包括:The photosensitive device according to claim 8 or 9, wherein the cooling from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持温度所述第一温度预设时长之后,以所述第一速度冷却至所述第二温度。After maintaining the temperature at the first temperature for a preset period of time, cooling to the second temperature at the first speed.
  11. 根据权利要求10所述的感光器件,其特征在于,所述预设时长为1分钟~120分钟。10. The photosensitive device according to claim 10, wherein the preset duration is 1 minute to 120 minutes.
  12. 根据权利要求7至11中任一项所述的感光器件,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The photosensitive device according to any one of claims 7 to 11, wherein the process method of the first heating and then cooling treatment is high temperature annealing.
  13. 根据权利要求6至12中任一项所述的感光器件,其特征在于,所述处理使得所述硅衬底上靠近表面的第一硅层的禁带宽度大于所述硅衬底上远离表面的第二硅层的禁带宽度;The photosensitive device according to any one of claims 6 to 12, wherein the treatment makes the forbidden band width of the first silicon layer on the silicon substrate closer to the surface larger than that on the silicon substrate away from the surface. The band gap of the second silicon layer;
    其中,所述感光区距离所述硅衬底的表面的深度大于所述第一硅层的厚度。Wherein, the depth of the photosensitive region from the surface of the silicon substrate is greater than the thickness of the first silicon layer.
  14. 根据权利要求2至5中任一项所述的感光器件,其特征在于,所述逻辑电路区在所述逻辑电路形成之前,经过表面硅层去除处理,所述表面硅层去除处理使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to any one of claims 2 to 5, wherein the logic circuit area undergoes a surface silicon layer removal treatment before the logic circuit is formed, and the surface silicon layer removal treatment makes the The logic circuit region does not include a silicon layer with a band gap greater than that of the photosensitive region.
  15. 根据权利要求14所述的感光器件,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The photosensitive device according to claim 14, wherein the surface silicon layer removal treatment is implemented by etching.
  16. 根据权利要求1至15中任一项所述的感光器件,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The photosensitive device according to any one of claims 1 to 15, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  17. 一种感光器件的制作方法,其特征在于,包括:A method for manufacturing a photosensitive device, which is characterized in that it comprises:
    对硅衬底进行处理;Process the silicon substrate;
    在所述处理之后,在所述硅衬底上形成感光区,所述感光区覆盖有表面钝化层,After the processing, a photosensitive area is formed on the silicon substrate, and the photosensitive area is covered with a surface passivation layer,
    其中,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。Wherein, the treatment makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive zone.
  18. 根据权利要求17所述的制作方法,其特征在于,所述对硅衬底进行处理,包括:The manufacturing method according to claim 17, wherein the processing the silicon substrate comprises:
    对所述硅衬底进行先加热后冷却处理。The silicon substrate is heated and then cooled.
  19. 根据权利要求18所述的制作方法,其特征在于,所述对所述硅衬底进行先加热后冷却处理,包括:18. The manufacturing method of claim 18, wherein the heating and then cooling the silicon substrate comprises:
    将所述硅衬底加热至第一温度;Heating the silicon substrate to a first temperature;
    以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度。The silicon substrate is cooled from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  20. 根据权利要求19所述的制作方法,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The manufacturing method of claim 19, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  21. 根据权利要求19或20所述的制作方法,其特征在于,所述以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度,包括:The manufacturing method according to claim 19 or 20, wherein the cooling the silicon substrate from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持所述硅衬底的温度为所述第一温度预设时长之后,以所述第一速度将所述硅衬底冷却至所述第二温度。After maintaining the temperature of the silicon substrate at the first temperature for a preset period of time, the silicon substrate is cooled to the second temperature at the first speed.
  22. 根据权利要求21所述的制作方法,其特征在于,所述预设时长为1分钟~120分钟。22. The production method of claim 21, wherein the preset duration is 1 minute to 120 minutes.
  23. 根据权利要求18至22中任一项所述的制作方法,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The manufacturing method according to any one of claims 18 to 22, wherein the process method of the first heating and then cooling treatment is high temperature annealing.
  24. 根据权利要求17至23中任一项所述的制作方法,其特征在于,所述硅衬底包括像素区与逻辑电路区,其中,所述感光区位于所述像素区;The manufacturing method according to any one of claims 17 to 23, wherein the silicon substrate comprises a pixel area and a logic circuit area, wherein the photosensitive area is located in the pixel area;
    其中,所述制作方法还包括:Wherein, the manufacturing method further includes:
    在所述逻辑电路区形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号。A logic circuit is formed in the logic circuit area, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion in the photosensitive area.
  25. 根据权利要求24所述的制作方法,其特征在于,所述制作方法还包括:The manufacturing method according to claim 24, wherein the manufacturing method further comprises:
    在所述处理之后,在形成所述逻辑电路之前,对所述逻辑电路区进行表面硅层去除处理,使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。After the processing, before forming the logic circuit, perform a surface silicon layer removal process on the logic circuit area, so that the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area .
  26. 根据权利要求25所述的制作方法,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The manufacturing method according to claim 25, wherein the surface silicon layer removal treatment is implemented by etching.
  27. 根据权利要求25或26所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面。The manufacturing method according to claim 25 or 26, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  28. 根据权利要求27所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。28. The manufacturing method of claim 27, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  29. 根据权利要求17至28中任一项所述的制作方法,其特征在于,所 述处理使得所述硅衬底上靠近表面的第一硅层的禁带宽度大于所述硅衬底上远离表面的第二硅层的禁带宽度;The manufacturing method according to any one of claims 17 to 28, wherein the processing makes the forbidden band width of the first silicon layer on the silicon substrate closer to the surface larger than that on the silicon substrate away from the surface. The band gap of the second silicon layer;
    其中,所述感光区距离所述硅衬底的表面的深度大于所述第一硅层的厚度。Wherein, the depth of the photosensitive region from the surface of the silicon substrate is greater than the thickness of the first silicon layer.
  30. 根据权利要求17至29中任一项所述的制作方法,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The manufacturing method according to any one of claims 17 to 29, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  31. 一种硅衬底,所述硅衬底用于形成感光区,所述感光区覆盖有表面钝化层,其特征在于,A silicon substrate is used to form a photosensitive area, and the photosensitive area is covered with a surface passivation layer, characterized in that:
    所述硅衬底中靠近表面的硅层的禁带宽度大于所述硅衬底中远离表面的硅层的禁带宽度,这能够使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The forbidden band width of the silicon layer near the surface in the silicon substrate is greater than the forbidden band width of the silicon layer far from the surface in the silicon substrate, which can make the forbidden band of at least the part near the surface in the surface passivation layer The width is greater than the forbidden band width of the photosensitive zone.
  32. 根据权利要求31所述的硅衬底,其特征在于,所述硅衬底包括像素区与逻辑电路区,其中,所述像素区用于形成所述感光区,所述逻辑电路区用于形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号;The silicon substrate according to claim 31, wherein the silicon substrate comprises a pixel area and a logic circuit area, wherein the pixel area is used to form the photosensitive area, and the logic circuit area is used to form A logic circuit, the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area;
    其中,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。Wherein, the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
  33. 根据权利要求32所述的硅衬底,其特征在于,所述逻辑电路区的表面低于所述像素区的表面。The silicon substrate of claim 32, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  34. 根据权利要求33所述的硅衬底,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The silicon substrate of claim 33, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  35. 根据权利要求31至34中任一项所述的硅衬底,其特征在于,所述硅衬底经过处理,所述处理使得所述硅衬底中靠近表面的硅层的禁带宽度大于所述硅衬底中远离表面的硅层的禁带宽度。The silicon substrate according to any one of claims 31 to 34, wherein the silicon substrate is processed so that the forbidden band width of the silicon layer near the surface of the silicon substrate is greater than that of the silicon layer. The forbidden band width of the silicon layer far away from the surface of the silicon substrate.
  36. 根据权利要求35所述的硅衬底,其特征在于,所述处理包括:先加热后冷却处理。The silicon substrate according to claim 35, wherein the treatment comprises: first heating and then cooling treatment.
  37. 根据权利要求36所述的硅衬底,其特征在于,所述先加热后冷却处理,包括:The silicon substrate of claim 36, wherein the heating first and then cooling treatment comprises:
    加热至第一温度;Heated to the first temperature;
    以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度。Cooling from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  38. 根据权利要求37所述的硅衬底,其特征在于,所述第一温度为1150 摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The silicon substrate of claim 37, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees per second. Celsius per second.
  39. 根据权利要求37或38所述的硅衬底,其特征在于,所述以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度,包括:The silicon substrate according to claim 37 or 38, wherein the cooling from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持所述第一温度预设时长之后,以所述第一速度冷却至所述第二温度。After maintaining the first temperature for a preset period of time, cooling to the second temperature at the first speed.
  40. 根据权利要求39所述的硅衬底,其特征在于,所述预设时长为1分钟~120分钟。The silicon substrate according to claim 39, wherein the preset duration is 1 minute to 120 minutes.
  41. 根据权利要求36至40中任一项所述的硅衬底,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The silicon substrate according to any one of claims 36 to 40, wherein the process method of the first heating and then cooling treatment is high temperature annealing.
  42. 根据权利要求32至34中任一项所述的硅衬底,其特征在于,所述硅衬底经过表面硅层去除处理,所述表面硅层去除处理使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The silicon substrate according to any one of claims 32 to 34, wherein the silicon substrate has undergone a surface silicon layer removal process, and the surface silicon layer removal process makes the logic circuit area not include a band gap. A silicon layer with a width greater than the forbidden band width of the photosensitive zone.
  43. 根据权利要求42所述的硅衬底,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The silicon substrate according to claim 42, wherein the surface silicon layer removal treatment is implemented by etching.
  44. 根据权利要求31至43中任一项所述的硅衬底,其特征在于,所述硅衬底用于形成互补金属氧化物半导体CMOS图像传感器。The silicon substrate according to any one of claims 31 to 43, wherein the silicon substrate is used to form a complementary metal oxide semiconductor CMOS image sensor.
  45. 一种硅衬底的制作方法,所述硅衬底用于形成感光区,所述感光区覆盖有表面钝化层,其特征在于,所述制作方法包括:A manufacturing method of a silicon substrate, wherein the silicon substrate is used to form a photosensitive area, and the photosensitive area is covered with a surface passivation layer, characterized in that the manufacturing method includes:
    对所述硅衬底进行处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The silicon substrate is processed, and the processing makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive zone.
  46. 根据权利要求45所述的制作方法,其特征在于,所述对所述硅衬底进行处理,包括:The manufacturing method of claim 45, wherein the processing the silicon substrate comprises:
    对所述硅衬底进行先加热后冷却处理。The silicon substrate is heated and then cooled.
  47. 根据权利要求46所述的制作方法,其特征在于,所述对所述硅衬底进行先加热后冷却处理,包括:The manufacturing method of claim 46, wherein the heating and then cooling the silicon substrate comprises:
    将所述硅衬底加热至第一温度;Heating the silicon substrate to a first temperature;
    以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度。The silicon substrate is cooled from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  48. 根据权利要求47所述的制作方法,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度 为80摄氏度每秒~200摄氏度每秒。The manufacturing method of claim 47, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  49. 根据权利要求47或48所述的制作方法,其特征在于,所述以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度,包括:The manufacturing method according to claim 47 or 48, wherein the cooling the silicon substrate from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持所述硅衬底的温度为所述第一温度预设时长之后,以所述第一速度将所述硅衬底冷却至所述第二温度。After maintaining the temperature of the silicon substrate at the first temperature for a preset period of time, the silicon substrate is cooled to the second temperature at the first speed.
  50. 根据权利要求49所述的制作方法,其特征在于,所述预设时长为1分钟~120分钟。The manufacturing method according to claim 49, wherein the preset duration is 1 minute to 120 minutes.
  51. 根据权利要求46至50中任一项所述的制作方法,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The manufacturing method according to any one of claims 46 to 50, wherein the process method of heating first and then cooling treatment is high temperature annealing.
  52. 根据权利要求45至51中任一项所述的制作方法,其特征在于,所述硅衬底包括像素区与逻辑电路区,其中,所述感光区位于所述像素区,所述逻辑电路区用于形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号;The manufacturing method according to any one of claims 45 to 51, wherein the silicon substrate comprises a pixel area and a logic circuit area, wherein the photosensitive area is located in the pixel area, and the logic circuit area Used to form a logic circuit, the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area;
    其中,所述制作方法还包括:Wherein, the manufacturing method further includes:
    在所述处理之后,对所述逻辑电路区进行表面硅层去除处理,使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。After the processing, a surface silicon layer removal process is performed on the logic circuit region, so that the logic circuit region does not include a silicon layer with a band gap greater than that of the photosensitive region.
  53. 根据权利要求52所述的制作方法,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The manufacturing method according to claim 52, wherein the surface silicon layer removal treatment is implemented by etching.
  54. 根据权利要求52或53所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面。The manufacturing method according to claim 52 or 53, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  55. 根据权利要求54所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The manufacturing method according to claim 54, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  56. 根据权利要求45至55中任一项所述的制作方法,其特征在于,所述硅衬底用于形成互补金属氧化物半导体CMOS图像传感器。The manufacturing method according to any one of claims 45 to 55, wherein the silicon substrate is used to form a complementary metal oxide semiconductor CMOS image sensor.
  57. 一种感光器件,其特征在于,包括:A photosensitive device, characterized in that it comprises:
    硅衬底,包括像素区与逻辑电路区;Silicon substrate, including pixel area and logic circuit area;
    感光区,位于所述像素区;The photosensitive area is located in the pixel area;
    逻辑电路,位于所述逻辑电路区,所述逻辑电路用于处理所述感光区光电转换得到的电信号,其中,所述逻辑电路区的表面低于所述像素区的表面。The logic circuit is located in the logic circuit area, and the logic circuit is used to process the electrical signals obtained by photoelectric conversion of the photosensitive area, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  58. 根据权利要求57所述的感光器件,其特征在于,所述感光区覆盖 有表面钝化层,所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The photosensitive device according to claim 57, wherein the photosensitive area is covered with a surface passivation layer, and the forbidden band width of at least the part close to the surface of the surface passivation layer is greater than the forbidden band width of the photosensitive area .
  59. 根据权利要求58所述的感光器件,其特征在于,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to claim 58, wherein the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
  60. 根据权利要求57至59中任一项所述的感光器件,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The photosensitive device according to any one of claims 57 to 59, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  61. 根据权利要求58至60中任一项所述的感光器件,其特征在于,所述硅衬底在所述感光区形成之前,经过处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The photosensitive device according to any one of claims 58 to 60, wherein the silicon substrate is processed before the photosensitive region is formed, and the processing makes the surface passivation layer at least close to the surface The forbidden band width of the part is greater than the forbidden band width of the photosensitive area.
  62. 根据权利要求61所述的感光器件,其特征在于,所述处理包括:先加热后冷却处理。The photosensitive device according to claim 61, wherein the processing comprises: first heating and then cooling processing.
  63. 根据权利要求62所述的感光器件,其特征在于,所述先加热后冷却处理包括:The photosensitive device according to claim 62, wherein the heating first and then cooling treatment comprises:
    加热至第一温度;Heated to the first temperature;
    以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度。Cooling from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  64. 根据权利要求63所述的感光器件,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The photosensitive device according to claim 63, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  65. 根据权利要求63或64所述的感光器件,其特征在于,所述以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度,包括:The photosensitive device according to claim 63 or 64, wherein the cooling from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持温度所述第一温度预设时长之后,以所述第一速度冷却至所述第二温度。After maintaining the temperature at the first temperature for a preset period of time, cooling to the second temperature at the first speed.
  66. 根据权利要求65所述的感光器件,其特征在于,所述预设时长为1分钟~120分钟。The photosensitive device according to claim 65, wherein the preset duration is 1 minute to 120 minutes.
  67. 根据权利要求62至66中任一项所述的感光器件,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The photosensitive device according to any one of claims 62 to 66, wherein the process method of the first heating and then cooling treatment is high temperature annealing.
  68. 根据权利要求61至67中任一项所述的感光器件,其特征在于,所述逻辑电路区在所述逻辑电路形成之前,经过表面硅层去除处理,所述表面硅层去除处理使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to any one of claims 61 to 67, wherein the logic circuit area undergoes a surface silicon layer removal treatment before the logic circuit is formed, and the surface silicon layer removal treatment makes the The logic circuit region does not include a silicon layer with a band gap greater than that of the photosensitive region.
  69. 根据权利要求68所述的感光器件,其特征在于,所述表面硅层去 除处理通过蚀刻方式实现。The photosensitive device according to claim 68, wherein the surface silicon layer removal treatment is achieved by etching.
  70. 根据权利要求57至69中任一项所述的感光器件,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The photosensitive device according to any one of claims 57 to 69, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  71. 一种感光器件的制作方法,其特征在于,包括:A method for manufacturing a photosensitive device, which is characterized in that it comprises:
    对包括像素区与逻辑电路区的硅衬底的所述逻辑电路区进行表面硅层去除处理,使所述逻辑电路区的表面低于所述像素区的表面;Performing surface silicon layer removal processing on the logic circuit region of the silicon substrate including the pixel region and the logic circuit region, so that the surface of the logic circuit region is lower than the surface of the pixel region;
    在所述像素区形成感光区;Forming a photosensitive area in the pixel area;
    在经过所述表面硅层去除处理之后的所述逻辑电路区上形成逻辑电路,所述逻辑电路用于处理所述感光区光电转换得到的电信号。A logic circuit is formed on the logic circuit area after the surface silicon layer removal process, and the logic circuit is used to process the electrical signal obtained by photoelectric conversion of the photosensitive area.
  72. 根据权利要求71所述的制作方法,其特征在于,所述感光区覆盖有表面钝化层;The manufacturing method according to claim 71, wherein the photosensitive area is covered with a surface passivation layer;
    其中,所述制作方法还包括:Wherein, the manufacturing method further includes:
    在所述表面硅层去除处理以及形成所述感光区之前,对所述硅衬底进行处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。Before the surface silicon layer removal treatment and the formation of the photosensitive area, the silicon substrate is processed, and the treatment makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the photosensitive area The forbidden band width.
  73. 根据权利要求72所述的制作方法,其特征在于,所述对硅衬底进行处理,包括:The manufacturing method according to claim 72, wherein said processing the silicon substrate comprises:
    对所述硅衬底进行先加热后冷却处理。The silicon substrate is heated and then cooled.
  74. 根据权利要求73所述的制作方法,其特征在于,所述对所述硅衬底进行先加热后冷却处理,包括:The manufacturing method of claim 73, wherein the heating and then cooling the silicon substrate comprises:
    将所述硅衬底加热至第一温度;Heating the silicon substrate to a first temperature;
    以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度。The silicon substrate is cooled from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  75. 根据权利要求74所述的制作方法,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The manufacturing method according to claim 74, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  76. 根据权利要求74或75所述的制作方法,其特征在于,所述以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度,包括:The manufacturing method according to claim 74 or 75, wherein the cooling the silicon substrate from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持所述硅衬底的温度为所述第一温度预设时长之后,以所述第一速度将所述硅衬底冷却至所述第二温度。After maintaining the temperature of the silicon substrate at the first temperature for a preset period of time, the silicon substrate is cooled to the second temperature at the first speed.
  77. 根据权利要求76所述的制作方法,其特征在于,所述预设时长为1分钟~120分钟。The manufacturing method according to claim 76, wherein the preset duration is 1 minute to 120 minutes.
  78. 根据权利要求73至77中任一项所述的制作方法,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The manufacturing method according to any one of claims 73 to 77, wherein the process method of heating first and then cooling treatment is high temperature annealing.
  79. 根据权利要求72至78中任一项所述的制作方法,其特征在于,所述表面硅层去除处理使得,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The manufacturing method according to any one of claims 72 to 78, wherein the surface silicon layer removal treatment is such that the logic circuit region does not include silicon with a band gap greater than that of the photosensitive region. Floor.
  80. 根据权利要求79所述的制作方法,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The manufacturing method according to claim 79, wherein the surface silicon layer removal treatment is implemented by etching.
  81. 根据权利要求71至80中任一项所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The manufacturing method according to any one of claims 71 to 80, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  82. 根据权利要求72至78中任一项所述的制作方法,其特征在于,所述处理使得所述硅衬底上靠近表面的第一硅层的禁带宽度大于所述硅衬底上远离表面的第二硅层的禁带宽度;The manufacturing method according to any one of claims 72 to 78, wherein the processing makes the forbidden band width of the first silicon layer on the silicon substrate closer to the surface larger than that on the silicon substrate away from the surface. The band gap of the second silicon layer;
    其中,所述感光区距离所述硅衬底的表面的深度大于所述第一硅层的厚度。Wherein, the depth of the photosensitive region from the surface of the silicon substrate is greater than the thickness of the first silicon layer.
  83. 根据权利要求71至82中任一项所述的制作方法,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The manufacturing method according to any one of claims 71 to 82, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  84. 一种感光器件,其特征在于,包括:A photosensitive device, characterized in that it comprises:
    硅衬底,包括像素区与逻辑电路区;Silicon substrate, including pixel area and logic circuit area;
    感光区,位于所述像素区,所述感光区覆盖有表面钝化层,所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度;The photosensitive area is located in the pixel area, the photosensitive area is covered with a surface passivation layer, and the forbidden band width of at least a part of the surface passivation layer close to the surface is greater than the forbidden band width of the photosensitive area;
    逻辑电路,位于所述逻辑电路区,所述逻辑电路用于处理所述感光区光电转换得到的电信号,其中,所述逻辑电路区的表面低于所述像素区的表面。The logic circuit is located in the logic circuit area, and the logic circuit is used to process the electrical signals obtained by photoelectric conversion of the photosensitive area, wherein the surface of the logic circuit area is lower than the surface of the pixel area.
  85. 根据权利要求84所述的感光器件,其特征在于,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to claim 84, wherein the logic circuit area does not include a silicon layer with a band gap greater than that of the photosensitive area.
  86. 根据权利要求84或85所述的感光器件,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The photosensitive device according to claim 84 or 85, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  87. 根据权利要求84至86中任一项所述的感光器件,其特征在于,所述硅衬底在所述感光区形成之前,经过处理,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。The photosensitive device according to any one of claims 84 to 86, wherein the silicon substrate is processed before the photosensitive region is formed, and the processing makes the surface passivation layer at least close to the surface The forbidden band width of the part is greater than the forbidden band width of the photosensitive area.
  88. 根据权利要求87所述的感光器件,其特征在于,所述处理包括:先加热后冷却处理。The photosensitive device according to claim 87, wherein the treatment comprises: first heating and then cooling treatment.
  89. 根据权利要求88所述的感光器件,其特征在于,所述先加热后冷却处理包括:The photosensitive device according to claim 88, wherein the heating first and then cooling treatment comprises:
    加热至第一温度;Heated to the first temperature;
    以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度。Cooling from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  90. 根据权利要求89所述的感光器件,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The photosensitive device according to claim 89, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  91. 根据权利要求89或90所述的感光器件,其特征在于,所述以大于自然冷却速度的第一速度从所述第一温度冷却至第二温度,包括:The photosensitive device according to claim 89 or 90, wherein the cooling from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持温度所述第一温度预设时长之后,以所述第一速度冷却至所述第二温度。After maintaining the temperature at the first temperature for a preset period of time, cooling to the second temperature at the first speed.
  92. 根据权利要求91所述的感光器件,其特征在于,所述预设时长为1分钟~120分钟。The photosensitive device according to claim 91, wherein the preset duration is 1 minute to 120 minutes.
  93. 根据权利要求88至92中任一项所述的感光器件,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The photosensitive device according to any one of claims 88 to 92, wherein the process method of the first heating and then cooling treatment is high temperature annealing.
  94. 根据权利要求84至93中任一项所述的感光器件,其特征在于,所述逻辑电路区在所述逻辑电路形成之前,经过表面硅层去除处理,所述表面硅层去除处理使得所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The photosensitive device according to any one of claims 84 to 93, wherein the logic circuit area is subjected to a surface silicon layer removal treatment before the logic circuit is formed, and the surface silicon layer removal treatment causes the The logic circuit region does not include a silicon layer with a band gap greater than that of the photosensitive region.
  95. 根据权利要求94所述的感光器件,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The photosensitive device according to claim 94, wherein the surface silicon layer removal treatment is implemented by etching.
  96. 根据权利要求84至95中任一项所述的感光器件,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The photosensitive device according to any one of claims 84 to 95, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  97. 一种感光器件的制作方法,其特征在于,包括:A method for manufacturing a photosensitive device, which is characterized in that it comprises:
    对包括像素区与逻辑电路区的硅衬底进行处理;Processing the silicon substrate including the pixel area and the logic circuit area;
    在所述处理之后,对所述逻辑电路区进行表面硅层去除处理,使所述逻辑电路区的表面低于所述像素区的表面;After the processing, performing surface silicon layer removal processing on the logic circuit area so that the surface of the logic circuit area is lower than the surface of the pixel area;
    在所述处理之后,在所述像素区形成感光区;After the processing, a photosensitive area is formed in the pixel area;
    在所述表面硅层去除处理之后,在所述逻辑电路区上形成逻辑电路,所 述逻辑电路用于处理所述感光区光电转换得到的电信号,After the removal of the surface silicon layer, a logic circuit is formed on the logic circuit area, and the logic circuit is used to process electrical signals obtained by photoelectric conversion of the photosensitive area,
    其中,所述处理使得所述表面钝化层中至少靠近表面的部分的禁带宽度大于所述感光区的禁带宽度。Wherein, the treatment makes the forbidden band width of at least the part close to the surface of the surface passivation layer larger than the forbidden band width of the photosensitive zone.
  98. 根据权利要求97所述的制作方法,其特征在于,所述对包括像素区与逻辑电路区的硅衬底进行处理,包括:The manufacturing method according to claim 97, wherein the processing the silicon substrate including the pixel area and the logic circuit area comprises:
    对所述硅衬底进行先加热后冷却处理。The silicon substrate is heated and then cooled.
  99. 根据权利要求98所述的制作方法,其特征在于,所述对所述硅衬底进行先加热后冷却处理,包括:The manufacturing method of claim 98, wherein the heating and then cooling the silicon substrate comprises:
    将所述硅衬底加热至第一温度;Heating the silicon substrate to a first temperature;
    以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度。The silicon substrate is cooled from the first temperature to the second temperature at a first speed greater than the natural cooling speed.
  100. 根据权利要求99所述的制作方法,其特征在于,所述第一温度为1150摄氏度~1250摄氏度,所述第二温度为室温~600摄氏度,所述第一速度为80摄氏度每秒~200摄氏度每秒。The manufacturing method of claim 99, wherein the first temperature is between 1150 degrees Celsius and 1250 degrees Celsius, the second temperature is between room temperature and 600 degrees Celsius, and the first speed is between 80 degrees Celsius and 200 degrees Celsius per second. Every second.
  101. 根据权利要求99或100所述的制作方法,其特征在于,所述以大于自然冷却速度的第一速度将所述硅衬底从所述第一温度冷却至第二温度,包括:The manufacturing method according to claim 99 or 100, wherein the cooling the silicon substrate from the first temperature to the second temperature at a first speed greater than a natural cooling speed comprises:
    在维持所述硅衬底的温度为所述第一温度预设时长之后,以所述第一速度将所述硅衬底冷却至所述第二温度。After maintaining the temperature of the silicon substrate at the first temperature for a preset period of time, the silicon substrate is cooled to the second temperature at the first speed.
  102. 根据权利要求101所述的制作方法,其特征在于,所述预设时长为1分钟~120分钟。The production method according to claim 101, wherein the preset duration is 1 minute to 120 minutes.
  103. 根据权利要求98至102中任一项所述的制作方法,其特征在于,所述先加热后冷却处理的工艺方法为高温退火。The manufacturing method according to any one of claims 98 to 102, wherein the process method of heating first and then cooling treatment is high temperature annealing.
  104. 根据权利要求97至103中任一项所述的制作方法,其特征在于,所述表面硅层去除处理使得,所述逻辑电路区不包括禁带宽度大于所述感光区的禁带宽度的硅层。The manufacturing method according to any one of claims 97 to 103, wherein the surface silicon layer removal treatment is such that the logic circuit region does not include silicon with a band gap greater than that of the photosensitive region. Floor.
  105. 根据权利要求104所述的制作方法,其特征在于,所述表面硅层去除处理通过蚀刻方式实现。The manufacturing method according to claim 104, wherein the surface silicon layer removal treatment is implemented by etching.
  106. 根据权利要求97至105中任一项所述的制作方法,其特征在于,所述逻辑电路区的表面低于所述像素区的表面的深度为0.01微米~0.1微米。The manufacturing method according to any one of claims 97 to 105, wherein the depth of the surface of the logic circuit area lower than the surface of the pixel area is 0.01 micrometers to 0.1 micrometers.
  107. 根据权利要求97至106中任一项所述的制作方法,其特征在于, 所述处理使得所述硅衬底上靠近表面的第一硅层的禁带宽度大于所述硅衬底上远离表面的第二硅层的禁带宽度;The manufacturing method according to any one of claims 97 to 106, wherein the processing makes the forbidden band width of the first silicon layer on the silicon substrate closer to the surface larger than that on the silicon substrate away from the surface The band gap of the second silicon layer;
    其中,所述感光区距离所述硅衬底的表面的深度大于所述第一硅层的厚度。Wherein, the depth of the photosensitive region from the surface of the silicon substrate is greater than the thickness of the first silicon layer.
  108. 根据权利要求97至107中任一项所述的制作方法,其特征在于,所述感光器件为互补金属氧化物半导体CMOS图像传感器。The manufacturing method according to any one of claims 97 to 107, wherein the photosensitive device is a complementary metal oxide semiconductor CMOS image sensor.
  109. 一种感光器件的制作装置,其特征在于,用于执行:A manufacturing device for photosensitive devices, which is characterized in that it is used to perform:
    如权利要求17至30中任一项所述的感光器件的制作方法,或者,The method of manufacturing a photosensitive device according to any one of claims 17 to 30, or,
    如权利要求71至83中任一项所述的感光器件的制作方法,或者The method of manufacturing a photosensitive device according to any one of claims 71 to 83, or
    如权利要求97至108中任一项所述的感光器件的制作方法。The method for manufacturing a photosensitive device according to any one of claims 97 to 108.
  110. 一种硅衬底的处理装置,其特征在于,用于执行如权利要求45至56中任一项所述的硅衬底的制作方法。A processing device for a silicon substrate, characterized in that it is used to implement the method for manufacturing a silicon substrate according to any one of claims 45 to 56.
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